Merge branch 'pcmcia' of git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia
[sfrench/cifs-2.6.git] / drivers / iommu / intel-svm.c
1 /*
2  * Copyright © 2015 Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * Authors: David Woodhouse <dwmw2@infradead.org>
14  */
15
16 #include <linux/intel-iommu.h>
17 #include <linux/mmu_notifier.h>
18 #include <linux/sched.h>
19 #include <linux/sched/mm.h>
20 #include <linux/slab.h>
21 #include <linux/intel-svm.h>
22 #include <linux/rculist.h>
23 #include <linux/pci.h>
24 #include <linux/pci-ats.h>
25 #include <linux/dmar.h>
26 #include <linux/interrupt.h>
27 #include <asm/page.h>
28
29 static irqreturn_t prq_event_thread(int irq, void *d);
30
31 struct pasid_entry {
32         u64 val;
33 };
34
35 struct pasid_state_entry {
36         u64 val;
37 };
38
39 int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
40 {
41         struct page *pages;
42         int order;
43
44         /* Start at 2 because it's defined as 2^(1+PSS) */
45         iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
46
47         /* Eventually I'm promised we will get a multi-level PASID table
48          * and it won't have to be physically contiguous. Until then,
49          * limit the size because 8MiB contiguous allocations can be hard
50          * to come by. The limit of 0x20000, which is 1MiB for each of
51          * the PASID and PASID-state tables, is somewhat arbitrary. */
52         if (iommu->pasid_max > 0x20000)
53                 iommu->pasid_max = 0x20000;
54
55         order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
56         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
57         if (!pages) {
58                 pr_warn("IOMMU: %s: Failed to allocate PASID table\n",
59                         iommu->name);
60                 return -ENOMEM;
61         }
62         iommu->pasid_table = page_address(pages);
63         pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order);
64
65         if (ecap_dis(iommu->ecap)) {
66                 /* Just making it explicit... */
67                 BUILD_BUG_ON(sizeof(struct pasid_entry) != sizeof(struct pasid_state_entry));
68                 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
69                 if (pages)
70                         iommu->pasid_state_table = page_address(pages);
71                 else
72                         pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
73                                 iommu->name);
74         }
75
76         idr_init(&iommu->pasid_idr);
77
78         return 0;
79 }
80
81 int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
82 {
83         int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
84
85         if (iommu->pasid_table) {
86                 free_pages((unsigned long)iommu->pasid_table, order);
87                 iommu->pasid_table = NULL;
88         }
89         if (iommu->pasid_state_table) {
90                 free_pages((unsigned long)iommu->pasid_state_table, order);
91                 iommu->pasid_state_table = NULL;
92         }
93         idr_destroy(&iommu->pasid_idr);
94         return 0;
95 }
96
97 #define PRQ_ORDER 0
98
99 int intel_svm_enable_prq(struct intel_iommu *iommu)
100 {
101         struct page *pages;
102         int irq, ret;
103
104         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
105         if (!pages) {
106                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
107                         iommu->name);
108                 return -ENOMEM;
109         }
110         iommu->prq = page_address(pages);
111
112         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
113         if (irq <= 0) {
114                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
115                        iommu->name);
116                 ret = -EINVAL;
117         err:
118                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
119                 iommu->prq = NULL;
120                 return ret;
121         }
122         iommu->pr_irq = irq;
123
124         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
125
126         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
127                                    iommu->prq_name, iommu);
128         if (ret) {
129                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
130                        iommu->name);
131                 dmar_free_hwirq(irq);
132                 goto err;
133         }
134         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
135         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
136         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
137
138         return 0;
139 }
140
141 int intel_svm_finish_prq(struct intel_iommu *iommu)
142 {
143         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
144         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
145         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
146
147         free_irq(iommu->pr_irq, iommu);
148         dmar_free_hwirq(iommu->pr_irq);
149         iommu->pr_irq = 0;
150
151         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
152         iommu->prq = NULL;
153
154         return 0;
155 }
156
157 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
158                                        unsigned long address, unsigned long pages, int ih, int gl)
159 {
160         struct qi_desc desc;
161
162         if (pages == -1) {
163                 /* For global kernel pages we have to flush them in *all* PASIDs
164                  * because that's the only option the hardware gives us. Despite
165                  * the fact that they are actually only accessible through one. */
166                 if (gl)
167                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
168                                 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE;
169                 else
170                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
171                                 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
172                 desc.high = 0;
173         } else {
174                 int mask = ilog2(__roundup_pow_of_two(pages));
175
176                 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
177                         QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
178                 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
179                         QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
180         }
181         qi_submit_sync(&desc, svm->iommu);
182
183         if (sdev->dev_iotlb) {
184                 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
185                         QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
186                 if (pages == -1) {
187                         desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
188                 } else if (pages > 1) {
189                         /* The least significant zero bit indicates the size. So,
190                          * for example, an "address" value of 0x12345f000 will
191                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
192                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
193                         unsigned long mask = __rounddown_pow_of_two(address ^ last);;
194
195                         desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
196                 } else {
197                         desc.high = QI_DEV_EIOTLB_ADDR(address);
198                 }
199                 qi_submit_sync(&desc, svm->iommu);
200         }
201 }
202
203 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
204                                   unsigned long pages, int ih, int gl)
205 {
206         struct intel_svm_dev *sdev;
207
208         /* Try deferred invalidate if available */
209         if (svm->iommu->pasid_state_table &&
210             !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
211                 return;
212
213         rcu_read_lock();
214         list_for_each_entry_rcu(sdev, &svm->devs, list)
215                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
216         rcu_read_unlock();
217 }
218
219 static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
220                              unsigned long address, pte_t pte)
221 {
222         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
223
224         intel_flush_svm_range(svm, address, 1, 1, 0);
225 }
226
227 /* Pages have been freed at this point */
228 static void intel_invalidate_range(struct mmu_notifier *mn,
229                                    struct mm_struct *mm,
230                                    unsigned long start, unsigned long end)
231 {
232         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
233
234         intel_flush_svm_range(svm, start,
235                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
236 }
237
238
239 static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid)
240 {
241         struct qi_desc desc;
242
243         desc.high = 0;
244         desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
245
246         qi_submit_sync(&desc, svm->iommu);
247 }
248
249 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
250 {
251         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
252         struct intel_svm_dev *sdev;
253
254         /* This might end up being called from exit_mmap(), *before* the page
255          * tables are cleared. And __mmu_notifier_release() will delete us from
256          * the list of notifiers so that our invalidate_range() callback doesn't
257          * get called when the page tables are cleared. So we need to protect
258          * against hardware accessing those page tables.
259          *
260          * We do it by clearing the entry in the PASID table and then flushing
261          * the IOTLB and the PASID table caches. This might upset hardware;
262          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
263          * page) so that we end up taking a fault that the hardware really
264          * *has* to handle gracefully without affecting other processes.
265          */
266         svm->iommu->pasid_table[svm->pasid].val = 0;
267         wmb();
268
269         rcu_read_lock();
270         list_for_each_entry_rcu(sdev, &svm->devs, list) {
271                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
272                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
273         }
274         rcu_read_unlock();
275
276 }
277
278 static const struct mmu_notifier_ops intel_mmuops = {
279         .flags = MMU_INVALIDATE_DOES_NOT_BLOCK,
280         .release = intel_mm_release,
281         .change_pte = intel_change_pte,
282         .invalidate_range = intel_invalidate_range,
283 };
284
285 static DEFINE_MUTEX(pasid_mutex);
286
287 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
288 {
289         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
290         struct intel_svm_dev *sdev;
291         struct intel_svm *svm = NULL;
292         struct mm_struct *mm = NULL;
293         int pasid_max;
294         int ret;
295
296         if (WARN_ON(!iommu || !iommu->pasid_table))
297                 return -EINVAL;
298
299         if (dev_is_pci(dev)) {
300                 pasid_max = pci_max_pasids(to_pci_dev(dev));
301                 if (pasid_max < 0)
302                         return -EINVAL;
303         } else
304                 pasid_max = 1 << 20;
305
306         if ((flags & SVM_FLAG_SUPERVISOR_MODE)) {
307                 if (!ecap_srs(iommu->ecap))
308                         return -EINVAL;
309         } else if (pasid) {
310                 mm = get_task_mm(current);
311                 BUG_ON(!mm);
312         }
313
314         mutex_lock(&pasid_mutex);
315         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
316                 int i;
317
318                 idr_for_each_entry(&iommu->pasid_idr, svm, i) {
319                         if (svm->mm != mm ||
320                             (svm->flags & SVM_FLAG_PRIVATE_PASID))
321                                 continue;
322
323                         if (svm->pasid >= pasid_max) {
324                                 dev_warn(dev,
325                                          "Limited PASID width. Cannot use existing PASID %d\n",
326                                          svm->pasid);
327                                 ret = -ENOSPC;
328                                 goto out;
329                         }
330
331                         list_for_each_entry(sdev, &svm->devs, list) {
332                                 if (dev == sdev->dev) {
333                                         if (sdev->ops != ops) {
334                                                 ret = -EBUSY;
335                                                 goto out;
336                                         }
337                                         sdev->users++;
338                                         goto success;
339                                 }
340                         }
341
342                         break;
343                 }
344         }
345
346         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
347         if (!sdev) {
348                 ret = -ENOMEM;
349                 goto out;
350         }
351         sdev->dev = dev;
352
353         ret = intel_iommu_enable_pasid(iommu, sdev);
354         if (ret || !pasid) {
355                 /* If they don't actually want to assign a PASID, this is
356                  * just an enabling check/preparation. */
357                 kfree(sdev);
358                 goto out;
359         }
360         /* Finish the setup now we know we're keeping it */
361         sdev->users = 1;
362         sdev->ops = ops;
363         init_rcu_head(&sdev->rcu);
364
365         if (!svm) {
366                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
367                 if (!svm) {
368                         ret = -ENOMEM;
369                         kfree(sdev);
370                         goto out;
371                 }
372                 svm->iommu = iommu;
373
374                 if (pasid_max > iommu->pasid_max)
375                         pasid_max = iommu->pasid_max;
376
377                 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
378                 ret = idr_alloc(&iommu->pasid_idr, svm,
379                                 !!cap_caching_mode(iommu->cap),
380                                 pasid_max - 1, GFP_KERNEL);
381                 if (ret < 0) {
382                         kfree(svm);
383                         goto out;
384                 }
385                 svm->pasid = ret;
386                 svm->notifier.ops = &intel_mmuops;
387                 svm->mm = mm;
388                 svm->flags = flags;
389                 INIT_LIST_HEAD_RCU(&svm->devs);
390                 ret = -ENOMEM;
391                 if (mm) {
392                         ret = mmu_notifier_register(&svm->notifier, mm);
393                         if (ret) {
394                                 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
395                                 kfree(svm);
396                                 kfree(sdev);
397                                 goto out;
398                         }
399                         iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1;
400                 } else
401                         iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11);
402                 wmb();
403                 /* In caching mode, we still have to flush with PASID 0 when
404                  * a PASID table entry becomes present. Not entirely clear
405                  * *why* that would be the case — surely we could just issue
406                  * a flush with the PASID value that we've changed? The PASID
407                  * is the index into the table, after all. It's not like domain
408                  * IDs in the case of the equivalent context-entry change in
409                  * caching mode. And for that matter it's not entirely clear why
410                  * a VMM would be in the business of caching the PASID table
411                  * anyway. Surely that can be left entirely to the guest? */
412                 if (cap_caching_mode(iommu->cap))
413                         intel_flush_pasid_dev(svm, sdev, 0);
414         }
415         list_add_rcu(&sdev->list, &svm->devs);
416
417  success:
418         *pasid = svm->pasid;
419         ret = 0;
420  out:
421         mutex_unlock(&pasid_mutex);
422         if (mm)
423                 mmput(mm);
424         return ret;
425 }
426 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
427
428 int intel_svm_unbind_mm(struct device *dev, int pasid)
429 {
430         struct intel_svm_dev *sdev;
431         struct intel_iommu *iommu;
432         struct intel_svm *svm;
433         int ret = -EINVAL;
434
435         mutex_lock(&pasid_mutex);
436         iommu = intel_svm_device_to_iommu(dev);
437         if (!iommu || !iommu->pasid_table)
438                 goto out;
439
440         svm = idr_find(&iommu->pasid_idr, pasid);
441         if (!svm)
442                 goto out;
443
444         list_for_each_entry(sdev, &svm->devs, list) {
445                 if (dev == sdev->dev) {
446                         ret = 0;
447                         sdev->users--;
448                         if (!sdev->users) {
449                                 list_del_rcu(&sdev->list);
450                                 /* Flush the PASID cache and IOTLB for this device.
451                                  * Note that we do depend on the hardware *not* using
452                                  * the PASID any more. Just as we depend on other
453                                  * devices never using PASIDs that they have no right
454                                  * to use. We have a *shared* PASID table, because it's
455                                  * large and has to be physically contiguous. So it's
456                                  * hard to be as defensive as we might like. */
457                                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
458                                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
459                                 kfree_rcu(sdev, rcu);
460
461                                 if (list_empty(&svm->devs)) {
462                                         svm->iommu->pasid_table[svm->pasid].val = 0;
463                                         wmb();
464
465                                         idr_remove(&svm->iommu->pasid_idr, svm->pasid);
466                                         if (svm->mm)
467                                                 mmu_notifier_unregister(&svm->notifier, svm->mm);
468
469                                         /* We mandate that no page faults may be outstanding
470                                          * for the PASID when intel_svm_unbind_mm() is called.
471                                          * If that is not obeyed, subtle errors will happen.
472                                          * Let's make them less subtle... */
473                                         memset(svm, 0x6b, sizeof(*svm));
474                                         kfree(svm);
475                                 }
476                         }
477                         break;
478                 }
479         }
480  out:
481         mutex_unlock(&pasid_mutex);
482
483         return ret;
484 }
485 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
486
487 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
488 {
489         struct intel_iommu *iommu;
490         struct intel_svm *svm;
491         int ret = -EINVAL;
492
493         mutex_lock(&pasid_mutex);
494         iommu = intel_svm_device_to_iommu(dev);
495         if (!iommu || !iommu->pasid_table)
496                 goto out;
497
498         svm = idr_find(&iommu->pasid_idr, pasid);
499         if (!svm)
500                 goto out;
501
502         /* init_mm is used in this case */
503         if (!svm->mm)
504                 ret = 1;
505         else if (atomic_read(&svm->mm->mm_users) > 0)
506                 ret = 1;
507         else
508                 ret = 0;
509
510  out:
511         mutex_unlock(&pasid_mutex);
512
513         return ret;
514 }
515 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
516
517 /* Page request queue descriptor */
518 struct page_req_dsc {
519         u64 srr:1;
520         u64 bof:1;
521         u64 pasid_present:1;
522         u64 lpig:1;
523         u64 pasid:20;
524         u64 bus:8;
525         u64 private:23;
526         u64 prg_index:9;
527         u64 rd_req:1;
528         u64 wr_req:1;
529         u64 exe_req:1;
530         u64 priv_req:1;
531         u64 devfn:8;
532         u64 addr:52;
533 };
534
535 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
536
537 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
538 {
539         unsigned long requested = 0;
540
541         if (req->exe_req)
542                 requested |= VM_EXEC;
543
544         if (req->rd_req)
545                 requested |= VM_READ;
546
547         if (req->wr_req)
548                 requested |= VM_WRITE;
549
550         return (requested & ~vma->vm_flags) != 0;
551 }
552
553 static bool is_canonical_address(u64 addr)
554 {
555         int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
556         long saddr = (long) addr;
557
558         return (((saddr << shift) >> shift) == saddr);
559 }
560
561 static irqreturn_t prq_event_thread(int irq, void *d)
562 {
563         struct intel_iommu *iommu = d;
564         struct intel_svm *svm = NULL;
565         int head, tail, handled = 0;
566
567         /* Clear PPR bit before reading head/tail registers, to
568          * ensure that we get a new interrupt if needed. */
569         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
570
571         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
572         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
573         while (head != tail) {
574                 struct intel_svm_dev *sdev;
575                 struct vm_area_struct *vma;
576                 struct page_req_dsc *req;
577                 struct qi_desc resp;
578                 int ret, result;
579                 u64 address;
580
581                 handled = 1;
582
583                 req = &iommu->prq[head / sizeof(*req)];
584
585                 result = QI_RESP_FAILURE;
586                 address = (u64)req->addr << VTD_PAGE_SHIFT;
587                 if (!req->pasid_present) {
588                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
589                                iommu->name, ((unsigned long long *)req)[0],
590                                ((unsigned long long *)req)[1]);
591                         goto bad_req;
592                 }
593
594                 if (!svm || svm->pasid != req->pasid) {
595                         rcu_read_lock();
596                         svm = idr_find(&iommu->pasid_idr, req->pasid);
597                         /* It *can't* go away, because the driver is not permitted
598                          * to unbind the mm while any page faults are outstanding.
599                          * So we only need RCU to protect the internal idr code. */
600                         rcu_read_unlock();
601
602                         if (!svm) {
603                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
604                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
605                                        ((unsigned long long *)req)[1]);
606                                 goto no_pasid;
607                         }
608                 }
609
610                 result = QI_RESP_INVALID;
611                 /* Since we're using init_mm.pgd directly, we should never take
612                  * any faults on kernel addresses. */
613                 if (!svm->mm)
614                         goto bad_req;
615                 /* If the mm is already defunct, don't handle faults. */
616                 if (!mmget_not_zero(svm->mm))
617                         goto bad_req;
618
619                 /* If address is not canonical, return invalid response */
620                 if (!is_canonical_address(address))
621                         goto bad_req;
622
623                 down_read(&svm->mm->mmap_sem);
624                 vma = find_extend_vma(svm->mm, address);
625                 if (!vma || address < vma->vm_start)
626                         goto invalid;
627
628                 if (access_error(vma, req))
629                         goto invalid;
630
631                 ret = handle_mm_fault(vma, address,
632                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
633                 if (ret & VM_FAULT_ERROR)
634                         goto invalid;
635
636                 result = QI_RESP_SUCCESS;
637         invalid:
638                 up_read(&svm->mm->mmap_sem);
639                 mmput(svm->mm);
640         bad_req:
641                 /* Accounting for major/minor faults? */
642                 rcu_read_lock();
643                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
644                         if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
645                                 break;
646                 }
647                 /* Other devices can go away, but the drivers are not permitted
648                  * to unbind while any page faults might be in flight. So it's
649                  * OK to drop the 'lock' here now we have it. */
650                 rcu_read_unlock();
651
652                 if (WARN_ON(&sdev->list == &svm->devs))
653                         sdev = NULL;
654
655                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
656                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
657                                 (req->exe_req << 1) | (req->priv_req);
658                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
659                 }
660                 /* We get here in the error case where the PASID lookup failed,
661                    and these can be NULL. Do not use them below this point! */
662                 sdev = NULL;
663                 svm = NULL;
664         no_pasid:
665                 if (req->lpig) {
666                         /* Page Group Response */
667                         resp.low = QI_PGRP_PASID(req->pasid) |
668                                 QI_PGRP_DID((req->bus << 8) | req->devfn) |
669                                 QI_PGRP_PASID_P(req->pasid_present) |
670                                 QI_PGRP_RESP_TYPE;
671                         resp.high = QI_PGRP_IDX(req->prg_index) |
672                                 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
673
674                         qi_submit_sync(&resp, iommu);
675                 } else if (req->srr) {
676                         /* Page Stream Response */
677                         resp.low = QI_PSTRM_IDX(req->prg_index) |
678                                 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
679                                 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
680                         resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
681                                 QI_PSTRM_RESP_CODE(result);
682
683                         qi_submit_sync(&resp, iommu);
684                 }
685
686                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
687         }
688
689         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
690
691         return IRQ_RETVAL(handled);
692 }