2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
57 #define AMD_IOMMU_MAPPING_ERROR 0
59 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61 #define LOOP_TIMEOUT 100000
63 /* IO virtual address start page frame number */
64 #define IOVA_START_PFN (1)
65 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
67 /* Reserved IOVA ranges */
68 #define MSI_RANGE_START (0xfee00000)
69 #define MSI_RANGE_END (0xfeefffff)
70 #define HT_RANGE_START (0xfd00000000ULL)
71 #define HT_RANGE_END (0xffffffffffULL)
74 * This bitmap is used to advertise the page sizes our hardware support
75 * to the IOMMU core, which will then use this information to split
76 * physically contiguous memory regions it is mapping into page sizes
79 * 512GB Pages are not supported due to a hardware bug
81 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
83 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
85 /* List of all available dev_data structures */
86 static LIST_HEAD(dev_data_list);
87 static DEFINE_SPINLOCK(dev_data_list_lock);
89 LIST_HEAD(ioapic_map);
91 LIST_HEAD(acpihid_map);
94 * Domain for untranslated devices - only allocated
95 * if iommu=pt passed on kernel cmd line.
97 const struct iommu_ops amd_iommu_ops;
99 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
100 int amd_iommu_max_glx_val = -1;
102 static const struct dma_map_ops amd_iommu_dma_ops;
105 * general struct to manage commands send to an IOMMU
111 struct kmem_cache *amd_iommu_irq_cache;
113 static void update_domain(struct protection_domain *domain);
114 static int protection_domain_init(struct protection_domain *domain);
115 static void detach_device(struct device *dev);
116 static void iova_domain_flush_tlb(struct iova_domain *iovad);
119 * Data container for a dma_ops specific protection domain
121 struct dma_ops_domain {
122 /* generic protection domain information */
123 struct protection_domain domain;
126 struct iova_domain iovad;
129 static struct iova_domain reserved_iova_ranges;
130 static struct lock_class_key reserved_rbtree_key;
132 /****************************************************************************
136 ****************************************************************************/
138 static inline int match_hid_uid(struct device *dev,
139 struct acpihid_map_entry *entry)
141 const char *hid, *uid;
143 hid = acpi_device_hid(ACPI_COMPANION(dev));
144 uid = acpi_device_uid(ACPI_COMPANION(dev));
150 return strcmp(hid, entry->hid);
153 return strcmp(hid, entry->hid);
155 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
158 static inline u16 get_pci_device_id(struct device *dev)
160 struct pci_dev *pdev = to_pci_dev(dev);
162 return PCI_DEVID(pdev->bus->number, pdev->devfn);
165 static inline int get_acpihid_device_id(struct device *dev,
166 struct acpihid_map_entry **entry)
168 struct acpihid_map_entry *p;
170 list_for_each_entry(p, &acpihid_map, list) {
171 if (!match_hid_uid(dev, p)) {
180 static inline int get_device_id(struct device *dev)
185 devid = get_pci_device_id(dev);
187 devid = get_acpihid_device_id(dev, NULL);
192 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
194 return container_of(dom, struct protection_domain, domain);
197 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
199 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
200 return container_of(domain, struct dma_ops_domain, domain);
203 static struct iommu_dev_data *alloc_dev_data(u16 devid)
205 struct iommu_dev_data *dev_data;
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
212 dev_data->devid = devid;
214 spin_lock_irqsave(&dev_data_list_lock, flags);
215 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
216 spin_unlock_irqrestore(&dev_data_list_lock, flags);
218 ratelimit_default_init(&dev_data->rs);
223 static struct iommu_dev_data *search_dev_data(u16 devid)
225 struct iommu_dev_data *dev_data;
228 spin_lock_irqsave(&dev_data_list_lock, flags);
229 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
230 if (dev_data->devid == devid)
237 spin_unlock_irqrestore(&dev_data_list_lock, flags);
242 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
244 *(u16 *)data = alias;
248 static u16 get_alias(struct device *dev)
250 struct pci_dev *pdev = to_pci_dev(dev);
251 u16 devid, ivrs_alias, pci_alias;
253 /* The callers make sure that get_device_id() does not fail here */
254 devid = get_device_id(dev);
255 ivrs_alias = amd_iommu_alias_table[devid];
256 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
258 if (ivrs_alias == pci_alias)
264 * The IVRS is fairly reliable in telling us about aliases, but it
265 * can't know about every screwy device. If we don't have an IVRS
266 * reported alias, use the PCI reported alias. In that case we may
267 * still need to initialize the rlookup and dev_table entries if the
268 * alias is to a non-existent device.
270 if (ivrs_alias == devid) {
271 if (!amd_iommu_rlookup_table[pci_alias]) {
272 amd_iommu_rlookup_table[pci_alias] =
273 amd_iommu_rlookup_table[devid];
274 memcpy(amd_iommu_dev_table[pci_alias].data,
275 amd_iommu_dev_table[devid].data,
276 sizeof(amd_iommu_dev_table[pci_alias].data));
282 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
283 "for device %s[%04x:%04x], kernel reported alias "
284 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
285 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
286 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
287 PCI_FUNC(pci_alias));
290 * If we don't have a PCI DMA alias and the IVRS alias is on the same
291 * bus, then the IVRS table may know about a quirk that we don't.
293 if (pci_alias == devid &&
294 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
295 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
296 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
297 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
304 static struct iommu_dev_data *find_dev_data(u16 devid)
306 struct iommu_dev_data *dev_data;
307 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
309 dev_data = search_dev_data(devid);
311 if (dev_data == NULL) {
312 dev_data = alloc_dev_data(devid);
314 if (translation_pre_enabled(iommu))
315 dev_data->defer_attach = true;
321 struct iommu_dev_data *get_dev_data(struct device *dev)
323 return dev->archdata.iommu;
325 EXPORT_SYMBOL(get_dev_data);
328 * Find or create an IOMMU group for a acpihid device.
330 static struct iommu_group *acpihid_device_group(struct device *dev)
332 struct acpihid_map_entry *p, *entry = NULL;
335 devid = get_acpihid_device_id(dev, &entry);
337 return ERR_PTR(devid);
339 list_for_each_entry(p, &acpihid_map, list) {
340 if ((devid == p->devid) && p->group)
341 entry->group = p->group;
345 entry->group = generic_device_group(dev);
347 iommu_group_ref_get(entry->group);
352 static bool pci_iommuv2_capable(struct pci_dev *pdev)
354 static const int caps[] = {
357 PCI_EXT_CAP_ID_PASID,
361 for (i = 0; i < 3; ++i) {
362 pos = pci_find_ext_capability(pdev, caps[i]);
370 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
372 struct iommu_dev_data *dev_data;
374 dev_data = get_dev_data(&pdev->dev);
376 return dev_data->errata & (1 << erratum) ? true : false;
380 * This function checks if the driver got a valid device from the caller to
381 * avoid dereferencing invalid pointers.
383 static bool check_device(struct device *dev)
387 if (!dev || !dev->dma_mask)
390 devid = get_device_id(dev);
394 /* Out of our scope? */
395 if (devid > amd_iommu_last_bdf)
398 if (amd_iommu_rlookup_table[devid] == NULL)
404 static void init_iommu_group(struct device *dev)
406 struct iommu_group *group;
408 group = iommu_group_get_for_dev(dev);
412 iommu_group_put(group);
415 static int iommu_init_device(struct device *dev)
417 struct iommu_dev_data *dev_data;
418 struct amd_iommu *iommu;
421 if (dev->archdata.iommu)
424 devid = get_device_id(dev);
428 iommu = amd_iommu_rlookup_table[devid];
430 dev_data = find_dev_data(devid);
434 dev_data->alias = get_alias(dev);
436 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
437 struct amd_iommu *iommu;
439 iommu = amd_iommu_rlookup_table[dev_data->devid];
440 dev_data->iommu_v2 = iommu->is_iommu_v2;
443 dev->archdata.iommu = dev_data;
445 iommu_device_link(&iommu->iommu, dev);
450 static void iommu_ignore_device(struct device *dev)
455 devid = get_device_id(dev);
459 alias = get_alias(dev);
461 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
462 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
464 amd_iommu_rlookup_table[devid] = NULL;
465 amd_iommu_rlookup_table[alias] = NULL;
468 static void iommu_uninit_device(struct device *dev)
470 struct iommu_dev_data *dev_data;
471 struct amd_iommu *iommu;
474 devid = get_device_id(dev);
478 iommu = amd_iommu_rlookup_table[devid];
480 dev_data = search_dev_data(devid);
484 if (dev_data->domain)
487 iommu_device_unlink(&iommu->iommu, dev);
489 iommu_group_remove_device(dev);
495 * We keep dev_data around for unplugged devices and reuse it when the
496 * device is re-plugged - not doing so would introduce a ton of races.
500 /****************************************************************************
502 * Interrupt handling functions
504 ****************************************************************************/
506 static void dump_dte_entry(u16 devid)
510 for (i = 0; i < 4; ++i)
511 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
512 amd_iommu_dev_table[devid].data[i]);
515 static void dump_command(unsigned long phys_addr)
517 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
520 for (i = 0; i < 4; ++i)
521 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
524 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
525 u64 address, int flags)
527 struct iommu_dev_data *dev_data = NULL;
528 struct pci_dev *pdev;
530 pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
532 dev_data = get_dev_data(&pdev->dev);
534 if (dev_data && __ratelimit(&dev_data->rs)) {
535 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
536 domain_id, address, flags);
537 } else if (printk_ratelimit()) {
538 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
539 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
540 domain_id, address, flags);
547 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
549 int type, devid, domid, flags;
550 volatile u32 *event = __evt;
555 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
556 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
557 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
558 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
559 address = (u64)(((u64)event[3]) << 32) | event[2];
562 /* Did we hit the erratum? */
563 if (++count == LOOP_TIMEOUT) {
564 pr_err("AMD-Vi: No event written to event log\n");
571 if (type == EVENT_TYPE_IO_FAULT) {
572 amd_iommu_report_page_fault(devid, domid, address, flags);
575 printk(KERN_ERR "AMD-Vi: Event logged [");
579 case EVENT_TYPE_ILL_DEV:
580 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
581 "address=0x%016llx flags=0x%04x]\n",
582 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
584 dump_dte_entry(devid);
586 case EVENT_TYPE_DEV_TAB_ERR:
587 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
588 "address=0x%016llx flags=0x%04x]\n",
589 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
592 case EVENT_TYPE_PAGE_TAB_ERR:
593 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
594 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
595 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
596 domid, address, flags);
598 case EVENT_TYPE_ILL_CMD:
599 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
600 dump_command(address);
602 case EVENT_TYPE_CMD_HARD_ERR:
603 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
604 "flags=0x%04x]\n", address, flags);
606 case EVENT_TYPE_IOTLB_INV_TO:
607 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
608 "address=0x%016llx]\n",
609 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
612 case EVENT_TYPE_INV_DEV_REQ:
613 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
614 "address=0x%016llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
619 printk(KERN_ERR "UNKNOWN type=0x%02x event[0]=0x%08x "
620 "event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
621 type, event[0], event[1], event[2], event[3]);
624 memset(__evt, 0, 4 * sizeof(u32));
627 static void iommu_poll_events(struct amd_iommu *iommu)
631 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
632 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
634 while (head != tail) {
635 iommu_print_event(iommu, iommu->evt_buf + head);
636 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
639 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
642 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
644 struct amd_iommu_fault fault;
646 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
647 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
651 fault.address = raw[1];
652 fault.pasid = PPR_PASID(raw[0]);
653 fault.device_id = PPR_DEVID(raw[0]);
654 fault.tag = PPR_TAG(raw[0]);
655 fault.flags = PPR_FLAGS(raw[0]);
657 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
660 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
664 if (iommu->ppr_log == NULL)
667 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
668 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
670 while (head != tail) {
675 raw = (u64 *)(iommu->ppr_log + head);
678 * Hardware bug: Interrupt may arrive before the entry is
679 * written to memory. If this happens we need to wait for the
682 for (i = 0; i < LOOP_TIMEOUT; ++i) {
683 if (PPR_REQ_TYPE(raw[0]) != 0)
688 /* Avoid memcpy function-call overhead */
693 * To detect the hardware bug we need to clear the entry
696 raw[0] = raw[1] = 0UL;
698 /* Update head pointer of hardware ring-buffer */
699 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
700 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
702 /* Handle PPR entry */
703 iommu_handle_ppr_entry(iommu, entry);
705 /* Refresh ring-buffer information */
706 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
707 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
711 #ifdef CONFIG_IRQ_REMAP
712 static int (*iommu_ga_log_notifier)(u32);
714 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
716 iommu_ga_log_notifier = notifier;
720 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
722 static void iommu_poll_ga_log(struct amd_iommu *iommu)
724 u32 head, tail, cnt = 0;
726 if (iommu->ga_log == NULL)
729 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
730 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
732 while (head != tail) {
736 raw = (u64 *)(iommu->ga_log + head);
739 /* Avoid memcpy function-call overhead */
742 /* Update head pointer of hardware ring-buffer */
743 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
744 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
746 /* Handle GA entry */
747 switch (GA_REQ_TYPE(log_entry)) {
749 if (!iommu_ga_log_notifier)
752 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
753 __func__, GA_DEVID(log_entry),
756 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
757 pr_err("AMD-Vi: GA log notifier failed.\n");
764 #endif /* CONFIG_IRQ_REMAP */
766 #define AMD_IOMMU_INT_MASK \
767 (MMIO_STATUS_EVT_INT_MASK | \
768 MMIO_STATUS_PPR_INT_MASK | \
769 MMIO_STATUS_GALOG_INT_MASK)
771 irqreturn_t amd_iommu_int_thread(int irq, void *data)
773 struct amd_iommu *iommu = (struct amd_iommu *) data;
774 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
776 while (status & AMD_IOMMU_INT_MASK) {
777 /* Enable EVT and PPR and GA interrupts again */
778 writel(AMD_IOMMU_INT_MASK,
779 iommu->mmio_base + MMIO_STATUS_OFFSET);
781 if (status & MMIO_STATUS_EVT_INT_MASK) {
782 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
783 iommu_poll_events(iommu);
786 if (status & MMIO_STATUS_PPR_INT_MASK) {
787 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
788 iommu_poll_ppr_log(iommu);
791 #ifdef CONFIG_IRQ_REMAP
792 if (status & MMIO_STATUS_GALOG_INT_MASK) {
793 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
794 iommu_poll_ga_log(iommu);
799 * Hardware bug: ERBT1312
800 * When re-enabling interrupt (by writing 1
801 * to clear the bit), the hardware might also try to set
802 * the interrupt bit in the event status register.
803 * In this scenario, the bit will be set, and disable
804 * subsequent interrupts.
806 * Workaround: The IOMMU driver should read back the
807 * status register and check if the interrupt bits are cleared.
808 * If not, driver will need to go through the interrupt handler
809 * again and re-clear the bits
811 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
816 irqreturn_t amd_iommu_int_handler(int irq, void *data)
818 return IRQ_WAKE_THREAD;
821 /****************************************************************************
823 * IOMMU command queuing functions
825 ****************************************************************************/
827 static int wait_on_sem(volatile u64 *sem)
831 while (*sem == 0 && i < LOOP_TIMEOUT) {
836 if (i == LOOP_TIMEOUT) {
837 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
844 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
845 struct iommu_cmd *cmd)
849 target = iommu->cmd_buf + iommu->cmd_buf_tail;
851 iommu->cmd_buf_tail += sizeof(*cmd);
852 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
854 /* Copy command to buffer */
855 memcpy(target, cmd, sizeof(*cmd));
857 /* Tell the IOMMU about it */
858 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
861 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
863 u64 paddr = iommu_virt_to_phys((void *)address);
865 WARN_ON(address & 0x7ULL);
867 memset(cmd, 0, sizeof(*cmd));
868 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
869 cmd->data[1] = upper_32_bits(paddr);
871 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
874 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
876 memset(cmd, 0, sizeof(*cmd));
877 cmd->data[0] = devid;
878 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
881 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
882 size_t size, u16 domid, int pde)
887 pages = iommu_num_pages(address, size, PAGE_SIZE);
892 * If we have to flush more than one page, flush all
893 * TLB entries for this domain
895 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
899 address &= PAGE_MASK;
901 memset(cmd, 0, sizeof(*cmd));
902 cmd->data[1] |= domid;
903 cmd->data[2] = lower_32_bits(address);
904 cmd->data[3] = upper_32_bits(address);
905 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
906 if (s) /* size bit - we flush more than one 4kb page */
907 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
908 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
909 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
912 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
913 u64 address, size_t size)
918 pages = iommu_num_pages(address, size, PAGE_SIZE);
923 * If we have to flush more than one page, flush all
924 * TLB entries for this domain
926 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
930 address &= PAGE_MASK;
932 memset(cmd, 0, sizeof(*cmd));
933 cmd->data[0] = devid;
934 cmd->data[0] |= (qdep & 0xff) << 24;
935 cmd->data[1] = devid;
936 cmd->data[2] = lower_32_bits(address);
937 cmd->data[3] = upper_32_bits(address);
938 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
940 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
943 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
944 u64 address, bool size)
946 memset(cmd, 0, sizeof(*cmd));
948 address &= ~(0xfffULL);
950 cmd->data[0] = pasid;
951 cmd->data[1] = domid;
952 cmd->data[2] = lower_32_bits(address);
953 cmd->data[3] = upper_32_bits(address);
954 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
955 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
957 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
958 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
961 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
962 int qdep, u64 address, bool size)
964 memset(cmd, 0, sizeof(*cmd));
966 address &= ~(0xfffULL);
968 cmd->data[0] = devid;
969 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
970 cmd->data[0] |= (qdep & 0xff) << 24;
971 cmd->data[1] = devid;
972 cmd->data[1] |= (pasid & 0xff) << 16;
973 cmd->data[2] = lower_32_bits(address);
974 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
975 cmd->data[3] = upper_32_bits(address);
977 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
978 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
981 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
982 int status, int tag, bool gn)
984 memset(cmd, 0, sizeof(*cmd));
986 cmd->data[0] = devid;
988 cmd->data[1] = pasid;
989 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
991 cmd->data[3] = tag & 0x1ff;
992 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
994 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
997 static void build_inv_all(struct iommu_cmd *cmd)
999 memset(cmd, 0, sizeof(*cmd));
1000 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1003 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1005 memset(cmd, 0, sizeof(*cmd));
1006 cmd->data[0] = devid;
1007 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1011 * Writes the command to the IOMMUs command buffer and informs the
1012 * hardware about the new command.
1014 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1015 struct iommu_cmd *cmd,
1018 unsigned int count = 0;
1019 u32 left, next_tail;
1021 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1023 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1026 /* Skip udelay() the first time around */
1028 if (count == LOOP_TIMEOUT) {
1029 pr_err("AMD-Vi: Command buffer timeout\n");
1036 /* Update head and recheck remaining space */
1037 iommu->cmd_buf_head = readl(iommu->mmio_base +
1038 MMIO_CMD_HEAD_OFFSET);
1043 copy_cmd_to_buffer(iommu, cmd);
1045 /* Do we need to make sure all commands are processed? */
1046 iommu->need_sync = sync;
1051 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1052 struct iommu_cmd *cmd,
1055 unsigned long flags;
1058 spin_lock_irqsave(&iommu->lock, flags);
1059 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1060 spin_unlock_irqrestore(&iommu->lock, flags);
1065 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1067 return iommu_queue_command_sync(iommu, cmd, true);
1071 * This function queues a completion wait command into the command
1072 * buffer of an IOMMU
1074 static int iommu_completion_wait(struct amd_iommu *iommu)
1076 struct iommu_cmd cmd;
1077 unsigned long flags;
1080 if (!iommu->need_sync)
1084 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1086 spin_lock_irqsave(&iommu->lock, flags);
1090 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1094 ret = wait_on_sem(&iommu->cmd_sem);
1097 spin_unlock_irqrestore(&iommu->lock, flags);
1102 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1104 struct iommu_cmd cmd;
1106 build_inv_dte(&cmd, devid);
1108 return iommu_queue_command(iommu, &cmd);
1111 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1115 for (devid = 0; devid <= 0xffff; ++devid)
1116 iommu_flush_dte(iommu, devid);
1118 iommu_completion_wait(iommu);
1122 * This function uses heavy locking and may disable irqs for some time. But
1123 * this is no issue because it is only called during resume.
1125 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1129 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1130 struct iommu_cmd cmd;
1131 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1133 iommu_queue_command(iommu, &cmd);
1136 iommu_completion_wait(iommu);
1139 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1141 struct iommu_cmd cmd;
1143 build_inv_all(&cmd);
1145 iommu_queue_command(iommu, &cmd);
1146 iommu_completion_wait(iommu);
1149 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1151 struct iommu_cmd cmd;
1153 build_inv_irt(&cmd, devid);
1155 iommu_queue_command(iommu, &cmd);
1158 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1162 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1163 iommu_flush_irt(iommu, devid);
1165 iommu_completion_wait(iommu);
1168 void iommu_flush_all_caches(struct amd_iommu *iommu)
1170 if (iommu_feature(iommu, FEATURE_IA)) {
1171 amd_iommu_flush_all(iommu);
1173 amd_iommu_flush_dte_all(iommu);
1174 amd_iommu_flush_irt_all(iommu);
1175 amd_iommu_flush_tlb_all(iommu);
1180 * Command send function for flushing on-device TLB
1182 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1183 u64 address, size_t size)
1185 struct amd_iommu *iommu;
1186 struct iommu_cmd cmd;
1189 qdep = dev_data->ats.qdep;
1190 iommu = amd_iommu_rlookup_table[dev_data->devid];
1192 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1194 return iommu_queue_command(iommu, &cmd);
1198 * Command send function for invalidating a device table entry
1200 static int device_flush_dte(struct iommu_dev_data *dev_data)
1202 struct amd_iommu *iommu;
1206 iommu = amd_iommu_rlookup_table[dev_data->devid];
1207 alias = dev_data->alias;
1209 ret = iommu_flush_dte(iommu, dev_data->devid);
1210 if (!ret && alias != dev_data->devid)
1211 ret = iommu_flush_dte(iommu, alias);
1215 if (dev_data->ats.enabled)
1216 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1222 * TLB invalidation function which is called from the mapping functions.
1223 * It invalidates a single PTE if the range to flush is within a single
1224 * page. Otherwise it flushes the whole TLB of the IOMMU.
1226 static void __domain_flush_pages(struct protection_domain *domain,
1227 u64 address, size_t size, int pde)
1229 struct iommu_dev_data *dev_data;
1230 struct iommu_cmd cmd;
1233 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1235 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1236 if (!domain->dev_iommu[i])
1240 * Devices of this domain are behind this IOMMU
1241 * We need a TLB flush
1243 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1246 list_for_each_entry(dev_data, &domain->dev_list, list) {
1248 if (!dev_data->ats.enabled)
1251 ret |= device_flush_iotlb(dev_data, address, size);
1257 static void domain_flush_pages(struct protection_domain *domain,
1258 u64 address, size_t size)
1260 __domain_flush_pages(domain, address, size, 0);
1263 /* Flush the whole IO/TLB for a given protection domain */
1264 static void domain_flush_tlb(struct protection_domain *domain)
1266 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1269 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1270 static void domain_flush_tlb_pde(struct protection_domain *domain)
1272 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1275 static void domain_flush_complete(struct protection_domain *domain)
1279 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1280 if (domain && !domain->dev_iommu[i])
1284 * Devices of this domain are behind this IOMMU
1285 * We need to wait for completion of all commands.
1287 iommu_completion_wait(amd_iommus[i]);
1293 * This function flushes the DTEs for all devices in domain
1295 static void domain_flush_devices(struct protection_domain *domain)
1297 struct iommu_dev_data *dev_data;
1299 list_for_each_entry(dev_data, &domain->dev_list, list)
1300 device_flush_dte(dev_data);
1303 /****************************************************************************
1305 * The functions below are used the create the page table mappings for
1306 * unity mapped regions.
1308 ****************************************************************************/
1311 * This function is used to add another level to an IO page table. Adding
1312 * another level increases the size of the address space by 9 bits to a size up
1315 static bool increase_address_space(struct protection_domain *domain,
1320 if (domain->mode == PAGE_MODE_6_LEVEL)
1321 /* address space already 64 bit large */
1324 pte = (void *)get_zeroed_page(gfp);
1328 *pte = PM_LEVEL_PDE(domain->mode,
1329 iommu_virt_to_phys(domain->pt_root));
1330 domain->pt_root = pte;
1332 domain->updated = true;
1337 static u64 *alloc_pte(struct protection_domain *domain,
1338 unsigned long address,
1339 unsigned long page_size,
1346 BUG_ON(!is_power_of_2(page_size));
1348 while (address > PM_LEVEL_SIZE(domain->mode))
1349 increase_address_space(domain, gfp);
1351 level = domain->mode - 1;
1352 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1353 address = PAGE_SIZE_ALIGN(address, page_size);
1354 end_lvl = PAGE_SIZE_LEVEL(page_size);
1356 while (level > end_lvl) {
1361 if (!IOMMU_PTE_PRESENT(__pte)) {
1362 page = (u64 *)get_zeroed_page(gfp);
1366 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1368 /* pte could have been changed somewhere. */
1369 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1370 free_page((unsigned long)page);
1375 /* No level skipping support yet */
1376 if (PM_PTE_LEVEL(*pte) != level)
1381 pte = IOMMU_PTE_PAGE(*pte);
1383 if (pte_page && level == end_lvl)
1386 pte = &pte[PM_LEVEL_INDEX(level, address)];
1393 * This function checks if there is a PTE for a given dma address. If
1394 * there is one, it returns the pointer to it.
1396 static u64 *fetch_pte(struct protection_domain *domain,
1397 unsigned long address,
1398 unsigned long *page_size)
1403 if (address > PM_LEVEL_SIZE(domain->mode))
1406 level = domain->mode - 1;
1407 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1408 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1413 if (!IOMMU_PTE_PRESENT(*pte))
1417 if (PM_PTE_LEVEL(*pte) == 7 ||
1418 PM_PTE_LEVEL(*pte) == 0)
1421 /* No level skipping support yet */
1422 if (PM_PTE_LEVEL(*pte) != level)
1427 /* Walk to the next level */
1428 pte = IOMMU_PTE_PAGE(*pte);
1429 pte = &pte[PM_LEVEL_INDEX(level, address)];
1430 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1433 if (PM_PTE_LEVEL(*pte) == 0x07) {
1434 unsigned long pte_mask;
1437 * If we have a series of large PTEs, make
1438 * sure to return a pointer to the first one.
1440 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1441 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1442 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1449 * Generic mapping functions. It maps a physical address into a DMA
1450 * address space. It allocates the page table pages if necessary.
1451 * In the future it can be extended to a generic mapping function
1452 * supporting all features of AMD IOMMU page tables like level skipping
1453 * and full 64 bit address spaces.
1455 static int iommu_map_page(struct protection_domain *dom,
1456 unsigned long bus_addr,
1457 unsigned long phys_addr,
1458 unsigned long page_size,
1465 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1466 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1468 if (!(prot & IOMMU_PROT_MASK))
1471 count = PAGE_SIZE_PTE_COUNT(page_size);
1472 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1477 for (i = 0; i < count; ++i)
1478 if (IOMMU_PTE_PRESENT(pte[i]))
1482 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1483 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1485 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1487 if (prot & IOMMU_PROT_IR)
1488 __pte |= IOMMU_PTE_IR;
1489 if (prot & IOMMU_PROT_IW)
1490 __pte |= IOMMU_PTE_IW;
1492 for (i = 0; i < count; ++i)
1500 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1501 unsigned long bus_addr,
1502 unsigned long page_size)
1504 unsigned long long unmapped;
1505 unsigned long unmap_size;
1508 BUG_ON(!is_power_of_2(page_size));
1512 while (unmapped < page_size) {
1514 pte = fetch_pte(dom, bus_addr, &unmap_size);
1519 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1520 for (i = 0; i < count; i++)
1524 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1525 unmapped += unmap_size;
1528 BUG_ON(unmapped && !is_power_of_2(unmapped));
1533 /****************************************************************************
1535 * The next functions belong to the address allocator for the dma_ops
1536 * interface functions.
1538 ****************************************************************************/
1541 static unsigned long dma_ops_alloc_iova(struct device *dev,
1542 struct dma_ops_domain *dma_dom,
1543 unsigned int pages, u64 dma_mask)
1545 unsigned long pfn = 0;
1547 pages = __roundup_pow_of_two(pages);
1549 if (dma_mask > DMA_BIT_MASK(32))
1550 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1551 IOVA_PFN(DMA_BIT_MASK(32)), false);
1554 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1555 IOVA_PFN(dma_mask), true);
1557 return (pfn << PAGE_SHIFT);
1560 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1561 unsigned long address,
1564 pages = __roundup_pow_of_two(pages);
1565 address >>= PAGE_SHIFT;
1567 free_iova_fast(&dma_dom->iovad, address, pages);
1570 /****************************************************************************
1572 * The next functions belong to the domain allocation. A domain is
1573 * allocated for every IOMMU as the default domain. If device isolation
1574 * is enabled, every device get its own domain. The most important thing
1575 * about domains is the page table mapping the DMA address space they
1578 ****************************************************************************/
1581 * This function adds a protection domain to the global protection domain list
1583 static void add_domain_to_list(struct protection_domain *domain)
1585 unsigned long flags;
1587 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1588 list_add(&domain->list, &amd_iommu_pd_list);
1589 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1593 * This function removes a protection domain to the global
1594 * protection domain list
1596 static void del_domain_from_list(struct protection_domain *domain)
1598 unsigned long flags;
1600 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1601 list_del(&domain->list);
1602 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1605 static u16 domain_id_alloc(void)
1607 unsigned long flags;
1610 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1611 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1613 if (id > 0 && id < MAX_DOMAIN_ID)
1614 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1617 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1622 static void domain_id_free(int id)
1624 unsigned long flags;
1626 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1627 if (id > 0 && id < MAX_DOMAIN_ID)
1628 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1629 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1632 #define DEFINE_FREE_PT_FN(LVL, FN) \
1633 static void free_pt_##LVL (unsigned long __pt) \
1641 for (i = 0; i < 512; ++i) { \
1642 /* PTE present? */ \
1643 if (!IOMMU_PTE_PRESENT(pt[i])) \
1647 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1648 PM_PTE_LEVEL(pt[i]) == 7) \
1651 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1654 free_page((unsigned long)pt); \
1657 DEFINE_FREE_PT_FN(l2, free_page)
1658 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1659 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1660 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1661 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1663 static void free_pagetable(struct protection_domain *domain)
1665 unsigned long root = (unsigned long)domain->pt_root;
1667 switch (domain->mode) {
1668 case PAGE_MODE_NONE:
1670 case PAGE_MODE_1_LEVEL:
1673 case PAGE_MODE_2_LEVEL:
1676 case PAGE_MODE_3_LEVEL:
1679 case PAGE_MODE_4_LEVEL:
1682 case PAGE_MODE_5_LEVEL:
1685 case PAGE_MODE_6_LEVEL:
1693 static void free_gcr3_tbl_level1(u64 *tbl)
1698 for (i = 0; i < 512; ++i) {
1699 if (!(tbl[i] & GCR3_VALID))
1702 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1704 free_page((unsigned long)ptr);
1708 static void free_gcr3_tbl_level2(u64 *tbl)
1713 for (i = 0; i < 512; ++i) {
1714 if (!(tbl[i] & GCR3_VALID))
1717 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1719 free_gcr3_tbl_level1(ptr);
1723 static void free_gcr3_table(struct protection_domain *domain)
1725 if (domain->glx == 2)
1726 free_gcr3_tbl_level2(domain->gcr3_tbl);
1727 else if (domain->glx == 1)
1728 free_gcr3_tbl_level1(domain->gcr3_tbl);
1730 BUG_ON(domain->glx != 0);
1732 free_page((unsigned long)domain->gcr3_tbl);
1735 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1737 domain_flush_tlb(&dom->domain);
1738 domain_flush_complete(&dom->domain);
1741 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1743 struct dma_ops_domain *dom;
1745 dom = container_of(iovad, struct dma_ops_domain, iovad);
1747 dma_ops_domain_flush_tlb(dom);
1751 * Free a domain, only used if something went wrong in the
1752 * allocation path and we need to free an already allocated page table
1754 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1759 del_domain_from_list(&dom->domain);
1761 put_iova_domain(&dom->iovad);
1763 free_pagetable(&dom->domain);
1766 domain_id_free(dom->domain.id);
1772 * Allocates a new protection domain usable for the dma_ops functions.
1773 * It also initializes the page table and the address allocator data
1774 * structures required for the dma_ops interface
1776 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1778 struct dma_ops_domain *dma_dom;
1780 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1784 if (protection_domain_init(&dma_dom->domain))
1787 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1788 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1789 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1790 if (!dma_dom->domain.pt_root)
1793 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1795 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1798 /* Initialize reserved ranges */
1799 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1801 add_domain_to_list(&dma_dom->domain);
1806 dma_ops_domain_free(dma_dom);
1812 * little helper function to check whether a given protection domain is a
1815 static bool dma_ops_domain(struct protection_domain *domain)
1817 return domain->flags & PD_DMA_OPS_MASK;
1820 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1826 if (domain->mode != PAGE_MODE_NONE)
1827 pte_root = iommu_virt_to_phys(domain->pt_root);
1829 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1830 << DEV_ENTRY_MODE_SHIFT;
1831 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1833 flags = amd_iommu_dev_table[devid].data[1];
1836 flags |= DTE_FLAG_IOTLB;
1839 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1841 if (iommu_feature(iommu, FEATURE_EPHSUP))
1842 pte_root |= 1ULL << DEV_ENTRY_PPR;
1845 if (domain->flags & PD_IOMMUV2_MASK) {
1846 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1847 u64 glx = domain->glx;
1850 pte_root |= DTE_FLAG_GV;
1851 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1853 /* First mask out possible old values for GCR3 table */
1854 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1857 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1860 /* Encode GCR3 table into DTE */
1861 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1864 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1867 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1871 flags &= ~DEV_DOMID_MASK;
1872 flags |= domain->id;
1874 amd_iommu_dev_table[devid].data[1] = flags;
1875 amd_iommu_dev_table[devid].data[0] = pte_root;
1878 static void clear_dte_entry(u16 devid)
1880 /* remove entry from the device table seen by the hardware */
1881 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1882 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1884 amd_iommu_apply_erratum_63(devid);
1887 static void do_attach(struct iommu_dev_data *dev_data,
1888 struct protection_domain *domain)
1890 struct amd_iommu *iommu;
1894 iommu = amd_iommu_rlookup_table[dev_data->devid];
1895 alias = dev_data->alias;
1896 ats = dev_data->ats.enabled;
1898 /* Update data structures */
1899 dev_data->domain = domain;
1900 list_add(&dev_data->list, &domain->dev_list);
1902 /* Do reference counting */
1903 domain->dev_iommu[iommu->index] += 1;
1904 domain->dev_cnt += 1;
1906 /* Update device table */
1907 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1908 if (alias != dev_data->devid)
1909 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1911 device_flush_dte(dev_data);
1914 static void do_detach(struct iommu_dev_data *dev_data)
1916 struct amd_iommu *iommu;
1920 * First check if the device is still attached. It might already
1921 * be detached from its domain because the generic
1922 * iommu_detach_group code detached it and we try again here in
1923 * our alias handling.
1925 if (!dev_data->domain)
1928 iommu = amd_iommu_rlookup_table[dev_data->devid];
1929 alias = dev_data->alias;
1931 /* decrease reference counters */
1932 dev_data->domain->dev_iommu[iommu->index] -= 1;
1933 dev_data->domain->dev_cnt -= 1;
1935 /* Update data structures */
1936 dev_data->domain = NULL;
1937 list_del(&dev_data->list);
1938 clear_dte_entry(dev_data->devid);
1939 if (alias != dev_data->devid)
1940 clear_dte_entry(alias);
1942 /* Flush the DTE entry */
1943 device_flush_dte(dev_data);
1947 * If a device is not yet associated with a domain, this function does
1948 * assigns it visible for the hardware
1950 static int __attach_device(struct iommu_dev_data *dev_data,
1951 struct protection_domain *domain)
1956 * Must be called with IRQs disabled. Warn here to detect early
1959 WARN_ON(!irqs_disabled());
1962 spin_lock(&domain->lock);
1965 if (dev_data->domain != NULL)
1968 /* Attach alias group root */
1969 do_attach(dev_data, domain);
1976 spin_unlock(&domain->lock);
1982 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1984 pci_disable_ats(pdev);
1985 pci_disable_pri(pdev);
1986 pci_disable_pasid(pdev);
1989 /* FIXME: Change generic reset-function to do the same */
1990 static int pri_reset_while_enabled(struct pci_dev *pdev)
1995 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1999 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2000 control |= PCI_PRI_CTRL_RESET;
2001 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2006 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2011 /* FIXME: Hardcode number of outstanding requests for now */
2013 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2015 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2017 /* Only allow access to user-accessible pages */
2018 ret = pci_enable_pasid(pdev, 0);
2022 /* First reset the PRI state of the device */
2023 ret = pci_reset_pri(pdev);
2028 ret = pci_enable_pri(pdev, reqs);
2033 ret = pri_reset_while_enabled(pdev);
2038 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2045 pci_disable_pri(pdev);
2046 pci_disable_pasid(pdev);
2051 /* FIXME: Move this to PCI code */
2052 #define PCI_PRI_TLP_OFF (1 << 15)
2054 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2059 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2063 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2065 return (status & PCI_PRI_TLP_OFF) ? true : false;
2069 * If a device is not yet associated with a domain, this function
2070 * assigns it visible for the hardware
2072 static int attach_device(struct device *dev,
2073 struct protection_domain *domain)
2075 struct pci_dev *pdev;
2076 struct iommu_dev_data *dev_data;
2077 unsigned long flags;
2080 dev_data = get_dev_data(dev);
2082 if (!dev_is_pci(dev))
2083 goto skip_ats_check;
2085 pdev = to_pci_dev(dev);
2086 if (domain->flags & PD_IOMMUV2_MASK) {
2087 if (!dev_data->passthrough)
2090 if (dev_data->iommu_v2) {
2091 if (pdev_iommuv2_enable(pdev) != 0)
2094 dev_data->ats.enabled = true;
2095 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2096 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2098 } else if (amd_iommu_iotlb_sup &&
2099 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2100 dev_data->ats.enabled = true;
2101 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2105 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2106 ret = __attach_device(dev_data, domain);
2107 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2110 * We might boot into a crash-kernel here. The crashed kernel
2111 * left the caches in the IOMMU dirty. So we have to flush
2112 * here to evict all dirty stuff.
2114 domain_flush_tlb_pde(domain);
2120 * Removes a device from a protection domain (unlocked)
2122 static void __detach_device(struct iommu_dev_data *dev_data)
2124 struct protection_domain *domain;
2127 * Must be called with IRQs disabled. Warn here to detect early
2130 WARN_ON(!irqs_disabled());
2132 if (WARN_ON(!dev_data->domain))
2135 domain = dev_data->domain;
2137 spin_lock(&domain->lock);
2139 do_detach(dev_data);
2141 spin_unlock(&domain->lock);
2145 * Removes a device from a protection domain (with devtable_lock held)
2147 static void detach_device(struct device *dev)
2149 struct protection_domain *domain;
2150 struct iommu_dev_data *dev_data;
2151 unsigned long flags;
2153 dev_data = get_dev_data(dev);
2154 domain = dev_data->domain;
2156 /* lock device table */
2157 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2158 __detach_device(dev_data);
2159 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2161 if (!dev_is_pci(dev))
2164 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2165 pdev_iommuv2_disable(to_pci_dev(dev));
2166 else if (dev_data->ats.enabled)
2167 pci_disable_ats(to_pci_dev(dev));
2169 dev_data->ats.enabled = false;
2172 static int amd_iommu_add_device(struct device *dev)
2174 struct iommu_dev_data *dev_data;
2175 struct iommu_domain *domain;
2176 struct amd_iommu *iommu;
2179 if (!check_device(dev) || get_dev_data(dev))
2182 devid = get_device_id(dev);
2186 iommu = amd_iommu_rlookup_table[devid];
2188 ret = iommu_init_device(dev);
2190 if (ret != -ENOTSUPP)
2191 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2194 iommu_ignore_device(dev);
2195 dev->dma_ops = &nommu_dma_ops;
2198 init_iommu_group(dev);
2200 dev_data = get_dev_data(dev);
2204 if (iommu_pass_through || dev_data->iommu_v2)
2205 iommu_request_dm_for_dev(dev);
2207 /* Domains are initialized for this device - have a look what we ended up with */
2208 domain = iommu_get_domain_for_dev(dev);
2209 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2210 dev_data->passthrough = true;
2212 dev->dma_ops = &amd_iommu_dma_ops;
2215 iommu_completion_wait(iommu);
2220 static void amd_iommu_remove_device(struct device *dev)
2222 struct amd_iommu *iommu;
2225 if (!check_device(dev))
2228 devid = get_device_id(dev);
2232 iommu = amd_iommu_rlookup_table[devid];
2234 iommu_uninit_device(dev);
2235 iommu_completion_wait(iommu);
2238 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2240 if (dev_is_pci(dev))
2241 return pci_device_group(dev);
2243 return acpihid_device_group(dev);
2246 /*****************************************************************************
2248 * The next functions belong to the dma_ops mapping/unmapping code.
2250 *****************************************************************************/
2253 * In the dma_ops path we only have the struct device. This function
2254 * finds the corresponding IOMMU, the protection domain and the
2255 * requestor id for a given device.
2256 * If the device is not yet associated with a domain this is also done
2259 static struct protection_domain *get_domain(struct device *dev)
2261 struct protection_domain *domain;
2262 struct iommu_domain *io_domain;
2264 if (!check_device(dev))
2265 return ERR_PTR(-EINVAL);
2267 domain = get_dev_data(dev)->domain;
2268 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2269 get_dev_data(dev)->defer_attach = false;
2270 io_domain = iommu_get_domain_for_dev(dev);
2271 domain = to_pdomain(io_domain);
2272 attach_device(dev, domain);
2275 return ERR_PTR(-EBUSY);
2277 if (!dma_ops_domain(domain))
2278 return ERR_PTR(-EBUSY);
2283 static void update_device_table(struct protection_domain *domain)
2285 struct iommu_dev_data *dev_data;
2287 list_for_each_entry(dev_data, &domain->dev_list, list) {
2288 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2289 dev_data->iommu_v2);
2291 if (dev_data->devid == dev_data->alias)
2294 /* There is an alias, update device table entry for it */
2295 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2296 dev_data->iommu_v2);
2300 static void update_domain(struct protection_domain *domain)
2302 if (!domain->updated)
2305 update_device_table(domain);
2307 domain_flush_devices(domain);
2308 domain_flush_tlb_pde(domain);
2310 domain->updated = false;
2313 static int dir2prot(enum dma_data_direction direction)
2315 if (direction == DMA_TO_DEVICE)
2316 return IOMMU_PROT_IR;
2317 else if (direction == DMA_FROM_DEVICE)
2318 return IOMMU_PROT_IW;
2319 else if (direction == DMA_BIDIRECTIONAL)
2320 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2326 * This function contains common code for mapping of a physically
2327 * contiguous memory region into DMA address space. It is used by all
2328 * mapping functions provided with this IOMMU driver.
2329 * Must be called with the domain lock held.
2331 static dma_addr_t __map_single(struct device *dev,
2332 struct dma_ops_domain *dma_dom,
2335 enum dma_data_direction direction,
2338 dma_addr_t offset = paddr & ~PAGE_MASK;
2339 dma_addr_t address, start, ret;
2344 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2347 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2348 if (address == AMD_IOMMU_MAPPING_ERROR)
2351 prot = dir2prot(direction);
2354 for (i = 0; i < pages; ++i) {
2355 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2356 PAGE_SIZE, prot, GFP_ATOMIC);
2365 if (unlikely(amd_iommu_np_cache)) {
2366 domain_flush_pages(&dma_dom->domain, address, size);
2367 domain_flush_complete(&dma_dom->domain);
2375 for (--i; i >= 0; --i) {
2377 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2380 domain_flush_tlb(&dma_dom->domain);
2381 domain_flush_complete(&dma_dom->domain);
2383 dma_ops_free_iova(dma_dom, address, pages);
2385 return AMD_IOMMU_MAPPING_ERROR;
2389 * Does the reverse of the __map_single function. Must be called with
2390 * the domain lock held too
2392 static void __unmap_single(struct dma_ops_domain *dma_dom,
2393 dma_addr_t dma_addr,
2397 dma_addr_t i, start;
2400 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2401 dma_addr &= PAGE_MASK;
2404 for (i = 0; i < pages; ++i) {
2405 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2409 if (amd_iommu_unmap_flush) {
2410 dma_ops_free_iova(dma_dom, dma_addr, pages);
2411 domain_flush_tlb(&dma_dom->domain);
2412 domain_flush_complete(&dma_dom->domain);
2414 pages = __roundup_pow_of_two(pages);
2415 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2420 * The exported map_single function for dma_ops.
2422 static dma_addr_t map_page(struct device *dev, struct page *page,
2423 unsigned long offset, size_t size,
2424 enum dma_data_direction dir,
2425 unsigned long attrs)
2427 phys_addr_t paddr = page_to_phys(page) + offset;
2428 struct protection_domain *domain;
2429 struct dma_ops_domain *dma_dom;
2432 domain = get_domain(dev);
2433 if (PTR_ERR(domain) == -EINVAL)
2434 return (dma_addr_t)paddr;
2435 else if (IS_ERR(domain))
2436 return AMD_IOMMU_MAPPING_ERROR;
2438 dma_mask = *dev->dma_mask;
2439 dma_dom = to_dma_ops_domain(domain);
2441 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2445 * The exported unmap_single function for dma_ops.
2447 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2448 enum dma_data_direction dir, unsigned long attrs)
2450 struct protection_domain *domain;
2451 struct dma_ops_domain *dma_dom;
2453 domain = get_domain(dev);
2457 dma_dom = to_dma_ops_domain(domain);
2459 __unmap_single(dma_dom, dma_addr, size, dir);
2462 static int sg_num_pages(struct device *dev,
2463 struct scatterlist *sglist,
2466 unsigned long mask, boundary_size;
2467 struct scatterlist *s;
2470 mask = dma_get_seg_boundary(dev);
2471 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2472 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2474 for_each_sg(sglist, s, nelems, i) {
2477 s->dma_address = npages << PAGE_SHIFT;
2478 p = npages % boundary_size;
2479 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2480 if (p + n > boundary_size)
2481 npages += boundary_size - p;
2489 * The exported map_sg function for dma_ops (handles scatter-gather
2492 static int map_sg(struct device *dev, struct scatterlist *sglist,
2493 int nelems, enum dma_data_direction direction,
2494 unsigned long attrs)
2496 int mapped_pages = 0, npages = 0, prot = 0, i;
2497 struct protection_domain *domain;
2498 struct dma_ops_domain *dma_dom;
2499 struct scatterlist *s;
2500 unsigned long address;
2503 domain = get_domain(dev);
2507 dma_dom = to_dma_ops_domain(domain);
2508 dma_mask = *dev->dma_mask;
2510 npages = sg_num_pages(dev, sglist, nelems);
2512 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2513 if (address == AMD_IOMMU_MAPPING_ERROR)
2516 prot = dir2prot(direction);
2518 /* Map all sg entries */
2519 for_each_sg(sglist, s, nelems, i) {
2520 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2522 for (j = 0; j < pages; ++j) {
2523 unsigned long bus_addr, phys_addr;
2526 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2527 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2528 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2536 /* Everything is mapped - write the right values into s->dma_address */
2537 for_each_sg(sglist, s, nelems, i) {
2538 s->dma_address += address + s->offset;
2539 s->dma_length = s->length;
2545 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2546 dev_name(dev), npages);
2548 for_each_sg(sglist, s, nelems, i) {
2549 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2551 for (j = 0; j < pages; ++j) {
2552 unsigned long bus_addr;
2554 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2555 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2563 free_iova_fast(&dma_dom->iovad, address, npages);
2570 * The exported map_sg function for dma_ops (handles scatter-gather
2573 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2574 int nelems, enum dma_data_direction dir,
2575 unsigned long attrs)
2577 struct protection_domain *domain;
2578 struct dma_ops_domain *dma_dom;
2579 unsigned long startaddr;
2582 domain = get_domain(dev);
2586 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2587 dma_dom = to_dma_ops_domain(domain);
2588 npages = sg_num_pages(dev, sglist, nelems);
2590 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2594 * The exported alloc_coherent function for dma_ops.
2596 static void *alloc_coherent(struct device *dev, size_t size,
2597 dma_addr_t *dma_addr, gfp_t flag,
2598 unsigned long attrs)
2600 u64 dma_mask = dev->coherent_dma_mask;
2601 struct protection_domain *domain;
2602 struct dma_ops_domain *dma_dom;
2605 domain = get_domain(dev);
2606 if (PTR_ERR(domain) == -EINVAL) {
2607 page = alloc_pages(flag, get_order(size));
2608 *dma_addr = page_to_phys(page);
2609 return page_address(page);
2610 } else if (IS_ERR(domain))
2613 dma_dom = to_dma_ops_domain(domain);
2614 size = PAGE_ALIGN(size);
2615 dma_mask = dev->coherent_dma_mask;
2616 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2619 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2621 if (!gfpflags_allow_blocking(flag))
2624 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2625 get_order(size), flag);
2631 dma_mask = *dev->dma_mask;
2633 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2634 size, DMA_BIDIRECTIONAL, dma_mask);
2636 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2639 return page_address(page);
2643 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2644 __free_pages(page, get_order(size));
2650 * The exported free_coherent function for dma_ops.
2652 static void free_coherent(struct device *dev, size_t size,
2653 void *virt_addr, dma_addr_t dma_addr,
2654 unsigned long attrs)
2656 struct protection_domain *domain;
2657 struct dma_ops_domain *dma_dom;
2660 page = virt_to_page(virt_addr);
2661 size = PAGE_ALIGN(size);
2663 domain = get_domain(dev);
2667 dma_dom = to_dma_ops_domain(domain);
2669 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2672 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2673 __free_pages(page, get_order(size));
2677 * This function is called by the DMA layer to find out if we can handle a
2678 * particular device. It is part of the dma_ops.
2680 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2682 if (!x86_dma_supported(dev, mask))
2684 return check_device(dev);
2687 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2689 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2692 static const struct dma_map_ops amd_iommu_dma_ops = {
2693 .alloc = alloc_coherent,
2694 .free = free_coherent,
2695 .map_page = map_page,
2696 .unmap_page = unmap_page,
2698 .unmap_sg = unmap_sg,
2699 .dma_supported = amd_iommu_dma_supported,
2700 .mapping_error = amd_iommu_mapping_error,
2703 static int init_reserved_iova_ranges(void)
2705 struct pci_dev *pdev = NULL;
2708 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2710 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2711 &reserved_rbtree_key);
2713 /* MSI memory range */
2714 val = reserve_iova(&reserved_iova_ranges,
2715 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2717 pr_err("Reserving MSI range failed\n");
2721 /* HT memory range */
2722 val = reserve_iova(&reserved_iova_ranges,
2723 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2725 pr_err("Reserving HT range failed\n");
2730 * Memory used for PCI resources
2731 * FIXME: Check whether we can reserve the PCI-hole completly
2733 for_each_pci_dev(pdev) {
2736 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2737 struct resource *r = &pdev->resource[i];
2739 if (!(r->flags & IORESOURCE_MEM))
2742 val = reserve_iova(&reserved_iova_ranges,
2746 pr_err("Reserve pci-resource range failed\n");
2755 int __init amd_iommu_init_api(void)
2759 ret = iova_cache_get();
2763 ret = init_reserved_iova_ranges();
2767 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2770 #ifdef CONFIG_ARM_AMBA
2771 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2775 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2782 int __init amd_iommu_init_dma_ops(void)
2784 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2788 * In case we don't initialize SWIOTLB (actually the common case
2789 * when AMD IOMMU is enabled and SME is not active), make sure there
2790 * are global dma_ops set as a fall-back for devices not handled by
2791 * this driver (for example non-PCI devices). When SME is active,
2792 * make sure that swiotlb variable remains set so the global dma_ops
2793 * continue to be SWIOTLB.
2796 dma_ops = &nommu_dma_ops;
2798 if (amd_iommu_unmap_flush)
2799 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2801 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2807 /*****************************************************************************
2809 * The following functions belong to the exported interface of AMD IOMMU
2811 * This interface allows access to lower level functions of the IOMMU
2812 * like protection domain handling and assignement of devices to domains
2813 * which is not possible with the dma_ops interface.
2815 *****************************************************************************/
2817 static void cleanup_domain(struct protection_domain *domain)
2819 struct iommu_dev_data *entry;
2820 unsigned long flags;
2822 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2824 while (!list_empty(&domain->dev_list)) {
2825 entry = list_first_entry(&domain->dev_list,
2826 struct iommu_dev_data, list);
2827 __detach_device(entry);
2830 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2833 static void protection_domain_free(struct protection_domain *domain)
2838 del_domain_from_list(domain);
2841 domain_id_free(domain->id);
2846 static int protection_domain_init(struct protection_domain *domain)
2848 spin_lock_init(&domain->lock);
2849 mutex_init(&domain->api_lock);
2850 domain->id = domain_id_alloc();
2853 INIT_LIST_HEAD(&domain->dev_list);
2858 static struct protection_domain *protection_domain_alloc(void)
2860 struct protection_domain *domain;
2862 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2866 if (protection_domain_init(domain))
2869 add_domain_to_list(domain);
2879 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2881 struct protection_domain *pdomain;
2882 struct dma_ops_domain *dma_domain;
2885 case IOMMU_DOMAIN_UNMANAGED:
2886 pdomain = protection_domain_alloc();
2890 pdomain->mode = PAGE_MODE_3_LEVEL;
2891 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2892 if (!pdomain->pt_root) {
2893 protection_domain_free(pdomain);
2897 pdomain->domain.geometry.aperture_start = 0;
2898 pdomain->domain.geometry.aperture_end = ~0ULL;
2899 pdomain->domain.geometry.force_aperture = true;
2902 case IOMMU_DOMAIN_DMA:
2903 dma_domain = dma_ops_domain_alloc();
2905 pr_err("AMD-Vi: Failed to allocate\n");
2908 pdomain = &dma_domain->domain;
2910 case IOMMU_DOMAIN_IDENTITY:
2911 pdomain = protection_domain_alloc();
2915 pdomain->mode = PAGE_MODE_NONE;
2921 return &pdomain->domain;
2924 static void amd_iommu_domain_free(struct iommu_domain *dom)
2926 struct protection_domain *domain;
2927 struct dma_ops_domain *dma_dom;
2929 domain = to_pdomain(dom);
2931 if (domain->dev_cnt > 0)
2932 cleanup_domain(domain);
2934 BUG_ON(domain->dev_cnt != 0);
2939 switch (dom->type) {
2940 case IOMMU_DOMAIN_DMA:
2941 /* Now release the domain */
2942 dma_dom = to_dma_ops_domain(domain);
2943 dma_ops_domain_free(dma_dom);
2946 if (domain->mode != PAGE_MODE_NONE)
2947 free_pagetable(domain);
2949 if (domain->flags & PD_IOMMUV2_MASK)
2950 free_gcr3_table(domain);
2952 protection_domain_free(domain);
2957 static void amd_iommu_detach_device(struct iommu_domain *dom,
2960 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2961 struct amd_iommu *iommu;
2964 if (!check_device(dev))
2967 devid = get_device_id(dev);
2971 if (dev_data->domain != NULL)
2974 iommu = amd_iommu_rlookup_table[devid];
2978 #ifdef CONFIG_IRQ_REMAP
2979 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2980 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2981 dev_data->use_vapic = 0;
2984 iommu_completion_wait(iommu);
2987 static int amd_iommu_attach_device(struct iommu_domain *dom,
2990 struct protection_domain *domain = to_pdomain(dom);
2991 struct iommu_dev_data *dev_data;
2992 struct amd_iommu *iommu;
2995 if (!check_device(dev))
2998 dev_data = dev->archdata.iommu;
3000 iommu = amd_iommu_rlookup_table[dev_data->devid];
3004 if (dev_data->domain)
3007 ret = attach_device(dev, domain);
3009 #ifdef CONFIG_IRQ_REMAP
3010 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3011 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3012 dev_data->use_vapic = 1;
3014 dev_data->use_vapic = 0;
3018 iommu_completion_wait(iommu);
3023 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3024 phys_addr_t paddr, size_t page_size, int iommu_prot)
3026 struct protection_domain *domain = to_pdomain(dom);
3030 if (domain->mode == PAGE_MODE_NONE)
3033 if (iommu_prot & IOMMU_READ)
3034 prot |= IOMMU_PROT_IR;
3035 if (iommu_prot & IOMMU_WRITE)
3036 prot |= IOMMU_PROT_IW;
3038 mutex_lock(&domain->api_lock);
3039 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3040 mutex_unlock(&domain->api_lock);
3045 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3048 struct protection_domain *domain = to_pdomain(dom);
3051 if (domain->mode == PAGE_MODE_NONE)
3054 mutex_lock(&domain->api_lock);
3055 unmap_size = iommu_unmap_page(domain, iova, page_size);
3056 mutex_unlock(&domain->api_lock);
3058 domain_flush_tlb_pde(domain);
3059 domain_flush_complete(domain);
3064 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3067 struct protection_domain *domain = to_pdomain(dom);
3068 unsigned long offset_mask, pte_pgsize;
3071 if (domain->mode == PAGE_MODE_NONE)
3074 pte = fetch_pte(domain, iova, &pte_pgsize);
3076 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3079 offset_mask = pte_pgsize - 1;
3080 __pte = *pte & PM_ADDR_MASK;
3082 return (__pte & ~offset_mask) | (iova & offset_mask);
3085 static bool amd_iommu_capable(enum iommu_cap cap)
3088 case IOMMU_CAP_CACHE_COHERENCY:
3090 case IOMMU_CAP_INTR_REMAP:
3091 return (irq_remapping_enabled == 1);
3092 case IOMMU_CAP_NOEXEC:
3099 static void amd_iommu_get_resv_regions(struct device *dev,
3100 struct list_head *head)
3102 struct iommu_resv_region *region;
3103 struct unity_map_entry *entry;
3106 devid = get_device_id(dev);
3110 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3114 if (devid < entry->devid_start || devid > entry->devid_end)
3117 length = entry->address_end - entry->address_start;
3118 if (entry->prot & IOMMU_PROT_IR)
3120 if (entry->prot & IOMMU_PROT_IW)
3121 prot |= IOMMU_WRITE;
3123 region = iommu_alloc_resv_region(entry->address_start,
3127 pr_err("Out of memory allocating dm-regions for %s\n",
3131 list_add_tail(®ion->list, head);
3134 region = iommu_alloc_resv_region(MSI_RANGE_START,
3135 MSI_RANGE_END - MSI_RANGE_START + 1,
3139 list_add_tail(®ion->list, head);
3141 region = iommu_alloc_resv_region(HT_RANGE_START,
3142 HT_RANGE_END - HT_RANGE_START + 1,
3143 0, IOMMU_RESV_RESERVED);
3146 list_add_tail(®ion->list, head);
3149 static void amd_iommu_put_resv_regions(struct device *dev,
3150 struct list_head *head)
3152 struct iommu_resv_region *entry, *next;
3154 list_for_each_entry_safe(entry, next, head, list)
3158 static void amd_iommu_apply_resv_region(struct device *dev,
3159 struct iommu_domain *domain,
3160 struct iommu_resv_region *region)
3162 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3163 unsigned long start, end;
3165 start = IOVA_PFN(region->start);
3166 end = IOVA_PFN(region->start + region->length - 1);
3168 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3171 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3174 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3175 return dev_data->defer_attach;
3178 const struct iommu_ops amd_iommu_ops = {
3179 .capable = amd_iommu_capable,
3180 .domain_alloc = amd_iommu_domain_alloc,
3181 .domain_free = amd_iommu_domain_free,
3182 .attach_dev = amd_iommu_attach_device,
3183 .detach_dev = amd_iommu_detach_device,
3184 .map = amd_iommu_map,
3185 .unmap = amd_iommu_unmap,
3186 .map_sg = default_iommu_map_sg,
3187 .iova_to_phys = amd_iommu_iova_to_phys,
3188 .add_device = amd_iommu_add_device,
3189 .remove_device = amd_iommu_remove_device,
3190 .device_group = amd_iommu_device_group,
3191 .get_resv_regions = amd_iommu_get_resv_regions,
3192 .put_resv_regions = amd_iommu_put_resv_regions,
3193 .apply_resv_region = amd_iommu_apply_resv_region,
3194 .is_attach_deferred = amd_iommu_is_attach_deferred,
3195 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3198 /*****************************************************************************
3200 * The next functions do a basic initialization of IOMMU for pass through
3203 * In passthrough mode the IOMMU is initialized and enabled but not used for
3204 * DMA-API translation.
3206 *****************************************************************************/
3208 /* IOMMUv2 specific functions */
3209 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3211 return atomic_notifier_chain_register(&ppr_notifier, nb);
3213 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3215 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3217 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3219 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3221 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3223 struct protection_domain *domain = to_pdomain(dom);
3224 unsigned long flags;
3226 spin_lock_irqsave(&domain->lock, flags);
3228 /* Update data structure */
3229 domain->mode = PAGE_MODE_NONE;
3230 domain->updated = true;
3232 /* Make changes visible to IOMMUs */
3233 update_domain(domain);
3235 /* Page-table is not visible to IOMMU anymore, so free it */
3236 free_pagetable(domain);
3238 spin_unlock_irqrestore(&domain->lock, flags);
3240 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3242 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3244 struct protection_domain *domain = to_pdomain(dom);
3245 unsigned long flags;
3248 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3251 /* Number of GCR3 table levels required */
3252 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3255 if (levels > amd_iommu_max_glx_val)
3258 spin_lock_irqsave(&domain->lock, flags);
3261 * Save us all sanity checks whether devices already in the
3262 * domain support IOMMUv2. Just force that the domain has no
3263 * devices attached when it is switched into IOMMUv2 mode.
3266 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3270 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3271 if (domain->gcr3_tbl == NULL)
3274 domain->glx = levels;
3275 domain->flags |= PD_IOMMUV2_MASK;
3276 domain->updated = true;
3278 update_domain(domain);
3283 spin_unlock_irqrestore(&domain->lock, flags);
3287 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3289 static int __flush_pasid(struct protection_domain *domain, int pasid,
3290 u64 address, bool size)
3292 struct iommu_dev_data *dev_data;
3293 struct iommu_cmd cmd;
3296 if (!(domain->flags & PD_IOMMUV2_MASK))
3299 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3302 * IOMMU TLB needs to be flushed before Device TLB to
3303 * prevent device TLB refill from IOMMU TLB
3305 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3306 if (domain->dev_iommu[i] == 0)
3309 ret = iommu_queue_command(amd_iommus[i], &cmd);
3314 /* Wait until IOMMU TLB flushes are complete */
3315 domain_flush_complete(domain);
3317 /* Now flush device TLBs */
3318 list_for_each_entry(dev_data, &domain->dev_list, list) {
3319 struct amd_iommu *iommu;
3323 There might be non-IOMMUv2 capable devices in an IOMMUv2
3326 if (!dev_data->ats.enabled)
3329 qdep = dev_data->ats.qdep;
3330 iommu = amd_iommu_rlookup_table[dev_data->devid];
3332 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3333 qdep, address, size);
3335 ret = iommu_queue_command(iommu, &cmd);
3340 /* Wait until all device TLBs are flushed */
3341 domain_flush_complete(domain);
3350 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3353 return __flush_pasid(domain, pasid, address, false);
3356 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3359 struct protection_domain *domain = to_pdomain(dom);
3360 unsigned long flags;
3363 spin_lock_irqsave(&domain->lock, flags);
3364 ret = __amd_iommu_flush_page(domain, pasid, address);
3365 spin_unlock_irqrestore(&domain->lock, flags);
3369 EXPORT_SYMBOL(amd_iommu_flush_page);
3371 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3373 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3377 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3379 struct protection_domain *domain = to_pdomain(dom);
3380 unsigned long flags;
3383 spin_lock_irqsave(&domain->lock, flags);
3384 ret = __amd_iommu_flush_tlb(domain, pasid);
3385 spin_unlock_irqrestore(&domain->lock, flags);
3389 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3391 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3398 index = (pasid >> (9 * level)) & 0x1ff;
3404 if (!(*pte & GCR3_VALID)) {
3408 root = (void *)get_zeroed_page(GFP_ATOMIC);
3412 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3415 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3423 static int __set_gcr3(struct protection_domain *domain, int pasid,
3428 if (domain->mode != PAGE_MODE_NONE)
3431 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3435 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3437 return __amd_iommu_flush_tlb(domain, pasid);
3440 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3444 if (domain->mode != PAGE_MODE_NONE)
3447 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3453 return __amd_iommu_flush_tlb(domain, pasid);
3456 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3459 struct protection_domain *domain = to_pdomain(dom);
3460 unsigned long flags;
3463 spin_lock_irqsave(&domain->lock, flags);
3464 ret = __set_gcr3(domain, pasid, cr3);
3465 spin_unlock_irqrestore(&domain->lock, flags);
3469 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3471 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3473 struct protection_domain *domain = to_pdomain(dom);
3474 unsigned long flags;
3477 spin_lock_irqsave(&domain->lock, flags);
3478 ret = __clear_gcr3(domain, pasid);
3479 spin_unlock_irqrestore(&domain->lock, flags);
3483 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3485 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3486 int status, int tag)
3488 struct iommu_dev_data *dev_data;
3489 struct amd_iommu *iommu;
3490 struct iommu_cmd cmd;
3492 dev_data = get_dev_data(&pdev->dev);
3493 iommu = amd_iommu_rlookup_table[dev_data->devid];
3495 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3496 tag, dev_data->pri_tlp);
3498 return iommu_queue_command(iommu, &cmd);
3500 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3502 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3504 struct protection_domain *pdomain;
3506 pdomain = get_domain(&pdev->dev);
3507 if (IS_ERR(pdomain))
3510 /* Only return IOMMUv2 domains */
3511 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3514 return &pdomain->domain;
3516 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3518 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3520 struct iommu_dev_data *dev_data;
3522 if (!amd_iommu_v2_supported())
3525 dev_data = get_dev_data(&pdev->dev);
3526 dev_data->errata |= (1 << erratum);
3528 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3530 int amd_iommu_device_info(struct pci_dev *pdev,
3531 struct amd_iommu_device_info *info)
3536 if (pdev == NULL || info == NULL)
3539 if (!amd_iommu_v2_supported())
3542 memset(info, 0, sizeof(*info));
3544 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3546 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3548 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3550 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3552 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3556 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3557 max_pasids = min(max_pasids, (1 << 20));
3559 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3560 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3562 features = pci_pasid_features(pdev);
3563 if (features & PCI_PASID_CAP_EXEC)
3564 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3565 if (features & PCI_PASID_CAP_PRIV)
3566 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3571 EXPORT_SYMBOL(amd_iommu_device_info);
3573 #ifdef CONFIG_IRQ_REMAP
3575 /*****************************************************************************
3577 * Interrupt Remapping Implementation
3579 *****************************************************************************/
3581 static struct irq_chip amd_ir_chip;
3583 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3587 dte = amd_iommu_dev_table[devid].data[2];
3588 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3589 dte |= iommu_virt_to_phys(table->table);
3590 dte |= DTE_IRQ_REMAP_INTCTL;
3591 dte |= DTE_IRQ_TABLE_LEN;
3592 dte |= DTE_IRQ_REMAP_ENABLE;
3594 amd_iommu_dev_table[devid].data[2] = dte;
3597 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3599 struct irq_remap_table *table = NULL;
3600 struct amd_iommu *iommu;
3601 unsigned long flags;
3604 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3606 iommu = amd_iommu_rlookup_table[devid];
3610 table = irq_lookup_table[devid];
3614 alias = amd_iommu_alias_table[devid];
3615 table = irq_lookup_table[alias];
3617 irq_lookup_table[devid] = table;
3618 set_dte_irq_entry(devid, table);
3619 iommu_flush_dte(iommu, devid);
3623 /* Nothing there yet, allocate new irq remapping table */
3624 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3628 /* Initialize table spin-lock */
3629 spin_lock_init(&table->lock);
3632 /* Keep the first 32 indexes free for IOAPIC interrupts */
3633 table->min_index = 32;
3635 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3636 if (!table->table) {
3642 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3643 memset(table->table, 0,
3644 MAX_IRQS_PER_TABLE * sizeof(u32));
3646 memset(table->table, 0,
3647 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3652 for (i = 0; i < 32; ++i)
3653 iommu->irte_ops->set_allocated(table, i);
3656 irq_lookup_table[devid] = table;
3657 set_dte_irq_entry(devid, table);
3658 iommu_flush_dte(iommu, devid);
3659 if (devid != alias) {
3660 irq_lookup_table[alias] = table;
3661 set_dte_irq_entry(alias, table);
3662 iommu_flush_dte(iommu, alias);
3666 iommu_completion_wait(iommu);
3669 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3674 static int alloc_irq_index(u16 devid, int count, bool align)
3676 struct irq_remap_table *table;
3677 int index, c, alignment = 1;
3678 unsigned long flags;
3679 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3684 table = get_irq_table(devid, false);
3689 alignment = roundup_pow_of_two(count);
3691 spin_lock_irqsave(&table->lock, flags);
3693 /* Scan table for free entries */
3694 for (index = ALIGN(table->min_index, alignment), c = 0;
3695 index < MAX_IRQS_PER_TABLE;) {
3696 if (!iommu->irte_ops->is_allocated(table, index)) {
3700 index = ALIGN(index + 1, alignment);
3706 iommu->irte_ops->set_allocated(table, index - c + 1);
3718 spin_unlock_irqrestore(&table->lock, flags);
3723 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3724 struct amd_ir_data *data)
3726 struct irq_remap_table *table;
3727 struct amd_iommu *iommu;
3728 unsigned long flags;
3729 struct irte_ga *entry;
3731 iommu = amd_iommu_rlookup_table[devid];
3735 table = get_irq_table(devid, false);
3739 spin_lock_irqsave(&table->lock, flags);
3741 entry = (struct irte_ga *)table->table;
3742 entry = &entry[index];
3743 entry->lo.fields_remap.valid = 0;
3744 entry->hi.val = irte->hi.val;
3745 entry->lo.val = irte->lo.val;
3746 entry->lo.fields_remap.valid = 1;
3750 spin_unlock_irqrestore(&table->lock, flags);
3752 iommu_flush_irt(iommu, devid);
3753 iommu_completion_wait(iommu);
3758 static int modify_irte(u16 devid, int index, union irte *irte)
3760 struct irq_remap_table *table;
3761 struct amd_iommu *iommu;
3762 unsigned long flags;
3764 iommu = amd_iommu_rlookup_table[devid];
3768 table = get_irq_table(devid, false);
3772 spin_lock_irqsave(&table->lock, flags);
3773 table->table[index] = irte->val;
3774 spin_unlock_irqrestore(&table->lock, flags);
3776 iommu_flush_irt(iommu, devid);
3777 iommu_completion_wait(iommu);
3782 static void free_irte(u16 devid, int index)
3784 struct irq_remap_table *table;
3785 struct amd_iommu *iommu;
3786 unsigned long flags;
3788 iommu = amd_iommu_rlookup_table[devid];
3792 table = get_irq_table(devid, false);
3796 spin_lock_irqsave(&table->lock, flags);
3797 iommu->irte_ops->clear_allocated(table, index);
3798 spin_unlock_irqrestore(&table->lock, flags);
3800 iommu_flush_irt(iommu, devid);
3801 iommu_completion_wait(iommu);
3804 static void irte_prepare(void *entry,
3805 u32 delivery_mode, u32 dest_mode,
3806 u8 vector, u32 dest_apicid, int devid)
3808 union irte *irte = (union irte *) entry;
3811 irte->fields.vector = vector;
3812 irte->fields.int_type = delivery_mode;
3813 irte->fields.destination = dest_apicid;
3814 irte->fields.dm = dest_mode;
3815 irte->fields.valid = 1;
3818 static void irte_ga_prepare(void *entry,
3819 u32 delivery_mode, u32 dest_mode,
3820 u8 vector, u32 dest_apicid, int devid)
3822 struct irte_ga *irte = (struct irte_ga *) entry;
3826 irte->lo.fields_remap.int_type = delivery_mode;
3827 irte->lo.fields_remap.dm = dest_mode;
3828 irte->hi.fields.vector = vector;
3829 irte->lo.fields_remap.destination = dest_apicid;
3830 irte->lo.fields_remap.valid = 1;
3833 static void irte_activate(void *entry, u16 devid, u16 index)
3835 union irte *irte = (union irte *) entry;
3837 irte->fields.valid = 1;
3838 modify_irte(devid, index, irte);
3841 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3843 struct irte_ga *irte = (struct irte_ga *) entry;
3845 irte->lo.fields_remap.valid = 1;
3846 modify_irte_ga(devid, index, irte, NULL);
3849 static void irte_deactivate(void *entry, u16 devid, u16 index)
3851 union irte *irte = (union irte *) entry;
3853 irte->fields.valid = 0;
3854 modify_irte(devid, index, irte);
3857 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3859 struct irte_ga *irte = (struct irte_ga *) entry;
3861 irte->lo.fields_remap.valid = 0;
3862 modify_irte_ga(devid, index, irte, NULL);
3865 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3866 u8 vector, u32 dest_apicid)
3868 union irte *irte = (union irte *) entry;
3870 irte->fields.vector = vector;
3871 irte->fields.destination = dest_apicid;
3872 modify_irte(devid, index, irte);
3875 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3876 u8 vector, u32 dest_apicid)
3878 struct irte_ga *irte = (struct irte_ga *) entry;
3879 struct iommu_dev_data *dev_data = search_dev_data(devid);
3881 if (!dev_data || !dev_data->use_vapic ||
3882 !irte->lo.fields_remap.guest_mode) {
3883 irte->hi.fields.vector = vector;
3884 irte->lo.fields_remap.destination = dest_apicid;
3885 modify_irte_ga(devid, index, irte, NULL);
3889 #define IRTE_ALLOCATED (~1U)
3890 static void irte_set_allocated(struct irq_remap_table *table, int index)
3892 table->table[index] = IRTE_ALLOCATED;
3895 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3897 struct irte_ga *ptr = (struct irte_ga *)table->table;
3898 struct irte_ga *irte = &ptr[index];
3900 memset(&irte->lo.val, 0, sizeof(u64));
3901 memset(&irte->hi.val, 0, sizeof(u64));
3902 irte->hi.fields.vector = 0xff;
3905 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3907 union irte *ptr = (union irte *)table->table;
3908 union irte *irte = &ptr[index];
3910 return irte->val != 0;
3913 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3915 struct irte_ga *ptr = (struct irte_ga *)table->table;
3916 struct irte_ga *irte = &ptr[index];
3918 return irte->hi.fields.vector != 0;
3921 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3923 table->table[index] = 0;
3926 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3928 struct irte_ga *ptr = (struct irte_ga *)table->table;
3929 struct irte_ga *irte = &ptr[index];
3931 memset(&irte->lo.val, 0, sizeof(u64));
3932 memset(&irte->hi.val, 0, sizeof(u64));
3935 static int get_devid(struct irq_alloc_info *info)
3939 switch (info->type) {
3940 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3941 devid = get_ioapic_devid(info->ioapic_id);
3943 case X86_IRQ_ALLOC_TYPE_HPET:
3944 devid = get_hpet_devid(info->hpet_id);
3946 case X86_IRQ_ALLOC_TYPE_MSI:
3947 case X86_IRQ_ALLOC_TYPE_MSIX:
3948 devid = get_device_id(&info->msi_dev->dev);
3958 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3960 struct amd_iommu *iommu;
3966 devid = get_devid(info);
3968 iommu = amd_iommu_rlookup_table[devid];
3970 return iommu->ir_domain;
3976 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3978 struct amd_iommu *iommu;
3984 switch (info->type) {
3985 case X86_IRQ_ALLOC_TYPE_MSI:
3986 case X86_IRQ_ALLOC_TYPE_MSIX:
3987 devid = get_device_id(&info->msi_dev->dev);
3991 iommu = amd_iommu_rlookup_table[devid];
3993 return iommu->msi_domain;
4002 struct irq_remap_ops amd_iommu_irq_ops = {
4003 .prepare = amd_iommu_prepare,
4004 .enable = amd_iommu_enable,
4005 .disable = amd_iommu_disable,
4006 .reenable = amd_iommu_reenable,
4007 .enable_faulting = amd_iommu_enable_faulting,
4008 .get_ir_irq_domain = get_ir_irq_domain,
4009 .get_irq_domain = get_irq_domain,
4012 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4013 struct irq_cfg *irq_cfg,
4014 struct irq_alloc_info *info,
4015 int devid, int index, int sub_handle)
4017 struct irq_2_irte *irte_info = &data->irq_2_irte;
4018 struct msi_msg *msg = &data->msi_entry;
4019 struct IO_APIC_route_entry *entry;
4020 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4025 data->irq_2_irte.devid = devid;
4026 data->irq_2_irte.index = index + sub_handle;
4027 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4028 apic->irq_dest_mode, irq_cfg->vector,
4029 irq_cfg->dest_apicid, devid);
4031 switch (info->type) {
4032 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4033 /* Setup IOAPIC entry */
4034 entry = info->ioapic_entry;
4035 info->ioapic_entry = NULL;
4036 memset(entry, 0, sizeof(*entry));
4037 entry->vector = index;
4039 entry->trigger = info->ioapic_trigger;
4040 entry->polarity = info->ioapic_polarity;
4041 /* Mask level triggered irqs. */
4042 if (info->ioapic_trigger)
4046 case X86_IRQ_ALLOC_TYPE_HPET:
4047 case X86_IRQ_ALLOC_TYPE_MSI:
4048 case X86_IRQ_ALLOC_TYPE_MSIX:
4049 msg->address_hi = MSI_ADDR_BASE_HI;
4050 msg->address_lo = MSI_ADDR_BASE_LO;
4051 msg->data = irte_info->index;
4060 struct amd_irte_ops irte_32_ops = {
4061 .prepare = irte_prepare,
4062 .activate = irte_activate,
4063 .deactivate = irte_deactivate,
4064 .set_affinity = irte_set_affinity,
4065 .set_allocated = irte_set_allocated,
4066 .is_allocated = irte_is_allocated,
4067 .clear_allocated = irte_clear_allocated,
4070 struct amd_irte_ops irte_128_ops = {
4071 .prepare = irte_ga_prepare,
4072 .activate = irte_ga_activate,
4073 .deactivate = irte_ga_deactivate,
4074 .set_affinity = irte_ga_set_affinity,
4075 .set_allocated = irte_ga_set_allocated,
4076 .is_allocated = irte_ga_is_allocated,
4077 .clear_allocated = irte_ga_clear_allocated,
4080 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4081 unsigned int nr_irqs, void *arg)
4083 struct irq_alloc_info *info = arg;
4084 struct irq_data *irq_data;
4085 struct amd_ir_data *data = NULL;
4086 struct irq_cfg *cfg;
4092 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4093 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4097 * With IRQ remapping enabled, don't need contiguous CPU vectors
4098 * to support multiple MSI interrupts.
4100 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4101 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4103 devid = get_devid(info);
4107 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4111 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4112 if (get_irq_table(devid, true))
4113 index = info->ioapic_pin;
4117 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4119 index = alloc_irq_index(devid, nr_irqs, align);
4122 pr_warn("Failed to allocate IRTE\n");
4124 goto out_free_parent;
4127 for (i = 0; i < nr_irqs; i++) {
4128 irq_data = irq_domain_get_irq_data(domain, virq + i);
4129 cfg = irqd_cfg(irq_data);
4130 if (!irq_data || !cfg) {
4136 data = kzalloc(sizeof(*data), GFP_KERNEL);
4140 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4141 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4143 data->entry = kzalloc(sizeof(struct irte_ga),
4150 irq_data->hwirq = (devid << 16) + i;
4151 irq_data->chip_data = data;
4152 irq_data->chip = &amd_ir_chip;
4153 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4154 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4160 for (i--; i >= 0; i--) {
4161 irq_data = irq_domain_get_irq_data(domain, virq + i);
4163 kfree(irq_data->chip_data);
4165 for (i = 0; i < nr_irqs; i++)
4166 free_irte(devid, index + i);
4168 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4172 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4173 unsigned int nr_irqs)
4175 struct irq_2_irte *irte_info;
4176 struct irq_data *irq_data;
4177 struct amd_ir_data *data;
4180 for (i = 0; i < nr_irqs; i++) {
4181 irq_data = irq_domain_get_irq_data(domain, virq + i);
4182 if (irq_data && irq_data->chip_data) {
4183 data = irq_data->chip_data;
4184 irte_info = &data->irq_2_irte;
4185 free_irte(irte_info->devid, irte_info->index);
4190 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4193 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4194 struct amd_ir_data *ir_data,
4195 struct irq_2_irte *irte_info,
4196 struct irq_cfg *cfg);
4198 static int irq_remapping_activate(struct irq_domain *domain,
4199 struct irq_data *irq_data, bool reserve)
4201 struct amd_ir_data *data = irq_data->chip_data;
4202 struct irq_2_irte *irte_info = &data->irq_2_irte;
4203 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4204 struct irq_cfg *cfg = irqd_cfg(irq_data);
4209 iommu->irte_ops->activate(data->entry, irte_info->devid,
4211 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4215 static void irq_remapping_deactivate(struct irq_domain *domain,
4216 struct irq_data *irq_data)
4218 struct amd_ir_data *data = irq_data->chip_data;
4219 struct irq_2_irte *irte_info = &data->irq_2_irte;
4220 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4223 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4227 static const struct irq_domain_ops amd_ir_domain_ops = {
4228 .alloc = irq_remapping_alloc,
4229 .free = irq_remapping_free,
4230 .activate = irq_remapping_activate,
4231 .deactivate = irq_remapping_deactivate,
4234 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4236 struct amd_iommu *iommu;
4237 struct amd_iommu_pi_data *pi_data = vcpu_info;
4238 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4239 struct amd_ir_data *ir_data = data->chip_data;
4240 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4241 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4242 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4245 * This device has never been set up for guest mode.
4246 * we should not modify the IRTE
4248 if (!dev_data || !dev_data->use_vapic)
4251 pi_data->ir_data = ir_data;
4254 * SVM tries to set up for VAPIC mode, but we are in
4255 * legacy mode. So, we force legacy mode instead.
4257 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4258 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4260 pi_data->is_guest_mode = false;
4263 iommu = amd_iommu_rlookup_table[irte_info->devid];
4267 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4268 if (pi_data->is_guest_mode) {
4270 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4271 irte->hi.fields.vector = vcpu_pi_info->vector;
4272 irte->lo.fields_vapic.ga_log_intr = 1;
4273 irte->lo.fields_vapic.guest_mode = 1;
4274 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4276 ir_data->cached_ga_tag = pi_data->ga_tag;
4279 struct irq_cfg *cfg = irqd_cfg(data);
4283 irte->hi.fields.vector = cfg->vector;
4284 irte->lo.fields_remap.guest_mode = 0;
4285 irte->lo.fields_remap.destination = cfg->dest_apicid;
4286 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4287 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4290 * This communicates the ga_tag back to the caller
4291 * so that it can do all the necessary clean up.
4293 ir_data->cached_ga_tag = 0;
4296 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4300 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4301 struct amd_ir_data *ir_data,
4302 struct irq_2_irte *irte_info,
4303 struct irq_cfg *cfg)
4307 * Atomically updates the IRTE with the new destination, vector
4308 * and flushes the interrupt entry cache.
4310 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4311 irte_info->index, cfg->vector,
4315 static int amd_ir_set_affinity(struct irq_data *data,
4316 const struct cpumask *mask, bool force)
4318 struct amd_ir_data *ir_data = data->chip_data;
4319 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4320 struct irq_cfg *cfg = irqd_cfg(data);
4321 struct irq_data *parent = data->parent_data;
4322 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4328 ret = parent->chip->irq_set_affinity(parent, mask, force);
4329 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4332 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4334 * After this point, all the interrupts will start arriving
4335 * at the new destination. So, time to cleanup the previous
4336 * vector allocation.
4338 send_cleanup_vector(cfg);
4340 return IRQ_SET_MASK_OK_DONE;
4343 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4345 struct amd_ir_data *ir_data = irq_data->chip_data;
4347 *msg = ir_data->msi_entry;
4350 static struct irq_chip amd_ir_chip = {
4352 .irq_ack = ir_ack_apic_edge,
4353 .irq_set_affinity = amd_ir_set_affinity,
4354 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4355 .irq_compose_msi_msg = ir_compose_msi_msg,
4358 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4360 struct fwnode_handle *fn;
4362 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4365 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4366 irq_domain_free_fwnode(fn);
4367 if (!iommu->ir_domain)
4370 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4371 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4377 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4379 unsigned long flags;
4380 struct amd_iommu *iommu;
4381 struct irq_remap_table *irt;
4382 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4383 int devid = ir_data->irq_2_irte.devid;
4384 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4385 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4387 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4388 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4391 iommu = amd_iommu_rlookup_table[devid];
4395 irt = get_irq_table(devid, false);
4399 spin_lock_irqsave(&irt->lock, flags);
4401 if (ref->lo.fields_vapic.guest_mode) {
4403 ref->lo.fields_vapic.destination = cpu;
4404 ref->lo.fields_vapic.is_run = is_run;
4408 spin_unlock_irqrestore(&irt->lock, flags);
4410 iommu_flush_irt(iommu, devid);
4411 iommu_completion_wait(iommu);
4414 EXPORT_SYMBOL(amd_iommu_update_ga);