drivers/infiniband/hw/qedr/main.c

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/module.h>
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_addr.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <rdma/iw_cm.h>
  37 #include <rdma/ib_mad.h>
  38 #include <linux/netdevice.h>
  39 #include <linux/iommu.h>
  40 #include <linux/pci.h>
  41 #include <net/addrconf.h>
  42
  43 #include <linux/qed/qed_chain.h>
  44 #include <linux/qed/qed_if.h>
  45 #include "qedr.h"
  46 #include "verbs.h"
  47 #include <rdma/qedr-abi.h>
  48 #include "qedr_iw_cm.h"
  49
  50 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
  51 MODULE_AUTHOR("QLogic Corporation");
  52 MODULE_LICENSE("Dual BSD/GPL");
  53
  54 #define QEDR_WQ_MULTIPLIER_DFT  (3)
  55
  56 static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
  57                                    enum ib_event_type type)
  58 {
  59         struct ib_event ibev;
  60
  61         ibev.device = &dev->ibdev;
  62         ibev.element.port_num = port_num;
  63         ibev.event = type;
  64
  65         ib_dispatch_event(&ibev);
  66 }
  67
  68 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
  69                                             u8 port_num)
  70 {
  71         return IB_LINK_LAYER_ETHERNET;
  72 }
  73
  74 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
  75 {
  76         struct qedr_dev *qedr = get_qedr_dev(ibdev);
  77         u32 fw_ver = (u32)qedr->attr.fw_ver;
  78
  79         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d. %d. %d. %d",
  80                  (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
  81                  (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
  82 }
  83
  84 static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num,
  85                                     struct ib_port_immutable *immutable)
  86 {
  87         struct ib_port_attr attr;
  88         int err;
  89
  90         err = qedr_query_port(ibdev, port_num, &attr);
  91         if (err)
  92                 return err;
  93
  94         immutable->pkey_tbl_len = attr.pkey_tbl_len;
  95         immutable->gid_tbl_len = attr.gid_tbl_len;
  96         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
  97             RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  98         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  99
 100         return 0;
 101 }
 102
 103 static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num,
 104                                   struct ib_port_immutable *immutable)
 105 {
 106         struct ib_port_attr attr;
 107         int err;
 108
 109         err = qedr_query_port(ibdev, port_num, &attr);
 110         if (err)
 111                 return err;
 112
 113         immutable->pkey_tbl_len = 1;
 114         immutable->gid_tbl_len = 1;
 115         immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
 116         immutable->max_mad_size = 0;
 117
 118         return 0;
 119 }
 120
 121 /* QEDR sysfs interface */
 122 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
 123                            char *buf)
 124 {
 125         struct qedr_dev *dev =
 126                 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
 127
 128         return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
 129 }
 130 static DEVICE_ATTR_RO(hw_rev);
 131
 132 static ssize_t hca_type_show(struct device *device,
 133                              struct device_attribute *attr, char *buf)
 134 {
 135         return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
 136 }
 137 static DEVICE_ATTR_RO(hca_type);
 138
 139 static struct attribute *qedr_attributes[] = {
 140         &dev_attr_hw_rev.attr,
 141         &dev_attr_hca_type.attr,
 142         NULL
 143 };
 144
 145 static const struct attribute_group qedr_attr_group = {
 146         .attrs = qedr_attributes,
 147 };
 148
 149 static const struct ib_device_ops qedr_iw_dev_ops = {
 150         .get_port_immutable = qedr_iw_port_immutable,
 151         .iw_accept = qedr_iw_accept,
 152         .iw_add_ref = qedr_iw_qp_add_ref,
 153         .iw_connect = qedr_iw_connect,
 154         .iw_create_listen = qedr_iw_create_listen,
 155         .iw_destroy_listen = qedr_iw_destroy_listen,
 156         .iw_get_qp = qedr_iw_get_qp,
 157         .iw_reject = qedr_iw_reject,
 158         .iw_rem_ref = qedr_iw_qp_rem_ref,
 159         .query_gid = qedr_iw_query_gid,
 160 };
 161
 162 static int qedr_iw_register_device(struct qedr_dev *dev)
 163 {
 164         dev->ibdev.node_type = RDMA_NODE_RNIC;
 165
 166         ib_set_device_ops(&dev->ibdev, &qedr_iw_dev_ops);
 167
 168         memcpy(dev->ibdev.iw_ifname,
 169                dev->ndev->name, sizeof(dev->ibdev.iw_ifname));
 170
 171         return 0;
 172 }
 173
 174 static const struct ib_device_ops qedr_roce_dev_ops = {
 175         .get_port_immutable = qedr_roce_port_immutable,
 176 };
 177
 178 static void qedr_roce_register_device(struct qedr_dev *dev)
 179 {
 180         dev->ibdev.node_type = RDMA_NODE_IB_CA;
 181
 182         ib_set_device_ops(&dev->ibdev, &qedr_roce_dev_ops);
 183 }
 184
 185 static const struct ib_device_ops qedr_dev_ops = {
 186         .alloc_mr = qedr_alloc_mr,
 187         .alloc_pd = qedr_alloc_pd,
 188         .alloc_ucontext = qedr_alloc_ucontext,
 189         .create_ah = qedr_create_ah,
 190         .create_cq = qedr_create_cq,
 191         .create_qp = qedr_create_qp,
 192         .create_srq = qedr_create_srq,
 193         .dealloc_pd = qedr_dealloc_pd,
 194         .dealloc_ucontext = qedr_dealloc_ucontext,
 195         .dereg_mr = qedr_dereg_mr,
 196         .destroy_ah = qedr_destroy_ah,
 197         .destroy_cq = qedr_destroy_cq,
 198         .destroy_qp = qedr_destroy_qp,
 199         .destroy_srq = qedr_destroy_srq,
 200         .get_dev_fw_str = qedr_get_dev_fw_str,
 201         .get_dma_mr = qedr_get_dma_mr,
 202         .get_link_layer = qedr_link_layer,
 203         .map_mr_sg = qedr_map_mr_sg,
 204         .mmap = qedr_mmap,
 205         .modify_port = qedr_modify_port,
 206         .modify_qp = qedr_modify_qp,
 207         .modify_srq = qedr_modify_srq,
 208         .poll_cq = qedr_poll_cq,
 209         .post_recv = qedr_post_recv,
 210         .post_send = qedr_post_send,
 211         .post_srq_recv = qedr_post_srq_recv,
 212         .process_mad = qedr_process_mad,
 213         .query_device = qedr_query_device,
 214         .query_pkey = qedr_query_pkey,
 215         .query_port = qedr_query_port,
 216         .query_qp = qedr_query_qp,
 217         .query_srq = qedr_query_srq,
 218         .reg_user_mr = qedr_reg_user_mr,
 219         .req_notify_cq = qedr_arm_cq,
 220         .resize_cq = qedr_resize_cq,
 221
 222         INIT_RDMA_OBJ_SIZE(ib_ah, qedr_ah, ibah),
 223         INIT_RDMA_OBJ_SIZE(ib_pd, qedr_pd, ibpd),
 224         INIT_RDMA_OBJ_SIZE(ib_srq, qedr_srq, ibsrq),
 225         INIT_RDMA_OBJ_SIZE(ib_ucontext, qedr_ucontext, ibucontext),
 226 };
 227
 228 static int qedr_register_device(struct qedr_dev *dev)
 229 {
 230         int rc;
 231
 232         dev->ibdev.node_guid = dev->attr.node_guid;
 233         memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
 234         dev->ibdev.owner = THIS_MODULE;
 235         dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION;
 236
 237         dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
 238                                      QEDR_UVERBS(QUERY_DEVICE) |
 239                                      QEDR_UVERBS(QUERY_PORT) |
 240                                      QEDR_UVERBS(ALLOC_PD) |
 241                                      QEDR_UVERBS(DEALLOC_PD) |
 242                                      QEDR_UVERBS(CREATE_COMP_CHANNEL) |
 243                                      QEDR_UVERBS(CREATE_CQ) |
 244                                      QEDR_UVERBS(RESIZE_CQ) |
 245                                      QEDR_UVERBS(DESTROY_CQ) |
 246                                      QEDR_UVERBS(REQ_NOTIFY_CQ) |
 247                                      QEDR_UVERBS(CREATE_QP) |
 248                                      QEDR_UVERBS(MODIFY_QP) |
 249                                      QEDR_UVERBS(QUERY_QP) |
 250                                      QEDR_UVERBS(DESTROY_QP) |
 251                                      QEDR_UVERBS(CREATE_SRQ) |
 252                                      QEDR_UVERBS(DESTROY_SRQ) |
 253                                      QEDR_UVERBS(QUERY_SRQ) |
 254                                      QEDR_UVERBS(MODIFY_SRQ) |
 255                                      QEDR_UVERBS(POST_SRQ_RECV) |
 256                                      QEDR_UVERBS(REG_MR) |
 257                                      QEDR_UVERBS(DEREG_MR) |
 258                                      QEDR_UVERBS(POLL_CQ) |
 259                                      QEDR_UVERBS(POST_SEND) |
 260                                      QEDR_UVERBS(POST_RECV);
 261
 262         if (IS_IWARP(dev)) {
 263                 rc = qedr_iw_register_device(dev);
 264                 if (rc)
 265                         return rc;
 266         } else {
 267                 qedr_roce_register_device(dev);
 268         }
 269
 270         dev->ibdev.phys_port_cnt = 1;
 271         dev->ibdev.num_comp_vectors = dev->num_cnq;
 272         dev->ibdev.dev.parent = &dev->pdev->dev;
 273
 274         rdma_set_device_sysfs_group(&dev->ibdev, &qedr_attr_group);
 275         ib_set_device_ops(&dev->ibdev, &qedr_dev_ops);
 276
 277         dev->ibdev.driver_id = RDMA_DRIVER_QEDR;
 278         rc = ib_device_set_netdev(&dev->ibdev, dev->ndev, 1);
 279         if (rc)
 280                 return rc;
 281
 282         return ib_register_device(&dev->ibdev, "qedr%d");
 283 }
 284
 285 /* This function allocates fast-path status block memory */
 286 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
 287                              struct qed_sb_info *sb_info, u16 sb_id)
 288 {
 289         struct status_block_e4 *sb_virt;
 290         dma_addr_t sb_phys;
 291         int rc;
 292
 293         sb_virt = dma_alloc_coherent(&dev->pdev->dev,
 294                                      sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
 295         if (!sb_virt)
 296                 return -ENOMEM;
 297
 298         rc = dev->ops->common->sb_init(dev->cdev, sb_info,
 299                                        sb_virt, sb_phys, sb_id,
 300                                        QED_SB_TYPE_CNQ);
 301         if (rc) {
 302                 pr_err("Status block initialization failed\n");
 303                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
 304                                   sb_virt, sb_phys);
 305                 return rc;
 306         }
 307
 308         return 0;
 309 }
 310
 311 static void qedr_free_mem_sb(struct qedr_dev *dev,
 312                              struct qed_sb_info *sb_info, int sb_id)
 313 {
 314         if (sb_info->sb_virt) {
 315                 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
 316                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
 317                                   (void *)sb_info->sb_virt, sb_info->sb_phys);
 318         }
 319 }
 320
 321 static void qedr_free_resources(struct qedr_dev *dev)
 322 {
 323         int i;
 324
 325         if (IS_IWARP(dev))
 326                 destroy_workqueue(dev->iwarp_wq);
 327
 328         for (i = 0; i < dev->num_cnq; i++) {
 329                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 330                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 331         }
 332
 333         kfree(dev->cnq_array);
 334         kfree(dev->sb_array);
 335         kfree(dev->sgid_tbl);
 336 }
 337
 338 static int qedr_alloc_resources(struct qedr_dev *dev)
 339 {
 340         struct qedr_cnq *cnq;
 341         __le16 *cons_pi;
 342         u16 n_entries;
 343         int i, rc;
 344
 345         dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid),
 346                                 GFP_KERNEL);
 347         if (!dev->sgid_tbl)
 348                 return -ENOMEM;
 349
 350         spin_lock_init(&dev->sgid_lock);
 351
 352         if (IS_IWARP(dev)) {
 353                 xa_init_flags(&dev->qps, XA_FLAGS_LOCK_IRQ);
 354                 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
 355         }
 356
 357         /* Allocate Status blocks for CNQ */
 358         dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
 359                                 GFP_KERNEL);
 360         if (!dev->sb_array) {
 361                 rc = -ENOMEM;
 362                 goto err1;
 363         }
 364
 365         dev->cnq_array = kcalloc(dev->num_cnq,
 366                                  sizeof(*dev->cnq_array), GFP_KERNEL);
 367         if (!dev->cnq_array) {
 368                 rc = -ENOMEM;
 369                 goto err2;
 370         }
 371
 372         dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
 373
 374         /* Allocate CNQ PBLs */
 375         n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
 376         for (i = 0; i < dev->num_cnq; i++) {
 377                 cnq = &dev->cnq_array[i];
 378
 379                 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
 380                                        dev->sb_start + i);
 381                 if (rc)
 382                         goto err3;
 383
 384                 rc = dev->ops->common->chain_alloc(dev->cdev,
 385                                                    QED_CHAIN_USE_TO_CONSUME,
 386                                                    QED_CHAIN_MODE_PBL,
 387                                                    QED_CHAIN_CNT_TYPE_U16,
 388                                                    n_entries,
 389                                                    sizeof(struct regpair *),
 390                                                    &cnq->pbl, NULL);
 391                 if (rc)
 392                         goto err4;
 393
 394                 cnq->dev = dev;
 395                 cnq->sb = &dev->sb_array[i];
 396                 cons_pi = dev->sb_array[i].sb_virt->pi_array;
 397                 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
 398                 cnq->index = i;
 399                 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
 400
 401                 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
 402                          i, qed_chain_get_cons_idx(&cnq->pbl));
 403         }
 404
 405         return 0;
 406 err4:
 407         qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 408 err3:
 409         for (--i; i >= 0; i--) {
 410                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 411                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 412         }
 413         kfree(dev->cnq_array);
 414 err2:
 415         kfree(dev->sb_array);
 416 err1:
 417         kfree(dev->sgid_tbl);
 418         return rc;
 419 }
 420
 421 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
 422 {
 423         int rc = pci_enable_atomic_ops_to_root(pdev,
 424                                                PCI_EXP_DEVCAP2_ATOMIC_COMP64);
 425
 426         if (rc) {
 427                 dev->atomic_cap = IB_ATOMIC_NONE;
 428                 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
 429         } else {
 430                 dev->atomic_cap = IB_ATOMIC_GLOB;
 431                 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
 432         }
 433 }
 434
 435 static const struct qed_rdma_ops *qed_ops;
 436
 437 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 438
 439 static irqreturn_t qedr_irq_handler(int irq, void *handle)
 440 {
 441         u16 hw_comp_cons, sw_comp_cons;
 442         struct qedr_cnq *cnq = handle;
 443         struct regpair *cq_handle;
 444         struct qedr_cq *cq;
 445
 446         qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
 447
 448         qed_sb_update_sb_idx(cnq->sb);
 449
 450         hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
 451         sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 452
 453         /* Align protocol-index and chain reads */
 454         rmb();
 455
 456         while (sw_comp_cons != hw_comp_cons) {
 457                 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
 458                 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
 459                                 cq_handle->lo);
 460
 461                 if (cq == NULL) {
 462                         DP_ERR(cnq->dev,
 463                                "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
 464                                cq_handle->hi, cq_handle->lo, sw_comp_cons,
 465                                hw_comp_cons);
 466
 467                         break;
 468                 }
 469
 470                 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
 471                         DP_ERR(cnq->dev,
 472                                "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
 473                                cq_handle->hi, cq_handle->lo, cq);
 474                         break;
 475                 }
 476
 477                 cq->arm_flags = 0;
 478
 479                 if (!cq->destroyed && cq->ibcq.comp_handler)
 480                         (*cq->ibcq.comp_handler)
 481                                 (&cq->ibcq, cq->ibcq.cq_context);
 482
 483                 /* The CQ's CNQ notification counter is checked before
 484                  * destroying the CQ in a busy-wait loop that waits for all of
 485                  * the CQ's CNQ interrupts to be processed. It is increased
 486                  * here, only after the completion handler, to ensure that the
 487                  * the handler is not running when the CQ is destroyed.
 488                  */
 489                 cq->cnq_notif++;
 490
 491                 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 492
 493                 cnq->n_comp++;
 494         }
 495
 496         qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
 497                                       sw_comp_cons);
 498
 499         qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
 500
 501         return IRQ_HANDLED;
 502 }
 503
 504 static void qedr_sync_free_irqs(struct qedr_dev *dev)
 505 {
 506         u32 vector;
 507         int i;
 508
 509         for (i = 0; i < dev->int_info.used_cnt; i++) {
 510                 if (dev->int_info.msix_cnt) {
 511                         vector = dev->int_info.msix[i * dev->num_hwfns].vector;
 512                         synchronize_irq(vector);
 513                         free_irq(vector, &dev->cnq_array[i]);
 514                 }
 515         }
 516
 517         dev->int_info.used_cnt = 0;
 518 }
 519
 520 static int qedr_req_msix_irqs(struct qedr_dev *dev)
 521 {
 522         int i, rc = 0;
 523
 524         if (dev->num_cnq > dev->int_info.msix_cnt) {
 525                 DP_ERR(dev,
 526                        "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
 527                        dev->num_cnq, dev->int_info.msix_cnt);
 528                 return -EINVAL;
 529         }
 530
 531         for (i = 0; i < dev->num_cnq; i++) {
 532                 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
 533                                  qedr_irq_handler, 0, dev->cnq_array[i].name,
 534                                  &dev->cnq_array[i]);
 535                 if (rc) {
 536                         DP_ERR(dev, "Request cnq %d irq failed\n", i);
 537                         qedr_sync_free_irqs(dev);
 538                 } else {
 539                         DP_DEBUG(dev, QEDR_MSG_INIT,
 540                                  "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
 541                                  dev->cnq_array[i].name, i,
 542                                  &dev->cnq_array[i]);
 543                         dev->int_info.used_cnt++;
 544                 }
 545         }
 546
 547         return rc;
 548 }
 549
 550 static int qedr_setup_irqs(struct qedr_dev *dev)
 551 {
 552         int rc;
 553
 554         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
 555
 556         /* Learn Interrupt configuration */
 557         rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
 558         if (rc < 0)
 559                 return rc;
 560
 561         rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
 562         if (rc) {
 563                 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
 564                 return rc;
 565         }
 566
 567         if (dev->int_info.msix_cnt) {
 568                 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
 569                          dev->int_info.msix_cnt);
 570                 rc = qedr_req_msix_irqs(dev);
 571                 if (rc)
 572                         return rc;
 573         }
 574
 575         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
 576
 577         return 0;
 578 }
 579
 580 static int qedr_set_device_attr(struct qedr_dev *dev)
 581 {
 582         struct qed_rdma_device *qed_attr;
 583         struct qedr_device_attr *attr;
 584         u32 page_size;
 585
 586         /* Part 1 - query core capabilities */
 587         qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
 588
 589         /* Part 2 - check capabilities */
 590         page_size = ~dev->attr.page_size_caps + 1;
 591         if (page_size > PAGE_SIZE) {
 592                 DP_ERR(dev,
 593                        "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
 594                        PAGE_SIZE, page_size);
 595                 return -ENODEV;
 596         }
 597
 598         /* Part 3 - copy and update capabilities */
 599         attr = &dev->attr;
 600         attr->vendor_id = qed_attr->vendor_id;
 601         attr->vendor_part_id = qed_attr->vendor_part_id;
 602         attr->hw_ver = qed_attr->hw_ver;
 603         attr->fw_ver = qed_attr->fw_ver;
 604         attr->node_guid = qed_attr->node_guid;
 605         attr->sys_image_guid = qed_attr->sys_image_guid;
 606         attr->max_cnq = qed_attr->max_cnq;
 607         attr->max_sge = qed_attr->max_sge;
 608         attr->max_inline = qed_attr->max_inline;
 609         attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
 610         attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
 611         attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
 612         attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
 613         attr->max_dev_resp_rd_atomic_resc =
 614             qed_attr->max_dev_resp_rd_atomic_resc;
 615         attr->max_cq = qed_attr->max_cq;
 616         attr->max_qp = qed_attr->max_qp;
 617         attr->max_mr = qed_attr->max_mr;
 618         attr->max_mr_size = qed_attr->max_mr_size;
 619         attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
 620         attr->max_mw = qed_attr->max_mw;
 621         attr->max_fmr = qed_attr->max_fmr;
 622         attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
 623         attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
 624         attr->max_pd = qed_attr->max_pd;
 625         attr->max_ah = qed_attr->max_ah;
 626         attr->max_pkey = qed_attr->max_pkey;
 627         attr->max_srq = qed_attr->max_srq;
 628         attr->max_srq_wr = qed_attr->max_srq_wr;
 629         attr->dev_caps = qed_attr->dev_caps;
 630         attr->page_size_caps = qed_attr->page_size_caps;
 631         attr->dev_ack_delay = qed_attr->dev_ack_delay;
 632         attr->reserved_lkey = qed_attr->reserved_lkey;
 633         attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
 634         attr->max_stats_queues = qed_attr->max_stats_queues;
 635
 636         return 0;
 637 }
 638
 639 static void qedr_unaffiliated_event(void *context, u8 event_code)
 640 {
 641         pr_err("unaffiliated event not implemented yet\n");
 642 }
 643
 644 static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
 645 {
 646 #define EVENT_TYPE_NOT_DEFINED  0
 647 #define EVENT_TYPE_CQ           1
 648 #define EVENT_TYPE_QP           2
 649 #define EVENT_TYPE_SRQ          3
 650         struct qedr_dev *dev = (struct qedr_dev *)context;
 651         struct regpair *async_handle = (struct regpair *)fw_handle;
 652         u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
 653         u8 event_type = EVENT_TYPE_NOT_DEFINED;
 654         struct ib_event event;
 655         struct ib_srq *ibsrq;
 656         struct qedr_srq *srq;
 657         unsigned long flags;
 658         struct ib_cq *ibcq;
 659         struct ib_qp *ibqp;
 660         struct qedr_cq *cq;
 661         struct qedr_qp *qp;
 662         u16 srq_id;
 663
 664         if (IS_ROCE(dev)) {
 665                 switch (e_code) {
 666                 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
 667                         event.event = IB_EVENT_CQ_ERR;
 668                         event_type = EVENT_TYPE_CQ;
 669                         break;
 670                 case ROCE_ASYNC_EVENT_SQ_DRAINED:
 671                         event.event = IB_EVENT_SQ_DRAINED;
 672                         event_type = EVENT_TYPE_QP;
 673                         break;
 674                 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
 675                         event.event = IB_EVENT_QP_FATAL;
 676                         event_type = EVENT_TYPE_QP;
 677                         break;
 678                 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
 679                         event.event = IB_EVENT_QP_REQ_ERR;
 680                         event_type = EVENT_TYPE_QP;
 681                         break;
 682                 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
 683                         event.event = IB_EVENT_QP_ACCESS_ERR;
 684                         event_type = EVENT_TYPE_QP;
 685                         break;
 686                 case ROCE_ASYNC_EVENT_SRQ_LIMIT:
 687                         event.event = IB_EVENT_SRQ_LIMIT_REACHED;
 688                         event_type = EVENT_TYPE_SRQ;
 689                         break;
 690                 case ROCE_ASYNC_EVENT_SRQ_EMPTY:
 691                         event.event = IB_EVENT_SRQ_ERR;
 692                         event_type = EVENT_TYPE_SRQ;
 693                         break;
 694                 default:
 695                         DP_ERR(dev, "unsupported event %d on handle=%llx\n",
 696                                e_code, roce_handle64);
 697                 }
 698         } else {
 699                 switch (e_code) {
 700                 case QED_IWARP_EVENT_SRQ_LIMIT:
 701                         event.event = IB_EVENT_SRQ_LIMIT_REACHED;
 702                         event_type = EVENT_TYPE_SRQ;
 703                         break;
 704                 case QED_IWARP_EVENT_SRQ_EMPTY:
 705                         event.event = IB_EVENT_SRQ_ERR;
 706                         event_type = EVENT_TYPE_SRQ;
 707                         break;
 708                 default:
 709                 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
 710                        roce_handle64);
 711                 }
 712         }
 713         switch (event_type) {
 714         case EVENT_TYPE_CQ:
 715                 cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
 716                 if (cq) {
 717                         ibcq = &cq->ibcq;
 718                         if (ibcq->event_handler) {
 719                                 event.device = ibcq->device;
 720                                 event.element.cq = ibcq;
 721                                 ibcq->event_handler(&event, ibcq->cq_context);
 722                         }
 723                 } else {
 724                         WARN(1,
 725                              "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
 726                              roce_handle64);
 727                 }
 728                 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq);
 729                 break;
 730         case EVENT_TYPE_QP:
 731                 qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
 732                 if (qp) {
 733                         ibqp = &qp->ibqp;
 734                         if (ibqp->event_handler) {
 735                                 event.device = ibqp->device;
 736                                 event.element.qp = ibqp;
 737                                 ibqp->event_handler(&event, ibqp->qp_context);
 738                         }
 739                 } else {
 740                         WARN(1,
 741                              "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
 742                              roce_handle64);
 743                 }
 744                 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp);
 745                 break;
 746         case EVENT_TYPE_SRQ:
 747                 srq_id = (u16)roce_handle64;
 748                 xa_lock_irqsave(&dev->srqs, flags);
 749                 srq = xa_load(&dev->srqs, srq_id);
 750                 if (srq) {
 751                         ibsrq = &srq->ibsrq;
 752                         if (ibsrq->event_handler) {
 753                                 event.device = ibsrq->device;
 754                                 event.element.srq = ibsrq;
 755                                 ibsrq->event_handler(&event,
 756                                                      ibsrq->srq_context);
 757                         }
 758                 } else {
 759                         DP_NOTICE(dev,
 760                                   "SRQ event with NULL pointer ibsrq. Handle=%llx\n",
 761                                   roce_handle64);
 762                 }
 763                 xa_unlock_irqrestore(&dev->srqs, flags);
 764                 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq);
 765         default:
 766                 break;
 767         }
 768 }
 769
 770 static int qedr_init_hw(struct qedr_dev *dev)
 771 {
 772         struct qed_rdma_add_user_out_params out_params;
 773         struct qed_rdma_start_in_params *in_params;
 774         struct qed_rdma_cnq_params *cur_pbl;
 775         struct qed_rdma_events events;
 776         dma_addr_t p_phys_table;
 777         u32 page_cnt;
 778         int rc = 0;
 779         int i;
 780
 781         in_params =  kzalloc(sizeof(*in_params), GFP_KERNEL);
 782         if (!in_params) {
 783                 rc = -ENOMEM;
 784                 goto out;
 785         }
 786
 787         in_params->desired_cnq = dev->num_cnq;
 788         for (i = 0; i < dev->num_cnq; i++) {
 789                 cur_pbl = &in_params->cnq_pbl_list[i];
 790
 791                 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
 792                 cur_pbl->num_pbl_pages = page_cnt;
 793
 794                 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
 795                 cur_pbl->pbl_ptr = (u64)p_phys_table;
 796         }
 797
 798         events.affiliated_event = qedr_affiliated_event;
 799         events.unaffiliated_event = qedr_unaffiliated_event;
 800         events.context = dev;
 801
 802         in_params->events = &events;
 803         in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
 804         in_params->max_mtu = dev->ndev->mtu;
 805         dev->iwarp_max_mtu = dev->ndev->mtu;
 806         ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
 807
 808         rc = dev->ops->rdma_init(dev->cdev, in_params);
 809         if (rc)
 810                 goto out;
 811
 812         rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
 813         if (rc)
 814                 goto out;
 815
 816         dev->db_addr = (void __iomem *)(uintptr_t)out_params.dpi_addr;
 817         dev->db_phys_addr = out_params.dpi_phys_addr;
 818         dev->db_size = out_params.dpi_size;
 819         dev->dpi = out_params.dpi;
 820
 821         rc = qedr_set_device_attr(dev);
 822 out:
 823         kfree(in_params);
 824         if (rc)
 825                 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
 826
 827         return rc;
 828 }
 829
 830 static void qedr_stop_hw(struct qedr_dev *dev)
 831 {
 832         dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
 833         dev->ops->rdma_stop(dev->rdma_ctx);
 834 }
 835
 836 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
 837                                  struct net_device *ndev)
 838 {
 839         struct qed_dev_rdma_info dev_info;
 840         struct qedr_dev *dev;
 841         int rc = 0;
 842
 843         dev = ib_alloc_device(qedr_dev, ibdev);
 844         if (!dev) {
 845                 pr_err("Unable to allocate ib device\n");
 846                 return NULL;
 847         }
 848
 849         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
 850
 851         dev->pdev = pdev;
 852         dev->ndev = ndev;
 853         dev->cdev = cdev;
 854
 855         qed_ops = qed_get_rdma_ops();
 856         if (!qed_ops) {
 857                 DP_ERR(dev, "Failed to get qed roce operations\n");
 858                 goto init_err;
 859         }
 860
 861         dev->ops = qed_ops;
 862         rc = qed_ops->fill_dev_info(cdev, &dev_info);
 863         if (rc)
 864                 goto init_err;
 865
 866         dev->user_dpm_enabled = dev_info.user_dpm_enabled;
 867         dev->rdma_type = dev_info.rdma_type;
 868         dev->num_hwfns = dev_info.common.num_hwfns;
 869         dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
 870
 871         dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
 872         if (!dev->num_cnq) {
 873                 DP_ERR(dev, "Failed. At least one CNQ is required.\n");
 874                 rc = -ENOMEM;
 875                 goto init_err;
 876         }
 877
 878         dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
 879
 880         qedr_pci_set_atomic(dev, pdev);
 881
 882         rc = qedr_alloc_resources(dev);
 883         if (rc)
 884                 goto init_err;
 885
 886         rc = qedr_init_hw(dev);
 887         if (rc)
 888                 goto alloc_err;
 889
 890         rc = qedr_setup_irqs(dev);
 891         if (rc)
 892                 goto irq_err;
 893
 894         rc = qedr_register_device(dev);
 895         if (rc) {
 896                 DP_ERR(dev, "Unable to allocate register device\n");
 897                 goto reg_err;
 898         }
 899
 900         if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 901                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
 902
 903         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
 904         return dev;
 905
 906 reg_err:
 907         qedr_sync_free_irqs(dev);
 908 irq_err:
 909         qedr_stop_hw(dev);
 910 alloc_err:
 911         qedr_free_resources(dev);
 912 init_err:
 913         ib_dealloc_device(&dev->ibdev);
 914         DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
 915
 916         return NULL;
 917 }
 918
 919 static void qedr_remove(struct qedr_dev *dev)
 920 {
 921         /* First unregister with stack to stop all the active traffic
 922          * of the registered clients.
 923          */
 924         ib_unregister_device(&dev->ibdev);
 925
 926         qedr_stop_hw(dev);
 927         qedr_sync_free_irqs(dev);
 928         qedr_free_resources(dev);
 929         ib_dealloc_device(&dev->ibdev);
 930 }
 931
 932 static void qedr_close(struct qedr_dev *dev)
 933 {
 934         if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 935                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
 936 }
 937
 938 static void qedr_shutdown(struct qedr_dev *dev)
 939 {
 940         qedr_close(dev);
 941         qedr_remove(dev);
 942 }
 943
 944 static void qedr_open(struct qedr_dev *dev)
 945 {
 946         if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 947                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
 948 }
 949
 950 static void qedr_mac_address_change(struct qedr_dev *dev)
 951 {
 952         union ib_gid *sgid = &dev->sgid_tbl[0];
 953         u8 guid[8], mac_addr[6];
 954         int rc;
 955
 956         /* Update SGID */
 957         ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
 958         guid[0] = mac_addr[0] ^ 2;
 959         guid[1] = mac_addr[1];
 960         guid[2] = mac_addr[2];
 961         guid[3] = 0xff;
 962         guid[4] = 0xfe;
 963         guid[5] = mac_addr[3];
 964         guid[6] = mac_addr[4];
 965         guid[7] = mac_addr[5];
 966         sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 967         memcpy(&sgid->raw[8], guid, sizeof(guid));
 968
 969         /* Update LL2 */
 970         rc = dev->ops->ll2_set_mac_filter(dev->cdev,
 971                                           dev->gsi_ll2_mac_address,
 972                                           dev->ndev->dev_addr);
 973
 974         ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
 975
 976         qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
 977
 978         if (rc)
 979                 DP_ERR(dev, "Error updating mac filter\n");
 980 }
 981
 982 /* event handling via NIC driver ensures that all the NIC specific
 983  * initialization done before RoCE driver notifies
 984  * event to stack.
 985  */
 986 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
 987 {
 988         switch (event) {
 989         case QEDE_UP:
 990                 qedr_open(dev);
 991                 break;
 992         case QEDE_DOWN:
 993                 qedr_close(dev);
 994                 break;
 995         case QEDE_CLOSE:
 996                 qedr_shutdown(dev);
 997                 break;
 998         case QEDE_CHANGE_ADDR:
 999                 qedr_mac_address_change(dev);
1000                 break;
1001         default:
1002                 pr_err("Event not supported\n");
1003         }
1004 }
1005
1006 static struct qedr_driver qedr_drv = {
1007         .name = "qedr_driver",
1008         .add = qedr_add,
1009         .remove = qedr_remove,
1010         .notify = qedr_notify,
1011 };
1012
1013 static int __init qedr_init_module(void)
1014 {
1015         return qede_rdma_register_driver(&qedr_drv);
1016 }
1017
1018 static void __exit qedr_exit_module(void)
1019 {
1020         qede_rdma_unregister_driver(&qedr_drv);
1021 }
1022
1023 module_init(qedr_init_module);
1024 module_exit(qedr_exit_module);