drivers/infiniband/hw/qedr/main.c

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/module.h>
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_addr.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <rdma/iw_cm.h>
  37 #include <rdma/ib_mad.h>
  38 #include <linux/netdevice.h>
  39 #include <linux/iommu.h>
  40 #include <linux/pci.h>
  41 #include <net/addrconf.h>
  42 #include <linux/idr.h>
  43
  44 #include <linux/qed/qed_chain.h>
  45 #include <linux/qed/qed_if.h>
  46 #include "qedr.h"
  47 #include "verbs.h"
  48 #include <rdma/qedr-abi.h>
  49 #include "qedr_iw_cm.h"
  50
  51 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
  52 MODULE_AUTHOR("QLogic Corporation");
  53 MODULE_LICENSE("Dual BSD/GPL");
  54
  55 #define QEDR_WQ_MULTIPLIER_DFT  (3)
  56
  57 static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
  58                                    enum ib_event_type type)
  59 {
  60         struct ib_event ibev;
  61
  62         ibev.device = &dev->ibdev;
  63         ibev.element.port_num = port_num;
  64         ibev.event = type;
  65
  66         ib_dispatch_event(&ibev);
  67 }
  68
  69 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
  70                                             u8 port_num)
  71 {
  72         return IB_LINK_LAYER_ETHERNET;
  73 }
  74
  75 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
  76 {
  77         struct qedr_dev *qedr = get_qedr_dev(ibdev);
  78         u32 fw_ver = (u32)qedr->attr.fw_ver;
  79
  80         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d. %d. %d. %d",
  81                  (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
  82                  (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
  83 }
  84
  85 static struct net_device *qedr_get_netdev(struct ib_device *dev, u8 port_num)
  86 {
  87         struct qedr_dev *qdev;
  88
  89         qdev = get_qedr_dev(dev);
  90         dev_hold(qdev->ndev);
  91
  92         /* The HW vendor's device driver must guarantee
  93          * that this function returns NULL before the net device has finished
  94          * NETDEV_UNREGISTER state.
  95          */
  96         return qdev->ndev;
  97 }
  98
  99 static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num,
 100                                     struct ib_port_immutable *immutable)
 101 {
 102         struct ib_port_attr attr;
 103         int err;
 104
 105         err = qedr_query_port(ibdev, port_num, &attr);
 106         if (err)
 107                 return err;
 108
 109         immutable->pkey_tbl_len = attr.pkey_tbl_len;
 110         immutable->gid_tbl_len = attr.gid_tbl_len;
 111         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
 112             RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
 113         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
 114
 115         return 0;
 116 }
 117
 118 static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num,
 119                                   struct ib_port_immutable *immutable)
 120 {
 121         struct ib_port_attr attr;
 122         int err;
 123
 124         err = qedr_query_port(ibdev, port_num, &attr);
 125         if (err)
 126                 return err;
 127
 128         immutable->pkey_tbl_len = 1;
 129         immutable->gid_tbl_len = 1;
 130         immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
 131         immutable->max_mad_size = 0;
 132
 133         return 0;
 134 }
 135
 136 /* QEDR sysfs interface */
 137 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
 138                            char *buf)
 139 {
 140         struct qedr_dev *dev =
 141                 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
 142
 143         return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
 144 }
 145 static DEVICE_ATTR_RO(hw_rev);
 146
 147 static ssize_t hca_type_show(struct device *device,
 148                              struct device_attribute *attr, char *buf)
 149 {
 150         return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
 151 }
 152 static DEVICE_ATTR_RO(hca_type);
 153
 154 static struct attribute *qedr_attributes[] = {
 155         &dev_attr_hw_rev.attr,
 156         &dev_attr_hca_type.attr,
 157         NULL
 158 };
 159
 160 static const struct attribute_group qedr_attr_group = {
 161         .attrs = qedr_attributes,
 162 };
 163
 164 static const struct ib_device_ops qedr_iw_dev_ops = {
 165         .get_port_immutable = qedr_iw_port_immutable,
 166         .query_gid = qedr_iw_query_gid,
 167 };
 168
 169 static int qedr_iw_register_device(struct qedr_dev *dev)
 170 {
 171         dev->ibdev.node_type = RDMA_NODE_RNIC;
 172
 173         ib_set_device_ops(&dev->ibdev, &qedr_iw_dev_ops);
 174
 175         dev->ibdev.iwcm = kzalloc(sizeof(*dev->ibdev.iwcm), GFP_KERNEL);
 176         if (!dev->ibdev.iwcm)
 177                 return -ENOMEM;
 178
 179         dev->ibdev.iwcm->connect = qedr_iw_connect;
 180         dev->ibdev.iwcm->accept = qedr_iw_accept;
 181         dev->ibdev.iwcm->reject = qedr_iw_reject;
 182         dev->ibdev.iwcm->create_listen = qedr_iw_create_listen;
 183         dev->ibdev.iwcm->destroy_listen = qedr_iw_destroy_listen;
 184         dev->ibdev.iwcm->add_ref = qedr_iw_qp_add_ref;
 185         dev->ibdev.iwcm->rem_ref = qedr_iw_qp_rem_ref;
 186         dev->ibdev.iwcm->get_qp = qedr_iw_get_qp;
 187
 188         memcpy(dev->ibdev.iwcm->ifname,
 189                dev->ndev->name, sizeof(dev->ibdev.iwcm->ifname));
 190
 191         return 0;
 192 }
 193
 194 static const struct ib_device_ops qedr_roce_dev_ops = {
 195         .get_port_immutable = qedr_roce_port_immutable,
 196 };
 197
 198 static void qedr_roce_register_device(struct qedr_dev *dev)
 199 {
 200         dev->ibdev.node_type = RDMA_NODE_IB_CA;
 201
 202         ib_set_device_ops(&dev->ibdev, &qedr_roce_dev_ops);
 203 }
 204
 205 static const struct ib_device_ops qedr_dev_ops = {
 206         .alloc_mr = qedr_alloc_mr,
 207         .alloc_pd = qedr_alloc_pd,
 208         .alloc_ucontext = qedr_alloc_ucontext,
 209         .create_ah = qedr_create_ah,
 210         .create_cq = qedr_create_cq,
 211         .create_qp = qedr_create_qp,
 212         .create_srq = qedr_create_srq,
 213         .dealloc_pd = qedr_dealloc_pd,
 214         .dealloc_ucontext = qedr_dealloc_ucontext,
 215         .dereg_mr = qedr_dereg_mr,
 216         .destroy_ah = qedr_destroy_ah,
 217         .destroy_cq = qedr_destroy_cq,
 218         .destroy_qp = qedr_destroy_qp,
 219         .destroy_srq = qedr_destroy_srq,
 220         .get_dev_fw_str = qedr_get_dev_fw_str,
 221         .get_dma_mr = qedr_get_dma_mr,
 222         .get_link_layer = qedr_link_layer,
 223         .get_netdev = qedr_get_netdev,
 224         .map_mr_sg = qedr_map_mr_sg,
 225         .mmap = qedr_mmap,
 226         .modify_port = qedr_modify_port,
 227         .modify_qp = qedr_modify_qp,
 228         .modify_srq = qedr_modify_srq,
 229         .poll_cq = qedr_poll_cq,
 230         .post_recv = qedr_post_recv,
 231         .post_send = qedr_post_send,
 232         .post_srq_recv = qedr_post_srq_recv,
 233         .process_mad = qedr_process_mad,
 234         .query_device = qedr_query_device,
 235         .query_pkey = qedr_query_pkey,
 236         .query_port = qedr_query_port,
 237         .query_qp = qedr_query_qp,
 238         .query_srq = qedr_query_srq,
 239         .reg_user_mr = qedr_reg_user_mr,
 240         .req_notify_cq = qedr_arm_cq,
 241         .resize_cq = qedr_resize_cq,
 242         INIT_RDMA_OBJ_SIZE(ib_pd, qedr_pd, ibpd),
 243         INIT_RDMA_OBJ_SIZE(ib_ucontext, qedr_ucontext, ibucontext),
 244 };
 245
 246 static int qedr_register_device(struct qedr_dev *dev)
 247 {
 248         int rc;
 249
 250         dev->ibdev.node_guid = dev->attr.node_guid;
 251         memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
 252         dev->ibdev.owner = THIS_MODULE;
 253         dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION;
 254
 255         dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
 256                                      QEDR_UVERBS(QUERY_DEVICE) |
 257                                      QEDR_UVERBS(QUERY_PORT) |
 258                                      QEDR_UVERBS(ALLOC_PD) |
 259                                      QEDR_UVERBS(DEALLOC_PD) |
 260                                      QEDR_UVERBS(CREATE_COMP_CHANNEL) |
 261                                      QEDR_UVERBS(CREATE_CQ) |
 262                                      QEDR_UVERBS(RESIZE_CQ) |
 263                                      QEDR_UVERBS(DESTROY_CQ) |
 264                                      QEDR_UVERBS(REQ_NOTIFY_CQ) |
 265                                      QEDR_UVERBS(CREATE_QP) |
 266                                      QEDR_UVERBS(MODIFY_QP) |
 267                                      QEDR_UVERBS(QUERY_QP) |
 268                                      QEDR_UVERBS(DESTROY_QP) |
 269                                      QEDR_UVERBS(CREATE_SRQ) |
 270                                      QEDR_UVERBS(DESTROY_SRQ) |
 271                                      QEDR_UVERBS(QUERY_SRQ) |
 272                                      QEDR_UVERBS(MODIFY_SRQ) |
 273                                      QEDR_UVERBS(POST_SRQ_RECV) |
 274                                      QEDR_UVERBS(REG_MR) |
 275                                      QEDR_UVERBS(DEREG_MR) |
 276                                      QEDR_UVERBS(POLL_CQ) |
 277                                      QEDR_UVERBS(POST_SEND) |
 278                                      QEDR_UVERBS(POST_RECV);
 279
 280         if (IS_IWARP(dev)) {
 281                 rc = qedr_iw_register_device(dev);
 282                 if (rc)
 283                         return rc;
 284         } else {
 285                 qedr_roce_register_device(dev);
 286         }
 287
 288         dev->ibdev.phys_port_cnt = 1;
 289         dev->ibdev.num_comp_vectors = dev->num_cnq;
 290         dev->ibdev.dev.parent = &dev->pdev->dev;
 291
 292         rdma_set_device_sysfs_group(&dev->ibdev, &qedr_attr_group);
 293         ib_set_device_ops(&dev->ibdev, &qedr_dev_ops);
 294
 295         dev->ibdev.driver_id = RDMA_DRIVER_QEDR;
 296         return ib_register_device(&dev->ibdev, "qedr%d");
 297 }
 298
 299 /* This function allocates fast-path status block memory */
 300 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
 301                              struct qed_sb_info *sb_info, u16 sb_id)
 302 {
 303         struct status_block_e4 *sb_virt;
 304         dma_addr_t sb_phys;
 305         int rc;
 306
 307         sb_virt = dma_alloc_coherent(&dev->pdev->dev,
 308                                      sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
 309         if (!sb_virt)
 310                 return -ENOMEM;
 311
 312         rc = dev->ops->common->sb_init(dev->cdev, sb_info,
 313                                        sb_virt, sb_phys, sb_id,
 314                                        QED_SB_TYPE_CNQ);
 315         if (rc) {
 316                 pr_err("Status block initialization failed\n");
 317                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
 318                                   sb_virt, sb_phys);
 319                 return rc;
 320         }
 321
 322         return 0;
 323 }
 324
 325 static void qedr_free_mem_sb(struct qedr_dev *dev,
 326                              struct qed_sb_info *sb_info, int sb_id)
 327 {
 328         if (sb_info->sb_virt) {
 329                 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
 330                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
 331                                   (void *)sb_info->sb_virt, sb_info->sb_phys);
 332         }
 333 }
 334
 335 static void qedr_free_resources(struct qedr_dev *dev)
 336 {
 337         int i;
 338
 339         if (IS_IWARP(dev))
 340                 destroy_workqueue(dev->iwarp_wq);
 341
 342         for (i = 0; i < dev->num_cnq; i++) {
 343                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 344                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 345         }
 346
 347         kfree(dev->cnq_array);
 348         kfree(dev->sb_array);
 349         kfree(dev->sgid_tbl);
 350 }
 351
 352 static int qedr_alloc_resources(struct qedr_dev *dev)
 353 {
 354         struct qedr_cnq *cnq;
 355         __le16 *cons_pi;
 356         u16 n_entries;
 357         int i, rc;
 358
 359         dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid),
 360                                 GFP_KERNEL);
 361         if (!dev->sgid_tbl)
 362                 return -ENOMEM;
 363
 364         spin_lock_init(&dev->sgid_lock);
 365
 366         if (IS_IWARP(dev)) {
 367                 spin_lock_init(&dev->qpidr.idr_lock);
 368                 idr_init(&dev->qpidr.idr);
 369                 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
 370         }
 371
 372         /* Allocate Status blocks for CNQ */
 373         dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
 374                                 GFP_KERNEL);
 375         if (!dev->sb_array) {
 376                 rc = -ENOMEM;
 377                 goto err1;
 378         }
 379
 380         dev->cnq_array = kcalloc(dev->num_cnq,
 381                                  sizeof(*dev->cnq_array), GFP_KERNEL);
 382         if (!dev->cnq_array) {
 383                 rc = -ENOMEM;
 384                 goto err2;
 385         }
 386
 387         dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
 388
 389         /* Allocate CNQ PBLs */
 390         n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
 391         for (i = 0; i < dev->num_cnq; i++) {
 392                 cnq = &dev->cnq_array[i];
 393
 394                 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
 395                                        dev->sb_start + i);
 396                 if (rc)
 397                         goto err3;
 398
 399                 rc = dev->ops->common->chain_alloc(dev->cdev,
 400                                                    QED_CHAIN_USE_TO_CONSUME,
 401                                                    QED_CHAIN_MODE_PBL,
 402                                                    QED_CHAIN_CNT_TYPE_U16,
 403                                                    n_entries,
 404                                                    sizeof(struct regpair *),
 405                                                    &cnq->pbl, NULL);
 406                 if (rc)
 407                         goto err4;
 408
 409                 cnq->dev = dev;
 410                 cnq->sb = &dev->sb_array[i];
 411                 cons_pi = dev->sb_array[i].sb_virt->pi_array;
 412                 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
 413                 cnq->index = i;
 414                 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
 415
 416                 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
 417                          i, qed_chain_get_cons_idx(&cnq->pbl));
 418         }
 419
 420         return 0;
 421 err4:
 422         qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 423 err3:
 424         for (--i; i >= 0; i--) {
 425                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 426                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 427         }
 428         kfree(dev->cnq_array);
 429 err2:
 430         kfree(dev->sb_array);
 431 err1:
 432         kfree(dev->sgid_tbl);
 433         return rc;
 434 }
 435
 436 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
 437 {
 438         int rc = pci_enable_atomic_ops_to_root(pdev,
 439                                                PCI_EXP_DEVCAP2_ATOMIC_COMP64);
 440
 441         if (rc) {
 442                 dev->atomic_cap = IB_ATOMIC_NONE;
 443                 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
 444         } else {
 445                 dev->atomic_cap = IB_ATOMIC_GLOB;
 446                 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
 447         }
 448 }
 449
 450 static const struct qed_rdma_ops *qed_ops;
 451
 452 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 453
 454 static irqreturn_t qedr_irq_handler(int irq, void *handle)
 455 {
 456         u16 hw_comp_cons, sw_comp_cons;
 457         struct qedr_cnq *cnq = handle;
 458         struct regpair *cq_handle;
 459         struct qedr_cq *cq;
 460
 461         qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
 462
 463         qed_sb_update_sb_idx(cnq->sb);
 464
 465         hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
 466         sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 467
 468         /* Align protocol-index and chain reads */
 469         rmb();
 470
 471         while (sw_comp_cons != hw_comp_cons) {
 472                 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
 473                 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
 474                                 cq_handle->lo);
 475
 476                 if (cq == NULL) {
 477                         DP_ERR(cnq->dev,
 478                                "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
 479                                cq_handle->hi, cq_handle->lo, sw_comp_cons,
 480                                hw_comp_cons);
 481
 482                         break;
 483                 }
 484
 485                 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
 486                         DP_ERR(cnq->dev,
 487                                "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
 488                                cq_handle->hi, cq_handle->lo, cq);
 489                         break;
 490                 }
 491
 492                 cq->arm_flags = 0;
 493
 494                 if (!cq->destroyed && cq->ibcq.comp_handler)
 495                         (*cq->ibcq.comp_handler)
 496                                 (&cq->ibcq, cq->ibcq.cq_context);
 497
 498                 /* The CQ's CNQ notification counter is checked before
 499                  * destroying the CQ in a busy-wait loop that waits for all of
 500                  * the CQ's CNQ interrupts to be processed. It is increased
 501                  * here, only after the completion handler, to ensure that the
 502                  * the handler is not running when the CQ is destroyed.
 503                  */
 504                 cq->cnq_notif++;
 505
 506                 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 507
 508                 cnq->n_comp++;
 509         }
 510
 511         qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
 512                                       sw_comp_cons);
 513
 514         qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
 515
 516         return IRQ_HANDLED;
 517 }
 518
 519 static void qedr_sync_free_irqs(struct qedr_dev *dev)
 520 {
 521         u32 vector;
 522         int i;
 523
 524         for (i = 0; i < dev->int_info.used_cnt; i++) {
 525                 if (dev->int_info.msix_cnt) {
 526                         vector = dev->int_info.msix[i * dev->num_hwfns].vector;
 527                         synchronize_irq(vector);
 528                         free_irq(vector, &dev->cnq_array[i]);
 529                 }
 530         }
 531
 532         dev->int_info.used_cnt = 0;
 533 }
 534
 535 static int qedr_req_msix_irqs(struct qedr_dev *dev)
 536 {
 537         int i, rc = 0;
 538
 539         if (dev->num_cnq > dev->int_info.msix_cnt) {
 540                 DP_ERR(dev,
 541                        "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
 542                        dev->num_cnq, dev->int_info.msix_cnt);
 543                 return -EINVAL;
 544         }
 545
 546         for (i = 0; i < dev->num_cnq; i++) {
 547                 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
 548                                  qedr_irq_handler, 0, dev->cnq_array[i].name,
 549                                  &dev->cnq_array[i]);
 550                 if (rc) {
 551                         DP_ERR(dev, "Request cnq %d irq failed\n", i);
 552                         qedr_sync_free_irqs(dev);
 553                 } else {
 554                         DP_DEBUG(dev, QEDR_MSG_INIT,
 555                                  "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
 556                                  dev->cnq_array[i].name, i,
 557                                  &dev->cnq_array[i]);
 558                         dev->int_info.used_cnt++;
 559                 }
 560         }
 561
 562         return rc;
 563 }
 564
 565 static int qedr_setup_irqs(struct qedr_dev *dev)
 566 {
 567         int rc;
 568
 569         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
 570
 571         /* Learn Interrupt configuration */
 572         rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
 573         if (rc < 0)
 574                 return rc;
 575
 576         rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
 577         if (rc) {
 578                 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
 579                 return rc;
 580         }
 581
 582         if (dev->int_info.msix_cnt) {
 583                 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
 584                          dev->int_info.msix_cnt);
 585                 rc = qedr_req_msix_irqs(dev);
 586                 if (rc)
 587                         return rc;
 588         }
 589
 590         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
 591
 592         return 0;
 593 }
 594
 595 static int qedr_set_device_attr(struct qedr_dev *dev)
 596 {
 597         struct qed_rdma_device *qed_attr;
 598         struct qedr_device_attr *attr;
 599         u32 page_size;
 600
 601         /* Part 1 - query core capabilities */
 602         qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
 603
 604         /* Part 2 - check capabilities */
 605         page_size = ~dev->attr.page_size_caps + 1;
 606         if (page_size > PAGE_SIZE) {
 607                 DP_ERR(dev,
 608                        "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
 609                        PAGE_SIZE, page_size);
 610                 return -ENODEV;
 611         }
 612
 613         /* Part 3 - copy and update capabilities */
 614         attr = &dev->attr;
 615         attr->vendor_id = qed_attr->vendor_id;
 616         attr->vendor_part_id = qed_attr->vendor_part_id;
 617         attr->hw_ver = qed_attr->hw_ver;
 618         attr->fw_ver = qed_attr->fw_ver;
 619         attr->node_guid = qed_attr->node_guid;
 620         attr->sys_image_guid = qed_attr->sys_image_guid;
 621         attr->max_cnq = qed_attr->max_cnq;
 622         attr->max_sge = qed_attr->max_sge;
 623         attr->max_inline = qed_attr->max_inline;
 624         attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
 625         attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
 626         attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
 627         attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
 628         attr->max_dev_resp_rd_atomic_resc =
 629             qed_attr->max_dev_resp_rd_atomic_resc;
 630         attr->max_cq = qed_attr->max_cq;
 631         attr->max_qp = qed_attr->max_qp;
 632         attr->max_mr = qed_attr->max_mr;
 633         attr->max_mr_size = qed_attr->max_mr_size;
 634         attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
 635         attr->max_mw = qed_attr->max_mw;
 636         attr->max_fmr = qed_attr->max_fmr;
 637         attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
 638         attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
 639         attr->max_pd = qed_attr->max_pd;
 640         attr->max_ah = qed_attr->max_ah;
 641         attr->max_pkey = qed_attr->max_pkey;
 642         attr->max_srq = qed_attr->max_srq;
 643         attr->max_srq_wr = qed_attr->max_srq_wr;
 644         attr->dev_caps = qed_attr->dev_caps;
 645         attr->page_size_caps = qed_attr->page_size_caps;
 646         attr->dev_ack_delay = qed_attr->dev_ack_delay;
 647         attr->reserved_lkey = qed_attr->reserved_lkey;
 648         attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
 649         attr->max_stats_queues = qed_attr->max_stats_queues;
 650
 651         return 0;
 652 }
 653
 654 static void qedr_unaffiliated_event(void *context, u8 event_code)
 655 {
 656         pr_err("unaffiliated event not implemented yet\n");
 657 }
 658
 659 static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
 660 {
 661 #define EVENT_TYPE_NOT_DEFINED  0
 662 #define EVENT_TYPE_CQ           1
 663 #define EVENT_TYPE_QP           2
 664 #define EVENT_TYPE_SRQ          3
 665         struct qedr_dev *dev = (struct qedr_dev *)context;
 666         struct regpair *async_handle = (struct regpair *)fw_handle;
 667         u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
 668         u8 event_type = EVENT_TYPE_NOT_DEFINED;
 669         struct ib_event event;
 670         struct ib_srq *ibsrq;
 671         struct qedr_srq *srq;
 672         unsigned long flags;
 673         struct ib_cq *ibcq;
 674         struct ib_qp *ibqp;
 675         struct qedr_cq *cq;
 676         struct qedr_qp *qp;
 677         u16 srq_id;
 678
 679         if (IS_ROCE(dev)) {
 680                 switch (e_code) {
 681                 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
 682                         event.event = IB_EVENT_CQ_ERR;
 683                         event_type = EVENT_TYPE_CQ;
 684                         break;
 685                 case ROCE_ASYNC_EVENT_SQ_DRAINED:
 686                         event.event = IB_EVENT_SQ_DRAINED;
 687                         event_type = EVENT_TYPE_QP;
 688                         break;
 689                 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
 690                         event.event = IB_EVENT_QP_FATAL;
 691                         event_type = EVENT_TYPE_QP;
 692                         break;
 693                 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
 694                         event.event = IB_EVENT_QP_REQ_ERR;
 695                         event_type = EVENT_TYPE_QP;
 696                         break;
 697                 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
 698                         event.event = IB_EVENT_QP_ACCESS_ERR;
 699                         event_type = EVENT_TYPE_QP;
 700                         break;
 701                 case ROCE_ASYNC_EVENT_SRQ_LIMIT:
 702                         event.event = IB_EVENT_SRQ_LIMIT_REACHED;
 703                         event_type = EVENT_TYPE_SRQ;
 704                         break;
 705                 case ROCE_ASYNC_EVENT_SRQ_EMPTY:
 706                         event.event = IB_EVENT_SRQ_ERR;
 707                         event_type = EVENT_TYPE_SRQ;
 708                         break;
 709                 default:
 710                         DP_ERR(dev, "unsupported event %d on handle=%llx\n",
 711                                e_code, roce_handle64);
 712                 }
 713         } else {
 714                 switch (e_code) {
 715                 case QED_IWARP_EVENT_SRQ_LIMIT:
 716                         event.event = IB_EVENT_SRQ_LIMIT_REACHED;
 717                         event_type = EVENT_TYPE_SRQ;
 718                         break;
 719                 case QED_IWARP_EVENT_SRQ_EMPTY:
 720                         event.event = IB_EVENT_SRQ_ERR;
 721                         event_type = EVENT_TYPE_SRQ;
 722                         break;
 723                 default:
 724                 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
 725                        roce_handle64);
 726                 }
 727         }
 728         switch (event_type) {
 729         case EVENT_TYPE_CQ:
 730                 cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
 731                 if (cq) {
 732                         ibcq = &cq->ibcq;
 733                         if (ibcq->event_handler) {
 734                                 event.device = ibcq->device;
 735                                 event.element.cq = ibcq;
 736                                 ibcq->event_handler(&event, ibcq->cq_context);
 737                         }
 738                 } else {
 739                         WARN(1,
 740                              "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
 741                              roce_handle64);
 742                 }
 743                 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq);
 744                 break;
 745         case EVENT_TYPE_QP:
 746                 qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
 747                 if (qp) {
 748                         ibqp = &qp->ibqp;
 749                         if (ibqp->event_handler) {
 750                                 event.device = ibqp->device;
 751                                 event.element.qp = ibqp;
 752                                 ibqp->event_handler(&event, ibqp->qp_context);
 753                         }
 754                 } else {
 755                         WARN(1,
 756                              "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
 757                              roce_handle64);
 758                 }
 759                 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp);
 760                 break;
 761         case EVENT_TYPE_SRQ:
 762                 srq_id = (u16)roce_handle64;
 763                 spin_lock_irqsave(&dev->srqidr.idr_lock, flags);
 764                 srq = idr_find(&dev->srqidr.idr, srq_id);
 765                 if (srq) {
 766                         ibsrq = &srq->ibsrq;
 767                         if (ibsrq->event_handler) {
 768                                 event.device = ibsrq->device;
 769                                 event.element.srq = ibsrq;
 770                                 ibsrq->event_handler(&event,
 771                                                      ibsrq->srq_context);
 772                         }
 773                 } else {
 774                         DP_NOTICE(dev,
 775                                   "SRQ event with NULL pointer ibsrq. Handle=%llx\n",
 776                                   roce_handle64);
 777                 }
 778                 spin_unlock_irqrestore(&dev->srqidr.idr_lock, flags);
 779                 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq);
 780         default:
 781                 break;
 782         }
 783 }
 784
 785 static int qedr_init_hw(struct qedr_dev *dev)
 786 {
 787         struct qed_rdma_add_user_out_params out_params;
 788         struct qed_rdma_start_in_params *in_params;
 789         struct qed_rdma_cnq_params *cur_pbl;
 790         struct qed_rdma_events events;
 791         dma_addr_t p_phys_table;
 792         u32 page_cnt;
 793         int rc = 0;
 794         int i;
 795
 796         in_params =  kzalloc(sizeof(*in_params), GFP_KERNEL);
 797         if (!in_params) {
 798                 rc = -ENOMEM;
 799                 goto out;
 800         }
 801
 802         in_params->desired_cnq = dev->num_cnq;
 803         for (i = 0; i < dev->num_cnq; i++) {
 804                 cur_pbl = &in_params->cnq_pbl_list[i];
 805
 806                 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
 807                 cur_pbl->num_pbl_pages = page_cnt;
 808
 809                 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
 810                 cur_pbl->pbl_ptr = (u64)p_phys_table;
 811         }
 812
 813         events.affiliated_event = qedr_affiliated_event;
 814         events.unaffiliated_event = qedr_unaffiliated_event;
 815         events.context = dev;
 816
 817         in_params->events = &events;
 818         in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
 819         in_params->max_mtu = dev->ndev->mtu;
 820         dev->iwarp_max_mtu = dev->ndev->mtu;
 821         ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
 822
 823         rc = dev->ops->rdma_init(dev->cdev, in_params);
 824         if (rc)
 825                 goto out;
 826
 827         rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
 828         if (rc)
 829                 goto out;
 830
 831         dev->db_addr = (void __iomem *)(uintptr_t)out_params.dpi_addr;
 832         dev->db_phys_addr = out_params.dpi_phys_addr;
 833         dev->db_size = out_params.dpi_size;
 834         dev->dpi = out_params.dpi;
 835
 836         rc = qedr_set_device_attr(dev);
 837 out:
 838         kfree(in_params);
 839         if (rc)
 840                 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
 841
 842         return rc;
 843 }
 844
 845 static void qedr_stop_hw(struct qedr_dev *dev)
 846 {
 847         dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
 848         dev->ops->rdma_stop(dev->rdma_ctx);
 849 }
 850
 851 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
 852                                  struct net_device *ndev)
 853 {
 854         struct qed_dev_rdma_info dev_info;
 855         struct qedr_dev *dev;
 856         int rc = 0;
 857
 858         dev = ib_alloc_device(qedr_dev, ibdev);
 859         if (!dev) {
 860                 pr_err("Unable to allocate ib device\n");
 861                 return NULL;
 862         }
 863
 864         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
 865
 866         dev->pdev = pdev;
 867         dev->ndev = ndev;
 868         dev->cdev = cdev;
 869
 870         qed_ops = qed_get_rdma_ops();
 871         if (!qed_ops) {
 872                 DP_ERR(dev, "Failed to get qed roce operations\n");
 873                 goto init_err;
 874         }
 875
 876         dev->ops = qed_ops;
 877         rc = qed_ops->fill_dev_info(cdev, &dev_info);
 878         if (rc)
 879                 goto init_err;
 880
 881         dev->user_dpm_enabled = dev_info.user_dpm_enabled;
 882         dev->rdma_type = dev_info.rdma_type;
 883         dev->num_hwfns = dev_info.common.num_hwfns;
 884         dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
 885
 886         dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
 887         if (!dev->num_cnq) {
 888                 DP_ERR(dev, "Failed. At least one CNQ is required.\n");
 889                 rc = -ENOMEM;
 890                 goto init_err;
 891         }
 892
 893         dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
 894
 895         qedr_pci_set_atomic(dev, pdev);
 896
 897         rc = qedr_alloc_resources(dev);
 898         if (rc)
 899                 goto init_err;
 900
 901         rc = qedr_init_hw(dev);
 902         if (rc)
 903                 goto alloc_err;
 904
 905         rc = qedr_setup_irqs(dev);
 906         if (rc)
 907                 goto irq_err;
 908
 909         rc = qedr_register_device(dev);
 910         if (rc) {
 911                 DP_ERR(dev, "Unable to allocate register device\n");
 912                 goto reg_err;
 913         }
 914
 915         if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 916                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
 917
 918         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
 919         return dev;
 920
 921 reg_err:
 922         qedr_sync_free_irqs(dev);
 923 irq_err:
 924         qedr_stop_hw(dev);
 925 alloc_err:
 926         qedr_free_resources(dev);
 927 init_err:
 928         ib_dealloc_device(&dev->ibdev);
 929         DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
 930
 931         return NULL;
 932 }
 933
 934 static void qedr_remove(struct qedr_dev *dev)
 935 {
 936         /* First unregister with stack to stop all the active traffic
 937          * of the registered clients.
 938          */
 939         ib_unregister_device(&dev->ibdev);
 940
 941         qedr_stop_hw(dev);
 942         qedr_sync_free_irqs(dev);
 943         qedr_free_resources(dev);
 944         ib_dealloc_device(&dev->ibdev);
 945 }
 946
 947 static void qedr_close(struct qedr_dev *dev)
 948 {
 949         if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 950                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
 951 }
 952
 953 static void qedr_shutdown(struct qedr_dev *dev)
 954 {
 955         qedr_close(dev);
 956         qedr_remove(dev);
 957 }
 958
 959 static void qedr_open(struct qedr_dev *dev)
 960 {
 961         if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
 962                 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
 963 }
 964
 965 static void qedr_mac_address_change(struct qedr_dev *dev)
 966 {
 967         union ib_gid *sgid = &dev->sgid_tbl[0];
 968         u8 guid[8], mac_addr[6];
 969         int rc;
 970
 971         /* Update SGID */
 972         ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
 973         guid[0] = mac_addr[0] ^ 2;
 974         guid[1] = mac_addr[1];
 975         guid[2] = mac_addr[2];
 976         guid[3] = 0xff;
 977         guid[4] = 0xfe;
 978         guid[5] = mac_addr[3];
 979         guid[6] = mac_addr[4];
 980         guid[7] = mac_addr[5];
 981         sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 982         memcpy(&sgid->raw[8], guid, sizeof(guid));
 983
 984         /* Update LL2 */
 985         rc = dev->ops->ll2_set_mac_filter(dev->cdev,
 986                                           dev->gsi_ll2_mac_address,
 987                                           dev->ndev->dev_addr);
 988
 989         ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
 990
 991         qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
 992
 993         if (rc)
 994                 DP_ERR(dev, "Error updating mac filter\n");
 995 }
 996
 997 /* event handling via NIC driver ensures that all the NIC specific
 998  * initialization done before RoCE driver notifies
 999  * event to stack.
1000  */
1001 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
1002 {
1003         switch (event) {
1004         case QEDE_UP:
1005                 qedr_open(dev);
1006                 break;
1007         case QEDE_DOWN:
1008                 qedr_close(dev);
1009                 break;
1010         case QEDE_CLOSE:
1011                 qedr_shutdown(dev);
1012                 break;
1013         case QEDE_CHANGE_ADDR:
1014                 qedr_mac_address_change(dev);
1015                 break;
1016         default:
1017                 pr_err("Event not supported\n");
1018         }
1019 }
1020
1021 static struct qedr_driver qedr_drv = {
1022         .name = "qedr_driver",
1023         .add = qedr_add,
1024         .remove = qedr_remove,
1025         .notify = qedr_notify,
1026 };
1027
1028 static int __init qedr_init_module(void)
1029 {
1030         return qede_rdma_register_driver(&qedr_drv);
1031 }
1032
1033 static void __exit qedr_exit_module(void)
1034 {
1035         qede_rdma_unregister_driver(&qedr_drv);
1036 }
1037
1038 module_init(qedr_init_module);
1039 module_exit(qedr_exit_module);