fce1c6db393b121b2c836ff632f3fa973062cbfc
[sfrench/cifs-2.6.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include "mlx5_ib.h"
38
39 /* not supported currently */
40 static int wq_signature;
41
42 enum {
43         MLX5_IB_ACK_REQ_FREQ    = 8,
44 };
45
46 enum {
47         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
48         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
49         MLX5_IB_LINK_TYPE_IB            = 0,
50         MLX5_IB_LINK_TYPE_ETH           = 1
51 };
52
53 enum {
54         MLX5_IB_SQ_STRIDE       = 6,
55 };
56
57 static const u32 mlx5_ib_opcode[] = {
58         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
59         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
60         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
61         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
62         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
63         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
64         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
65         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
66         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
67         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
68         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
69         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
70         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
71         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
72 };
73
74 struct mlx5_wqe_eth_pad {
75         u8 rsvd0[16];
76 };
77
78 enum raw_qp_set_mask_map {
79         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
80         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
81 };
82
83 struct mlx5_modify_raw_qp_param {
84         u16 operation;
85
86         u32 set_mask; /* raw_qp_set_mask_map */
87         u32 rate_limit;
88         u8 rq_q_ctr_id;
89 };
90
91 static void get_cqs(enum ib_qp_type qp_type,
92                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
93                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
94
95 static int is_qp0(enum ib_qp_type qp_type)
96 {
97         return qp_type == IB_QPT_SMI;
98 }
99
100 static int is_sqp(enum ib_qp_type qp_type)
101 {
102         return is_qp0(qp_type) || is_qp1(qp_type);
103 }
104
105 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
106 {
107         return mlx5_buf_offset(&qp->buf, offset);
108 }
109
110 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
111 {
112         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
113 }
114
115 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
116 {
117         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
118 }
119
120 /**
121  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
122  *
123  * @qp: QP to copy from.
124  * @send: copy from the send queue when non-zero, use the receive queue
125  *        otherwise.
126  * @wqe_index:  index to start copying from. For send work queues, the
127  *              wqe_index is in units of MLX5_SEND_WQE_BB.
128  *              For receive work queue, it is the number of work queue
129  *              element in the queue.
130  * @buffer: destination buffer.
131  * @length: maximum number of bytes to copy.
132  *
133  * Copies at least a single WQE, but may copy more data.
134  *
135  * Return: the number of bytes copied, or an error code.
136  */
137 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
138                           void *buffer, u32 length,
139                           struct mlx5_ib_qp_base *base)
140 {
141         struct ib_device *ibdev = qp->ibqp.device;
142         struct mlx5_ib_dev *dev = to_mdev(ibdev);
143         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
144         size_t offset;
145         size_t wq_end;
146         struct ib_umem *umem = base->ubuffer.umem;
147         u32 first_copy_length;
148         int wqe_length;
149         int ret;
150
151         if (wq->wqe_cnt == 0) {
152                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
153                             qp->ibqp.qp_type);
154                 return -EINVAL;
155         }
156
157         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
158         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
159
160         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
161                 return -EINVAL;
162
163         if (offset > umem->length ||
164             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
165                 return -EINVAL;
166
167         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
168         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
169         if (ret)
170                 return ret;
171
172         if (send) {
173                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
174                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
175
176                 wqe_length = ds * MLX5_WQE_DS_UNITS;
177         } else {
178                 wqe_length = 1 << wq->wqe_shift;
179         }
180
181         if (wqe_length <= first_copy_length)
182                 return first_copy_length;
183
184         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
185                                 wqe_length - first_copy_length);
186         if (ret)
187                 return ret;
188
189         return wqe_length;
190 }
191
192 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
193 {
194         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
195         struct ib_event event;
196
197         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
198                 /* This event is only valid for trans_qps */
199                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
200         }
201
202         if (ibqp->event_handler) {
203                 event.device     = ibqp->device;
204                 event.element.qp = ibqp;
205                 switch (type) {
206                 case MLX5_EVENT_TYPE_PATH_MIG:
207                         event.event = IB_EVENT_PATH_MIG;
208                         break;
209                 case MLX5_EVENT_TYPE_COMM_EST:
210                         event.event = IB_EVENT_COMM_EST;
211                         break;
212                 case MLX5_EVENT_TYPE_SQ_DRAINED:
213                         event.event = IB_EVENT_SQ_DRAINED;
214                         break;
215                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
216                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
217                         break;
218                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
219                         event.event = IB_EVENT_QP_FATAL;
220                         break;
221                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
222                         event.event = IB_EVENT_PATH_MIG_ERR;
223                         break;
224                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
225                         event.event = IB_EVENT_QP_REQ_ERR;
226                         break;
227                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
228                         event.event = IB_EVENT_QP_ACCESS_ERR;
229                         break;
230                 default:
231                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
232                         return;
233                 }
234
235                 ibqp->event_handler(&event, ibqp->qp_context);
236         }
237 }
238
239 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
240                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
241 {
242         int wqe_size;
243         int wq_size;
244
245         /* Sanity check RQ size before proceeding */
246         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
247                 return -EINVAL;
248
249         if (!has_rq) {
250                 qp->rq.max_gs = 0;
251                 qp->rq.wqe_cnt = 0;
252                 qp->rq.wqe_shift = 0;
253                 cap->max_recv_wr = 0;
254                 cap->max_recv_sge = 0;
255         } else {
256                 if (ucmd) {
257                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
258                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
259                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
260                         qp->rq.max_post = qp->rq.wqe_cnt;
261                 } else {
262                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
263                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
264                         wqe_size = roundup_pow_of_two(wqe_size);
265                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
266                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
267                         qp->rq.wqe_cnt = wq_size / wqe_size;
268                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
269                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
270                                             wqe_size,
271                                             MLX5_CAP_GEN(dev->mdev,
272                                                          max_wqe_sz_rq));
273                                 return -EINVAL;
274                         }
275                         qp->rq.wqe_shift = ilog2(wqe_size);
276                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
277                         qp->rq.max_post = qp->rq.wqe_cnt;
278                 }
279         }
280
281         return 0;
282 }
283
284 static int sq_overhead(struct ib_qp_init_attr *attr)
285 {
286         int size = 0;
287
288         switch (attr->qp_type) {
289         case IB_QPT_XRC_INI:
290                 size += sizeof(struct mlx5_wqe_xrc_seg);
291                 /* fall through */
292         case IB_QPT_RC:
293                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
294                         max(sizeof(struct mlx5_wqe_atomic_seg) +
295                             sizeof(struct mlx5_wqe_raddr_seg),
296                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
297                             sizeof(struct mlx5_mkey_seg));
298                 break;
299
300         case IB_QPT_XRC_TGT:
301                 return 0;
302
303         case IB_QPT_UC:
304                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
305                         max(sizeof(struct mlx5_wqe_raddr_seg),
306                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
307                             sizeof(struct mlx5_mkey_seg));
308                 break;
309
310         case IB_QPT_UD:
311                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
312                         size += sizeof(struct mlx5_wqe_eth_pad) +
313                                 sizeof(struct mlx5_wqe_eth_seg);
314                 /* fall through */
315         case IB_QPT_SMI:
316         case MLX5_IB_QPT_HW_GSI:
317                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
318                         sizeof(struct mlx5_wqe_datagram_seg);
319                 break;
320
321         case MLX5_IB_QPT_REG_UMR:
322                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
323                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
324                         sizeof(struct mlx5_mkey_seg);
325                 break;
326
327         default:
328                 return -EINVAL;
329         }
330
331         return size;
332 }
333
334 static int calc_send_wqe(struct ib_qp_init_attr *attr)
335 {
336         int inl_size = 0;
337         int size;
338
339         size = sq_overhead(attr);
340         if (size < 0)
341                 return size;
342
343         if (attr->cap.max_inline_data) {
344                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
345                         attr->cap.max_inline_data;
346         }
347
348         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
349         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
350             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
351                         return MLX5_SIG_WQE_SIZE;
352         else
353                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
354 }
355
356 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
357 {
358         int max_sge;
359
360         if (attr->qp_type == IB_QPT_RC)
361                 max_sge = (min_t(int, wqe_size, 512) -
362                            sizeof(struct mlx5_wqe_ctrl_seg) -
363                            sizeof(struct mlx5_wqe_raddr_seg)) /
364                         sizeof(struct mlx5_wqe_data_seg);
365         else if (attr->qp_type == IB_QPT_XRC_INI)
366                 max_sge = (min_t(int, wqe_size, 512) -
367                            sizeof(struct mlx5_wqe_ctrl_seg) -
368                            sizeof(struct mlx5_wqe_xrc_seg) -
369                            sizeof(struct mlx5_wqe_raddr_seg)) /
370                         sizeof(struct mlx5_wqe_data_seg);
371         else
372                 max_sge = (wqe_size - sq_overhead(attr)) /
373                         sizeof(struct mlx5_wqe_data_seg);
374
375         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
376                      sizeof(struct mlx5_wqe_data_seg));
377 }
378
379 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
380                         struct mlx5_ib_qp *qp)
381 {
382         int wqe_size;
383         int wq_size;
384
385         if (!attr->cap.max_send_wr)
386                 return 0;
387
388         wqe_size = calc_send_wqe(attr);
389         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
390         if (wqe_size < 0)
391                 return wqe_size;
392
393         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
394                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
395                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
396                 return -EINVAL;
397         }
398
399         qp->max_inline_data = wqe_size - sq_overhead(attr) -
400                               sizeof(struct mlx5_wqe_inline_seg);
401         attr->cap.max_inline_data = qp->max_inline_data;
402
403         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
404                 qp->signature_en = true;
405
406         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
407         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
408         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
409                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
410                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
411                             qp->sq.wqe_cnt,
412                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
413                 return -ENOMEM;
414         }
415         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
416         qp->sq.max_gs = get_send_sge(attr, wqe_size);
417         if (qp->sq.max_gs < attr->cap.max_send_sge)
418                 return -ENOMEM;
419
420         attr->cap.max_send_sge = qp->sq.max_gs;
421         qp->sq.max_post = wq_size / wqe_size;
422         attr->cap.max_send_wr = qp->sq.max_post;
423
424         return wq_size;
425 }
426
427 static int set_user_buf_size(struct mlx5_ib_dev *dev,
428                             struct mlx5_ib_qp *qp,
429                             struct mlx5_ib_create_qp *ucmd,
430                             struct mlx5_ib_qp_base *base,
431                             struct ib_qp_init_attr *attr)
432 {
433         int desc_sz = 1 << qp->sq.wqe_shift;
434
435         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
436                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
437                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
438                 return -EINVAL;
439         }
440
441         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
442                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
443                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
444                 return -EINVAL;
445         }
446
447         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
448
449         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
450                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
451                              qp->sq.wqe_cnt,
452                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
453                 return -EINVAL;
454         }
455
456         if (attr->qp_type == IB_QPT_RAW_PACKET) {
457                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
458                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
459         } else {
460                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
461                                          (qp->sq.wqe_cnt << 6);
462         }
463
464         return 0;
465 }
466
467 static int qp_has_rq(struct ib_qp_init_attr *attr)
468 {
469         if (attr->qp_type == IB_QPT_XRC_INI ||
470             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
471             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
472             !attr->cap.max_recv_wr)
473                 return 0;
474
475         return 1;
476 }
477
478 static int first_med_bfreg(void)
479 {
480         return 1;
481 }
482
483 static int next_bfreg(int n)
484 {
485         n++;
486
487         while (((n % 4) & 2))
488                 n++;
489
490         return n;
491 }
492
493 enum {
494         /* this is the first blue flame register in the array of bfregs assigned
495          * to a processes. Since we do not use it for blue flame but rather
496          * regular 64 bit doorbells, we do not need a lock for maintaiing
497          * "odd/even" order
498          */
499         NUM_NON_BLUE_FLAME_BFREGS = 1,
500 };
501
502 static int num_med_bfreg(struct mlx5_bfreg_info *bfregi)
503 {
504         int n;
505
506         n = bfregi->num_uars * MLX5_NON_FP_BFREGS_PER_UAR -
507                 bfregi->num_low_latency_bfregs - NUM_NON_BLUE_FLAME_BFREGS;
508
509         return n >= 0 ? n : 0;
510 }
511
512 static int max_bfregi(struct mlx5_bfreg_info *bfregi)
513 {
514         return bfregi->num_uars * 4;
515 }
516
517 static int first_hi_bfreg(struct mlx5_bfreg_info *bfregi)
518 {
519         int med;
520
521         med = num_med_bfreg(bfregi);
522         return next_bfreg(med);
523 }
524
525 static int alloc_high_class_bfreg(struct mlx5_bfreg_info *bfregi)
526 {
527         int i;
528
529         for (i = first_hi_bfreg(bfregi); i < max_bfregi(bfregi); i = next_bfreg(i)) {
530                 if (!test_bit(i, bfregi->bitmap)) {
531                         set_bit(i, bfregi->bitmap);
532                         bfregi->count[i]++;
533                         return i;
534                 }
535         }
536
537         return -ENOMEM;
538 }
539
540 static int alloc_med_class_bfreg(struct mlx5_bfreg_info *bfregi)
541 {
542         int minidx = first_med_bfreg();
543         int i;
544
545         for (i = first_med_bfreg(); i < first_hi_bfreg(bfregi); i = next_bfreg(i)) {
546                 if (bfregi->count[i] < bfregi->count[minidx])
547                         minidx = i;
548                 if (!bfregi->count[minidx])
549                         break;
550         }
551
552         bfregi->count[minidx]++;
553         return minidx;
554 }
555
556 static int alloc_bfreg(struct mlx5_bfreg_info *bfregi,
557                        enum mlx5_ib_latency_class lat)
558 {
559         int bfregn = -EINVAL;
560
561         mutex_lock(&bfregi->lock);
562         switch (lat) {
563         case MLX5_IB_LATENCY_CLASS_LOW:
564                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
565                 bfregn = 0;
566                 bfregi->count[bfregn]++;
567                 break;
568
569         case MLX5_IB_LATENCY_CLASS_MEDIUM:
570                 if (bfregi->ver < 2)
571                         bfregn = -ENOMEM;
572                 else
573                         bfregn = alloc_med_class_bfreg(bfregi);
574                 break;
575
576         case MLX5_IB_LATENCY_CLASS_HIGH:
577                 if (bfregi->ver < 2)
578                         bfregn = -ENOMEM;
579                 else
580                         bfregn = alloc_high_class_bfreg(bfregi);
581                 break;
582
583         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
584                 bfregn = 2;
585                 break;
586         }
587         mutex_unlock(&bfregi->lock);
588
589         return bfregn;
590 }
591
592 static void free_med_class_bfreg(struct mlx5_bfreg_info *bfregi, int bfregn)
593 {
594         clear_bit(bfregn, bfregi->bitmap);
595         --bfregi->count[bfregn];
596 }
597
598 static void free_high_class_bfreg(struct mlx5_bfreg_info *bfregi, int bfregn)
599 {
600         clear_bit(bfregn, bfregi->bitmap);
601         --bfregi->count[bfregn];
602 }
603
604 static void free_bfreg(struct mlx5_bfreg_info *bfregi, int bfregn)
605 {
606         int nbfregs = bfregi->num_uars * MLX5_BFREGS_PER_UAR;
607         int high_bfreg = nbfregs - bfregi->num_low_latency_bfregs;
608
609         mutex_lock(&bfregi->lock);
610         if (bfregn == 0) {
611                 --bfregi->count[bfregn];
612                 goto out;
613         }
614
615         if (bfregn < high_bfreg) {
616                 free_med_class_bfreg(bfregi, bfregn);
617                 goto out;
618         }
619
620         free_high_class_bfreg(bfregi, bfregn);
621
622 out:
623         mutex_unlock(&bfregi->lock);
624 }
625
626 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
627 {
628         switch (state) {
629         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
630         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
631         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
632         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
633         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
634         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
635         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
636         default:                return -1;
637         }
638 }
639
640 static int to_mlx5_st(enum ib_qp_type type)
641 {
642         switch (type) {
643         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
644         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
645         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
646         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
647         case IB_QPT_XRC_INI:
648         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
649         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
650         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
651         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
652         case IB_QPT_RAW_PACKET:
653         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
654         case IB_QPT_MAX:
655         default:                return -EINVAL;
656         }
657 }
658
659 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
660                              struct mlx5_ib_cq *recv_cq);
661 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
662                                struct mlx5_ib_cq *recv_cq);
663
664 static int bfregn_to_uar_index(struct mlx5_bfreg_info *bfregi, int bfregn)
665 {
666         return bfregi->uars[bfregn / MLX5_BFREGS_PER_UAR].index;
667 }
668
669 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
670                             struct ib_pd *pd,
671                             unsigned long addr, size_t size,
672                             struct ib_umem **umem,
673                             int *npages, int *page_shift, int *ncont,
674                             u32 *offset)
675 {
676         int err;
677
678         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
679         if (IS_ERR(*umem)) {
680                 mlx5_ib_dbg(dev, "umem_get failed\n");
681                 return PTR_ERR(*umem);
682         }
683
684         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
685
686         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
687         if (err) {
688                 mlx5_ib_warn(dev, "bad offset\n");
689                 goto err_umem;
690         }
691
692         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
693                     addr, size, *npages, *page_shift, *ncont, *offset);
694
695         return 0;
696
697 err_umem:
698         ib_umem_release(*umem);
699         *umem = NULL;
700
701         return err;
702 }
703
704 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
705 {
706         struct mlx5_ib_ucontext *context;
707
708         context = to_mucontext(pd->uobject->context);
709         mlx5_ib_db_unmap_user(context, &rwq->db);
710         if (rwq->umem)
711                 ib_umem_release(rwq->umem);
712 }
713
714 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
715                           struct mlx5_ib_rwq *rwq,
716                           struct mlx5_ib_create_wq *ucmd)
717 {
718         struct mlx5_ib_ucontext *context;
719         int page_shift = 0;
720         int npages;
721         u32 offset = 0;
722         int ncont = 0;
723         int err;
724
725         if (!ucmd->buf_addr)
726                 return -EINVAL;
727
728         context = to_mucontext(pd->uobject->context);
729         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
730                                rwq->buf_size, 0, 0);
731         if (IS_ERR(rwq->umem)) {
732                 mlx5_ib_dbg(dev, "umem_get failed\n");
733                 err = PTR_ERR(rwq->umem);
734                 return err;
735         }
736
737         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
738                            &ncont, NULL);
739         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
740                                      &rwq->rq_page_offset);
741         if (err) {
742                 mlx5_ib_warn(dev, "bad offset\n");
743                 goto err_umem;
744         }
745
746         rwq->rq_num_pas = ncont;
747         rwq->page_shift = page_shift;
748         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
749         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
750
751         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
752                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
753                     npages, page_shift, ncont, offset);
754
755         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
756         if (err) {
757                 mlx5_ib_dbg(dev, "map failed\n");
758                 goto err_umem;
759         }
760
761         rwq->create_type = MLX5_WQ_USER;
762         return 0;
763
764 err_umem:
765         ib_umem_release(rwq->umem);
766         return err;
767 }
768
769 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
770                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
771                           struct ib_qp_init_attr *attr,
772                           u32 **in,
773                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
774                           struct mlx5_ib_qp_base *base)
775 {
776         struct mlx5_ib_ucontext *context;
777         struct mlx5_ib_create_qp ucmd;
778         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
779         int page_shift = 0;
780         int uar_index;
781         int npages;
782         u32 offset = 0;
783         int bfregn;
784         int ncont = 0;
785         __be64 *pas;
786         void *qpc;
787         int err;
788
789         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
790         if (err) {
791                 mlx5_ib_dbg(dev, "copy failed\n");
792                 return err;
793         }
794
795         context = to_mucontext(pd->uobject->context);
796         /*
797          * TBD: should come from the verbs when we have the API
798          */
799         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
800                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
801                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
802         else {
803                 bfregn = alloc_bfreg(&context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
804                 if (bfregn < 0) {
805                         mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
806                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
807                         bfregn = alloc_bfreg(&context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
808                         if (bfregn < 0) {
809                                 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
810                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
811                                 bfregn = alloc_bfreg(&context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
812                                 if (bfregn < 0) {
813                                         mlx5_ib_warn(dev, "bfreg allocation failed\n");
814                                         return bfregn;
815                                 }
816                         }
817                 }
818         }
819
820         uar_index = bfregn_to_uar_index(&context->bfregi, bfregn);
821         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
822
823         qp->rq.offset = 0;
824         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
825         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
826
827         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
828         if (err)
829                 goto err_bfreg;
830
831         if (ucmd.buf_addr && ubuffer->buf_size) {
832                 ubuffer->buf_addr = ucmd.buf_addr;
833                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
834                                        ubuffer->buf_size,
835                                        &ubuffer->umem, &npages, &page_shift,
836                                        &ncont, &offset);
837                 if (err)
838                         goto err_bfreg;
839         } else {
840                 ubuffer->umem = NULL;
841         }
842
843         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
844                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
845         *in = mlx5_vzalloc(*inlen);
846         if (!*in) {
847                 err = -ENOMEM;
848                 goto err_umem;
849         }
850
851         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
852         if (ubuffer->umem)
853                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
854
855         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
856
857         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
858         MLX5_SET(qpc, qpc, page_offset, offset);
859
860         MLX5_SET(qpc, qpc, uar_page, uar_index);
861         resp->bfreg_index = bfregn;
862         qp->bfregn = bfregn;
863
864         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
865         if (err) {
866                 mlx5_ib_dbg(dev, "map failed\n");
867                 goto err_free;
868         }
869
870         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
871         if (err) {
872                 mlx5_ib_dbg(dev, "copy failed\n");
873                 goto err_unmap;
874         }
875         qp->create_type = MLX5_QP_USER;
876
877         return 0;
878
879 err_unmap:
880         mlx5_ib_db_unmap_user(context, &qp->db);
881
882 err_free:
883         kvfree(*in);
884
885 err_umem:
886         if (ubuffer->umem)
887                 ib_umem_release(ubuffer->umem);
888
889 err_bfreg:
890         free_bfreg(&context->bfregi, bfregn);
891         return err;
892 }
893
894 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
895                             struct mlx5_ib_qp_base *base)
896 {
897         struct mlx5_ib_ucontext *context;
898
899         context = to_mucontext(pd->uobject->context);
900         mlx5_ib_db_unmap_user(context, &qp->db);
901         if (base->ubuffer.umem)
902                 ib_umem_release(base->ubuffer.umem);
903         free_bfreg(&context->bfregi, qp->bfregn);
904 }
905
906 static int create_kernel_qp(struct mlx5_ib_dev *dev,
907                             struct ib_qp_init_attr *init_attr,
908                             struct mlx5_ib_qp *qp,
909                             u32 **in, int *inlen,
910                             struct mlx5_ib_qp_base *base)
911 {
912         int uar_index;
913         void *qpc;
914         int err;
915
916         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
917                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
918                                         IB_QP_CREATE_IPOIB_UD_LSO |
919                                         mlx5_ib_create_qp_sqpn_qp1()))
920                 return -EINVAL;
921
922         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
923                 qp->bf.bfreg = &dev->fp_bfreg;
924         else
925                 qp->bf.bfreg = &dev->bfreg;
926
927         qp->bf.buf_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
928         uar_index = qp->bf.bfreg->index;
929
930         err = calc_sq_size(dev, init_attr, qp);
931         if (err < 0) {
932                 mlx5_ib_dbg(dev, "err %d\n", err);
933                 return err;
934         }
935
936         qp->rq.offset = 0;
937         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
938         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
939
940         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
941         if (err) {
942                 mlx5_ib_dbg(dev, "err %d\n", err);
943                 return err;
944         }
945
946         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
947         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
948                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
949         *in = mlx5_vzalloc(*inlen);
950         if (!*in) {
951                 err = -ENOMEM;
952                 goto err_buf;
953         }
954
955         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
956         MLX5_SET(qpc, qpc, uar_page, uar_index);
957         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
958
959         /* Set "fast registration enabled" for all kernel QPs */
960         MLX5_SET(qpc, qpc, fre, 1);
961         MLX5_SET(qpc, qpc, rlky, 1);
962
963         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
964                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
965                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
966         }
967
968         mlx5_fill_page_array(&qp->buf,
969                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
970
971         err = mlx5_db_alloc(dev->mdev, &qp->db);
972         if (err) {
973                 mlx5_ib_dbg(dev, "err %d\n", err);
974                 goto err_free;
975         }
976
977         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
978         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
979         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
980         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
981         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
982
983         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
984             !qp->sq.w_list || !qp->sq.wqe_head) {
985                 err = -ENOMEM;
986                 goto err_wrid;
987         }
988         qp->create_type = MLX5_QP_KERNEL;
989
990         return 0;
991
992 err_wrid:
993         kfree(qp->sq.wqe_head);
994         kfree(qp->sq.w_list);
995         kfree(qp->sq.wrid);
996         kfree(qp->sq.wr_data);
997         kfree(qp->rq.wrid);
998         mlx5_db_free(dev->mdev, &qp->db);
999
1000 err_free:
1001         kvfree(*in);
1002
1003 err_buf:
1004         mlx5_buf_free(dev->mdev, &qp->buf);
1005         return err;
1006 }
1007
1008 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1009 {
1010         kfree(qp->sq.wqe_head);
1011         kfree(qp->sq.w_list);
1012         kfree(qp->sq.wrid);
1013         kfree(qp->sq.wr_data);
1014         kfree(qp->rq.wrid);
1015         mlx5_db_free(dev->mdev, &qp->db);
1016         mlx5_buf_free(dev->mdev, &qp->buf);
1017 }
1018
1019 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1020 {
1021         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1022             (attr->qp_type == IB_QPT_XRC_INI))
1023                 return MLX5_SRQ_RQ;
1024         else if (!qp->has_rq)
1025                 return MLX5_ZERO_LEN_RQ;
1026         else
1027                 return MLX5_NON_ZERO_RQ;
1028 }
1029
1030 static int is_connected(enum ib_qp_type qp_type)
1031 {
1032         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1033                 return 1;
1034
1035         return 0;
1036 }
1037
1038 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1039                                     struct mlx5_ib_sq *sq, u32 tdn)
1040 {
1041         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1042         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1043
1044         MLX5_SET(tisc, tisc, transport_domain, tdn);
1045         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1046 }
1047
1048 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1049                                       struct mlx5_ib_sq *sq)
1050 {
1051         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1052 }
1053
1054 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1055                                    struct mlx5_ib_sq *sq, void *qpin,
1056                                    struct ib_pd *pd)
1057 {
1058         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1059         __be64 *pas;
1060         void *in;
1061         void *sqc;
1062         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1063         void *wq;
1064         int inlen;
1065         int err;
1066         int page_shift = 0;
1067         int npages;
1068         int ncont = 0;
1069         u32 offset = 0;
1070
1071         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1072                                &sq->ubuffer.umem, &npages, &page_shift,
1073                                &ncont, &offset);
1074         if (err)
1075                 return err;
1076
1077         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1078         in = mlx5_vzalloc(inlen);
1079         if (!in) {
1080                 err = -ENOMEM;
1081                 goto err_umem;
1082         }
1083
1084         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1085         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1086         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1087         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1088         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1089         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1090         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1091
1092         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1093         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1094         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1095         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1096         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1097         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1098         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1099         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1100         MLX5_SET(wq, wq, page_offset, offset);
1101
1102         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1103         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1104
1105         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1106
1107         kvfree(in);
1108
1109         if (err)
1110                 goto err_umem;
1111
1112         return 0;
1113
1114 err_umem:
1115         ib_umem_release(sq->ubuffer.umem);
1116         sq->ubuffer.umem = NULL;
1117
1118         return err;
1119 }
1120
1121 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1122                                      struct mlx5_ib_sq *sq)
1123 {
1124         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1125         ib_umem_release(sq->ubuffer.umem);
1126 }
1127
1128 static int get_rq_pas_size(void *qpc)
1129 {
1130         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1131         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1132         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1133         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1134         u32 po_quanta     = 1 << (log_page_size - 6);
1135         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1136         u32 page_size     = 1 << log_page_size;
1137         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1138         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1139
1140         return rq_num_pas * sizeof(u64);
1141 }
1142
1143 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1144                                    struct mlx5_ib_rq *rq, void *qpin)
1145 {
1146         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1147         __be64 *pas;
1148         __be64 *qp_pas;
1149         void *in;
1150         void *rqc;
1151         void *wq;
1152         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1153         int inlen;
1154         int err;
1155         u32 rq_pas_size = get_rq_pas_size(qpc);
1156
1157         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1158         in = mlx5_vzalloc(inlen);
1159         if (!in)
1160                 return -ENOMEM;
1161
1162         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1163         MLX5_SET(rqc, rqc, vsd, 1);
1164         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1165         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1166         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1167         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1168         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1169
1170         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1171                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1172
1173         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1174         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1175         MLX5_SET(wq, wq, end_padding_mode,
1176                  MLX5_GET(qpc, qpc, end_padding_mode));
1177         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1178         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1179         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1180         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1181         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1182         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1183
1184         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1185         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1186         memcpy(pas, qp_pas, rq_pas_size);
1187
1188         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1189
1190         kvfree(in);
1191
1192         return err;
1193 }
1194
1195 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1196                                      struct mlx5_ib_rq *rq)
1197 {
1198         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1199 }
1200
1201 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1202                                     struct mlx5_ib_rq *rq, u32 tdn)
1203 {
1204         u32 *in;
1205         void *tirc;
1206         int inlen;
1207         int err;
1208
1209         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1210         in = mlx5_vzalloc(inlen);
1211         if (!in)
1212                 return -ENOMEM;
1213
1214         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1215         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1216         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1217         MLX5_SET(tirc, tirc, transport_domain, tdn);
1218
1219         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1220
1221         kvfree(in);
1222
1223         return err;
1224 }
1225
1226 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1227                                       struct mlx5_ib_rq *rq)
1228 {
1229         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1230 }
1231
1232 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1233                                 u32 *in,
1234                                 struct ib_pd *pd)
1235 {
1236         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1237         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1238         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1239         struct ib_uobject *uobj = pd->uobject;
1240         struct ib_ucontext *ucontext = uobj->context;
1241         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1242         int err;
1243         u32 tdn = mucontext->tdn;
1244
1245         if (qp->sq.wqe_cnt) {
1246                 err = create_raw_packet_qp_tis(dev, sq, tdn);
1247                 if (err)
1248                         return err;
1249
1250                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1251                 if (err)
1252                         goto err_destroy_tis;
1253
1254                 sq->base.container_mibqp = qp;
1255         }
1256
1257         if (qp->rq.wqe_cnt) {
1258                 rq->base.container_mibqp = qp;
1259
1260                 err = create_raw_packet_qp_rq(dev, rq, in);
1261                 if (err)
1262                         goto err_destroy_sq;
1263
1264
1265                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1266                 if (err)
1267                         goto err_destroy_rq;
1268         }
1269
1270         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1271                                                      rq->base.mqp.qpn;
1272
1273         return 0;
1274
1275 err_destroy_rq:
1276         destroy_raw_packet_qp_rq(dev, rq);
1277 err_destroy_sq:
1278         if (!qp->sq.wqe_cnt)
1279                 return err;
1280         destroy_raw_packet_qp_sq(dev, sq);
1281 err_destroy_tis:
1282         destroy_raw_packet_qp_tis(dev, sq);
1283
1284         return err;
1285 }
1286
1287 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1288                                   struct mlx5_ib_qp *qp)
1289 {
1290         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1291         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1292         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1293
1294         if (qp->rq.wqe_cnt) {
1295                 destroy_raw_packet_qp_tir(dev, rq);
1296                 destroy_raw_packet_qp_rq(dev, rq);
1297         }
1298
1299         if (qp->sq.wqe_cnt) {
1300                 destroy_raw_packet_qp_sq(dev, sq);
1301                 destroy_raw_packet_qp_tis(dev, sq);
1302         }
1303 }
1304
1305 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1306                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1307 {
1308         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1309         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1310
1311         sq->sq = &qp->sq;
1312         rq->rq = &qp->rq;
1313         sq->doorbell = &qp->db;
1314         rq->doorbell = &qp->db;
1315 }
1316
1317 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1318 {
1319         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1320 }
1321
1322 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1323                                  struct ib_pd *pd,
1324                                  struct ib_qp_init_attr *init_attr,
1325                                  struct ib_udata *udata)
1326 {
1327         struct ib_uobject *uobj = pd->uobject;
1328         struct ib_ucontext *ucontext = uobj->context;
1329         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1330         struct mlx5_ib_create_qp_resp resp = {};
1331         int inlen;
1332         int err;
1333         u32 *in;
1334         void *tirc;
1335         void *hfso;
1336         u32 selected_fields = 0;
1337         size_t min_resp_len;
1338         u32 tdn = mucontext->tdn;
1339         struct mlx5_ib_create_qp_rss ucmd = {};
1340         size_t required_cmd_sz;
1341
1342         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1343                 return -EOPNOTSUPP;
1344
1345         if (init_attr->create_flags || init_attr->send_cq)
1346                 return -EINVAL;
1347
1348         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1349         if (udata->outlen < min_resp_len)
1350                 return -EINVAL;
1351
1352         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1353         if (udata->inlen < required_cmd_sz) {
1354                 mlx5_ib_dbg(dev, "invalid inlen\n");
1355                 return -EINVAL;
1356         }
1357
1358         if (udata->inlen > sizeof(ucmd) &&
1359             !ib_is_udata_cleared(udata, sizeof(ucmd),
1360                                  udata->inlen - sizeof(ucmd))) {
1361                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1362                 return -EOPNOTSUPP;
1363         }
1364
1365         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1366                 mlx5_ib_dbg(dev, "copy failed\n");
1367                 return -EFAULT;
1368         }
1369
1370         if (ucmd.comp_mask) {
1371                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1372                 return -EOPNOTSUPP;
1373         }
1374
1375         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1376                 mlx5_ib_dbg(dev, "invalid reserved\n");
1377                 return -EOPNOTSUPP;
1378         }
1379
1380         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1381         if (err) {
1382                 mlx5_ib_dbg(dev, "copy failed\n");
1383                 return -EINVAL;
1384         }
1385
1386         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1387         in = mlx5_vzalloc(inlen);
1388         if (!in)
1389                 return -ENOMEM;
1390
1391         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1392         MLX5_SET(tirc, tirc, disp_type,
1393                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1394         MLX5_SET(tirc, tirc, indirect_table,
1395                  init_attr->rwq_ind_tbl->ind_tbl_num);
1396         MLX5_SET(tirc, tirc, transport_domain, tdn);
1397
1398         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1399         switch (ucmd.rx_hash_function) {
1400         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1401         {
1402                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1403                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1404
1405                 if (len != ucmd.rx_key_len) {
1406                         err = -EINVAL;
1407                         goto err;
1408                 }
1409
1410                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1411                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1412                 memcpy(rss_key, ucmd.rx_hash_key, len);
1413                 break;
1414         }
1415         default:
1416                 err = -EOPNOTSUPP;
1417                 goto err;
1418         }
1419
1420         if (!ucmd.rx_hash_fields_mask) {
1421                 /* special case when this TIR serves as steering entry without hashing */
1422                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1423                         goto create_tir;
1424                 err = -EINVAL;
1425                 goto err;
1426         }
1427
1428         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1429              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1430              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1431              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1432                 err = -EINVAL;
1433                 goto err;
1434         }
1435
1436         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1437         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1438             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1439                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1440                          MLX5_L3_PROT_TYPE_IPV4);
1441         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1442                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1443                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1444                          MLX5_L3_PROT_TYPE_IPV6);
1445
1446         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1447              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1448              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1449              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1450                 err = -EINVAL;
1451                 goto err;
1452         }
1453
1454         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1455         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1456             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1457                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1458                          MLX5_L4_PROT_TYPE_TCP);
1459         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1460                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1461                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1462                          MLX5_L4_PROT_TYPE_UDP);
1463
1464         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1465             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1466                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1467
1468         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1469             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1470                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1471
1472         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1473             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1474                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1475
1476         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1477             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1478                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1479
1480         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1481
1482 create_tir:
1483         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1484
1485         if (err)
1486                 goto err;
1487
1488         kvfree(in);
1489         /* qpn is reserved for that QP */
1490         qp->trans_qp.base.mqp.qpn = 0;
1491         qp->flags |= MLX5_IB_QP_RSS;
1492         return 0;
1493
1494 err:
1495         kvfree(in);
1496         return err;
1497 }
1498
1499 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1500                             struct ib_qp_init_attr *init_attr,
1501                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1502 {
1503         struct mlx5_ib_resources *devr = &dev->devr;
1504         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1505         struct mlx5_core_dev *mdev = dev->mdev;
1506         struct mlx5_ib_create_qp_resp resp;
1507         struct mlx5_ib_cq *send_cq;
1508         struct mlx5_ib_cq *recv_cq;
1509         unsigned long flags;
1510         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1511         struct mlx5_ib_create_qp ucmd;
1512         struct mlx5_ib_qp_base *base;
1513         void *qpc;
1514         u32 *in;
1515         int err;
1516
1517         base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1518                &qp->raw_packet_qp.rq.base :
1519                &qp->trans_qp.base;
1520
1521         mutex_init(&qp->mutex);
1522         spin_lock_init(&qp->sq.lock);
1523         spin_lock_init(&qp->rq.lock);
1524
1525         if (init_attr->rwq_ind_tbl) {
1526                 if (!udata)
1527                         return -ENOSYS;
1528
1529                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1530                 return err;
1531         }
1532
1533         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1534                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1535                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1536                         return -EINVAL;
1537                 } else {
1538                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1539                 }
1540         }
1541
1542         if (init_attr->create_flags &
1543                         (IB_QP_CREATE_CROSS_CHANNEL |
1544                          IB_QP_CREATE_MANAGED_SEND |
1545                          IB_QP_CREATE_MANAGED_RECV)) {
1546                 if (!MLX5_CAP_GEN(mdev, cd)) {
1547                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1548                         return -EINVAL;
1549                 }
1550                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1551                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1552                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1553                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1554                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1555                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1556         }
1557
1558         if (init_attr->qp_type == IB_QPT_UD &&
1559             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1560                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1561                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1562                         return -EOPNOTSUPP;
1563                 }
1564
1565         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1566                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1567                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1568                         return -EOPNOTSUPP;
1569                 }
1570                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1571                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1572                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1573                         return -EOPNOTSUPP;
1574                 }
1575                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1576         }
1577
1578         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1579                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1580
1581         if (pd && pd->uobject) {
1582                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1583                         mlx5_ib_dbg(dev, "copy failed\n");
1584                         return -EFAULT;
1585                 }
1586
1587                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1588                                         &ucmd, udata->inlen, &uidx);
1589                 if (err)
1590                         return err;
1591
1592                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1593                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1594         } else {
1595                 qp->wq_sig = !!wq_signature;
1596         }
1597
1598         qp->has_rq = qp_has_rq(init_attr);
1599         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1600                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1601         if (err) {
1602                 mlx5_ib_dbg(dev, "err %d\n", err);
1603                 return err;
1604         }
1605
1606         if (pd) {
1607                 if (pd->uobject) {
1608                         __u32 max_wqes =
1609                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1610                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1611                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1612                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1613                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1614                                 return -EINVAL;
1615                         }
1616                         if (ucmd.sq_wqe_count > max_wqes) {
1617                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1618                                             ucmd.sq_wqe_count, max_wqes);
1619                                 return -EINVAL;
1620                         }
1621                         if (init_attr->create_flags &
1622                             mlx5_ib_create_qp_sqpn_qp1()) {
1623                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1624                                 return -EINVAL;
1625                         }
1626                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1627                                              &resp, &inlen, base);
1628                         if (err)
1629                                 mlx5_ib_dbg(dev, "err %d\n", err);
1630                 } else {
1631                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1632                                                base);
1633                         if (err)
1634                                 mlx5_ib_dbg(dev, "err %d\n", err);
1635                 }
1636
1637                 if (err)
1638                         return err;
1639         } else {
1640                 in = mlx5_vzalloc(inlen);
1641                 if (!in)
1642                         return -ENOMEM;
1643
1644                 qp->create_type = MLX5_QP_EMPTY;
1645         }
1646
1647         if (is_sqp(init_attr->qp_type))
1648                 qp->port = init_attr->port_num;
1649
1650         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1651
1652         MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1653         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1654
1655         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1656                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1657         else
1658                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1659
1660
1661         if (qp->wq_sig)
1662                 MLX5_SET(qpc, qpc, wq_signature, 1);
1663
1664         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1665                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1666
1667         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1668                 MLX5_SET(qpc, qpc, cd_master, 1);
1669         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1670                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1671         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1672                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1673
1674         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1675                 int rcqe_sz;
1676                 int scqe_sz;
1677
1678                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1679                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1680
1681                 if (rcqe_sz == 128)
1682                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1683                 else
1684                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1685
1686                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1687                         if (scqe_sz == 128)
1688                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1689                         else
1690                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1691                 }
1692         }
1693
1694         if (qp->rq.wqe_cnt) {
1695                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1696                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1697         }
1698
1699         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1700
1701         if (qp->sq.wqe_cnt)
1702                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1703         else
1704                 MLX5_SET(qpc, qpc, no_sq, 1);
1705
1706         /* Set default resources */
1707         switch (init_attr->qp_type) {
1708         case IB_QPT_XRC_TGT:
1709                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1710                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1711                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1712                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1713                 break;
1714         case IB_QPT_XRC_INI:
1715                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1716                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1717                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1718                 break;
1719         default:
1720                 if (init_attr->srq) {
1721                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1722                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1723                 } else {
1724                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1725                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1726                 }
1727         }
1728
1729         if (init_attr->send_cq)
1730                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1731
1732         if (init_attr->recv_cq)
1733                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1734
1735         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1736
1737         /* 0xffffff means we ask to work with cqe version 0 */
1738         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1739                 MLX5_SET(qpc, qpc, user_index, uidx);
1740
1741         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1742         if (init_attr->qp_type == IB_QPT_UD &&
1743             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1744                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1745                 qp->flags |= MLX5_IB_QP_LSO;
1746         }
1747
1748         if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1749                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1750                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1751                 err = create_raw_packet_qp(dev, qp, in, pd);
1752         } else {
1753                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1754         }
1755
1756         if (err) {
1757                 mlx5_ib_dbg(dev, "create qp failed\n");
1758                 goto err_create;
1759         }
1760
1761         kvfree(in);
1762
1763         base->container_mibqp = qp;
1764         base->mqp.event = mlx5_ib_qp_event;
1765
1766         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1767                 &send_cq, &recv_cq);
1768         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1769         mlx5_ib_lock_cqs(send_cq, recv_cq);
1770         /* Maintain device to QPs access, needed for further handling via reset
1771          * flow
1772          */
1773         list_add_tail(&qp->qps_list, &dev->qp_list);
1774         /* Maintain CQ to QPs access, needed for further handling via reset flow
1775          */
1776         if (send_cq)
1777                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1778         if (recv_cq)
1779                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1780         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1781         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1782
1783         return 0;
1784
1785 err_create:
1786         if (qp->create_type == MLX5_QP_USER)
1787                 destroy_qp_user(pd, qp, base);
1788         else if (qp->create_type == MLX5_QP_KERNEL)
1789                 destroy_qp_kernel(dev, qp);
1790
1791         kvfree(in);
1792         return err;
1793 }
1794
1795 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1796         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1797 {
1798         if (send_cq) {
1799                 if (recv_cq) {
1800                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1801                                 spin_lock(&send_cq->lock);
1802                                 spin_lock_nested(&recv_cq->lock,
1803                                                  SINGLE_DEPTH_NESTING);
1804                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1805                                 spin_lock(&send_cq->lock);
1806                                 __acquire(&recv_cq->lock);
1807                         } else {
1808                                 spin_lock(&recv_cq->lock);
1809                                 spin_lock_nested(&send_cq->lock,
1810                                                  SINGLE_DEPTH_NESTING);
1811                         }
1812                 } else {
1813                         spin_lock(&send_cq->lock);
1814                         __acquire(&recv_cq->lock);
1815                 }
1816         } else if (recv_cq) {
1817                 spin_lock(&recv_cq->lock);
1818                 __acquire(&send_cq->lock);
1819         } else {
1820                 __acquire(&send_cq->lock);
1821                 __acquire(&recv_cq->lock);
1822         }
1823 }
1824
1825 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1826         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1827 {
1828         if (send_cq) {
1829                 if (recv_cq) {
1830                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1831                                 spin_unlock(&recv_cq->lock);
1832                                 spin_unlock(&send_cq->lock);
1833                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1834                                 __release(&recv_cq->lock);
1835                                 spin_unlock(&send_cq->lock);
1836                         } else {
1837                                 spin_unlock(&send_cq->lock);
1838                                 spin_unlock(&recv_cq->lock);
1839                         }
1840                 } else {
1841                         __release(&recv_cq->lock);
1842                         spin_unlock(&send_cq->lock);
1843                 }
1844         } else if (recv_cq) {
1845                 __release(&send_cq->lock);
1846                 spin_unlock(&recv_cq->lock);
1847         } else {
1848                 __release(&recv_cq->lock);
1849                 __release(&send_cq->lock);
1850         }
1851 }
1852
1853 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1854 {
1855         return to_mpd(qp->ibqp.pd);
1856 }
1857
1858 static void get_cqs(enum ib_qp_type qp_type,
1859                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1860                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1861 {
1862         switch (qp_type) {
1863         case IB_QPT_XRC_TGT:
1864                 *send_cq = NULL;
1865                 *recv_cq = NULL;
1866                 break;
1867         case MLX5_IB_QPT_REG_UMR:
1868         case IB_QPT_XRC_INI:
1869                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1870                 *recv_cq = NULL;
1871                 break;
1872
1873         case IB_QPT_SMI:
1874         case MLX5_IB_QPT_HW_GSI:
1875         case IB_QPT_RC:
1876         case IB_QPT_UC:
1877         case IB_QPT_UD:
1878         case IB_QPT_RAW_IPV6:
1879         case IB_QPT_RAW_ETHERTYPE:
1880         case IB_QPT_RAW_PACKET:
1881                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1882                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1883                 break;
1884
1885         case IB_QPT_MAX:
1886         default:
1887                 *send_cq = NULL;
1888                 *recv_cq = NULL;
1889                 break;
1890         }
1891 }
1892
1893 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1894                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1895                                 u8 lag_tx_affinity);
1896
1897 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1898 {
1899         struct mlx5_ib_cq *send_cq, *recv_cq;
1900         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1901         unsigned long flags;
1902         int err;
1903
1904         if (qp->ibqp.rwq_ind_tbl) {
1905                 destroy_rss_raw_qp_tir(dev, qp);
1906                 return;
1907         }
1908
1909         base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1910                &qp->raw_packet_qp.rq.base :
1911                &qp->trans_qp.base;
1912
1913         if (qp->state != IB_QPS_RESET) {
1914                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1915                         err = mlx5_core_qp_modify(dev->mdev,
1916                                                   MLX5_CMD_OP_2RST_QP, 0,
1917                                                   NULL, &base->mqp);
1918                 } else {
1919                         struct mlx5_modify_raw_qp_param raw_qp_param = {
1920                                 .operation = MLX5_CMD_OP_2RST_QP
1921                         };
1922
1923                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1924                 }
1925                 if (err)
1926                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1927                                      base->mqp.qpn);
1928         }
1929
1930         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1931                 &send_cq, &recv_cq);
1932
1933         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1934         mlx5_ib_lock_cqs(send_cq, recv_cq);
1935         /* del from lists under both locks above to protect reset flow paths */
1936         list_del(&qp->qps_list);
1937         if (send_cq)
1938                 list_del(&qp->cq_send_list);
1939
1940         if (recv_cq)
1941                 list_del(&qp->cq_recv_list);
1942
1943         if (qp->create_type == MLX5_QP_KERNEL) {
1944                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1945                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1946                 if (send_cq != recv_cq)
1947                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1948                                            NULL);
1949         }
1950         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1951         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1952
1953         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1954                 destroy_raw_packet_qp(dev, qp);
1955         } else {
1956                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1957                 if (err)
1958                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1959                                      base->mqp.qpn);
1960         }
1961
1962         if (qp->create_type == MLX5_QP_KERNEL)
1963                 destroy_qp_kernel(dev, qp);
1964         else if (qp->create_type == MLX5_QP_USER)
1965                 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1966 }
1967
1968 static const char *ib_qp_type_str(enum ib_qp_type type)
1969 {
1970         switch (type) {
1971         case IB_QPT_SMI:
1972                 return "IB_QPT_SMI";
1973         case IB_QPT_GSI:
1974                 return "IB_QPT_GSI";
1975         case IB_QPT_RC:
1976                 return "IB_QPT_RC";
1977         case IB_QPT_UC:
1978                 return "IB_QPT_UC";
1979         case IB_QPT_UD:
1980                 return "IB_QPT_UD";
1981         case IB_QPT_RAW_IPV6:
1982                 return "IB_QPT_RAW_IPV6";
1983         case IB_QPT_RAW_ETHERTYPE:
1984                 return "IB_QPT_RAW_ETHERTYPE";
1985         case IB_QPT_XRC_INI:
1986                 return "IB_QPT_XRC_INI";
1987         case IB_QPT_XRC_TGT:
1988                 return "IB_QPT_XRC_TGT";
1989         case IB_QPT_RAW_PACKET:
1990                 return "IB_QPT_RAW_PACKET";
1991         case MLX5_IB_QPT_REG_UMR:
1992                 return "MLX5_IB_QPT_REG_UMR";
1993         case IB_QPT_MAX:
1994         default:
1995                 return "Invalid QP type";
1996         }
1997 }
1998
1999 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2000                                 struct ib_qp_init_attr *init_attr,
2001                                 struct ib_udata *udata)
2002 {
2003         struct mlx5_ib_dev *dev;
2004         struct mlx5_ib_qp *qp;
2005         u16 xrcdn = 0;
2006         int err;
2007
2008         if (pd) {
2009                 dev = to_mdev(pd->device);
2010
2011                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2012                         if (!pd->uobject) {
2013                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2014                                 return ERR_PTR(-EINVAL);
2015                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2016                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2017                                 return ERR_PTR(-EINVAL);
2018                         }
2019                 }
2020         } else {
2021                 /* being cautious here */
2022                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2023                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2024                         pr_warn("%s: no PD for transport %s\n", __func__,
2025                                 ib_qp_type_str(init_attr->qp_type));
2026                         return ERR_PTR(-EINVAL);
2027                 }
2028                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2029         }
2030
2031         switch (init_attr->qp_type) {
2032         case IB_QPT_XRC_TGT:
2033         case IB_QPT_XRC_INI:
2034                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2035                         mlx5_ib_dbg(dev, "XRC not supported\n");
2036                         return ERR_PTR(-ENOSYS);
2037                 }
2038                 init_attr->recv_cq = NULL;
2039                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2040                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2041                         init_attr->send_cq = NULL;
2042                 }
2043
2044                 /* fall through */
2045         case IB_QPT_RAW_PACKET:
2046         case IB_QPT_RC:
2047         case IB_QPT_UC:
2048         case IB_QPT_UD:
2049         case IB_QPT_SMI:
2050         case MLX5_IB_QPT_HW_GSI:
2051         case MLX5_IB_QPT_REG_UMR:
2052                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2053                 if (!qp)
2054                         return ERR_PTR(-ENOMEM);
2055
2056                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2057                 if (err) {
2058                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2059                         kfree(qp);
2060                         return ERR_PTR(err);
2061                 }
2062
2063                 if (is_qp0(init_attr->qp_type))
2064                         qp->ibqp.qp_num = 0;
2065                 else if (is_qp1(init_attr->qp_type))
2066                         qp->ibqp.qp_num = 1;
2067                 else
2068                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2069
2070                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2071                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2072                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2073                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2074
2075                 qp->trans_qp.xrcdn = xrcdn;
2076
2077                 break;
2078
2079         case IB_QPT_GSI:
2080                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2081
2082         case IB_QPT_RAW_IPV6:
2083         case IB_QPT_RAW_ETHERTYPE:
2084         case IB_QPT_MAX:
2085         default:
2086                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2087                             init_attr->qp_type);
2088                 /* Don't support raw QPs */
2089                 return ERR_PTR(-EINVAL);
2090         }
2091
2092         return &qp->ibqp;
2093 }
2094
2095 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2096 {
2097         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2098         struct mlx5_ib_qp *mqp = to_mqp(qp);
2099
2100         if (unlikely(qp->qp_type == IB_QPT_GSI))
2101                 return mlx5_ib_gsi_destroy_qp(qp);
2102
2103         destroy_qp_common(dev, mqp);
2104
2105         kfree(mqp);
2106
2107         return 0;
2108 }
2109
2110 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2111                                    int attr_mask)
2112 {
2113         u32 hw_access_flags = 0;
2114         u8 dest_rd_atomic;
2115         u32 access_flags;
2116
2117         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2118                 dest_rd_atomic = attr->max_dest_rd_atomic;
2119         else
2120                 dest_rd_atomic = qp->trans_qp.resp_depth;
2121
2122         if (attr_mask & IB_QP_ACCESS_FLAGS)
2123                 access_flags = attr->qp_access_flags;
2124         else
2125                 access_flags = qp->trans_qp.atomic_rd_en;
2126
2127         if (!dest_rd_atomic)
2128                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2129
2130         if (access_flags & IB_ACCESS_REMOTE_READ)
2131                 hw_access_flags |= MLX5_QP_BIT_RRE;
2132         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2133                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2134         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2135                 hw_access_flags |= MLX5_QP_BIT_RWE;
2136
2137         return cpu_to_be32(hw_access_flags);
2138 }
2139
2140 enum {
2141         MLX5_PATH_FLAG_FL       = 1 << 0,
2142         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2143         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2144 };
2145
2146 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2147 {
2148         if (rate == IB_RATE_PORT_CURRENT) {
2149                 return 0;
2150         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2151                 return -EINVAL;
2152         } else {
2153                 while (rate != IB_RATE_2_5_GBPS &&
2154                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2155                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2156                         --rate;
2157         }
2158
2159         return rate + MLX5_STAT_RATE_OFFSET;
2160 }
2161
2162 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2163                                       struct mlx5_ib_sq *sq, u8 sl)
2164 {
2165         void *in;
2166         void *tisc;
2167         int inlen;
2168         int err;
2169
2170         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2171         in = mlx5_vzalloc(inlen);
2172         if (!in)
2173                 return -ENOMEM;
2174
2175         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2176
2177         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2178         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2179
2180         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2181
2182         kvfree(in);
2183
2184         return err;
2185 }
2186
2187 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2188                                          struct mlx5_ib_sq *sq, u8 tx_affinity)
2189 {
2190         void *in;
2191         void *tisc;
2192         int inlen;
2193         int err;
2194
2195         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2196         in = mlx5_vzalloc(inlen);
2197         if (!in)
2198                 return -ENOMEM;
2199
2200         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2201
2202         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2203         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2204
2205         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2206
2207         kvfree(in);
2208
2209         return err;
2210 }
2211
2212 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2213                          const struct ib_ah_attr *ah,
2214                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2215                          u32 path_flags, const struct ib_qp_attr *attr,
2216                          bool alt)
2217 {
2218         enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2219         int err;
2220
2221         if (attr_mask & IB_QP_PKEY_INDEX)
2222                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2223                                                      attr->pkey_index);
2224
2225         if (ah->ah_flags & IB_AH_GRH) {
2226                 if (ah->grh.sgid_index >=
2227                     dev->mdev->port_caps[port - 1].gid_table_len) {
2228                         pr_err("sgid_index (%u) too large. max is %d\n",
2229                                ah->grh.sgid_index,
2230                                dev->mdev->port_caps[port - 1].gid_table_len);
2231                         return -EINVAL;
2232                 }
2233         }
2234
2235         if (ll == IB_LINK_LAYER_ETHERNET) {
2236                 if (!(ah->ah_flags & IB_AH_GRH))
2237                         return -EINVAL;
2238                 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2239                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2240                                                           ah->grh.sgid_index);
2241                 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2242         } else {
2243                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2244                 path->fl_free_ar |=
2245                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2246                 path->rlid = cpu_to_be16(ah->dlid);
2247                 path->grh_mlid = ah->src_path_bits & 0x7f;
2248                 if (ah->ah_flags & IB_AH_GRH)
2249                         path->grh_mlid  |= 1 << 7;
2250                 path->dci_cfi_prio_sl = ah->sl & 0xf;
2251         }
2252
2253         if (ah->ah_flags & IB_AH_GRH) {
2254                 path->mgid_index = ah->grh.sgid_index;
2255                 path->hop_limit  = ah->grh.hop_limit;
2256                 path->tclass_flowlabel =
2257                         cpu_to_be32((ah->grh.traffic_class << 20) |
2258                                     (ah->grh.flow_label));
2259                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2260         }
2261
2262         err = ib_rate_to_mlx5(dev, ah->static_rate);
2263         if (err < 0)
2264                 return err;
2265         path->static_rate = err;
2266         path->port = port;
2267
2268         if (attr_mask & IB_QP_TIMEOUT)
2269                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2270
2271         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2272                 return modify_raw_packet_eth_prio(dev->mdev,
2273                                                   &qp->raw_packet_qp.sq,
2274                                                   ah->sl & 0xf);
2275
2276         return 0;
2277 }
2278
2279 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2280         [MLX5_QP_STATE_INIT] = {
2281                 [MLX5_QP_STATE_INIT] = {
2282                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2283                                           MLX5_QP_OPTPAR_RAE            |
2284                                           MLX5_QP_OPTPAR_RWE            |
2285                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2286                                           MLX5_QP_OPTPAR_PRI_PORT,
2287                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2288                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2289                                           MLX5_QP_OPTPAR_PRI_PORT,
2290                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2291                                           MLX5_QP_OPTPAR_Q_KEY          |
2292                                           MLX5_QP_OPTPAR_PRI_PORT,
2293                 },
2294                 [MLX5_QP_STATE_RTR] = {
2295                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2296                                           MLX5_QP_OPTPAR_RRE            |
2297                                           MLX5_QP_OPTPAR_RAE            |
2298                                           MLX5_QP_OPTPAR_RWE            |
2299                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2300                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2301                                           MLX5_QP_OPTPAR_RWE            |
2302                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2303                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2304                                           MLX5_QP_OPTPAR_Q_KEY,
2305                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2306                                            MLX5_QP_OPTPAR_Q_KEY,
2307                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2308                                           MLX5_QP_OPTPAR_RRE            |
2309                                           MLX5_QP_OPTPAR_RAE            |
2310                                           MLX5_QP_OPTPAR_RWE            |
2311                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2312                 },
2313         },
2314         [MLX5_QP_STATE_RTR] = {
2315                 [MLX5_QP_STATE_RTS] = {
2316                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2317                                           MLX5_QP_OPTPAR_RRE            |
2318                                           MLX5_QP_OPTPAR_RAE            |
2319                                           MLX5_QP_OPTPAR_RWE            |
2320                                           MLX5_QP_OPTPAR_PM_STATE       |
2321                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2322                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2323                                           MLX5_QP_OPTPAR_RWE            |
2324                                           MLX5_QP_OPTPAR_PM_STATE,
2325                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2326                 },
2327         },
2328         [MLX5_QP_STATE_RTS] = {
2329                 [MLX5_QP_STATE_RTS] = {
2330                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2331                                           MLX5_QP_OPTPAR_RAE            |
2332                                           MLX5_QP_OPTPAR_RWE            |
2333                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2334                                           MLX5_QP_OPTPAR_PM_STATE       |
2335                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2336                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2337                                           MLX5_QP_OPTPAR_PM_STATE       |
2338                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2339                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2340                                           MLX5_QP_OPTPAR_SRQN           |
2341                                           MLX5_QP_OPTPAR_CQN_RCV,
2342                 },
2343         },
2344         [MLX5_QP_STATE_SQER] = {
2345                 [MLX5_QP_STATE_RTS] = {
2346                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2347                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2348                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2349                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2350                                            MLX5_QP_OPTPAR_RWE           |
2351                                            MLX5_QP_OPTPAR_RAE           |
2352                                            MLX5_QP_OPTPAR_RRE,
2353                 },
2354         },
2355 };
2356
2357 static int ib_nr_to_mlx5_nr(int ib_mask)
2358 {
2359         switch (ib_mask) {
2360         case IB_QP_STATE:
2361                 return 0;
2362         case IB_QP_CUR_STATE:
2363                 return 0;
2364         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2365                 return 0;
2366         case IB_QP_ACCESS_FLAGS:
2367                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2368                         MLX5_QP_OPTPAR_RAE;
2369         case IB_QP_PKEY_INDEX:
2370                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2371         case IB_QP_PORT:
2372                 return MLX5_QP_OPTPAR_PRI_PORT;
2373         case IB_QP_QKEY:
2374                 return MLX5_QP_OPTPAR_Q_KEY;
2375         case IB_QP_AV:
2376                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2377                         MLX5_QP_OPTPAR_PRI_PORT;
2378         case IB_QP_PATH_MTU:
2379                 return 0;
2380         case IB_QP_TIMEOUT:
2381                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2382         case IB_QP_RETRY_CNT:
2383                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2384         case IB_QP_RNR_RETRY:
2385                 return MLX5_QP_OPTPAR_RNR_RETRY;
2386         case IB_QP_RQ_PSN:
2387                 return 0;
2388         case IB_QP_MAX_QP_RD_ATOMIC:
2389                 return MLX5_QP_OPTPAR_SRA_MAX;
2390         case IB_QP_ALT_PATH:
2391                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2392         case IB_QP_MIN_RNR_TIMER:
2393                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2394         case IB_QP_SQ_PSN:
2395                 return 0;
2396         case IB_QP_MAX_DEST_RD_ATOMIC:
2397                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2398                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2399         case IB_QP_PATH_MIG_STATE:
2400                 return MLX5_QP_OPTPAR_PM_STATE;
2401         case IB_QP_CAP:
2402                 return 0;
2403         case IB_QP_DEST_QPN:
2404                 return 0;
2405         }
2406         return 0;
2407 }
2408
2409 static int ib_mask_to_mlx5_opt(int ib_mask)
2410 {
2411         int result = 0;
2412         int i;
2413
2414         for (i = 0; i < 8 * sizeof(int); i++) {
2415                 if ((1 << i) & ib_mask)
2416                         result |= ib_nr_to_mlx5_nr(1 << i);
2417         }
2418
2419         return result;
2420 }
2421
2422 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2423                                    struct mlx5_ib_rq *rq, int new_state,
2424                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2425 {
2426         void *in;
2427         void *rqc;
2428         int inlen;
2429         int err;
2430
2431         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2432         in = mlx5_vzalloc(inlen);
2433         if (!in)
2434                 return -ENOMEM;
2435
2436         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2437
2438         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2439         MLX5_SET(rqc, rqc, state, new_state);
2440
2441         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2442                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2443                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2444                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2445                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2446                 } else
2447                         pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2448                                      dev->ib_dev.name);
2449         }
2450
2451         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2452         if (err)
2453                 goto out;
2454
2455         rq->state = new_state;
2456
2457 out:
2458         kvfree(in);
2459         return err;
2460 }
2461
2462 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2463                                    struct mlx5_ib_sq *sq,
2464                                    int new_state,
2465                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2466 {
2467         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2468         u32 old_rate = ibqp->rate_limit;
2469         u32 new_rate = old_rate;
2470         u16 rl_index = 0;
2471         void *in;
2472         void *sqc;
2473         int inlen;
2474         int err;
2475
2476         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2477         in = mlx5_vzalloc(inlen);
2478         if (!in)
2479                 return -ENOMEM;
2480
2481         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2482
2483         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2484         MLX5_SET(sqc, sqc, state, new_state);
2485
2486         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2487                 if (new_state != MLX5_SQC_STATE_RDY)
2488                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2489                                 __func__);
2490                 else
2491                         new_rate = raw_qp_param->rate_limit;
2492         }
2493
2494         if (old_rate != new_rate) {
2495                 if (new_rate) {
2496                         err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2497                         if (err) {
2498                                 pr_err("Failed configuring rate %u: %d\n",
2499                                        new_rate, err);
2500                                 goto out;
2501                         }
2502                 }
2503
2504                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2505                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2506         }
2507
2508         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2509         if (err) {
2510                 /* Remove new rate from table if failed */
2511                 if (new_rate &&
2512                     old_rate != new_rate)
2513                         mlx5_rl_remove_rate(dev, new_rate);
2514                 goto out;
2515         }
2516
2517         /* Only remove the old rate after new rate was set */
2518         if ((old_rate &&
2519             (old_rate != new_rate)) ||
2520             (new_state != MLX5_SQC_STATE_RDY))
2521                 mlx5_rl_remove_rate(dev, old_rate);
2522
2523         ibqp->rate_limit = new_rate;
2524         sq->state = new_state;
2525
2526 out:
2527         kvfree(in);
2528         return err;
2529 }
2530
2531 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2532                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2533                                 u8 tx_affinity)
2534 {
2535         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2536         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2537         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2538         int modify_rq = !!qp->rq.wqe_cnt;
2539         int modify_sq = !!qp->sq.wqe_cnt;
2540         int rq_state;
2541         int sq_state;
2542         int err;
2543
2544         switch (raw_qp_param->operation) {
2545         case MLX5_CMD_OP_RST2INIT_QP:
2546                 rq_state = MLX5_RQC_STATE_RDY;
2547                 sq_state = MLX5_SQC_STATE_RDY;
2548                 break;
2549         case MLX5_CMD_OP_2ERR_QP:
2550                 rq_state = MLX5_RQC_STATE_ERR;
2551                 sq_state = MLX5_SQC_STATE_ERR;
2552                 break;
2553         case MLX5_CMD_OP_2RST_QP:
2554                 rq_state = MLX5_RQC_STATE_RST;
2555                 sq_state = MLX5_SQC_STATE_RST;
2556                 break;
2557         case MLX5_CMD_OP_RTR2RTS_QP:
2558         case MLX5_CMD_OP_RTS2RTS_QP:
2559                 if (raw_qp_param->set_mask ==
2560                     MLX5_RAW_QP_RATE_LIMIT) {
2561                         modify_rq = 0;
2562                         sq_state = sq->state;
2563                 } else {
2564                         return raw_qp_param->set_mask ? -EINVAL : 0;
2565                 }
2566                 break;
2567         case MLX5_CMD_OP_INIT2INIT_QP:
2568         case MLX5_CMD_OP_INIT2RTR_QP:
2569                 if (raw_qp_param->set_mask)
2570                         return -EINVAL;
2571                 else
2572                         return 0;
2573         default:
2574                 WARN_ON(1);
2575                 return -EINVAL;
2576         }
2577
2578         if (modify_rq) {
2579                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2580                 if (err)
2581                         return err;
2582         }
2583
2584         if (modify_sq) {
2585                 if (tx_affinity) {
2586                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2587                                                             tx_affinity);
2588                         if (err)
2589                                 return err;
2590                 }
2591
2592                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2593         }
2594
2595         return 0;
2596 }
2597
2598 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2599                                const struct ib_qp_attr *attr, int attr_mask,
2600                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2601 {
2602         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2603                 [MLX5_QP_STATE_RST] = {
2604                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2605                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2606                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2607                 },
2608                 [MLX5_QP_STATE_INIT]  = {
2609                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2610                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2611                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2612                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2613                 },
2614                 [MLX5_QP_STATE_RTR]   = {
2615                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2616                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2617                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2618                 },
2619                 [MLX5_QP_STATE_RTS]   = {
2620                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2621                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2622                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2623                 },
2624                 [MLX5_QP_STATE_SQD] = {
2625                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2626                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2627                 },
2628                 [MLX5_QP_STATE_SQER] = {
2629                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2630                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2631                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2632                 },
2633                 [MLX5_QP_STATE_ERR] = {
2634                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2635                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2636                 }
2637         };
2638
2639         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2640         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2641         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2642         struct mlx5_ib_cq *send_cq, *recv_cq;
2643         struct mlx5_qp_context *context;
2644         struct mlx5_ib_pd *pd;
2645         struct mlx5_ib_port *mibport = NULL;
2646         enum mlx5_qp_state mlx5_cur, mlx5_new;
2647         enum mlx5_qp_optpar optpar;
2648         int mlx5_st;
2649         int err;
2650         u16 op;
2651         u8 tx_affinity = 0;
2652
2653         context = kzalloc(sizeof(*context), GFP_KERNEL);
2654         if (!context)
2655                 return -ENOMEM;
2656
2657         err = to_mlx5_st(ibqp->qp_type);
2658         if (err < 0) {
2659                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2660                 goto out;
2661         }
2662
2663         context->flags = cpu_to_be32(err << 16);
2664
2665         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2666                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2667         } else {
2668                 switch (attr->path_mig_state) {
2669                 case IB_MIG_MIGRATED:
2670                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2671                         break;
2672                 case IB_MIG_REARM:
2673                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2674                         break;
2675                 case IB_MIG_ARMED:
2676                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2677                         break;
2678                 }
2679         }
2680
2681         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2682                 if ((ibqp->qp_type == IB_QPT_RC) ||
2683                     (ibqp->qp_type == IB_QPT_UD &&
2684                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2685                     (ibqp->qp_type == IB_QPT_UC) ||
2686                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2687                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
2688                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2689                         if (mlx5_lag_is_active(dev->mdev)) {
2690                                 tx_affinity = (unsigned int)atomic_add_return(1,
2691                                                 &dev->roce.next_port) %
2692                                                 MLX5_MAX_PORTS + 1;
2693                                 context->flags |= cpu_to_be32(tx_affinity << 24);
2694                         }
2695                 }
2696         }
2697
2698         if (is_sqp(ibqp->qp_type)) {
2699                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2700         } else if (ibqp->qp_type == IB_QPT_UD ||
2701                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2702                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2703         } else if (attr_mask & IB_QP_PATH_MTU) {
2704                 if (attr->path_mtu < IB_MTU_256 ||
2705                     attr->path_mtu > IB_MTU_4096) {
2706                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2707                         err = -EINVAL;
2708                         goto out;
2709                 }
2710                 context->mtu_msgmax = (attr->path_mtu << 5) |
2711                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2712         }
2713
2714         if (attr_mask & IB_QP_DEST_QPN)
2715                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2716
2717         if (attr_mask & IB_QP_PKEY_INDEX)
2718                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2719
2720         /* todo implement counter_index functionality */
2721
2722         if (is_sqp(ibqp->qp_type))
2723                 context->pri_path.port = qp->port;
2724
2725         if (attr_mask & IB_QP_PORT)
2726                 context->pri_path.port = attr->port_num;
2727
2728         if (attr_mask & IB_QP_AV) {
2729                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2730                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2731                                     attr_mask, 0, attr, false);
2732                 if (err)
2733                         goto out;
2734         }
2735
2736         if (attr_mask & IB_QP_TIMEOUT)
2737                 context->pri_path.ackto_lt |= attr->timeout << 3;
2738
2739         if (attr_mask & IB_QP_ALT_PATH) {
2740                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2741                                     &context->alt_path,
2742                                     attr->alt_port_num,
2743                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2744                                     0, attr, true);
2745                 if (err)
2746                         goto out;
2747         }
2748
2749         pd = get_pd(qp);
2750         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2751                 &send_cq, &recv_cq);
2752
2753         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2754         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2755         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2756         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2757
2758         if (attr_mask & IB_QP_RNR_RETRY)
2759                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2760
2761         if (attr_mask & IB_QP_RETRY_CNT)
2762                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2763
2764         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2765                 if (attr->max_rd_atomic)
2766                         context->params1 |=
2767                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2768         }
2769
2770         if (attr_mask & IB_QP_SQ_PSN)
2771                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2772
2773         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2774                 if (attr->max_dest_rd_atomic)
2775                         context->params2 |=
2776                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2777         }
2778
2779         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2780                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2781
2782         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2783                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2784
2785         if (attr_mask & IB_QP_RQ_PSN)
2786                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2787
2788         if (attr_mask & IB_QP_QKEY)
2789                 context->qkey = cpu_to_be32(attr->qkey);
2790
2791         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2792                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2793
2794         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2795                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2796                                qp->port) - 1;
2797                 mibport = &dev->port[port_num];
2798                 context->qp_counter_set_usr_page |=
2799                         cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2800         }
2801
2802         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2803                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2804
2805         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2806                 context->deth_sqpn = cpu_to_be32(1);
2807
2808         mlx5_cur = to_mlx5_state(cur_state);
2809         mlx5_new = to_mlx5_state(new_state);
2810         mlx5_st = to_mlx5_st(ibqp->qp_type);
2811         if (mlx5_st < 0)
2812                 goto out;
2813
2814         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2815             !optab[mlx5_cur][mlx5_new])
2816                 goto out;
2817
2818         op = optab[mlx5_cur][mlx5_new];
2819         optpar = ib_mask_to_mlx5_opt(attr_mask);
2820         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2821
2822         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2823                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2824
2825                 raw_qp_param.operation = op;
2826                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2827                         raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2828                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2829                 }
2830
2831                 if (attr_mask & IB_QP_RATE_LIMIT) {
2832                         raw_qp_param.rate_limit = attr->rate_limit;
2833                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2834                 }
2835
2836                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2837         } else {
2838                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2839                                           &base->mqp);
2840         }
2841
2842         if (err)
2843                 goto out;
2844
2845         qp->state = new_state;
2846
2847         if (attr_mask & IB_QP_ACCESS_FLAGS)
2848                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2849         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2850                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2851         if (attr_mask & IB_QP_PORT)
2852                 qp->port = attr->port_num;
2853         if (attr_mask & IB_QP_ALT_PATH)
2854                 qp->trans_qp.alt_port = attr->alt_port_num;
2855
2856         /*
2857          * If we moved a kernel QP to RESET, clean up all old CQ
2858          * entries and reinitialize the QP.
2859          */
2860         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2861                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2862                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2863                 if (send_cq != recv_cq)
2864                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2865
2866                 qp->rq.head = 0;
2867                 qp->rq.tail = 0;
2868                 qp->sq.head = 0;
2869                 qp->sq.tail = 0;
2870                 qp->sq.cur_post = 0;
2871                 qp->sq.last_poll = 0;
2872                 qp->db.db[MLX5_RCV_DBR] = 0;
2873                 qp->db.db[MLX5_SND_DBR] = 0;
2874         }
2875
2876 out:
2877         kfree(context);
2878         return err;
2879 }
2880
2881 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2882                       int attr_mask, struct ib_udata *udata)
2883 {
2884         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2885         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2886         enum ib_qp_type qp_type;
2887         enum ib_qp_state cur_state, new_state;
2888         int err = -EINVAL;
2889         int port;
2890         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2891
2892         if (ibqp->rwq_ind_tbl)
2893                 return -ENOSYS;
2894
2895         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2896                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2897
2898         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2899                 IB_QPT_GSI : ibqp->qp_type;
2900
2901         mutex_lock(&qp->mutex);
2902
2903         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2904         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2905
2906         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2907                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2908                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2909         }
2910
2911         if (qp_type != MLX5_IB_QPT_REG_UMR &&
2912             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2913                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2914                             cur_state, new_state, ibqp->qp_type, attr_mask);
2915                 goto out;
2916         }
2917
2918         if ((attr_mask & IB_QP_PORT) &&
2919             (attr->port_num == 0 ||
2920              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2921                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2922                             attr->port_num, dev->num_ports);
2923                 goto out;
2924         }
2925
2926         if (attr_mask & IB_QP_PKEY_INDEX) {
2927                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2928                 if (attr->pkey_index >=
2929                     dev->mdev->port_caps[port - 1].pkey_table_len) {
2930                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2931                                     attr->pkey_index);
2932                         goto out;
2933                 }
2934         }
2935
2936         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2937             attr->max_rd_atomic >
2938             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2939                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2940                             attr->max_rd_atomic);
2941                 goto out;
2942         }
2943
2944         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2945             attr->max_dest_rd_atomic >
2946             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2947                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2948                             attr->max_dest_rd_atomic);
2949                 goto out;
2950         }
2951
2952         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2953                 err = 0;
2954                 goto out;
2955         }
2956
2957         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2958
2959 out:
2960         mutex_unlock(&qp->mutex);
2961         return err;
2962 }
2963
2964 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2965 {
2966         struct mlx5_ib_cq *cq;
2967         unsigned cur;
2968
2969         cur = wq->head - wq->tail;
2970         if (likely(cur + nreq < wq->max_post))
2971                 return 0;
2972
2973         cq = to_mcq(ib_cq);
2974         spin_lock(&cq->lock);
2975         cur = wq->head - wq->tail;
2976         spin_unlock(&cq->lock);
2977
2978         return cur + nreq >= wq->max_post;
2979 }
2980
2981 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2982                                           u64 remote_addr, u32 rkey)
2983 {
2984         rseg->raddr    = cpu_to_be64(remote_addr);
2985         rseg->rkey     = cpu_to_be32(rkey);
2986         rseg->reserved = 0;
2987 }
2988
2989 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2990                          struct ib_send_wr *wr, void *qend,
2991                          struct mlx5_ib_qp *qp, int *size)
2992 {
2993         void *seg = eseg;
2994
2995         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2996
2997         if (wr->send_flags & IB_SEND_IP_CSUM)
2998                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2999                                  MLX5_ETH_WQE_L4_CSUM;
3000
3001         seg += sizeof(struct mlx5_wqe_eth_seg);
3002         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3003
3004         if (wr->opcode == IB_WR_LSO) {
3005                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3006                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
3007                 u64 left, leftlen, copysz;
3008                 void *pdata = ud_wr->header;
3009
3010                 left = ud_wr->hlen;
3011                 eseg->mss = cpu_to_be16(ud_wr->mss);
3012                 eseg->inline_hdr_sz = cpu_to_be16(left);
3013
3014                 /*
3015                  * check if there is space till the end of queue, if yes,
3016                  * copy all in one shot, otherwise copy till the end of queue,
3017                  * rollback and than the copy the left
3018                  */
3019                 leftlen = qend - (void *)eseg->inline_hdr_start;
3020                 copysz = min_t(u64, leftlen, left);
3021
3022                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3023
3024                 if (likely(copysz > size_of_inl_hdr_start)) {
3025                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3026                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3027                 }
3028
3029                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3030                         seg = mlx5_get_send_wqe(qp, 0);
3031                         left -= copysz;
3032                         pdata += copysz;
3033                         memcpy(seg, pdata, left);
3034                         seg += ALIGN(left, 16);
3035                         *size += ALIGN(left, 16) / 16;
3036                 }
3037         }
3038
3039         return seg;
3040 }
3041
3042 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3043                              struct ib_send_wr *wr)
3044 {
3045         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3046         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3047         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3048 }
3049
3050 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3051 {
3052         dseg->byte_count = cpu_to_be32(sg->length);
3053         dseg->lkey       = cpu_to_be32(sg->lkey);
3054         dseg->addr       = cpu_to_be64(sg->addr);
3055 }
3056
3057 static u64 get_xlt_octo(u64 bytes)
3058 {
3059         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3060                MLX5_IB_UMR_OCTOWORD;
3061 }
3062
3063 static __be64 frwr_mkey_mask(void)
3064 {
3065         u64 result;
3066
3067         result = MLX5_MKEY_MASK_LEN             |
3068                 MLX5_MKEY_MASK_PAGE_SIZE        |
3069                 MLX5_MKEY_MASK_START_ADDR       |
3070                 MLX5_MKEY_MASK_EN_RINVAL        |
3071                 MLX5_MKEY_MASK_KEY              |
3072                 MLX5_MKEY_MASK_LR               |
3073                 MLX5_MKEY_MASK_LW               |
3074                 MLX5_MKEY_MASK_RR               |
3075                 MLX5_MKEY_MASK_RW               |
3076                 MLX5_MKEY_MASK_A                |
3077                 MLX5_MKEY_MASK_SMALL_FENCE      |
3078                 MLX5_MKEY_MASK_FREE;
3079
3080         return cpu_to_be64(result);
3081 }
3082
3083 static __be64 sig_mkey_mask(void)
3084 {
3085         u64 result;
3086
3087         result = MLX5_MKEY_MASK_LEN             |
3088                 MLX5_MKEY_MASK_PAGE_SIZE        |
3089                 MLX5_MKEY_MASK_START_ADDR       |
3090                 MLX5_MKEY_MASK_EN_SIGERR        |
3091                 MLX5_MKEY_MASK_EN_RINVAL        |
3092                 MLX5_MKEY_MASK_KEY              |
3093                 MLX5_MKEY_MASK_LR               |
3094                 MLX5_MKEY_MASK_LW               |
3095                 MLX5_MKEY_MASK_RR               |
3096                 MLX5_MKEY_MASK_RW               |
3097                 MLX5_MKEY_MASK_SMALL_FENCE      |
3098                 MLX5_MKEY_MASK_FREE             |
3099                 MLX5_MKEY_MASK_BSF_EN;
3100
3101         return cpu_to_be64(result);
3102 }
3103
3104 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3105                             struct mlx5_ib_mr *mr)
3106 {
3107         int size = mr->ndescs * mr->desc_size;
3108
3109         memset(umr, 0, sizeof(*umr));
3110
3111         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3112         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3113         umr->mkey_mask = frwr_mkey_mask();
3114 }
3115
3116 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3117 {
3118         memset(umr, 0, sizeof(*umr));
3119         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3120         umr->flags = MLX5_UMR_INLINE;
3121 }
3122
3123 static __be64 get_umr_enable_mr_mask(void)
3124 {
3125         u64 result;
3126
3127         result = MLX5_MKEY_MASK_KEY |
3128                  MLX5_MKEY_MASK_FREE;
3129
3130         return cpu_to_be64(result);
3131 }
3132
3133 static __be64 get_umr_disable_mr_mask(void)
3134 {
3135         u64 result;
3136
3137         result = MLX5_MKEY_MASK_FREE;
3138
3139         return cpu_to_be64(result);
3140 }
3141
3142 static __be64 get_umr_update_translation_mask(void)
3143 {
3144         u64 result;
3145
3146         result = MLX5_MKEY_MASK_LEN |
3147                  MLX5_MKEY_MASK_PAGE_SIZE |
3148                  MLX5_MKEY_MASK_START_ADDR;
3149
3150         return cpu_to_be64(result);
3151 }
3152
3153 static __be64 get_umr_update_access_mask(int atomic)
3154 {
3155         u64 result;
3156
3157         result = MLX5_MKEY_MASK_LR |
3158                  MLX5_MKEY_MASK_LW |
3159                  MLX5_MKEY_MASK_RR |
3160                  MLX5_MKEY_MASK_RW;
3161
3162         if (atomic)
3163                 result |= MLX5_MKEY_MASK_A;
3164
3165         return cpu_to_be64(result);
3166 }
3167
3168 static __be64 get_umr_update_pd_mask(void)
3169 {
3170         u64 result;
3171
3172         result = MLX5_MKEY_MASK_PD;
3173
3174         return cpu_to_be64(result);
3175 }
3176
3177 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3178                                 struct ib_send_wr *wr, int atomic)
3179 {
3180         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3181
3182         memset(umr, 0, sizeof(*umr));
3183
3184         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3185                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3186         else
3187                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3188
3189         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3190         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3191                 u64 offset = get_xlt_octo(umrwr->offset);
3192
3193                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3194                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3195                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3196         }
3197         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3198                 umr->mkey_mask |= get_umr_update_translation_mask();
3199         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3200                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3201                 umr->mkey_mask |= get_umr_update_pd_mask();
3202         }
3203         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3204                 umr->mkey_mask |= get_umr_enable_mr_mask();
3205         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3206                 umr->mkey_mask |= get_umr_disable_mr_mask();
3207
3208         if (!wr->num_sge)
3209                 umr->flags |= MLX5_UMR_INLINE;
3210 }
3211
3212 static u8 get_umr_flags(int acc)
3213 {
3214         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3215                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3216                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3217                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3218                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3219 }
3220
3221 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3222                              struct mlx5_ib_mr *mr,
3223                              u32 key, int access)
3224 {
3225         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3226
3227         memset(seg, 0, sizeof(*seg));
3228
3229         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3230                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3231         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3232                 /* KLMs take twice the size of MTTs */
3233                 ndescs *= 2;
3234
3235         seg->flags = get_umr_flags(access) | mr->access_mode;
3236         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3237         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3238         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3239         seg->len = cpu_to_be64(mr->ibmr.length);
3240         seg->xlt_oct_size = cpu_to_be32(ndescs);
3241 }
3242
3243 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3244 {
3245         memset(seg, 0, sizeof(*seg));
3246         seg->status = MLX5_MKEY_STATUS_FREE;
3247 }
3248
3249 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3250 {
3251         struct mlx5_umr_wr *umrwr = umr_wr(wr);
3252
3253         memset(seg, 0, sizeof(*seg));
3254         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3255                 seg->status = MLX5_MKEY_STATUS_FREE;
3256
3257         seg->flags = convert_access(umrwr->access_flags);
3258         if (umrwr->pd)
3259                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3260         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3261             !umrwr->length)
3262                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3263
3264         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3265         seg->len = cpu_to_be64(umrwr->length);
3266         seg->log2_page_size = umrwr->page_shift;
3267         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3268                                        mlx5_mkey_variant(umrwr->mkey));
3269 }
3270
3271 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3272                              struct mlx5_ib_mr *mr,
3273                              struct mlx5_ib_pd *pd)
3274 {
3275         int bcount = mr->desc_size * mr->ndescs;
3276
3277         dseg->addr = cpu_to_be64(mr->desc_map);
3278         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3279         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3280 }
3281
3282 static __be32 send_ieth(struct ib_send_wr *wr)
3283 {
3284         switch (wr->opcode) {
3285         case IB_WR_SEND_WITH_IMM:
3286         case IB_WR_RDMA_WRITE_WITH_IMM:
3287                 return wr->ex.imm_data;
3288
3289         case IB_WR_SEND_WITH_INV:
3290                 return cpu_to_be32(wr->ex.invalidate_rkey);
3291
3292         default:
3293                 return 0;
3294         }
3295 }
3296
3297 static u8 calc_sig(void *wqe, int size)
3298 {
3299         u8 *p = wqe;
3300         u8 res = 0;
3301         int i;
3302
3303         for (i = 0; i < size; i++)
3304                 res ^= p[i];
3305
3306         return ~res;
3307 }
3308
3309 static u8 wq_sig(void *wqe)
3310 {
3311         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3312 }
3313
3314 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3315                             void *wqe, int *sz)
3316 {
3317         struct mlx5_wqe_inline_seg *seg;
3318         void *qend = qp->sq.qend;
3319         void *addr;
3320         int inl = 0;
3321         int copy;
3322         int len;
3323         int i;
3324
3325         seg = wqe;
3326         wqe += sizeof(*seg);
3327         for (i = 0; i < wr->num_sge; i++) {
3328                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3329                 len  = wr->sg_list[i].length;
3330                 inl += len;
3331
3332                 if (unlikely(inl > qp->max_inline_data))
3333                         return -ENOMEM;
3334
3335                 if (unlikely(wqe + len > qend)) {
3336                         copy = qend - wqe;
3337                         memcpy(wqe, addr, copy);
3338                         addr += copy;
3339                         len -= copy;
3340                         wqe = mlx5_get_send_wqe(qp, 0);
3341                 }
3342                 memcpy(wqe, addr, len);
3343                 wqe += len;
3344         }
3345
3346         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3347
3348         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3349
3350         return 0;
3351 }
3352
3353 static u16 prot_field_size(enum ib_signature_type type)
3354 {
3355         switch (type) {
3356         case IB_SIG_TYPE_T10_DIF:
3357                 return MLX5_DIF_SIZE;
3358         default:
3359                 return 0;
3360         }
3361 }
3362
3363 static u8 bs_selector(int block_size)
3364 {
3365         switch (block_size) {
3366         case 512:           return 0x1;
3367         case 520:           return 0x2;
3368         case 4096:          return 0x3;
3369         case 4160:          return 0x4;
3370         case 1073741824:    return 0x5;
3371         default:            return 0;
3372         }
3373 }
3374
3375 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3376                               struct mlx5_bsf_inl *inl)
3377 {
3378         /* Valid inline section and allow BSF refresh */
3379         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3380                                        MLX5_BSF_REFRESH_DIF);
3381         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3382         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3383         /* repeating block */
3384         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3385         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3386                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
3387
3388         if (domain->sig.dif.ref_remap)
3389                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3390
3391         if (domain->sig.dif.app_escape) {
3392                 if (domain->sig.dif.ref_escape)
3393                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3394                 else
3395                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3396         }
3397
3398         inl->dif_app_bitmask_check =
3399                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3400 }
3401
3402 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3403                         struct ib_sig_attrs *sig_attrs,
3404                         struct mlx5_bsf *bsf, u32 data_size)
3405 {
3406         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3407         struct mlx5_bsf_basic *basic = &bsf->basic;
3408         struct ib_sig_domain *mem = &sig_attrs->mem;
3409         struct ib_sig_domain *wire = &sig_attrs->wire;
3410
3411         memset(bsf, 0, sizeof(*bsf));
3412
3413         /* Basic + Extended + Inline */
3414         basic->bsf_size_sbs = 1 << 7;
3415         /* Input domain check byte mask */
3416         basic->check_byte_mask = sig_attrs->check_mask;
3417         basic->raw_data_size = cpu_to_be32(data_size);
3418
3419         /* Memory domain */
3420         switch (sig_attrs->mem.sig_type) {
3421         case IB_SIG_TYPE_NONE:
3422                 break;
3423         case IB_SIG_TYPE_T10_DIF:
3424                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3425                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3426                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3427                 break;
3428         default:
3429                 return -EINVAL;
3430         }
3431
3432         /* Wire domain */
3433         switch (sig_attrs->wire.sig_type) {
3434         case IB_SIG_TYPE_NONE:
3435                 break;
3436         case IB_SIG_TYPE_T10_DIF:
3437                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3438                     mem->sig_type == wire->sig_type) {
3439                         /* Same block structure */
3440                         basic->bsf_size_sbs |= 1 << 4;
3441                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3442                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3443                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3444                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3445                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3446                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3447                 } else
3448                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3449
3450                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3451                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3452                 break;
3453         default:
3454                 return -EINVAL;
3455         }
3456
3457         return 0;
3458 }
3459
3460 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3461                                 struct mlx5_ib_qp *qp, void **seg, int *size)
3462 {
3463         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3464         struct ib_mr *sig_mr = wr->sig_mr;
3465         struct mlx5_bsf *bsf;
3466         u32 data_len = wr->wr.sg_list->length;
3467         u32 data_key = wr->wr.sg_list->lkey;
3468         u64 data_va = wr->wr.sg_list->addr;
3469         int ret;
3470         int wqe_size;
3471
3472         if (!wr->prot ||
3473             (data_key == wr->prot->lkey &&
3474              data_va == wr->prot->addr &&
3475              data_len == wr->prot->length)) {
3476                 /**
3477                  * Source domain doesn't contain signature information
3478                  * or data and protection are interleaved in memory.
3479                  * So need construct:
3480                  *                  ------------------
3481                  *                 |     data_klm     |
3482                  *                  ------------------
3483                  *                 |       BSF        |
3484                  *                  ------------------
3485                  **/
3486                 struct mlx5_klm *data_klm = *seg;
3487
3488                 data_klm->bcount = cpu_to_be32(data_len);
3489                 data_klm->key = cpu_to_be32(data_key);
3490                 data_klm->va = cpu_to_be64(data_va);
3491                 wqe_size = ALIGN(sizeof(*data_klm), 64);
3492         } else {
3493                 /**
3494                  * Source domain contains signature information
3495                  * So need construct a strided block format:
3496                  *               ---------------------------
3497                  *              |     stride_block_ctrl     |
3498                  *               ---------------------------
3499                  *              |          data_klm         |
3500                  *               ---------------------------
3501                  *              |          prot_klm         |
3502                  *               ---------------------------
3503                  *              |             BSF           |
3504                  *               ---------------------------
3505                  **/
3506                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3507                 struct mlx5_stride_block_entry *data_sentry;
3508                 struct mlx5_stride_block_entry *prot_sentry;
3509                 u32 prot_key = wr->prot->lkey;
3510                 u64 prot_va = wr->prot->addr;
3511                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3512                 int prot_size;
3513
3514                 sblock_ctrl = *seg;
3515                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3516                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3517
3518                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3519                 if (!prot_size) {
3520                         pr_err("Bad block size given: %u\n", block_size);
3521                         return -EINVAL;
3522                 }
3523                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3524                                                             prot_size);
3525              &nbs