drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <linux/mlx5/fs.h>
  38 #include "mlx5_ib.h"
  39 #include "ib_rep.h"
  40 #include "cmd.h"
  41
  42 /* not supported currently */
  43 static int wq_signature;
  44
  45 enum {
  46         MLX5_IB_ACK_REQ_FREQ    = 8,
  47 };
  48
  49 enum {
  50         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  51         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  52         MLX5_IB_LINK_TYPE_IB            = 0,
  53         MLX5_IB_LINK_TYPE_ETH           = 1
  54 };
  55
  56 enum {
  57         MLX5_IB_SQ_STRIDE       = 6,
  58         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  59 };
  60
  61 static const u32 mlx5_ib_opcode[] = {
  62         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  63         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  64         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  65         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  66         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  67         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  68         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  69         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  70         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  71         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  72         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  73         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  74         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  75         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  76 };
  77
  78 struct mlx5_wqe_eth_pad {
  79         u8 rsvd0[16];
  80 };
  81
  82 enum raw_qp_set_mask_map {
  83         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  84         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  85 };
  86
  87 struct mlx5_modify_raw_qp_param {
  88         u16 operation;
  89
  90         u32 set_mask; /* raw_qp_set_mask_map */
  91
  92         struct mlx5_rate_limit rl;
  93
  94         u8 rq_q_ctr_id;
  95 };
  96
  97 static void get_cqs(enum ib_qp_type qp_type,
  98                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  99                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 100
 101 static int is_qp0(enum ib_qp_type qp_type)
 102 {
 103         return qp_type == IB_QPT_SMI;
 104 }
 105
 106 static int is_sqp(enum ib_qp_type qp_type)
 107 {
 108         return is_qp0(qp_type) || is_qp1(qp_type);
 109 }
 110
 111 /**
 112  * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
 113  * to kernel buffer
 114  *
 115  * @umem: User space memory where the WQ is
 116  * @buffer: buffer to copy to
 117  * @buflen: buffer length
 118  * @wqe_index: index of WQE to copy from
 119  * @wq_offset: offset to start of WQ
 120  * @wq_wqe_cnt: number of WQEs in WQ
 121  * @wq_wqe_shift: log2 of WQE size
 122  * @bcnt: number of bytes to copy
 123  * @bytes_copied: number of bytes to copy (return value)
 124  *
 125  * Copies from start of WQE bcnt or less bytes.
 126  * Does not gurantee to copy the entire WQE.
 127  *
 128  * Return: zero on success, or an error code.
 129  */
 130 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem,
 131                                         void *buffer,
 132                                         u32 buflen,
 133                                         int wqe_index,
 134                                         int wq_offset,
 135                                         int wq_wqe_cnt,
 136                                         int wq_wqe_shift,
 137                                         int bcnt,
 138                                         size_t *bytes_copied)
 139 {
 140         size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
 141         size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
 142         size_t copy_length;
 143         int ret;
 144
 145         /* don't copy more than requested, more than buffer length or
 146          * beyond WQ end
 147          */
 148         copy_length = min_t(u32, buflen, wq_end - offset);
 149         copy_length = min_t(u32, copy_length, bcnt);
 150
 151         ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
 152         if (ret)
 153                 return ret;
 154
 155         if (!ret && bytes_copied)
 156                 *bytes_copied = copy_length;
 157
 158         return 0;
 159 }
 160
 161 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp,
 162                              int wqe_index,
 163                              void *buffer,
 164                              int buflen,
 165                              size_t *bc)
 166 {
 167         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 168         struct ib_umem *umem = base->ubuffer.umem;
 169         struct mlx5_ib_wq *wq = &qp->sq;
 170         struct mlx5_wqe_ctrl_seg *ctrl;
 171         size_t bytes_copied;
 172         size_t bytes_copied2;
 173         size_t wqe_length;
 174         int ret;
 175         int ds;
 176
 177         if (buflen < sizeof(*ctrl))
 178                 return -EINVAL;
 179
 180         /* at first read as much as possible */
 181         ret = mlx5_ib_read_user_wqe_common(umem,
 182                                            buffer,
 183                                            buflen,
 184                                            wqe_index,
 185                                            wq->offset,
 186                                            wq->wqe_cnt,
 187                                            wq->wqe_shift,
 188                                            buflen,
 189                                            &bytes_copied);
 190         if (ret)
 191                 return ret;
 192
 193         /* we need at least control segment size to proceed */
 194         if (bytes_copied < sizeof(*ctrl))
 195                 return -EINVAL;
 196
 197         ctrl = buffer;
 198         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 199         wqe_length = ds * MLX5_WQE_DS_UNITS;
 200
 201         /* if we copied enough then we are done */
 202         if (bytes_copied >= wqe_length) {
 203                 *bc = bytes_copied;
 204                 return 0;
 205         }
 206
 207         /* otherwise this a wrapped around wqe
 208          * so read the remaining bytes starting
 209          * from  wqe_index 0
 210          */
 211         ret = mlx5_ib_read_user_wqe_common(umem,
 212                                            buffer + bytes_copied,
 213                                            buflen - bytes_copied,
 214                                            0,
 215                                            wq->offset,
 216                                            wq->wqe_cnt,
 217                                            wq->wqe_shift,
 218                                            wqe_length - bytes_copied,
 219                                            &bytes_copied2);
 220
 221         if (ret)
 222                 return ret;
 223         *bc = bytes_copied + bytes_copied2;
 224         return 0;
 225 }
 226
 227 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp,
 228                              int wqe_index,
 229                              void *buffer,
 230                              int buflen,
 231                              size_t *bc)
 232 {
 233         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 234         struct ib_umem *umem = base->ubuffer.umem;
 235         struct mlx5_ib_wq *wq = &qp->rq;
 236         size_t bytes_copied;
 237         int ret;
 238
 239         ret = mlx5_ib_read_user_wqe_common(umem,
 240                                            buffer,
 241                                            buflen,
 242                                            wqe_index,
 243                                            wq->offset,
 244                                            wq->wqe_cnt,
 245                                            wq->wqe_shift,
 246                                            buflen,
 247                                            &bytes_copied);
 248
 249         if (ret)
 250                 return ret;
 251         *bc = bytes_copied;
 252         return 0;
 253 }
 254
 255 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq,
 256                               int wqe_index,
 257                               void *buffer,
 258                               int buflen,
 259                               size_t *bc)
 260 {
 261         struct ib_umem *umem = srq->umem;
 262         size_t bytes_copied;
 263         int ret;
 264
 265         ret = mlx5_ib_read_user_wqe_common(umem,
 266                                            buffer,
 267                                            buflen,
 268                                            wqe_index,
 269                                            0,
 270                                            srq->msrq.max,
 271                                            srq->msrq.wqe_shift,
 272                                            buflen,
 273                                            &bytes_copied);
 274
 275         if (ret)
 276                 return ret;
 277         *bc = bytes_copied;
 278         return 0;
 279 }
 280
 281 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 282 {
 283         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 284         struct ib_event event;
 285
 286         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 287                 /* This event is only valid for trans_qps */
 288                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 289         }
 290
 291         if (ibqp->event_handler) {
 292                 event.device     = ibqp->device;
 293                 event.element.qp = ibqp;
 294                 switch (type) {
 295                 case MLX5_EVENT_TYPE_PATH_MIG:
 296                         event.event = IB_EVENT_PATH_MIG;
 297                         break;
 298                 case MLX5_EVENT_TYPE_COMM_EST:
 299                         event.event = IB_EVENT_COMM_EST;
 300                         break;
 301                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 302                         event.event = IB_EVENT_SQ_DRAINED;
 303                         break;
 304                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 305                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 306                         break;
 307                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 308                         event.event = IB_EVENT_QP_FATAL;
 309                         break;
 310                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 311                         event.event = IB_EVENT_PATH_MIG_ERR;
 312                         break;
 313                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 314                         event.event = IB_EVENT_QP_REQ_ERR;
 315                         break;
 316                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 317                         event.event = IB_EVENT_QP_ACCESS_ERR;
 318                         break;
 319                 default:
 320                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 321                         return;
 322                 }
 323
 324                 ibqp->event_handler(&event, ibqp->qp_context);
 325         }
 326 }
 327
 328 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 329                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 330 {
 331         int wqe_size;
 332         int wq_size;
 333
 334         /* Sanity check RQ size before proceeding */
 335         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 336                 return -EINVAL;
 337
 338         if (!has_rq) {
 339                 qp->rq.max_gs = 0;
 340                 qp->rq.wqe_cnt = 0;
 341                 qp->rq.wqe_shift = 0;
 342                 cap->max_recv_wr = 0;
 343                 cap->max_recv_sge = 0;
 344         } else {
 345                 if (ucmd) {
 346                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 347                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 348                                 return -EINVAL;
 349                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 350                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 351                                 return -EINVAL;
 352                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 353                         qp->rq.max_post = qp->rq.wqe_cnt;
 354                 } else {
 355                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 356                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 357                         wqe_size = roundup_pow_of_two(wqe_size);
 358                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 359                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 360                         qp->rq.wqe_cnt = wq_size / wqe_size;
 361                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 362                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 363                                             wqe_size,
 364                                             MLX5_CAP_GEN(dev->mdev,
 365                                                          max_wqe_sz_rq));
 366                                 return -EINVAL;
 367                         }
 368                         qp->rq.wqe_shift = ilog2(wqe_size);
 369                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 370                         qp->rq.max_post = qp->rq.wqe_cnt;
 371                 }
 372         }
 373
 374         return 0;
 375 }
 376
 377 static int sq_overhead(struct ib_qp_init_attr *attr)
 378 {
 379         int size = 0;
 380
 381         switch (attr->qp_type) {
 382         case IB_QPT_XRC_INI:
 383                 size += sizeof(struct mlx5_wqe_xrc_seg);
 384                 /* fall through */
 385         case IB_QPT_RC:
 386                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 387                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 388                             sizeof(struct mlx5_wqe_raddr_seg),
 389                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 390                             sizeof(struct mlx5_mkey_seg) +
 391                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 392                             MLX5_IB_UMR_OCTOWORD);
 393                 break;
 394
 395         case IB_QPT_XRC_TGT:
 396                 return 0;
 397
 398         case IB_QPT_UC:
 399                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 400                         max(sizeof(struct mlx5_wqe_raddr_seg),
 401                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 402                             sizeof(struct mlx5_mkey_seg));
 403                 break;
 404
 405         case IB_QPT_UD:
 406                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 407                         size += sizeof(struct mlx5_wqe_eth_pad) +
 408                                 sizeof(struct mlx5_wqe_eth_seg);
 409                 /* fall through */
 410         case IB_QPT_SMI:
 411         case MLX5_IB_QPT_HW_GSI:
 412                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 413                         sizeof(struct mlx5_wqe_datagram_seg);
 414                 break;
 415
 416         case MLX5_IB_QPT_REG_UMR:
 417                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 418                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 419                         sizeof(struct mlx5_mkey_seg);
 420                 break;
 421
 422         default:
 423                 return -EINVAL;
 424         }
 425
 426         return size;
 427 }
 428
 429 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 430 {
 431         int inl_size = 0;
 432         int size;
 433
 434         size = sq_overhead(attr);
 435         if (size < 0)
 436                 return size;
 437
 438         if (attr->cap.max_inline_data) {
 439                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 440                         attr->cap.max_inline_data;
 441         }
 442
 443         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 444         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 445             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 446                         return MLX5_SIG_WQE_SIZE;
 447         else
 448                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 449 }
 450
 451 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 452 {
 453         int max_sge;
 454
 455         if (attr->qp_type == IB_QPT_RC)
 456                 max_sge = (min_t(int, wqe_size, 512) -
 457                            sizeof(struct mlx5_wqe_ctrl_seg) -
 458                            sizeof(struct mlx5_wqe_raddr_seg)) /
 459                         sizeof(struct mlx5_wqe_data_seg);
 460         else if (attr->qp_type == IB_QPT_XRC_INI)
 461                 max_sge = (min_t(int, wqe_size, 512) -
 462                            sizeof(struct mlx5_wqe_ctrl_seg) -
 463                            sizeof(struct mlx5_wqe_xrc_seg) -
 464                            sizeof(struct mlx5_wqe_raddr_seg)) /
 465                         sizeof(struct mlx5_wqe_data_seg);
 466         else
 467                 max_sge = (wqe_size - sq_overhead(attr)) /
 468                         sizeof(struct mlx5_wqe_data_seg);
 469
 470         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 471                      sizeof(struct mlx5_wqe_data_seg));
 472 }
 473
 474 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 475                         struct mlx5_ib_qp *qp)
 476 {
 477         int wqe_size;
 478         int wq_size;
 479
 480         if (!attr->cap.max_send_wr)
 481                 return 0;
 482
 483         wqe_size = calc_send_wqe(attr);
 484         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 485         if (wqe_size < 0)
 486                 return wqe_size;
 487
 488         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 489                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 490                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 491                 return -EINVAL;
 492         }
 493
 494         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 495                               sizeof(struct mlx5_wqe_inline_seg);
 496         attr->cap.max_inline_data = qp->max_inline_data;
 497
 498         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 499                 qp->signature_en = true;
 500
 501         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 502         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 503         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 504                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 505                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 506                             qp->sq.wqe_cnt,
 507                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 508                 return -ENOMEM;
 509         }
 510         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 511         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 512         if (qp->sq.max_gs < attr->cap.max_send_sge)
 513                 return -ENOMEM;
 514
 515         attr->cap.max_send_sge = qp->sq.max_gs;
 516         qp->sq.max_post = wq_size / wqe_size;
 517         attr->cap.max_send_wr = qp->sq.max_post;
 518
 519         return wq_size;
 520 }
 521
 522 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 523                             struct mlx5_ib_qp *qp,
 524                             struct mlx5_ib_create_qp *ucmd,
 525                             struct mlx5_ib_qp_base *base,
 526                             struct ib_qp_init_attr *attr)
 527 {
 528         int desc_sz = 1 << qp->sq.wqe_shift;
 529
 530         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 531                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 532                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 533                 return -EINVAL;
 534         }
 535
 536         if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
 537                 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
 538                              ucmd->sq_wqe_count);
 539                 return -EINVAL;
 540         }
 541
 542         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 543
 544         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 545                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 546                              qp->sq.wqe_cnt,
 547                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 548                 return -EINVAL;
 549         }
 550
 551         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 552             qp->flags & MLX5_IB_QP_UNDERLAY) {
 553                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 554                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 555         } else {
 556                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 557                                          (qp->sq.wqe_cnt << 6);
 558         }
 559
 560         return 0;
 561 }
 562
 563 static int qp_has_rq(struct ib_qp_init_attr *attr)
 564 {
 565         if (attr->qp_type == IB_QPT_XRC_INI ||
 566             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 567             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 568             !attr->cap.max_recv_wr)
 569                 return 0;
 570
 571         return 1;
 572 }
 573
 574 enum {
 575         /* this is the first blue flame register in the array of bfregs assigned
 576          * to a processes. Since we do not use it for blue flame but rather
 577          * regular 64 bit doorbells, we do not need a lock for maintaiing
 578          * "odd/even" order
 579          */
 580         NUM_NON_BLUE_FLAME_BFREGS = 1,
 581 };
 582
 583 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 584 {
 585         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 586 }
 587
 588 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 589                          struct mlx5_bfreg_info *bfregi)
 590 {
 591         int n;
 592
 593         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 594             NUM_NON_BLUE_FLAME_BFREGS;
 595
 596         return n >= 0 ? n : 0;
 597 }
 598
 599 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 600                            struct mlx5_bfreg_info *bfregi)
 601 {
 602         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 603 }
 604
 605 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 606                           struct mlx5_bfreg_info *bfregi)
 607 {
 608         int med;
 609
 610         med = num_med_bfreg(dev, bfregi);
 611         return ++med;
 612 }
 613
 614 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 615                                   struct mlx5_bfreg_info *bfregi)
 616 {
 617         int i;
 618
 619         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 620                 if (!bfregi->count[i]) {
 621                         bfregi->count[i]++;
 622                         return i;
 623                 }
 624         }
 625
 626         return -ENOMEM;
 627 }
 628
 629 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 630                                  struct mlx5_bfreg_info *bfregi)
 631 {
 632         int minidx = first_med_bfreg(dev, bfregi);
 633         int i;
 634
 635         if (minidx < 0)
 636                 return minidx;
 637
 638         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 639                 if (bfregi->count[i] < bfregi->count[minidx])
 640                         minidx = i;
 641                 if (!bfregi->count[minidx])
 642                         break;
 643         }
 644
 645         bfregi->count[minidx]++;
 646         return minidx;
 647 }
 648
 649 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 650                        struct mlx5_bfreg_info *bfregi)
 651 {
 652         int bfregn = -ENOMEM;
 653
 654         mutex_lock(&bfregi->lock);
 655         if (bfregi->ver >= 2) {
 656                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 657                 if (bfregn < 0)
 658                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 659         }
 660
 661         if (bfregn < 0) {
 662                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 663                 bfregn = 0;
 664                 bfregi->count[bfregn]++;
 665         }
 666         mutex_unlock(&bfregi->lock);
 667
 668         return bfregn;
 669 }
 670
 671 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 672 {
 673         mutex_lock(&bfregi->lock);
 674         bfregi->count[bfregn]--;
 675         mutex_unlock(&bfregi->lock);
 676 }
 677
 678 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 679 {
 680         switch (state) {
 681         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 682         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 683         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 684         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 685         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 686         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 687         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 688         default:                return -1;
 689         }
 690 }
 691
 692 static int to_mlx5_st(enum ib_qp_type type)
 693 {
 694         switch (type) {
 695         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 696         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 697         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 698         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 699         case IB_QPT_XRC_INI:
 700         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 701         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 702         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 703         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 704         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 705         case IB_QPT_RAW_PACKET:
 706         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 707         case IB_QPT_MAX:
 708         default:                return -EINVAL;
 709         }
 710 }
 711
 712 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 713                              struct mlx5_ib_cq *recv_cq);
 714 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 715                                struct mlx5_ib_cq *recv_cq);
 716
 717 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 718                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 719                         bool dyn_bfreg)
 720 {
 721         unsigned int bfregs_per_sys_page;
 722         u32 index_of_sys_page;
 723         u32 offset;
 724
 725         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 726                                 MLX5_NON_FP_BFREGS_PER_UAR;
 727         index_of_sys_page = bfregn / bfregs_per_sys_page;
 728
 729         if (dyn_bfreg) {
 730                 index_of_sys_page += bfregi->num_static_sys_pages;
 731
 732                 if (index_of_sys_page >= bfregi->num_sys_pages)
 733                         return -EINVAL;
 734
 735                 if (bfregn > bfregi->num_dyn_bfregs ||
 736                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 737                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 738                         return -EINVAL;
 739                 }
 740         }
 741
 742         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 743         return bfregi->sys_pages[index_of_sys_page] + offset;
 744 }
 745
 746 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 747                             unsigned long addr, size_t size,
 748                             struct ib_umem **umem, int *npages, int *page_shift,
 749                             int *ncont, u32 *offset)
 750 {
 751         int err;
 752
 753         *umem = ib_umem_get(udata, addr, size, 0, 0);
 754         if (IS_ERR(*umem)) {
 755                 mlx5_ib_dbg(dev, "umem_get failed\n");
 756                 return PTR_ERR(*umem);
 757         }
 758
 759         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 760
 761         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 762         if (err) {
 763                 mlx5_ib_warn(dev, "bad offset\n");
 764                 goto err_umem;
 765         }
 766
 767         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 768                     addr, size, *npages, *page_shift, *ncont, *offset);
 769
 770         return 0;
 771
 772 err_umem:
 773         ib_umem_release(*umem);
 774         *umem = NULL;
 775
 776         return err;
 777 }
 778
 779 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 780                             struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
 781 {
 782         struct mlx5_ib_ucontext *context =
 783                 rdma_udata_to_drv_context(
 784                         udata,
 785                         struct mlx5_ib_ucontext,
 786                         ibucontext);
 787
 788         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 789                 atomic_dec(&dev->delay_drop.rqs_cnt);
 790
 791         mlx5_ib_db_unmap_user(context, &rwq->db);
 792         if (rwq->umem)
 793                 ib_umem_release(rwq->umem);
 794 }
 795
 796 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 797                           struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
 798                           struct mlx5_ib_create_wq *ucmd)
 799 {
 800         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
 801                 udata, struct mlx5_ib_ucontext, ibucontext);
 802         int page_shift = 0;
 803         int npages;
 804         u32 offset = 0;
 805         int ncont = 0;
 806         int err;
 807
 808         if (!ucmd->buf_addr)
 809                 return -EINVAL;
 810
 811         rwq->umem = ib_umem_get(udata, ucmd->buf_addr, rwq->buf_size, 0, 0);
 812         if (IS_ERR(rwq->umem)) {
 813                 mlx5_ib_dbg(dev, "umem_get failed\n");
 814                 err = PTR_ERR(rwq->umem);
 815                 return err;
 816         }
 817
 818         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 819                            &ncont, NULL);
 820         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 821                                      &rwq->rq_page_offset);
 822         if (err) {
 823                 mlx5_ib_warn(dev, "bad offset\n");
 824                 goto err_umem;
 825         }
 826
 827         rwq->rq_num_pas = ncont;
 828         rwq->page_shift = page_shift;
 829         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 830         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 831
 832         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 833                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 834                     npages, page_shift, ncont, offset);
 835
 836         err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
 837         if (err) {
 838                 mlx5_ib_dbg(dev, "map failed\n");
 839                 goto err_umem;
 840         }
 841
 842         rwq->create_type = MLX5_WQ_USER;
 843         return 0;
 844
 845 err_umem:
 846         ib_umem_release(rwq->umem);
 847         return err;
 848 }
 849
 850 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 851                          struct mlx5_bfreg_info *bfregi, int bfregn)
 852 {
 853         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 854                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 855 }
 856
 857 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 858                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 859                           struct ib_qp_init_attr *attr,
 860                           u32 **in,
 861                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 862                           struct mlx5_ib_qp_base *base)
 863 {
 864         struct mlx5_ib_ucontext *context;
 865         struct mlx5_ib_create_qp ucmd;
 866         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 867         int page_shift = 0;
 868         int uar_index = 0;
 869         int npages;
 870         u32 offset = 0;
 871         int bfregn;
 872         int ncont = 0;
 873         __be64 *pas;
 874         void *qpc;
 875         int err;
 876         u16 uid;
 877
 878         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 879         if (err) {
 880                 mlx5_ib_dbg(dev, "copy failed\n");
 881                 return err;
 882         }
 883
 884         context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
 885                                             ibucontext);
 886         if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
 887                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 888                                                 ucmd.bfreg_index, true);
 889                 if (uar_index < 0)
 890                         return uar_index;
 891
 892                 bfregn = MLX5_IB_INVALID_BFREG;
 893         } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
 894                 /*
 895                  * TBD: should come from the verbs when we have the API
 896                  */
 897                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 898                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
 899         }
 900         else {
 901                 bfregn = alloc_bfreg(dev, &context->bfregi);
 902                 if (bfregn < 0)
 903                         return bfregn;
 904         }
 905
 906         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 907         if (bfregn != MLX5_IB_INVALID_BFREG)
 908                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 909                                                 false);
 910
 911         qp->rq.offset = 0;
 912         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 913         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 914
 915         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 916         if (err)
 917                 goto err_bfreg;
 918
 919         if (ucmd.buf_addr && ubuffer->buf_size) {
 920                 ubuffer->buf_addr = ucmd.buf_addr;
 921                 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
 922                                        ubuffer->buf_size, &ubuffer->umem,
 923                                        &npages, &page_shift, &ncont, &offset);
 924                 if (err)
 925                         goto err_bfreg;
 926         } else {
 927                 ubuffer->umem = NULL;
 928         }
 929
 930         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 931                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 932         *in = kvzalloc(*inlen, GFP_KERNEL);
 933         if (!*in) {
 934                 err = -ENOMEM;
 935                 goto err_umem;
 936         }
 937
 938         uid = (attr->qp_type != IB_QPT_XRC_TGT &&
 939                attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
 940         MLX5_SET(create_qp_in, *in, uid, uid);
 941         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 942         if (ubuffer->umem)
 943                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 944
 945         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 946
 947         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 948         MLX5_SET(qpc, qpc, page_offset, offset);
 949
 950         MLX5_SET(qpc, qpc, uar_page, uar_index);
 951         if (bfregn != MLX5_IB_INVALID_BFREG)
 952                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 953         else
 954                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
 955         qp->bfregn = bfregn;
 956
 957         err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db);
 958         if (err) {
 959                 mlx5_ib_dbg(dev, "map failed\n");
 960                 goto err_free;
 961         }
 962
 963         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
 964         if (err) {
 965                 mlx5_ib_dbg(dev, "copy failed\n");
 966                 goto err_unmap;
 967         }
 968         qp->create_type = MLX5_QP_USER;
 969
 970         return 0;
 971
 972 err_unmap:
 973         mlx5_ib_db_unmap_user(context, &qp->db);
 974
 975 err_free:
 976         kvfree(*in);
 977
 978 err_umem:
 979         if (ubuffer->umem)
 980                 ib_umem_release(ubuffer->umem);
 981
 982 err_bfreg:
 983         if (bfregn != MLX5_IB_INVALID_BFREG)
 984                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
 985         return err;
 986 }
 987
 988 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 989                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base,
 990                             struct ib_udata *udata)
 991 {
 992         struct mlx5_ib_ucontext *context =
 993                 rdma_udata_to_drv_context(
 994                         udata,
 995                         struct mlx5_ib_ucontext,
 996                         ibucontext);
 997
 998         mlx5_ib_db_unmap_user(context, &qp->db);
 999         if (base->ubuffer.umem)
1000                 ib_umem_release(base->ubuffer.umem);
1001
1002         /*
1003          * Free only the BFREGs which are handled by the kernel.
1004          * BFREGs of UARs allocated dynamically are handled by user.
1005          */
1006         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1007                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1008 }
1009
1010 /* get_sq_edge - Get the next nearby edge.
1011  *
1012  * An 'edge' is defined as the first following address after the end
1013  * of the fragment or the SQ. Accordingly, during the WQE construction
1014  * which repetitively increases the pointer to write the next data, it
1015  * simply should check if it gets to an edge.
1016  *
1017  * @sq - SQ buffer.
1018  * @idx - Stride index in the SQ buffer.
1019  *
1020  * Return:
1021  *      The new edge.
1022  */
1023 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
1024 {
1025         void *fragment_end;
1026
1027         fragment_end = mlx5_frag_buf_get_wqe
1028                 (&sq->fbc,
1029                  mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
1030
1031         return fragment_end + MLX5_SEND_WQE_BB;
1032 }
1033
1034 static int create_kernel_qp(struct mlx5_ib_dev *dev,
1035                             struct ib_qp_init_attr *init_attr,
1036                             struct mlx5_ib_qp *qp,
1037                             u32 **in, int *inlen,
1038                             struct mlx5_ib_qp_base *base)
1039 {
1040         int uar_index;
1041         void *qpc;
1042         int err;
1043
1044         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
1045                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
1046                                         IB_QP_CREATE_IPOIB_UD_LSO |
1047                                         IB_QP_CREATE_NETIF_QP |
1048                                         mlx5_ib_create_qp_sqpn_qp1()))
1049                 return -EINVAL;
1050
1051         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1052                 qp->bf.bfreg = &dev->fp_bfreg;
1053         else
1054                 qp->bf.bfreg = &dev->bfreg;
1055
1056         /* We need to divide by two since each register is comprised of
1057          * two buffers of identical size, namely odd and even
1058          */
1059         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1060         uar_index = qp->bf.bfreg->index;
1061
1062         err = calc_sq_size(dev, init_attr, qp);
1063         if (err < 0) {
1064                 mlx5_ib_dbg(dev, "err %d\n", err);
1065                 return err;
1066         }
1067
1068         qp->rq.offset = 0;
1069         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1070         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1071
1072         err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1073                                        &qp->buf, dev->mdev->priv.numa_node);
1074         if (err) {
1075                 mlx5_ib_dbg(dev, "err %d\n", err);
1076                 return err;
1077         }
1078
1079         if (qp->rq.wqe_cnt)
1080                 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1081                               ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1082
1083         if (qp->sq.wqe_cnt) {
1084                 int sq_strides_offset = (qp->sq.offset  & (PAGE_SIZE - 1)) /
1085                                         MLX5_SEND_WQE_BB;
1086                 mlx5_init_fbc_offset(qp->buf.frags +
1087                                      (qp->sq.offset / PAGE_SIZE),
1088                                      ilog2(MLX5_SEND_WQE_BB),
1089                                      ilog2(qp->sq.wqe_cnt),
1090                                      sq_strides_offset, &qp->sq.fbc);
1091
1092                 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1093         }
1094
1095         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1096                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1097         *in = kvzalloc(*inlen, GFP_KERNEL);
1098         if (!*in) {
1099                 err = -ENOMEM;
1100                 goto err_buf;
1101         }
1102
1103         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1104         MLX5_SET(qpc, qpc, uar_page, uar_index);
1105         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1106
1107         /* Set "fast registration enabled" for all kernel QPs */
1108         MLX5_SET(qpc, qpc, fre, 1);
1109         MLX5_SET(qpc, qpc, rlky, 1);
1110
1111         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
1112                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1113                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1114         }
1115
1116         mlx5_fill_page_frag_array(&qp->buf,
1117                                   (__be64 *)MLX5_ADDR_OF(create_qp_in,
1118                                                          *in, pas));
1119
1120         err = mlx5_db_alloc(dev->mdev, &qp->db);
1121         if (err) {
1122                 mlx5_ib_dbg(dev, "err %d\n", err);
1123                 goto err_free;
1124         }
1125
1126         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1127                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1128         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1129                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1130         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1131                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1132         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1133                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1134         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1135                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1136
1137         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1138             !qp->sq.w_list || !qp->sq.wqe_head) {
1139                 err = -ENOMEM;
1140                 goto err_wrid;
1141         }
1142         qp->create_type = MLX5_QP_KERNEL;
1143
1144         return 0;
1145
1146 err_wrid:
1147         kvfree(qp->sq.wqe_head);
1148         kvfree(qp->sq.w_list);
1149         kvfree(qp->sq.wrid);
1150         kvfree(qp->sq.wr_data);
1151         kvfree(qp->rq.wrid);
1152         mlx5_db_free(dev->mdev, &qp->db);
1153
1154 err_free:
1155         kvfree(*in);
1156
1157 err_buf:
1158         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1159         return err;
1160 }
1161
1162 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1163 {
1164         kvfree(qp->sq.wqe_head);
1165         kvfree(qp->sq.w_list);
1166         kvfree(qp->sq.wrid);
1167         kvfree(qp->sq.wr_data);
1168         kvfree(qp->rq.wrid);
1169         mlx5_db_free(dev->mdev, &qp->db);
1170         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1171 }
1172
1173 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1174 {
1175         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1176             (attr->qp_type == MLX5_IB_QPT_DCI) ||
1177             (attr->qp_type == IB_QPT_XRC_INI))
1178                 return MLX5_SRQ_RQ;
1179         else if (!qp->has_rq)
1180                 return MLX5_ZERO_LEN_RQ;
1181         else
1182                 return MLX5_NON_ZERO_RQ;
1183 }
1184
1185 static int is_connected(enum ib_qp_type qp_type)
1186 {
1187         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1188             qp_type == MLX5_IB_QPT_DCI)
1189                 return 1;
1190
1191         return 0;
1192 }
1193
1194 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1195                                     struct mlx5_ib_qp *qp,
1196                                     struct mlx5_ib_sq *sq, u32 tdn,
1197                                     struct ib_pd *pd)
1198 {
1199         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1200         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1201
1202         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1203         MLX5_SET(tisc, tisc, transport_domain, tdn);
1204         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1205                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1206
1207         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1208 }
1209
1210 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1211                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1212 {
1213         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1214 }
1215
1216 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1217                                        struct mlx5_ib_sq *sq)
1218 {
1219         if (sq->flow_rule)
1220                 mlx5_del_flow_rules(sq->flow_rule);
1221 }
1222
1223 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1224                                    struct ib_udata *udata,
1225                                    struct mlx5_ib_sq *sq, void *qpin,
1226                                    struct ib_pd *pd)
1227 {
1228         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1229         __be64 *pas;
1230         void *in;
1231         void *sqc;
1232         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1233         void *wq;
1234         int inlen;
1235         int err;
1236         int page_shift = 0;
1237         int npages;
1238         int ncont = 0;
1239         u32 offset = 0;
1240
1241         err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1242                                &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1243                                &offset);
1244         if (err)
1245                 return err;
1246
1247         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1248         in = kvzalloc(inlen, GFP_KERNEL);
1249         if (!in) {
1250                 err = -ENOMEM;
1251                 goto err_umem;
1252         }
1253
1254         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1255         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1256         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1257         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1258                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1259         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1260         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1261         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1262         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1263         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1264         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1265             MLX5_CAP_ETH(dev->mdev, swp))
1266                 MLX5_SET(sqc, sqc, allow_swp, 1);
1267
1268         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1269         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1270         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1271         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1272         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1273         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1274         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1275         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1276         MLX5_SET(wq, wq, page_offset, offset);
1277
1278         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1279         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1280
1281         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1282
1283         kvfree(in);
1284
1285         if (err)
1286                 goto err_umem;
1287
1288         err = create_flow_rule_vport_sq(dev, sq);
1289         if (err)
1290                 goto err_flow;
1291
1292         return 0;
1293
1294 err_flow:
1295         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1296
1297 err_umem:
1298         ib_umem_release(sq->ubuffer.umem);
1299         sq->ubuffer.umem = NULL;
1300
1301         return err;
1302 }
1303
1304 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1305                                      struct mlx5_ib_sq *sq)
1306 {
1307         destroy_flow_rule_vport_sq(dev, sq);
1308         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1309         ib_umem_release(sq->ubuffer.umem);
1310 }
1311
1312 static size_t get_rq_pas_size(void *qpc)
1313 {
1314         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1315         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1316         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1317         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1318         u32 po_quanta     = 1 << (log_page_size - 6);
1319         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1320         u32 page_size     = 1 << log_page_size;
1321         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1322         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1323
1324         return rq_num_pas * sizeof(u64);
1325 }
1326
1327 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1328                                    struct mlx5_ib_rq *rq, void *qpin,
1329                                    size_t qpinlen, struct ib_pd *pd)
1330 {
1331         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1332         __be64 *pas;
1333         __be64 *qp_pas;
1334         void *in;
1335         void *rqc;
1336         void *wq;
1337         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1338         size_t rq_pas_size = get_rq_pas_size(qpc);
1339         size_t inlen;
1340         int err;
1341
1342         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1343                 return -EINVAL;
1344
1345         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1346         in = kvzalloc(inlen, GFP_KERNEL);
1347         if (!in)
1348                 return -ENOMEM;
1349
1350         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1351         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1352         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1353                 MLX5_SET(rqc, rqc, vsd, 1);
1354         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1355         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1356         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1357         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1358         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1359
1360         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1361                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1362
1363         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1364         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1365         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1366                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1367         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1368         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1369         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1370         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1371         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1372         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1373
1374         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1375         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1376         memcpy(pas, qp_pas, rq_pas_size);
1377
1378         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1379
1380         kvfree(in);
1381
1382         return err;
1383 }
1384
1385 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1386                                      struct mlx5_ib_rq *rq)
1387 {
1388         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1389 }
1390
1391 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1392 {
1393         return  (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1394                  MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1395                  MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1396 }
1397
1398 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1399                                       struct mlx5_ib_rq *rq,
1400                                       u32 qp_flags_en,
1401                                       struct ib_pd *pd)
1402 {
1403         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1404                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1405                 mlx5_ib_disable_lb(dev, false, true);
1406         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1407 }
1408
1409 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1410                                     struct mlx5_ib_rq *rq, u32 tdn,
1411                                     u32 *qp_flags_en,
1412                                     struct ib_pd *pd)
1413 {
1414         u8 lb_flag = 0;
1415         u32 *in;
1416         void *tirc;
1417         int inlen;
1418         int err;
1419
1420         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1421         in = kvzalloc(inlen, GFP_KERNEL);
1422         if (!in)
1423                 return -ENOMEM;
1424
1425         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1426         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1427         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1428         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1429         MLX5_SET(tirc, tirc, transport_domain, tdn);
1430         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1431                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1432
1433         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1434                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1435
1436         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1437                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1438
1439         if (dev->rep) {
1440                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1441                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1442         }
1443
1444         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1445
1446         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1447
1448         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1449                 err = mlx5_ib_enable_lb(dev, false, true);
1450
1451                 if (err)
1452                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1453         }
1454         kvfree(in);
1455
1456         return err;
1457 }
1458
1459 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1460                                 u32 *in, size_t inlen,
1461                                 struct ib_pd *pd,
1462                                 struct ib_udata *udata,
1463                                 struct mlx5_ib_create_qp_resp *resp)
1464 {
1465         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1466         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1467         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1468         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1469                 udata, struct mlx5_ib_ucontext, ibucontext);
1470         int err;
1471         u32 tdn = mucontext->tdn;
1472         u16 uid = to_mpd(pd)->uid;
1473
1474         if (qp->sq.wqe_cnt) {
1475                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1476                 if (err)
1477                         return err;
1478
1479                 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1480                 if (err)
1481                         goto err_destroy_tis;
1482
1483                 if (uid) {
1484                         resp->tisn = sq->tisn;
1485                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1486                         resp->sqn = sq->base.mqp.qpn;
1487                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1488                 }
1489
1490                 sq->base.container_mibqp = qp;
1491                 sq->base.mqp.event = mlx5_ib_qp_event;
1492         }
1493
1494         if (qp->rq.wqe_cnt) {
1495                 rq->base.container_mibqp = qp;
1496
1497                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1498                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1499                 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1500                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1501                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1502                 if (err)
1503                         goto err_destroy_sq;
1504
1505                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
1506                 if (err)
1507                         goto err_destroy_rq;
1508
1509                 if (uid) {
1510                         resp->rqn = rq->base.mqp.qpn;
1511                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1512                         resp->tirn = rq->tirn;
1513                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1514                 }
1515         }
1516
1517         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1518                                                      rq->base.mqp.qpn;
1519         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1520         if (err)
1521                 goto err_destroy_tir;
1522
1523         return 0;
1524
1525 err_destroy_tir:
1526         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1527 err_destroy_rq:
1528         destroy_raw_packet_qp_rq(dev, rq);
1529 err_destroy_sq:
1530         if (!qp->sq.wqe_cnt)
1531                 return err;
1532         destroy_raw_packet_qp_sq(dev, sq);
1533 err_destroy_tis:
1534         destroy_raw_packet_qp_tis(dev, sq, pd);
1535
1536         return err;
1537 }
1538
1539 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1540                                   struct mlx5_ib_qp *qp)
1541 {
1542         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1543         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1544         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1545
1546         if (qp->rq.wqe_cnt) {
1547                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1548                 destroy_raw_packet_qp_rq(dev, rq);
1549         }
1550
1551         if (qp->sq.wqe_cnt) {
1552                 destroy_raw_packet_qp_sq(dev, sq);
1553                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1554         }
1555 }
1556
1557 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1558                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1559 {
1560         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1561         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1562
1563         sq->sq = &qp->sq;
1564         rq->rq = &qp->rq;
1565         sq->doorbell = &qp->db;
1566         rq->doorbell = &qp->db;
1567 }
1568
1569 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1570 {
1571         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1572                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1573                 mlx5_ib_disable_lb(dev, false, true);
1574         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1575                              to_mpd(qp->ibqp.pd)->uid);
1576 }
1577
1578 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1579                                  struct ib_pd *pd,
1580                                  struct ib_qp_init_attr *init_attr,
1581                                  struct ib_udata *udata)
1582 {
1583         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1584                 udata, struct mlx5_ib_ucontext, ibucontext);
1585         struct mlx5_ib_create_qp_resp resp = {};
1586         int inlen;
1587         int err;
1588         u32 *in;
1589         void *tirc;
1590         void *hfso;
1591         u32 selected_fields = 0;
1592         u32 outer_l4;
1593         size_t min_resp_len;
1594         u32 tdn = mucontext->tdn;
1595         struct mlx5_ib_create_qp_rss ucmd = {};
1596         size_t required_cmd_sz;
1597         u8 lb_flag = 0;
1598
1599         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1600                 return -EOPNOTSUPP;
1601
1602         if (init_attr->create_flags || init_attr->send_cq)
1603                 return -EINVAL;
1604
1605         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1606         if (udata->outlen < min_resp_len)
1607                 return -EINVAL;
1608
1609         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1610         if (udata->inlen < required_cmd_sz) {
1611                 mlx5_ib_dbg(dev, "invalid inlen\n");
1612                 return -EINVAL;
1613         }
1614
1615         if (udata->inlen > sizeof(ucmd) &&
1616             !ib_is_udata_cleared(udata, sizeof(ucmd),
1617                                  udata->inlen - sizeof(ucmd))) {
1618                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1619                 return -EOPNOTSUPP;
1620         }
1621
1622         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1623                 mlx5_ib_dbg(dev, "copy failed\n");
1624                 return -EFAULT;
1625         }
1626
1627         if (ucmd.comp_mask) {
1628                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1629                 return -EOPNOTSUPP;
1630         }
1631
1632         if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1633                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1634                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1635                 mlx5_ib_dbg(dev, "invalid flags\n");
1636                 return -EOPNOTSUPP;
1637         }
1638
1639         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1640             !tunnel_offload_supported(dev->mdev)) {
1641                 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1642                 return -EOPNOTSUPP;
1643         }
1644
1645         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1646             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1647                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1648                 return -EOPNOTSUPP;
1649         }
1650
1651         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1652                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1653                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1654         }
1655
1656         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1657                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1658                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1659         }
1660
1661         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1662         if (err) {
1663                 mlx5_ib_dbg(dev, "copy failed\n");
1664                 return -EINVAL;
1665         }
1666
1667         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1668         in = kvzalloc(inlen, GFP_KERNEL);
1669         if (!in)
1670                 return -ENOMEM;
1671
1672         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1673         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1674         MLX5_SET(tirc, tirc, disp_type,
1675                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1676         MLX5_SET(tirc, tirc, indirect_table,
1677                  init_attr->rwq_ind_tbl->ind_tbl_num);
1678         MLX5_SET(tirc, tirc, transport_domain, tdn);
1679
1680         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1681
1682         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1683                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1684
1685         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1686
1687         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1688                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1689         else
1690                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1691
1692         switch (ucmd.rx_hash_function) {
1693         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1694         {
1695                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1696                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1697
1698                 if (len != ucmd.rx_key_len) {
1699                         err = -EINVAL;
1700                         goto err;
1701                 }
1702
1703                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1704                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1705                 memcpy(rss_key, ucmd.rx_hash_key, len);
1706                 break;
1707         }
1708         default:
1709                 err = -EOPNOTSUPP;
1710                 goto err;
1711         }
1712
1713         if (!ucmd.rx_hash_fields_mask) {
1714                 /* special case when this TIR serves as steering entry without hashing */
1715                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1716                         goto create_tir;
1717                 err = -EINVAL;
1718                 goto err;
1719         }
1720
1721         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1722              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1723              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1724              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1725                 err = -EINVAL;
1726                 goto err;
1727         }
1728
1729         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1730         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1731             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1732                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1733                          MLX5_L3_PROT_TYPE_IPV4);
1734         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1735                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1736                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1737                          MLX5_L3_PROT_TYPE_IPV6);
1738
1739         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1740                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1741                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1742                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1743                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1744
1745         /* Check that only one l4 protocol is set */
1746         if (outer_l4 & (outer_l4 - 1)) {
1747                 err = -EINVAL;
1748                 goto err;
1749         }
1750
1751         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1752         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1753             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1754                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1755                          MLX5_L4_PROT_TYPE_TCP);
1756         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1757                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1758                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1759                          MLX5_L4_PROT_TYPE_UDP);
1760
1761         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1762             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1763                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1764
1765         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1766             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1767                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1768
1769         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1770             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1771                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1772
1773         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1774             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1775                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1776
1777         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1778                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1779
1780         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1781
1782 create_tir:
1783         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1784
1785         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1786                 err = mlx5_ib_enable_lb(dev, false, true);
1787
1788                 if (err)
1789                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1790                                              to_mpd(pd)->uid);
1791         }
1792
1793         if (err)
1794                 goto err;
1795
1796         if (mucontext->devx_uid) {
1797                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1798                 resp.tirn = qp->rss_qp.tirn;
1799         }
1800
1801         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1802         if (err)
1803                 goto err_copy;
1804
1805         kvfree(in);
1806         /* qpn is reserved for that QP */
1807         qp->trans_qp.base.mqp.qpn = 0;
1808         qp->flags |= MLX5_IB_QP_RSS;
1809         return 0;
1810
1811 err_copy:
1812         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1813 err:
1814         kvfree(in);
1815         return err;
1816 }
1817
1818 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1819                                          void *qpc)
1820 {
1821         int rcqe_sz;
1822
1823         if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1824                 return;
1825
1826         rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1827
1828         if (rcqe_sz == 128) {
1829                 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1830                 return;
1831         }
1832
1833         if (init_attr->qp_type != MLX5_IB_QPT_DCT)
1834                 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1835 }
1836
1837 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1838                                          struct ib_qp_init_attr *init_attr,
1839                                          struct mlx5_ib_create_qp *ucmd,
1840                                          void *qpc)
1841 {
1842         enum ib_qp_type qpt = init_attr->qp_type;
1843         int scqe_sz;
1844         bool allow_scat_cqe = 0;
1845
1846         if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1847                 return;
1848
1849         if (ucmd)
1850                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1851
1852         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1853                 return;
1854
1855         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1856         if (scqe_sz == 128) {
1857                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1858                 return;
1859         }
1860
1861         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1862             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1863                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1864 }
1865
1866 static int atomic_size_to_mode(int size_mask)
1867 {
1868         /* driver does not support atomic_size > 256B
1869          * and does not know how to translate bigger sizes
1870          */
1871         int supported_size_mask = size_mask & 0x1ff;
1872         int log_max_size;
1873
1874         if (!supported_size_mask)
1875                 return -EOPNOTSUPP;
1876
1877         log_max_size = __fls(supported_size_mask);
1878
1879         if (log_max_size > 3)
1880                 return log_max_size;
1881
1882         return MLX5_ATOMIC_MODE_8B;
1883 }
1884
1885 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1886                            enum ib_qp_type qp_type)
1887 {
1888         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1889         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1890         int atomic_mode = -EOPNOTSUPP;
1891         int atomic_size_mask;
1892
1893         if (!atomic)
1894                 return -EOPNOTSUPP;
1895
1896         if (qp_type == MLX5_IB_QPT_DCT)
1897                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1898         else
1899                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1900
1901         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1902             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1903                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1904
1905         if (atomic_mode <= 0 &&
1906             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1907              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1908                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1909
1910         return atomic_mode;
1911 }
1912
1913 static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1914 {
1915         return (input & ~supported) == 0;
1916 }
1917
1918 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1919                             struct ib_qp_init_attr *init_attr,
1920                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1921 {
1922         struct mlx5_ib_resources *devr = &dev->devr;
1923         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1924         struct mlx5_core_dev *mdev = dev->mdev;
1925         struct mlx5_ib_create_qp_resp resp = {};
1926         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
1927                 udata, struct mlx5_ib_ucontext, ibucontext);
1928         struct mlx5_ib_cq *send_cq;
1929         struct mlx5_ib_cq *recv_cq;
1930         unsigned long flags;
1931         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1932         struct mlx5_ib_create_qp ucmd;
1933         struct mlx5_ib_qp_base *base;
1934         int mlx5_st;
1935         void *qpc;
1936         u32 *in;
1937         int err;
1938
1939         mutex_init(&qp->mutex);
1940         spin_lock_init(&qp->sq.lock);
1941         spin_lock_init(&qp->rq.lock);
1942
1943         mlx5_st = to_mlx5_st(init_attr->qp_type);
1944         if (mlx5_st < 0)
1945                 return -EINVAL;
1946
1947         if (init_attr->rwq_ind_tbl) {
1948                 if (!udata)
1949                         return -ENOSYS;
1950
1951                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1952                 return err;
1953         }
1954
1955         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1956                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1957                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1958                         return -EINVAL;
1959                 } else {
1960                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1961                 }
1962         }
1963
1964         if (init_attr->create_flags &
1965                         (IB_QP_CREATE_CROSS_CHANNEL |
1966                          IB_QP_CREATE_MANAGED_SEND |
1967                          IB_QP_CREATE_MANAGED_RECV)) {
1968                 if (!MLX5_CAP_GEN(mdev, cd)) {
1969                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1970                         return -EINVAL;
1971                 }
1972                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1973                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1974                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1975                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1976                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1977                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1978         }
1979
1980         if (init_attr->qp_type == IB_QPT_UD &&
1981             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1982                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1983                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1984                         return -EOPNOTSUPP;
1985                 }
1986
1987         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1988                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1989                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1990                         return -EOPNOTSUPP;
1991                 }
1992                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1993                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1994                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1995                         return -EOPNOTSUPP;
1996                 }
1997                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1998         }
1999
2000         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2001                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2002
2003         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
2004                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
2005                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
2006                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
2007                         return -EOPNOTSUPP;
2008                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
2009         }
2010
2011         if (udata) {
2012                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
2013                         mlx5_ib_dbg(dev, "copy failed\n");
2014                         return -EFAULT;
2015                 }
2016
2017                 if (!check_flags_mask(ucmd.flags,
2018                                       MLX5_QP_FLAG_ALLOW_SCATTER_CQE |
2019                                       MLX5_QP_FLAG_BFREG_INDEX |
2020                                       MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE |
2021                                       MLX5_QP_FLAG_SCATTER_CQE |
2022                                       MLX5_QP_FLAG_SIGNATURE |
2023                                       MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC |
2024                                       MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2025                                       MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2026                                       MLX5_QP_FLAG_TYPE_DCI |
2027                                       MLX5_QP_FLAG_TYPE_DCT))
2028                         return -EINVAL;
2029
2030                 err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx);
2031                 if (err)
2032                         return err;
2033
2034                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
2035                 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
2036                         qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
2037                 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
2038                         if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
2039                             !tunnel_offload_supported(mdev)) {
2040                                 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
2041                                 return -EOPNOTSUPP;
2042                         }
2043                         qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
2044                 }
2045
2046                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
2047                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2048                                 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
2049                                 return -EOPNOTSUPP;
2050                         }
2051                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
2052                 }
2053
2054                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
2055                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2056                                 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
2057                                 return -EOPNOTSUPP;
2058                         }
2059                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
2060                 }
2061
2062                 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) {
2063                         if (init_attr->qp_type != IB_QPT_RC ||
2064                                 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) {
2065                                 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n");
2066                                 return -EOPNOTSUPP;
2067                         }
2068                         qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT;
2069                 }
2070
2071                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
2072                         if (init_attr->qp_type != IB_QPT_UD ||
2073                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
2074                              MLX5_CAP_PORT_TYPE_IB) ||
2075                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
2076                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
2077                                 return -EOPNOTSUPP;
2078                         }
2079
2080                         qp->flags |= MLX5_IB_QP_UNDERLAY;
2081                         qp->underlay_qpn = init_attr->source_qpn;
2082                 }
2083         } else {
2084                 qp->wq_sig = !!wq_signature;
2085         }
2086
2087         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2088                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2089                &qp->raw_packet_qp.rq.base :
2090                &qp->trans_qp.base;
2091
2092         qp->has_rq = qp_has_rq(init_attr);
2093         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
2094                           qp, udata ? &ucmd : NULL);
2095         if (err) {
2096                 mlx5_ib_dbg(dev, "err %d\n", err);
2097                 return err;
2098         }
2099
2100         if (pd) {
2101                 if (udata) {
2102                         __u32 max_wqes =
2103                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
2104                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
2105                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
2106                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
2107                                 mlx5_ib_dbg(dev, "invalid rq params\n");
2108                                 return -EINVAL;
2109                         }
2110                         if (ucmd.sq_wqe_count > max_wqes) {
2111                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
2112                                             ucmd.sq_wqe_count, max_wqes);
2113                                 return -EINVAL;
2114                         }
2115                         if (init_attr->create_flags &
2116                             mlx5_ib_create_qp_sqpn_qp1()) {
2117                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
2118                                 return -EINVAL;
2119                         }
2120                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2121                                              &resp, &inlen, base);
2122                         if (err)
2123                                 mlx5_ib_dbg(dev, "err %d\n", err);
2124                 } else {
2125                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2126                                                base);
2127                         if (err)
2128                                 mlx5_ib_dbg(dev, "err %d\n", err);
2129                 }
2130
2131                 if (err)
2132                         return err;
2133         } else {
2134                 in = kvzalloc(inlen, GFP_KERNEL);
2135                 if (!in)
2136                         return -ENOMEM;
2137
2138                 qp->create_type = MLX5_QP_EMPTY;
2139         }
2140
2141         if (is_sqp(init_attr->qp_type))
2142                 qp->port = init_attr->port_num;
2143
2144         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2145
2146         MLX5_SET(qpc, qpc, st, mlx5_st);
2147         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2148
2149         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
2150                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2151         else
2152                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2153
2154
2155         if (qp->wq_sig)
2156                 MLX5_SET(qpc, qpc, wq_signature, 1);
2157
2158         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2159                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2160
2161         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
2162                 MLX5_SET(qpc, qpc, cd_master, 1);
2163         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
2164                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2165         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
2166                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2167         if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT)
2168                 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2169         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
2170                 configure_responder_scat_cqe(init_attr, qpc);
2171                 configure_requester_scat_cqe(dev, init_attr,
2172                                              udata ? &ucmd : NULL,
2173                                              qpc);
2174         }
2175
2176         if (qp->rq.wqe_cnt) {
2177                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2178                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2179         }
2180
2181         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2182
2183         if (qp->sq.wqe_cnt) {
2184                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2185         } else {
2186                 MLX5_SET(qpc, qpc, no_sq, 1);
2187                 if (init_attr->srq &&
2188                     init_attr->srq->srq_type == IB_SRQT_TM)
2189                         MLX5_SET(qpc, qpc, offload_type,
2190                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2191         }
2192
2193         /* Set default resources */
2194         switch (init_attr->qp_type) {
2195         case IB_QPT_XRC_TGT:
2196                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2197                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2198                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2199                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2200                 break;
2201         case IB_QPT_XRC_INI:
2202                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2203                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2204                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2205                 break;
2206         default:
2207                 if (init_attr->srq) {
2208                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2209                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2210                 } else {
2211                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2212                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2213                 }
2214         }
2215
2216         if (init_attr->send_cq)
2217                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2218
2219         if (init_attr->recv_cq)
2220                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2221
2222         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2223
2224         /* 0xffffff means we ask to work with cqe version 0 */
2225         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2226                 MLX5_SET(qpc, qpc, user_index, uidx);
2227
2228         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2229         if (init_attr->qp_type == IB_QPT_UD &&
2230             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
2231                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2232                 qp->flags |= MLX5_IB_QP_LSO;
2233         }
2234
2235         if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2236                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2237                         mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2238                         err = -EOPNOTSUPP;
2239                         goto err;
2240                 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2241                         MLX5_SET(qpc, qpc, end_padding_mode,
2242                                  MLX5_WQ_END_PAD_MODE_ALIGN);
2243                 } else {
2244                         qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2245                 }
2246         }
2247
2248         if (inlen < 0) {
2249                 err = -EINVAL;
2250                 goto err;
2251         }
2252
2253         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2254             qp->flags & MLX5_IB_QP_UNDERLAY) {
2255                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2256                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2257                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2258                                            &resp);
2259         } else {
2260                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2261         }
2262
2263         if (err) {
2264                 mlx5_ib_dbg(dev, "create qp failed\n");
2265                 goto err_create;
2266         }
2267
2268         kvfree(in);
2269
2270         base->container_mibqp = qp;
2271         base->mqp.event = mlx5_ib_qp_event;
2272
2273         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2274                 &send_cq, &recv_cq);
2275         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2276         mlx5_ib_lock_cqs(send_cq, recv_cq);
2277         /* Maintain device to QPs access, needed for further handling via reset
2278          * flow
2279          */
2280         list_add_tail(&qp->qps_list, &dev->qp_list);
2281         /* Maintain CQ to QPs access, needed for further handling via reset flow
2282          */
2283         if (send_cq)
2284                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2285         if (recv_cq)
2286                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2287         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2288         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2289
2290         return 0;
2291
2292 err_create:
2293         if (qp->create_type == MLX5_QP_USER)
2294                 destroy_qp_user(dev, pd, qp, base, udata);
2295         else if (qp->create_type == MLX5_QP_KERNEL)
2296                 destroy_qp_kernel(dev, qp);
2297
2298 err:
2299         kvfree(in);
2300         return err;
2301 }
2302
2303 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2304         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2305 {
2306         if (send_cq) {
2307                 if (recv_cq) {
2308                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2309                                 spin_lock(&send_cq->lock);
2310                                 spin_lock_nested(&recv_cq->lock,
2311                                                  SINGLE_DEPTH_NESTING);
2312                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2313                                 spin_lock(&send_cq->lock);
2314                                 __acquire(&recv_cq->lock);
2315                         } else {
2316                                 spin_lock(&recv_cq->lock);
2317                                 spin_lock_nested(&send_cq->lock,
2318                                                  SINGLE_DEPTH_NESTING);
2319                         }
2320                 } else {
2321                         spin_lock(&send_cq->lock);
2322                         __acquire(&recv_cq->lock);
2323                 }
2324         } else if (recv_cq) {
2325                 spin_lock(&recv_cq->lock);
2326                 __acquire(&send_cq->lock);
2327         } else {
2328                 __acquire(&send_cq->lock);
2329                 __acquire(&recv_cq->lock);
2330         }
2331 }
2332
2333 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2334         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2335 {
2336         if (send_cq) {
2337                 if (recv_cq) {
2338                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2339                                 spin_unlock(&recv_cq->lock);
2340                                 spin_unlock(&send_cq->lock);
2341                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2342                                 __release(&recv_cq->lock);
2343                                 spin_unlock(&send_cq->lock);
2344                         } else {
2345                                 spin_unlock(&send_cq->lock);
2346                                 spin_unlock(&recv_cq->lock);
2347                         }
2348                 } else {
2349                         __release(&recv_cq->lock);
2350                         spin_unlock(&send_cq->lock);
2351                 }
2352         } else if (recv_cq) {
2353                 __release(&send_cq->lock);
2354                 spin_unlock(&recv_cq->lock);
2355         } else {
2356                 __release(&recv_cq->lock);
2357                 __release(&send_cq->lock);
2358         }
2359 }
2360
2361 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2362 {
2363         return to_mpd(qp->ibqp.pd);
2364 }
2365
2366 static void get_cqs(enum ib_qp_type qp_type,
2367                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2368                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2369 {
2370         switch (qp_type) {
2371         case IB_QPT_XRC_TGT:
2372                 *send_cq = NULL;
2373                 *recv_cq = NULL;
2374                 break;
2375         case MLX5_IB_QPT_REG_UMR:
2376         case IB_QPT_XRC_INI:
2377                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2378                 *recv_cq = NULL;
2379                 break;
2380
2381         case IB_QPT_SMI:
2382         case MLX5_IB_QPT_HW_GSI:
2383         case IB_QPT_RC:
2384         case IB_QPT_UC:
2385         case IB_QPT_UD:
2386         case IB_QPT_RAW_IPV6:
2387         case IB_QPT_RAW_ETHERTYPE:
2388         case IB_QPT_RAW_PACKET:
2389                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2390                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2391                 break;
2392
2393         case IB_QPT_MAX:
2394         default:
2395                 *send_cq = NULL;
2396                 *recv_cq = NULL;
2397                 break;
2398         }
2399 }
2400
2401 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2402                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2403                                 u8 lag_tx_affinity);
2404
2405 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2406                               struct ib_udata *udata)
2407 {
2408         struct mlx5_ib_cq *send_cq, *recv_cq;
2409         struct mlx5_ib_qp_base *base;
2410         unsigned long flags;
2411         int err;
2412
2413         if (qp->ibqp.rwq_ind_tbl) {
2414                 destroy_rss_raw_qp_tir(dev, qp);
2415                 return;
2416         }
2417
2418         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2419                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2420                &qp->raw_packet_qp.rq.base :
2421                &qp->trans_qp.base;
2422
2423         if (qp->state != IB_QPS_RESET) {
2424                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2425                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2426                         err = mlx5_core_qp_modify(dev->mdev,
2427                                                   MLX5_CMD_OP_2RST_QP, 0,
2428                                                   NULL, &base->mqp);
2429                 } else {
2430                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2431                                 .operation = MLX5_CMD_OP_2RST_QP
2432                         };
2433
2434                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2435                 }
2436                 if (err)
2437                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2438                                      base->mqp.qpn);
2439         }
2440
2441         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2442                 &send_cq, &recv_cq);
2443
2444         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2445         mlx5_ib_lock_cqs(send_cq, recv_cq);
2446         /* del from lists under both locks above to protect reset flow paths */
2447         list_del(&qp->qps_list);
2448         if (send_cq)
2449                 list_del(&qp->cq_send_list);
2450
2451         if (recv_cq)
2452                 list_del(&qp->cq_recv_list);
2453
2454         if (qp->create_type == MLX5_QP_KERNEL) {
2455                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2456                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2457                 if (send_cq != recv_cq)
2458                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2459                                            NULL);
2460         }
2461         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2462         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2463
2464         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2465             qp->flags & MLX5_IB_QP_UNDERLAY) {
2466                 destroy_raw_packet_qp(dev, qp);
2467         } else {
2468                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2469                 if (err)
2470                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2471                                      base->mqp.qpn);
2472         }
2473
2474         if (qp->create_type == MLX5_QP_KERNEL)
2475                 destroy_qp_kernel(dev, qp);
2476         else if (qp->create_type == MLX5_QP_USER)
2477                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata);
2478 }
2479
2480 static const char *ib_qp_type_str(enum ib_qp_type type)
2481 {
2482         switch (type) {
2483         case IB_QPT_SMI:
2484                 return "IB_QPT_SMI";
2485         case IB_QPT_GSI:
2486                 return "IB_QPT_GSI";
2487         case IB_QPT_RC:
2488                 return "IB_QPT_RC";
2489         case IB_QPT_UC:
2490                 return "IB_QPT_UC";
2491         case IB_QPT_UD:
2492                 return "IB_QPT_UD";
2493         case IB_QPT_RAW_IPV6:
2494                 return "IB_QPT_RAW_IPV6";
2495         case IB_QPT_RAW_ETHERTYPE:
2496                 return "IB_QPT_RAW_ETHERTYPE";
2497         case IB_QPT_XRC_INI:
2498                 return "IB_QPT_XRC_INI";
2499         case IB_QPT_XRC_TGT:
2500                 return "IB_QPT_XRC_TGT";
2501         case IB_QPT_RAW_PACKET:
2502                 return "IB_QPT_RAW_PACKET";
2503         case MLX5_IB_QPT_REG_UMR:
2504                 return "MLX5_IB_QPT_REG_UMR";
2505         case IB_QPT_DRIVER:
2506                 return "IB_QPT_DRIVER";
2507         case IB_QPT_MAX:
2508         default:
2509                 return "Invalid QP type";
2510         }
2511 }
2512
2513 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2514                                         struct ib_qp_init_attr *attr,
2515                                         struct mlx5_ib_create_qp *ucmd,
2516                                         struct ib_udata *udata)
2517 {
2518         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2519                 udata, struct mlx5_ib_ucontext, ibucontext);
2520         struct mlx5_ib_qp *qp;
2521         int err = 0;
2522         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2523         void *dctc;
2524
2525         if (!attr->srq || !attr->recv_cq)
2526                 return ERR_PTR(-EINVAL);
2527
2528         err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx);
2529         if (err)
2530                 return ERR_PTR(err);
2531
2532         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2533         if (!qp)
2534                 return ERR_PTR(-ENOMEM);
2535
2536         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2537         if (!qp->dct.in) {
2538                 err = -ENOMEM;
2539                 goto err_free;
2540         }
2541
2542         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2543         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2544         qp->qp_sub_type = MLX5_IB_QPT_DCT;
2545         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2546         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2547         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2548         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2549         MLX5_SET(dctc, dctc, user_index, uidx);
2550
2551         if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2552                 configure_responder_scat_cqe(attr, dctc);
2553
2554         qp->state = IB_QPS_RESET;
2555
2556         return &qp->ibqp;
2557 err_free:
2558         kfree(qp);
2559         return ERR_PTR(err);
2560 }
2561
2562 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2563                            struct ib_qp_init_attr *init_attr,
2564                            struct mlx5_ib_create_qp *ucmd,
2565                            struct ib_udata *udata)
2566 {
2567         enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2568         int err;
2569
2570         if (!udata)
2571                 return -EINVAL;
2572
2573         if (udata->inlen < sizeof(*ucmd)) {
2574                 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2575                 return -EINVAL;
2576         }
2577         err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2578         if (err)
2579                 return err;
2580
2581         if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2582                 init_attr->qp_type = MLX5_IB_QPT_DCI;
2583         } else {
2584                 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2585                         init_attr->qp_type = MLX5_IB_QPT_DCT;
2586                 } else {
2587                         mlx5_ib_dbg(dev, "Invalid QP flags\n");
2588                         return -EINVAL;
2589                 }
2590         }
2591
2592         if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2593                 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2594                 return -EOPNOTSUPP;
2595         }
2596
2597         return 0;
2598 }
2599
2600 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2601                                 struct ib_qp_init_attr *verbs_init_attr,
2602                                 struct ib_udata *udata)
2603 {
2604         struct mlx5_ib_dev *dev;
2605         struct mlx5_ib_qp *qp;
2606         u16 xrcdn = 0;
2607         int err;
2608         struct ib_qp_init_attr mlx_init_attr;
2609         struct ib_qp_init_attr *init_attr = verbs_init_attr;
2610         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2611                 udata, struct mlx5_ib_ucontext, ibucontext);
2612
2613         if (pd) {
2614                 dev = to_mdev(pd->device);
2615
2616                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2617                         if (!ucontext) {
2618                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2619                                 return ERR_PTR(-EINVAL);
2620                         } else if (!ucontext->cqe_version) {
2621                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2622                                 return ERR_PTR(-EINVAL);
2623                         }
2624                 }
2625         } else {
2626                 /* being cautious here */
2627                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2628                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2629                         pr_warn("%s: no PD for transport %s\n", __func__,
2630                                 ib_qp_type_str(init_attr->qp_type));
2631                         return ERR_PTR(-EINVAL);
2632                 }
2633                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2634         }
2635
2636         if (init_attr->qp_type == IB_QPT_DRIVER) {
2637                 struct mlx5_ib_create_qp ucmd;
2638
2639                 init_attr = &mlx_init_attr;
2640                 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2641                 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2642                 if (err)
2643                         return ERR_PTR(err);
2644
2645                 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2646                         if (init_attr->cap.max_recv_wr ||
2647                             init_attr->cap.max_recv_sge) {
2648                                 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2649                                 return ERR_PTR(-EINVAL);
2650                         }
2651                 } else {
2652                         return mlx5_ib_create_dct(pd, init_attr, &ucmd, udata);
2653                 }
2654         }
2655
2656         switch (init_attr->qp_type) {
2657         case IB_QPT_XRC_TGT:
2658         case IB_QPT_XRC_INI:
2659                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2660                         mlx5_ib_dbg(dev, "XRC not supported\n");
2661                         return ERR_PTR(-ENOSYS);
2662                 }
2663                 init_attr->recv_cq = NULL;
2664                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2665                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2666                         init_attr->send_cq = NULL;
2667                 }
2668
2669                 /* fall through */
2670         case IB_QPT_RAW_PACKET:
2671         case IB_QPT_RC:
2672         case IB_QPT_UC:
2673         case IB_QPT_UD:
2674         case IB_QPT_SMI:
2675         case MLX5_IB_QPT_HW_GSI:
2676         case MLX5_IB_QPT_REG_UMR:
2677         case MLX5_IB_QPT_DCI:
2678                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2679                 if (!qp)
2680                         return ERR_PTR(-ENOMEM);
2681
2682                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2683                 if (err) {
2684                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2685                         kfree(qp);
2686                         return ERR_PTR(err);
2687                 }
2688
2689                 if (is_qp0(init_attr->qp_type))
2690                         qp->ibqp.qp_num = 0;
2691                 else if (is_qp1(init_attr->qp_type))
2692                         qp->ibqp.qp_num = 1;
2693                 else
2694                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2695
2696                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2697                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2698                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2699                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2700
2701                 qp->trans_qp.xrcdn = xrcdn;
2702
2703                 break;
2704
2705         case IB_QPT_GSI:
2706                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2707
2708         case IB_QPT_RAW_IPV6:
2709         case IB_QPT_RAW_ETHERTYPE:
2710         case IB_QPT_MAX:
2711         default:
2712                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2713                             init_attr->qp_type);
2714                 /* Don't support raw QPs */
2715                 return ERR_PTR(-EINVAL);
2716         }
2717
2718         if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2719                 qp->qp_sub_type = init_attr->qp_type;
2720
2721         return &qp->ibqp;
2722 }
2723
2724 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2725 {
2726         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2727
2728         if (mqp->state == IB_QPS_RTR) {
2729                 int err;
2730
2731                 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2732                 if (err) {
2733                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2734                         return err;
2735                 }
2736         }
2737
2738         kfree(mqp->dct.in);
2739         kfree(mqp);
2740         return 0;
2741 }
2742
2743 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
2744 {
2745         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2746         struct mlx5_ib_qp *mqp = to_mqp(qp);
2747
2748         if (unlikely(qp->qp_type == IB_QPT_GSI))
2749                 return mlx5_ib_gsi_destroy_qp(qp);
2750
2751         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2752                 return mlx5_ib_destroy_dct(mqp);
2753
2754         destroy_qp_common(dev, mqp, udata);
2755
2756         kfree(mqp);
2757
2758         return 0;
2759 }
2760
2761 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2762                                 const struct ib_qp_attr *attr,
2763                                 int attr_mask, __be32 *hw_access_flags_be)
2764 {
2765         u8 dest_rd_atomic;
2766         u32 access_flags, hw_access_flags = 0;
2767
2768         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2769
2770         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2771                 dest_rd_atomic = attr->max_dest_rd_atomic;
2772         else
2773                 dest_rd_atomic = qp->trans_qp.resp_depth;
2774
2775         if (attr_mask & IB_QP_ACCESS_FLAGS)
2776                 access_flags = attr->qp_access_flags;
2777         else
2778                 access_flags = qp->trans_qp.atomic_rd_en;
2779
2780         if (!dest_rd_atomic)
2781                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2782
2783         if (access_flags & IB_ACCESS_REMOTE_READ)
2784                 hw_access_flags |= MLX5_QP_BIT_RRE;
2785         if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
2786                 int atomic_mode;
2787
2788                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2789                 if (atomic_mode < 0)
2790                         return -EOPNOTSUPP;
2791
2792                 hw_access_flags |= MLX5_QP_BIT_RAE;
2793                 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2794         }
2795
2796         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2797                 hw_access_flags |= MLX5_QP_BIT_RWE;
2798
2799         *hw_access_flags_be = cpu_to_be32(hw_access_flags);
2800
2801         return 0;
2802 }
2803
2804 enum {
2805         MLX5_PATH_FLAG_FL       = 1 << 0,
2806         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2807         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2808 };
2809
2810 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2811 {
2812         if (rate == IB_RATE_PORT_CURRENT)
2813                 return 0;
2814
2815         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
2816                 return -EINVAL;
2817
2818         while (rate != IB_RATE_PORT_CURRENT &&
2819                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2820                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2821                 --rate;
2822
2823         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2824 }
2825
2826 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2827                                       struct mlx5_ib_sq *sq, u8 sl,
2828                                       struct ib_pd *pd)
2829 {
2830         void *in;
2831         void *tisc;
2832         int inlen;
2833         int err;
2834
2835         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2836         in = kvzalloc(inlen, GFP_KERNEL);
2837         if (!in)
2838                 return -ENOMEM;
2839
2840         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2841         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2842
2843         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2844         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2845
2846         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2847
2848         kvfree(in);
2849
2850         return err;
2851 }
2852
2853 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2854                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
2855                                          struct ib_pd *pd)
2856 {
2857         void *in;
2858         void *tisc;
2859         int inlen;
2860         int err;
2861
2862         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2863         in = kvzalloc(inlen, GFP_KERNEL);
2864         if (!in)
2865                 return -ENOMEM;
2866
2867         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2868         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2869
2870         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2871         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2872
2873         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2874
2875         kvfree(in);
2876
2877         return err;
2878 }
2879
2880 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2881                          const struct rdma_ah_attr *ah,
2882                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2883                          u32 path_flags, const struct ib_qp_attr *attr,
2884                          bool alt)
2885 {
2886         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2887         int err;
2888         enum ib_gid_type gid_type;
2889         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2890         u8 sl = rdma_ah_get_sl(ah);
2891
2892         if (attr_mask & IB_QP_PKEY_INDEX)
2893                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2894                                                      attr->pkey_index);
2895
2896         if (ah_flags & IB_AH_GRH) {
2897                 if (grh->sgid_index >=
2898                     dev->mdev->port_caps[port - 1].gid_table_len) {
2899                         pr_err("sgid_index (%u) too large. max is %d\n",
2900                                grh->sgid_index,
2901                                dev->mdev->port_caps[port - 1].gid_table_len);
2902                         return -EINVAL;
2903                 }
2904         }
2905
2906         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2907                 if (!(ah_flags & IB_AH_GRH))
2908                         return -EINVAL;
2909
2910                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2911                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2912                     qp->ibqp.qp_type == IB_QPT_UC ||
2913                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2914                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2915                         path->udp_sport =
2916                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2917                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2918                 gid_type = ah->grh.sgid_attr->gid_type;
2919                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2920                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2921         } else {
2922                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2923                 path->fl_free_ar |=
2924                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2925                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2926                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2927                 if (ah_flags & IB_AH_GRH)
2928                         path->grh_mlid  |= 1 << 7;
2929                 path->dci_cfi_prio_sl = sl & 0xf;
2930         }
2931
2932         if (ah_flags & IB_AH_GRH) {
2933                 path->mgid_index = grh->sgid_index;
2934                 path->hop_limit  = grh->hop_limit;
2935                 path->tclass_flowlabel =
2936                         cpu_to_be32((grh->traffic_class << 20) |
2937                                     (grh->flow_label));
2938                 memcpy(path->rgid, grh->dgid.raw, 16);
2939         }
2940
2941         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2942         if (err < 0)
2943                 return err;
2944         path->static_rate = err;
2945         path->port = port;
2946
2947         if (attr_mask & IB_QP_TIMEOUT)
2948                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2949
2950         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2951                 return modify_raw_packet_eth_prio(dev->mdev,
2952                                                   &qp->raw_packet_qp.sq,
2953                                                   sl & 0xf, qp->ibqp.pd);
2954
2955         return 0;
2956 }
2957
2958 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2959         [MLX5_QP_STATE_INIT] = {
2960                 [MLX5_QP_STATE_INIT] = {
2961                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2962                                           MLX5_QP_OPTPAR_RAE            |
2963                                           MLX5_QP_OPTPAR_RWE            |
2964                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2965                                           MLX5_QP_OPTPAR_PRI_PORT,
2966                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2967                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2968                                           MLX5_QP_OPTPAR_PRI_PORT,
2969                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2970                                           MLX5_QP_OPTPAR_Q_KEY          |
2971                                           MLX5_QP_OPTPAR_PRI_PORT,
2972                 },
2973                 [MLX5_QP_STATE_RTR] = {
2974                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2975                                           MLX5_QP_OPTPAR_RRE            |
2976                                           MLX5_QP_OPTPAR_RAE            |
2977                                           MLX5_QP_OPTPAR_RWE            |
2978                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2979                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2980                                           MLX5_QP_OPTPAR_RWE            |
2981                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2982                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2983                                           MLX5_QP_OPTPAR_Q_KEY,
2984                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2985                                            MLX5_QP_OPTPAR_Q_KEY,
2986                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2987                                           MLX5_QP_OPTPAR_RRE            |
2988                                           MLX5_QP_OPTPAR_RAE            |
2989                                           MLX5_QP_OPTPAR_RWE            |
2990                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2991                 },
2992         },
2993         [MLX5_QP_STATE_RTR] = {
2994                 [MLX5_QP_STATE_RTS] = {
2995                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2996                                           MLX5_QP_OPTPAR_RRE            |
2997                                           MLX5_QP_OPTPAR_RAE            |
2998                                           MLX5_QP_OPTPAR_RWE            |
2999                                           MLX5_QP_OPTPAR_PM_STATE       |
3000                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3001                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3002                                           MLX5_QP_OPTPAR_RWE            |
3003                                           MLX5_QP_OPTPAR_PM_STATE,
3004                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3005                 },
3006         },
3007         [MLX5_QP_STATE_RTS] = {
3008                 [MLX5_QP_STATE_RTS] = {
3009                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3010                                           MLX5_QP_OPTPAR_RAE            |
3011                                           MLX5_QP_OPTPAR_RWE            |
3012                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3013                                           MLX5_QP_OPTPAR_PM_STATE       |
3014                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3015                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3016                                           MLX5_QP_OPTPAR_PM_STATE       |
3017                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3018                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
3019                                           MLX5_QP_OPTPAR_SRQN           |
3020                                           MLX5_QP_OPTPAR_CQN_RCV,
3021                 },
3022         },
3023         [MLX5_QP_STATE_SQER] = {
3024                 [MLX5_QP_STATE_RTS] = {
3025                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
3026                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3027                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
3028                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
3029                                            MLX5_QP_OPTPAR_RWE           |
3030                                            MLX5_QP_OPTPAR_RAE           |
3031                                            MLX5_QP_OPTPAR_RRE,
3032                 },
3033         },
3034 };
3035
3036 static int ib_nr_to_mlx5_nr(int ib_mask)
3037 {
3038         switch (ib_mask) {
3039         case IB_QP_STATE:
3040                 return 0;
3041         case IB_QP_CUR_STATE:
3042                 return 0;
3043         case IB_QP_EN_SQD_ASYNC_NOTIFY:
3044                 return 0;
3045         case IB_QP_ACCESS_FLAGS:
3046                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3047                         MLX5_QP_OPTPAR_RAE;
3048         case IB_QP_PKEY_INDEX:
3049                 return MLX5_QP_OPTPAR_PKEY_INDEX;
3050         case IB_QP_PORT:
3051                 return MLX5_QP_OPTPAR_PRI_PORT;
3052         case IB_QP_QKEY:
3053                 return MLX5_QP_OPTPAR_Q_KEY;
3054         case IB_QP_AV:
3055                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3056                         MLX5_QP_OPTPAR_PRI_PORT;
3057         case IB_QP_PATH_MTU:
3058                 return 0;
3059         case IB_QP_TIMEOUT:
3060                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3061         case IB_QP_RETRY_CNT:
3062                 return MLX5_QP_OPTPAR_RETRY_COUNT;
3063         case IB_QP_RNR_RETRY:
3064                 return MLX5_QP_OPTPAR_RNR_RETRY;
3065         case IB_QP_RQ_PSN:
3066                 return 0;
3067         case IB_QP_MAX_QP_RD_ATOMIC:
3068                 return MLX5_QP_OPTPAR_SRA_MAX;
3069         case IB_QP_ALT_PATH:
3070                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3071         case IB_QP_MIN_RNR_TIMER:
3072                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3073         case IB_QP_SQ_PSN:
3074                 return 0;
3075         case IB_QP_MAX_DEST_RD_ATOMIC:
3076                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3077                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3078         case IB_QP_PATH_MIG_STATE:
3079                 return MLX5_QP_OPTPAR_PM_STATE;
3080         case IB_QP_CAP:
3081                 return 0;
3082         case IB_QP_DEST_QPN:
3083                 return 0;
3084         }
3085         return 0;
3086 }
3087
3088 static int ib_mask_to_mlx5_opt(int ib_mask)
3089 {
3090         int result = 0;
3091         int i;
3092
3093         for (i = 0; i < 8 * sizeof(int); i++) {
3094                 if ((1 << i) & ib_mask)
3095                         result |= ib_nr_to_mlx5_nr(1 << i);
3096         }
3097
3098         return result;
3099 }
3100
3101 static int modify_raw_packet_qp_rq(
3102         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3103         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3104 {
3105         void *in;
3106         void *rqc;
3107         int inlen;
3108         int err;
3109
3110         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3111         in = kvzalloc(inlen, GFP_KERNEL);
3112         if (!in)
3113                 return -ENOMEM;
3114
3115         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3116         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3117
3118         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3119         MLX5_SET(rqc, rqc, state, new_state);
3120
3121         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3122                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3123                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
3124                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3125                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3126                 } else
3127                         dev_info_once(
3128                                 &dev->ib_dev.dev,
3129                                 "RAW PACKET QP counters are not supported on current FW\n");
3130         }
3131
3132         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
3133         if (err)
3134                 goto out;
3135
3136         rq->state = new_state;
3137
3138 out:
3139         kvfree(in);
3140         return err;
3141 }
3142
3143 static int modify_raw_packet_qp_sq(
3144         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3145         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3146 {
3147         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3148         struct mlx5_rate_limit old_rl = ibqp->rl;
3149         struct mlx5_rate_limit new_rl = old_rl;
3150         bool new_rate_added = false;
3151         u16 rl_index = 0;
3152         void *in;
3153         void *sqc;
3154         int inlen;
3155         int err;
3156
3157         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3158         in = kvzalloc(inlen, GFP_KERNEL);
3159         if (!in)
3160                 return -ENOMEM;
3161
3162         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3163         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3164
3165         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3166         MLX5_SET(sqc, sqc, state, new_state);
3167
3168         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3169                 if (new_state != MLX5_SQC_STATE_RDY)
3170                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3171                                 __func__);
3172                 else
3173                         new_rl = raw_qp_param->rl;
3174         }
3175
3176         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3177                 if (new_rl.rate) {
3178                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3179                         if (err) {
3180                                 pr_err("Failed configuring rate limit(err %d): \
3181                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3182                                        err, new_rl.rate, new_rl.max_burst_sz,
3183                                        new_rl.typical_pkt_sz);
3184
3185                                 goto out;
3186                         }
3187                         new_rate_added = true;
3188                 }
3189
3190                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3191                 /* index 0 means no limit */
3192                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3193         }
3194
3195         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
3196         if (err) {
3197                 /* Remove new rate from table if failed */
3198                 if (new_rate_added)
3199                         mlx5_rl_remove_rate(dev, &new_rl);
3200                 goto out;
3201         }
3202
3203         /* Only remove the old rate after new rate was set */
3204         if ((old_rl.rate &&
3205              !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3206             (new_state != MLX5_SQC_STATE_RDY))
3207                 mlx5_rl_remove_rate(dev, &old_rl);
3208
3209         ibqp->rl = new_rl;
3210         sq->state = new_state;
3211
3212 out:
3213         kvfree(in);
3214         return err;
3215 }
3216
3217 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3218                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3219                                 u8 tx_affinity)
3220 {
3221         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3222         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3223         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3224         int modify_rq = !!qp->rq.wqe_cnt;
3225         int modify_sq = !!qp->sq.wqe_cnt;
3226         int rq_state;
3227         int sq_state;
3228         int err;
3229
3230         switch (raw_qp_param->operation) {
3231         case MLX5_CMD_OP_RST2INIT_QP:
3232                 rq_state = MLX5_RQC_STATE_RDY;
3233                 sq_state = MLX5_SQC_STATE_RDY;
3234                 break;
3235         case MLX5_CMD_OP_2ERR_QP:
3236                 rq_state = MLX5_RQC_STATE_ERR;
3237                 sq_state = MLX5_SQC_STATE_ERR;
3238                 break;
3239         case MLX5_CMD_OP_2RST_QP:
3240                 rq_state = MLX5_RQC_STATE_RST;
3241                 sq_state = MLX5_SQC_STATE_RST;
3242                 break;
3243         case MLX5_CMD_OP_RTR2RTS_QP:
3244         case MLX5_CMD_OP_RTS2RTS_QP:
3245                 if (raw_qp_param->set_mask ==
3246                     MLX5_RAW_QP_RATE_LIMIT) {
3247                         modify_rq = 0;
3248                         sq_state = sq->state;
3249                 } else {
3250                         return raw_qp_param->set_mask ? -EINVAL : 0;
3251                 }
3252                 break;
3253         case MLX5_CMD_OP_INIT2INIT_QP:
3254         case MLX5_CMD_OP_INIT2RTR_QP:
3255                 if (raw_qp_param->set_mask)
3256                         return -EINVAL;
3257                 else
3258                         return 0;
3259         default:
3260                 WARN_ON(1);
3261                 return -EINVAL;
3262         }
3263
3264         if (modify_rq) {
3265                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3266                                                qp->ibqp.pd);
3267                 if (err)
3268                         return err;
3269         }
3270
3271         if (modify_sq) {
3272                 if (tx_affinity) {
3273                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3274                                                             tx_affinity,
3275                                                             qp->ibqp.pd);
3276                         if (err)
3277                                 return err;
3278                 }
3279
3280                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3281                                                raw_qp_param, qp->ibqp.pd);
3282         }
3283
3284         return 0;
3285 }
3286
3287 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3288                                     struct mlx5_ib_pd *pd,
3289                                     struct mlx5_ib_qp_base *qp_base,
3290                                     u8 port_num, struct ib_udata *udata)
3291 {
3292         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3293                 udata, struct mlx5_ib_ucontext, ibucontext);
3294         unsigned int tx_port_affinity;
3295
3296         if (ucontext) {
3297                 tx_port_affinity = (unsigned int)atomic_add_return(
3298                                            1, &ucontext->tx_port_affinity) %
3299                                            MLX5_MAX_PORTS +
3300                                    1;
3301                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3302                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3303         } else {
3304                 tx_port_affinity =
3305                         (unsigned int)atomic_add_return(
3306                                 1, &dev->roce[port_num].tx_port_affinity) %
3307                                 MLX5_MAX_PORTS +
3308                         1;
3309                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3310                                 tx_port_affinity, qp_base->mqp.qpn);
3311         }
3312
3313         return tx_port_affinity;
3314 }
3315
3316 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3317                                const struct ib_qp_attr *attr, int attr_mask,
3318                                enum ib_qp_state cur_state,
3319                                enum ib_qp_state new_state,
3320                                const struct mlx5_ib_modify_qp *ucmd,
3321                                struct ib_udata *udata)
3322 {
3323         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3324                 [MLX5_QP_STATE_RST] = {
3325                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3326                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3327                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3328                 },
3329                 [MLX5_QP_STATE_INIT]  = {
3330                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3331                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3332                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3333                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3334                 },
3335                 [MLX5_QP_STATE_RTR]   = {
3336                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3337                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3338                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3339                 },
3340                 [MLX5_QP_STATE_RTS]   = {
3341                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3342                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3343                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3344                 },
3345                 [MLX5_QP_STATE_SQD] = {
3346                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3347                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3348                 },
3349                 [MLX5_QP_STATE_SQER] = {
3350                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3351                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3352                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3353                 },
3354                 [MLX5_QP_STATE_ERR] = {
3355                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3356                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3357                 }
3358         };
3359
3360         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3361         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3362         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3363         struct mlx5_ib_cq *send_cq, *recv_cq;
3364         struct mlx5_qp_context *context;
3365         struct mlx5_ib_pd *pd;
3366         struct mlx5_ib_port *mibport = NULL;
3367         enum mlx5_qp_state mlx5_cur, mlx5_new;
3368         enum mlx5_qp_optpar optpar;
3369         int mlx5_st;
3370         int err;
3371         u16 op;
3372         u8 tx_affinity = 0;
3373
3374         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3375                              qp->qp_sub_type : ibqp->qp_type);
3376         if (mlx5_st < 0)
3377                 return -EINVAL;
3378
3379         context = kzalloc(sizeof(*context), GFP_KERNEL);
3380         if (!context)
3381                 return -ENOMEM;
3382
3383         pd = get_pd(qp);
3384         context->flags = cpu_to_be32(mlx5_st << 16);
3385
3386         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3387                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3388         } else {
3389                 switch (attr->path_mig_state) {
3390                 case IB_MIG_MIGRATED:
3391                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3392                         break;
3393                 case IB_MIG_REARM:
3394                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3395                         break;
3396                 case IB_MIG_ARMED:
3397                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3398                         break;
3399                 }
3400         }
3401
3402         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3403                 if ((ibqp->qp_type == IB_QPT_RC) ||
3404                     (ibqp->qp_type == IB_QPT_UD &&
3405                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3406                     (ibqp->qp_type == IB_QPT_UC) ||
3407                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3408                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3409                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3410                         if (dev->lag_active) {
3411                                 u8 p = mlx5_core_native_port_num(dev->mdev);
3412                                 tx_affinity = get_tx_affinity(dev, pd, base, p,
3413                                                               udata);
3414                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3415                         }
3416                 }
3417         }
3418
3419         if (is_sqp(ibqp->qp_type)) {
3420                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3421         } else if ((ibqp->qp_type == IB_QPT_UD &&
3422                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3423                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3424                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3425         } else if (attr_mask & IB_QP_PATH_MTU) {
3426                 if (attr->path_mtu < IB_MTU_256 ||
3427                     attr->path_mtu > IB_MTU_4096) {
3428                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3429                         err = -EINVAL;
3430                         goto out;
3431                 }
3432                 context->mtu_msgmax = (attr->path_mtu << 5) |
3433                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3434         }
3435
3436         if (attr_mask & IB_QP_DEST_QPN)
3437                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3438
3439         if (attr_mask & IB_QP_PKEY_INDEX)
3440                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3441
3442         /* todo implement counter_index functionality */
3443
3444         if (is_sqp(ibqp->qp_type))
3445                 context->pri_path.port = qp->port;
3446
3447         if (attr_mask & IB_QP_PORT)
3448                 context->pri_path.port = attr->port_num;
3449
3450         if (attr_mask & IB_QP_AV) {
3451                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3452                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3453                                     attr_mask, 0, attr, false);
3454                 if (err)
3455                         goto out;
3456         }
3457
3458         if (attr_mask & IB_QP_TIMEOUT)
3459                 context->pri_path.ackto_lt |= attr->timeout << 3;
3460
3461         if (attr_mask & IB_QP_ALT_PATH) {
3462                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3463                                     &context->alt_path,
3464                                     attr->alt_port_num,
3465                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3466                                     0, attr, true);
3467                 if (err)
3468                         goto out;
3469         }
3470
3471         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3472                 &send_cq, &recv_cq);
3473
3474         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3475         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3476         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3477         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3478
3479         if (attr_mask & IB_QP_RNR_RETRY)
3480                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3481
3482         if (attr_mask & IB_QP_RETRY_CNT)
3483                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3484
3485         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3486                 if (attr->max_rd_atomic)
3487                         context->params1 |=
3488                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3489         }
3490
3491         if (attr_mask & IB_QP_SQ_PSN)
3492                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3493
3494         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3495                 if (attr->max_dest_rd_atomic)
3496                         context->params2 |=
3497                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3498         }
3499
3500         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3501                 __be32 access_flags;
3502
3503                 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3504                 if (err)
3505                         goto out;
3506
3507                 context->params2 |= access_flags;
3508         }
3509
3510         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3511                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3512
3513         if (attr_mask & IB_QP_RQ_PSN)
3514                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3515
3516         if (attr_mask & IB_QP_QKEY)
3517                 context->qkey = cpu_to_be32(attr->qkey);
3518
3519         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3520                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3521
3522         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3523                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3524                                qp->port) - 1;
3525
3526                 /* Underlay port should be used - index 0 function per port */
3527                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3528                         port_num = 0;
3529
3530                 mibport = &dev->port[port_num];
3531                 context->qp_counter_set_usr_page |=
3532                         cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3533         }
3534
3535         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3536                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3537
3538         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3539                 context->deth_sqpn = cpu_to_be32(1);
3540
3541         mlx5_cur = to_mlx5_state(cur_state);
3542         mlx5_new = to_mlx5_state(new_state);
3543
3544         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3545             !optab[mlx5_cur][mlx5_new]) {
3546                 err = -EINVAL;
3547                 goto out;
3548         }
3549
3550         op = optab[mlx5_cur][mlx5_new];
3551         optpar = ib_mask_to_mlx5_opt(attr_mask);
3552         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3553
3554         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3555             qp->flags & MLX5_IB_QP_UNDERLAY) {
3556                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3557
3558                 raw_qp_param.operation = op;
3559                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3560                         raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3561                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3562                 }
3563
3564                 if (attr_mask & IB_QP_RATE_LIMIT) {
3565                         raw_qp_param.rl.rate = attr->rate_limit;
3566
3567                         if (ucmd->burst_info.max_burst_sz) {
3568                                 if (attr->rate_limit &&
3569                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3570                                         raw_qp_param.rl.max_burst_sz =
3571                                                 ucmd->burst_info.max_burst_sz;
3572                                 } else {
3573                                         err = -EINVAL;
3574                                         goto out;
3575                                 }
3576                         }
3577
3578                         if (ucmd->burst_info.typical_pkt_sz) {
3579                                 if (attr->rate_limit &&
3580                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3581                                         raw_qp_param.rl.typical_pkt_sz =
3582                                                 ucmd->burst_info.typical_pkt_sz;
3583                                 } else {
3584                                         err = -EINVAL;
3585                                         goto out;
3586                                 }
3587                         }
3588
3589                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3590                 }
3591
3592                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3593         } else {
3594                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3595                                           &base->mqp);
3596         }
3597
3598         if (err)
3599                 goto out;
3600
3601         qp->state = new_state;
3602
3603         if (attr_mask & IB_QP_ACCESS_FLAGS)
3604                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3605         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3606                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3607         if (attr_mask & IB_QP_PORT)
3608                 qp->port = attr->port_num;
3609         if (attr_mask & IB_QP_ALT_PATH)
3610                 qp->trans_qp.alt_port = attr->alt_port_num;
3611
3612         /*
3613          * If we moved a kernel QP to RESET, clean up all old CQ
3614          * entries and reinitialize the QP.
3615          */
3616         if (new_state == IB_QPS_RESET &&
3617             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3618                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3619                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3620                 if (send_cq != recv_cq)
3621                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3622
3623                 qp->rq.head = 0;
3624                 qp->rq.tail = 0;
3625                 qp->sq.head = 0;
3626                 qp->sq.tail = 0;
3627                 qp->sq.cur_post = 0;
3628                 if (qp->sq.wqe_cnt)
3629                         qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
3630                 qp->db.db[MLX5_RCV_DBR] = 0;
3631                 qp->db.db[MLX5_SND_DBR] = 0;
3632         }
3633
3634 out:
3635         kfree(context);
3636         return err;
3637 }
3638
3639 static inline bool is_valid_mask(int mask, int req, int opt)
3640 {
3641         if ((mask & req) != req)
3642                 return false;
3643
3644         if (mask & ~(req | opt))
3645                 return false;
3646
3647         return true;
3648 }
3649
3650 /* check valid transition for driver QP types
3651  * for now the only QP type that this function supports is DCI
3652  */
3653 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3654                                 enum ib_qp_attr_mask attr_mask)
3655 {
3656         int req = IB_QP_STATE;
3657         int opt = 0;
3658
3659         if (new_state == IB_QPS_RESET) {
3660                 return is_valid_mask(attr_mask, req, opt);
3661         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3662                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3663                 return is_valid_mask(attr_mask, req, opt);
3664         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3665                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3666                 return is_valid_mask(attr_mask, req, opt);
3667         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3668                 req |= IB_QP_PATH_MTU;
3669                 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
3670                 return is_valid_mask(attr_mask, req, opt);
3671         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3672                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3673                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3674                 opt = IB_QP_MIN_RNR_TIMER;
3675                 return is_valid_mask(attr_mask, req, opt);
3676         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3677                 opt = IB_QP_MIN_RNR_TIMER;
3678                 return is_valid_mask(attr_mask, req, opt);
3679         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3680                 return is_valid_mask(attr_mask, req, opt);
3681         }
3682         return false;
3683 }
3684
3685 /* mlx5_ib_modify_dct: modify a DCT QP
3686  * valid transitions are:
3687  * RESET to INIT: must set access_flags, pkey_index and port
3688  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3689  *                         mtu, gid_index and hop_limit
3690  * Other transitions and attributes are illegal
3691  */
3692 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3693                               int attr_mask, struct ib_udata *udata)
3694 {
3695         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3696         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3697         enum ib_qp_state cur_state, new_state;
3698         int err = 0;
3699         int required = IB_QP_STATE;
3700         void *dctc;
3701
3702         if (!(attr_mask & IB_QP_STATE))
3703                 return -EINVAL;
3704
3705         cur_state = qp->state;
3706         new_state = attr->qp_state;
3707
3708         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3709         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3710                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3711                 if (!is_valid_mask(attr_mask, required, 0))
3712                         return -EINVAL;
3713
3714                 if (attr->port_num == 0 ||
3715                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3716                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3717                                     attr->port_num, dev->num_ports);
3718                         return -EINVAL;
3719                 }
3720                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3721                         MLX5_SET(dctc, dctc, rre, 1);
3722                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3723                         MLX5_SET(dctc, dctc, rwe, 1);
3724                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3725                         int atomic_mode;
3726
3727                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3728                         if (atomic_mode < 0)
3729                                 return -EOPNOTSUPP;
3730
3731                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
3732                         MLX5_SET(dctc, dctc, rae, 1);
3733                 }
3734                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3735                 MLX5_SET(dctc, dctc, port, attr->port_num);
3736                 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3737
3738         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3739                 struct mlx5_ib_modify_qp_resp resp = {};
3740                 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0};
3741                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3742                                    sizeof(resp.dctn);
3743
3744                 if (udata->outlen < min_resp_len)
3745                         return -EINVAL;
3746                 resp.response_length = min_resp_len;
3747
3748                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3749                 if (!is_valid_mask(attr_mask, required, 0))
3750                         return -EINVAL;
3751                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3752                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3753                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3754                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3755                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3756                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3757
3758                 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3759                                            MLX5_ST_SZ_BYTES(create_dct_in), out,
3760                                            sizeof(out));
3761                 if (err)
3762                         return err;
3763                 resp.dctn = qp->dct.mdct.mqp.qpn;
3764                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3765                 if (err) {
3766                         mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3767                         return err;
3768                 }
3769         } else {
3770                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3771                 return -EINVAL;
3772         }
3773         if (err)
3774                 qp->state = IB_QPS_ERR;
3775         else
3776                 qp->state = new_state;
3777         return err;
3778 }
3779
3780 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3781                       int attr_mask, struct ib_udata *udata)
3782 {
3783         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3784         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3785         struct mlx5_ib_modify_qp ucmd = {};
3786         enum ib_qp_type qp_type;
3787         enum ib_qp_state cur_state, new_state;
3788         size_t required_cmd_sz;
3789         int err = -EINVAL;
3790         int port;
3791
3792         if (ibqp->rwq_ind_tbl)
3793                 return -ENOSYS;
3794
3795         if (udata && udata->inlen) {
3796                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3797                         sizeof(ucmd.reserved);
3798                 if (udata->inlen < required_cmd_sz)
3799                         return -EINVAL;
3800
3801                 if (udata->inlen > sizeof(ucmd) &&
3802                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3803                                          udata->inlen - sizeof(ucmd)))
3804                         return -EOPNOTSUPP;
3805
3806                 if (ib_copy_from_udata(&ucmd, udata,
3807                                        min(udata->inlen, sizeof(ucmd))))
3808                         return -EFAULT;
3809
3810                 if (ucmd.comp_mask ||
3811                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3812                     memchr_inv(&ucmd.burst_info.reserved, 0,
3813                                sizeof(ucmd.burst_info.reserved)))
3814                         return -EOPNOTSUPP;
3815         }
3816
3817         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3818                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3819
3820         if (ibqp->qp_type == IB_QPT_DRIVER)
3821                 qp_type = qp->qp_sub_type;
3822         else
3823                 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3824                         IB_QPT_GSI : ibqp->qp_type;
3825
3826         if (qp_type == MLX5_IB_QPT_DCT)
3827                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3828
3829         mutex_lock(&qp->mutex);
3830
3831         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3832         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3833
3834         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3835                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3836         }
3837
3838         if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3839                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3840                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3841                                     attr_mask);
3842                         goto out;
3843                 }
3844         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3845                    qp_type != MLX5_IB_QPT_DCI &&
3846                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3847                                        attr_mask)) {
3848                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3849                             cur_state, new_state, ibqp->qp_type, attr_mask);
3850                 goto out;
3851         } else if (qp_type == MLX5_IB_QPT_DCI &&
3852                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3853                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3854                             cur_state, new_state, qp_type, attr_mask);
3855                 goto out;
3856         }
3857
3858         if ((attr_mask & IB_QP_PORT) &&
3859             (attr->port_num == 0 ||
3860              attr->port_num > dev->num_ports)) {
3861                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3862                             attr->port_num, dev->num_ports);
3863                 goto out;
3864         }
3865
3866         if (attr_mask & IB_QP_PKEY_INDEX) {
3867                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3868                 if (attr->pkey_index >=
3869                     dev->mdev->port_caps[port - 1].pkey_table_len) {
3870                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3871                                     attr->pkey_index);
3872                         goto out;
3873                 }
3874         }
3875
3876         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3877             attr->max_rd_atomic >
3878             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3879                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3880                             attr->max_rd_atomic);
3881                 goto out;
3882         }
3883
3884         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3885             attr->max_dest_rd_atomic >
3886             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3887                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3888                             attr->max_dest_rd_atomic);
3889                 goto out;
3890         }
3891
3892         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3893                 err = 0;
3894                 goto out;
3895         }
3896
3897         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3898                                   new_state, &ucmd, udata);
3899
3900 out:
3901         mutex_unlock(&qp->mutex);
3902         return err;
3903 }
3904
3905 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3906                                    u32 wqe_sz, void **cur_edge)
3907 {
3908         u32 idx;
3909
3910         idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
3911         *cur_edge = get_sq_edge(sq, idx);
3912
3913         *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
3914 }
3915
3916 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
3917  * next nearby edge and get new address translation for current WQE position.
3918  * @sq - SQ buffer.
3919  * @seg: Current WQE position (16B aligned).
3920  * @wqe_sz: Total current WQE size [16B].
3921  * @cur_edge: Updated current edge.
3922  */
3923 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3924                                          u32 wqe_sz, void **cur_edge)
3925 {
3926         if (likely(*seg != *cur_edge))
3927                 return;
3928
3929         _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
3930 }
3931
3932 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
3933  * pointers. At the end @seg is aligned to 16B regardless the copied size.
3934  * @sq - SQ buffer.
3935  * @cur_edge: Updated current edge.
3936  * @seg: Current WQE position (16B aligned).
3937  * @wqe_sz: Total current WQE size [16B].
3938  * @src: Pointer to copy from.
3939  * @n: Number of bytes to copy.
3940  */
3941 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
3942                                    void **seg, u32 *wqe_sz, const void *src,
3943                                    size_t n)
3944 {
3945         while (likely(n)) {
3946                 size_t leftlen = *cur_edge - *seg;
3947                 size_t copysz = min_t(size_t, leftlen, n);
3948                 size_t stride;
3949
3950                 memcpy(*seg, src, copysz);
3951
3952                 n -= copysz;
3953                 src += copysz;
3954                 stride = !n ? ALIGN(copysz, 16) : copysz;
3955                 *seg += stride;
3956                 *wqe_sz += stride >> 4;
3957                 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
3958         }
3959 }
3960
3961 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3962 {
3963         struct mlx5_ib_cq *cq;
3964         unsigned cur;
3965
3966         cur = wq->head - wq->tail;
3967         if (likely(cur + nreq < wq->max_post))
3968                 return 0;
3969
3970         cq = to_mcq(ib_cq);
3971         spin_lock(&cq->lock);
3972         cur = wq->head - wq->tail;
3973         spin_unlock(&cq->lock);
3974
3975         return cur + nreq >= wq->max_post;
3976 }
3977
3978 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3979                                           u64 remote_addr, u32 rkey)
3980 {
3981         rseg->raddr    = cpu_to_be64(remote_addr);
3982         rseg->rkey     = cpu_to_be32(rkey);
3983         rseg->reserved = 0;
3984 }
3985
3986 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
3987                         void **seg, int *size, void **cur_edge)
3988 {
3989         struct mlx5_wqe_eth_seg *eseg = *seg;
3990
3991         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3992
3993         if (wr->send_flags & IB_SEND_IP_CSUM)
3994                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3995                                  MLX5_ETH_WQE_L4_CSUM;
3996
3997         if (wr->opcode == IB_WR_LSO) {
3998                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3999                 size_t left, copysz;
4000                 void *pdata = ud_wr->header;
4001                 size_t stride;
4002
4003                 left = ud_wr->hlen;
4004                 eseg->mss = cpu_to_be16(ud_wr->mss);
4005                 eseg->inline_hdr.sz = cpu_to_be16(left);
4006
4007                 /* memcpy_send_wqe should get a 16B align address. Hence, we
4008                  * first copy up to the current edge and then, if needed,
4009                  * fall-through to memcpy_send_wqe.
4010                  */
4011                 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
4012                                left);
4013                 memcpy(eseg->inline_hdr.start, pdata, copysz);
4014                 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
4015                                sizeof(eseg->inline_hdr.start) + copysz, 16);
4016                 *size += stride / 16;
4017                 *seg += stride;
4018
4019                 if (copysz < left) {
4020                         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4021                         left -= copysz;
4022                         pdata += copysz;
4023                         memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
4024                                         left);
4025                 }
4026
4027                 return;
4028         }
4029
4030         *seg += sizeof(struct mlx5_wqe_eth_seg);
4031         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
4032 }
4033
4034 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
4035                              const struct ib_send_wr *wr)
4036 {
4037         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
4038         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
4039         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
4040 }
4041
4042 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
4043 {
4044         dseg->byte_count = cpu_to_be32(sg->length);
4045         dseg->lkey       = cpu_to_be32(sg->lkey);
4046         dseg->addr       = cpu_to_be64(sg->addr);
4047 }
4048
4049 static u64 get_xlt_octo(u64 bytes)
4050 {
4051         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
4052                MLX5_IB_UMR_OCTOWORD;
4053 }
4054
4055 static __be64 frwr_mkey_mask(void)
4056 {
4057         u64 result;
4058
4059         result = MLX5_MKEY_MASK_LEN             |
4060                 MLX5_MKEY_MASK_PAGE_SIZE        |
4061                 MLX5_MKEY_MASK_START_ADDR       |
4062                 MLX5_MKEY_MASK_EN_RINVAL        |
4063                 MLX5_MKEY_MASK_KEY              |
4064                 MLX5_MKEY_MASK_LR               |
4065                 MLX5_MKEY_MASK_LW               |
4066                 MLX5_MKEY_MASK_RR               |
4067                 MLX5_MKEY_MASK_RW               |
4068                 MLX5_MKEY_MASK_A                |
4069                 MLX5_MKEY_MASK_SMALL_FENCE      |
4070                 MLX5_MKEY_MASK_FREE;
4071
4072         return cpu_to_be64(result);
4073 }
4074
4075 static __be64 sig_mkey_mask(void)
4076 {
4077         u64 result;
4078
4079         result = MLX5_MKEY_MASK_LEN             |
4080                 MLX5_MKEY_MASK_PAGE_SIZE        |
4081                 MLX5_MKEY_MASK_START_ADDR       |
4082                 MLX5_MKEY_MASK_EN_SIGERR        |
4083                 MLX5_MKEY_MASK_EN_RINVAL        |
4084                 MLX5_MKEY_MASK_KEY              |
4085                 MLX5_MKEY_MASK_LR               |
4086                 MLX5_MKEY_MASK_LW               |
4087                 MLX5_MKEY_MASK_RR               |
4088                 MLX5_MKEY_MASK_RW               |
4089                 MLX5_MKEY_MASK_SMALL_FENCE      |
4090                 MLX5_MKEY_MASK_FREE             |
4091                 MLX5_MKEY_MASK_BSF_EN;
4092
4093         return cpu_to_be64(result);
4094 }
4095
4096 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
4097                             struct mlx5_ib_mr *mr, bool umr_inline)
4098 {
4099         int size = mr->ndescs * mr->desc_size;
4100
4101         memset(umr, 0, sizeof(*umr));
4102
4103         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
4104         if (umr_inline)
4105                 umr->flags |= MLX5_UMR_INLINE;
4106         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4107         umr->mkey_mask = frwr_mkey_mask();
4108 }
4109
4110 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
4111 {
4112         memset(umr, 0, sizeof(*umr));
4113         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
4114         umr->flags = MLX5_UMR_INLINE;
4115 }
4116
4117 static __be64 get_umr_enable_mr_mask(void)
4118 {
4119         u64 result;
4120
4121         result = MLX5_MKEY_MASK_KEY |
4122                  MLX5_MKEY_MASK_FREE;
4123
4124         return cpu_to_be64(result);
4125 }
4126
4127 static __be64 get_umr_disable_mr_mask(void)
4128 {
4129         u64 result;
4130
4131         result = MLX5_MKEY_MASK_FREE;
4132
4133         return cpu_to_be64(result);
4134 }
4135
4136 static __be64 get_umr_update_translation_mask(void)
4137 {
4138         u64 result;
4139
4140         result = MLX5_MKEY_MASK_LEN |
4141                  MLX5_MKEY_MASK_PAGE_SIZE |
4142                  MLX5_MKEY_MASK_START_ADDR;
4143
4144         return cpu_to_be64(result);
4145 }
4146
4147 static __be64 get_umr_update_access_mask(int atomic)
4148 {
4149         u64 result;
4150
4151         result = MLX5_MKEY_MASK_LR |
4152                  MLX5_MKEY_MASK_LW |
4153                  MLX5_MKEY_MASK_RR |
4154                  MLX5_MKEY_MASK_RW;
4155
4156         if (atomic)
4157                 result |= MLX5_MKEY_MASK_A;
4158
4159         return cpu_to_be64(result);
4160 }
4161
4162 static __be64 get_umr_update_pd_mask(void)
4163 {
4164         u64 result;
4165
4166         result = MLX5_MKEY_MASK_PD;
4167
4168         return cpu_to_be64(result);
4169 }
4170
4171 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4172 {
4173         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4174              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4175             (mask & MLX5_MKEY_MASK_A &&
4176              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4177                 return -EPERM;
4178         return 0;
4179 }
4180
4181 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4182                                struct mlx5_wqe_umr_ctrl_seg *umr,
4183                                const struct ib_send_wr *wr, int atomic)
4184 {
4185         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4186
4187         memset(umr, 0, sizeof(*umr));
4188
4189         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4190                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
4191         else
4192                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
4193
4194         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4195         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4196                 u64 offset = get_xlt_octo(umrwr->offset);
4197
4198                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4199                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4200                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
4201         }
4202         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4203                 umr->mkey_mask |= get_umr_update_translation_mask();
4204         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4205                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4206                 umr->mkey_mask |= get_umr_update_pd_mask();
4207         }
4208         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4209                 umr->mkey_mask |= get_umr_enable_mr_mask();
4210         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4211                 umr->mkey_mask |= get_umr_disable_mr_mask();
4212
4213         if (!wr->num_sge)
4214                 umr->flags |= MLX5_UMR_INLINE;
4215
4216         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4217 }
4218
4219 static u8 get_umr_flags(int acc)
4220 {
4221         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
4222                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
4223                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
4224                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
4225                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4226 }
4227
4228 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4229                              struct mlx5_ib_mr *mr,
4230                              u32 key, int access)
4231 {
4232         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
4233
4234         memset(seg, 0, sizeof(*seg));
4235
4236         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4237                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4238         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4239                 /* KLMs take twice the size of MTTs */
4240                 ndescs *= 2;
4241
4242         seg->flags = get_umr_flags(access) | mr->access_mode;
4243         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4244         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4245         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4246         seg->len = cpu_to_be64(mr->ibmr.length);
4247         seg->xlt_oct_size = cpu_to_be32(ndescs);
4248 }
4249
4250 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4251 {
4252         memset(seg, 0, sizeof(*seg));
4253         seg->status = MLX5_MKEY_STATUS_FREE;
4254 }
4255
4256 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4257                                  const struct ib_send_wr *wr)
4258 {
4259         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4260
4261         memset(seg, 0, sizeof(*seg));
4262         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4263                 seg->status = MLX5_MKEY_STATUS_FREE;
4264
4265         seg->flags = convert_access(umrwr->access_flags);
4266         if (umrwr->pd)
4267                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4268         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4269             !umrwr->length)
4270                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4271
4272         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4273         seg->len = cpu_to_be64(umrwr->length);
4274         seg->log2_page_size = umrwr->page_shift;
4275         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4276                                        mlx5_mkey_variant(umrwr->mkey));
4277 }
4278
4279 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4280                              struct mlx5_ib_mr *mr,
4281                              struct mlx5_ib_pd *pd)
4282 {
4283         int bcount = mr->desc_size * mr->ndescs;
4284
4285         dseg->addr = cpu_to_be64(mr->desc_map);
4286         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4287         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4288 }
4289
4290 static __be32 send_ieth(const struct ib_send_wr *wr)
4291 {
4292         switch (wr->opcode) {
4293         case IB_WR_SEND_WITH_IMM:
4294         case IB_WR_RDMA_WRITE_WITH_IMM:
4295                 return wr->ex.imm_data;
4296
4297         case IB_WR_SEND_WITH_INV:
4298                 return cpu_to_be32(wr->ex.invalidate_rkey);
4299
4300         default:
4301                 return 0;
4302         }
4303 }
4304
4305 static u8 calc_sig(void *wqe, int size)
4306 {
4307         u8 *p = wqe;
4308         u8 res = 0;
4309         int i;
4310
4311         for (i = 0; i < size; i++)
4312                 res ^= p[i];
4313
4314         return ~res;
4315 }
4316
4317 static u8 wq_sig(void *wqe)
4318 {
4319         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4320 }
4321
4322 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4323                             void **wqe, int *wqe_sz, void **cur_edge)
4324 {
4325         struct mlx5_wqe_inline_seg *seg;
4326         size_t offset;
4327         int inl = 0;
4328         int i;
4329
4330         seg = *wqe;
4331         *wqe += sizeof(*seg);
4332         offset = sizeof(*seg);
4333
4334         for (i = 0; i < wr->num_sge; i++) {
4335                 size_t len  = wr->sg_list[i].length;
4336                 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4337
4338                 inl += len;
4339
4340                 if (unlikely(inl > qp->max_inline_data))
4341                         return -ENOMEM;
4342
4343                 while (likely(len)) {
4344                         size_t leftlen;
4345                         size_t copysz;
4346
4347                         handle_post_send_edge(&qp->sq, wqe,
4348                                               *wqe_sz + (offset >> 4),
4349                                               cur_edge);
4350
4351                         leftlen = *cur_edge - *wqe;
4352                         copysz = min_t(size_t, leftlen, len);
4353
4354                         memcpy(*wqe, addr, copysz);
4355                         len -= copysz;
4356                         addr += copysz;
4357                         *wqe += copysz;
4358                         offset += copysz;
4359                 }
4360         }
4361
4362         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4363
4364         *wqe_sz +=  ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4365
4366         return 0;
4367 }
4368
4369 static u16 prot_field_size(enum ib_signature_type type)
4370 {
4371         switch (type) {
4372         case IB_SIG_TYPE_T10_DIF:
4373                 return MLX5_DIF_SIZE;
4374         default:
4375                 return 0;
4376         }
4377 }
4378
4379 static u8 bs_selector(int block_size)
4380 {
4381         switch (block_size) {
4382         case 512:           return 0x1;
4383         case 520:           return 0x2;
4384         case 4096:          return 0x3;
4385         case 4160:          return 0x4;
4386         case 1073741824:    return 0x5;
4387         default:            return 0;
4388         }
4389 }
4390
4391 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4392                               struct mlx5_bsf_inl *inl)
4393 {
4394         /* Valid inline section and allow BSF refresh */
4395         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4396                                        MLX5_BSF_REFRESH_DIF);
4397         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4398         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4399         /* repeating block */
4400         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4401         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4402                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4403
4404         if (domain->sig.dif.ref_remap)
4405                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4406
4407         if (domain->sig.dif.app_escape) {
4408                 if (domain->sig.dif.ref_escape)
4409                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4410                 else
4411                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4412         }
4413
4414         inl->dif_app_bitmask_check =
4415                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4416 }
4417
4418 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4419                         struct ib_sig_attrs *sig_attrs,
4420                         struct mlx5_bsf *bsf, u32 data_size)
4421 {
4422         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4423         struct mlx5_bsf_basic *basic = &bsf->basic;
4424         struct ib_sig_domain *mem = &sig_attrs->mem;
4425         struct ib_sig_domain *wire = &sig_attrs->wire;
4426
4427         memset(bsf, 0, sizeof(*bsf));
4428
4429         /* Basic + Extended + Inline */
4430         basic->bsf_size_sbs = 1 << 7;
4431         /* Input domain check byte mask */
4432         basic->check_byte_mask = sig_attrs->check_mask;
4433         basic->raw_data_size = cpu_to_be32(data_size);
4434
4435         /* Memory domain */
4436         switch (sig_attrs->mem.sig_type) {
4437         case IB_SIG_TYPE_NONE:
4438                 break;
4439         case IB_SIG_TYPE_T10_DIF:
4440                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4441                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4442                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4443                 break;
4444         default:
4445                 return -EINVAL;
4446         }
4447
4448         /* Wire domain */
4449         switch (sig_attrs->wire.sig_type) {
4450         case IB_SIG_TYPE_NONE:
4451                 break;
4452         case IB_SIG_TYPE_T10_DIF:
4453                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4454                     mem->sig_type == wire->sig_type) {
4455                         /* Same block structure */
4456                         basic->bsf_size_sbs |= 1 << 4;
4457                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4458                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4459                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4460                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4461                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4462                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4463                 } else
4464                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4465
4466                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4467                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4468                 break;
4469         default:
4470                 return -EINVAL;
4471         }
4472
4473         return 0;
4474 }
4475
4476 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
4477                                 struct mlx5_ib_qp *qp, void **seg,
4478                                 int *size, void **cur_edge)
4479 {
4480         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4481         struct ib_mr *sig_mr = wr->sig_mr;
4482         struct mlx5_bsf *bsf;
4483         u32 data_len = wr->wr.sg_list->length;
4484         u32 data_key = wr->wr.sg_list->lkey;
4485         u64 data_va = wr->wr.sg_list->addr;
4486         int ret;
4487         int wqe_size;
4488
4489         if (!wr->prot ||
4490             (data_key == wr->prot->lkey &&
4491              data_va == wr->prot->addr &&
4492              data_len == wr->prot->length)) {
4493                 /**
4494                  * Source domain doesn't contain signature information
4495                  * or data and protection are interleaved in memory.
4496                  * So need construct:
4497                  *                  ------------------
4498                  *                 |     data_klm     |
4499                  *                  ------------------
4500                  *                 |       BSF        |
4501                  *                  ------------------
4502                  **/
4503                 struct mlx5_klm *data_klm = *seg;
4504
4505                 data_klm->bcount = cpu_to_be32(data_len);
4506                 data_klm->key = cpu_to_be32(data_key);
4507                 data_klm->va = cpu_to_be64(data_va);
4508                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4509         } else {
4510                 /**
4511                  * Source domain contains signature information
4512                  * So need construct a strided block format:
4513                  *               ---------------------------
4514                  *              |     stride_block_ctrl     |
4515                  *               ---------------------------
4516                  *              |          data_klm         |
4517                  *               ---------------------------
4518                  *              |          prot_klm         |
4519                  *               ---------------------------
4520                  *              |             BSF           |
4521                  *               ---------------------------
4522                  **/
4523                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4524                 struct mlx5_stride_block_entry *data_sentry;
4525                 struct mlx5_stride_block_entry *prot_sentry;
4526                 u32 prot_key = wr->prot->lkey;
4527                 u64 prot_va = wr->prot->addr;
4528                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4529                 int prot_size;
4530
4531                 sblock_ctrl = *seg;
4532                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4533                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4534
4535                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4536                 if (!prot_size) {
4537                         pr_err("Bad block size given: %u\n", block_size);
4538                         return -EINVAL;
4539                 }
4540                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4541                                                             prot_size);
4542                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4543                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4544                 sblock_ctrl->num_entries = cpu_to_be16(2);
4545
4546                 data_sentry->bcount = cpu_to_be16(block_size);
4547                 data_sentry->key = cpu_to_be32(data_key);
4548                 data_sentry->va = cpu_to_be64(data_va);
4549                 data_sentry->stride = cpu_to_be16(block_size);
4550
4551                 prot_sentry->bcount = cpu_to_be16(prot_size);
4552                 prot_sentry->key = cpu_to_be32(prot_key);
4553                 prot_sentry->va = cpu_to_be64(prot_va);
4554                 prot_sentry->stride = cpu_to_be16(prot_size);
4555
4556                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4557                                  sizeof(*prot_sentry), 64);
4558         }
4559
4560         *seg += wqe_size;
4561         *size += wqe_size / 16;
4562         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4563
4564         bsf = *seg;
4565         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4566         if (ret)
4567                 return -EINVAL;
4568
4569         *seg += sizeof(*bsf);
4570         *size += sizeof(*bsf) / 16;
4571         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4572
4573         return 0;
4574 }
4575
4576 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4577                                  const struct ib_sig_handover_wr *wr, u32 size,
4578                                  u32 length, u32 pdn)
4579 {
4580         struct ib_mr *sig_mr = wr->sig_mr;
4581         u32 sig_key = sig_mr->rkey;
4582         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4583
4584         memset(seg, 0, sizeof(*seg));
4585
4586         seg->flags = get_umr_flags(wr->access_flags) |
4587                                    MLX5_MKC_ACCESS_MODE_KLMS;
4588         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4589         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4590                                     MLX5_MKEY_BSF_EN | pdn);
4591         seg->len = cpu_to_be64(length);
4592         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4593         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4594 }
4595
4596 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4597                                 u32 size)
4598 {
4599         memset(umr, 0, sizeof(*umr));
4600
4601         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4602         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4603         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4604         umr->mkey_mask = sig_mkey_mask();
4605 }
4606
4607
4608 static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4609                           struct mlx5_ib_qp *qp, void **seg, int *size,
4610                           void **cur_edge)
4611 {
4612         const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4613         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4614         u32 pdn = get_pd(qp)->pdn;
4615         u32 xlt_size;
4616         int region_len, ret;
4617
4618         if (unlikely(wr->wr.num_sge != 1) ||
4619             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4620             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4621             unlikely(!sig_mr->sig->sig_status_checked))
4622                 return -EINVAL;
4623
4624         /* length of the protected region, data + protection */
4625         region_len = wr->wr.sg_list->length;
4626         if (wr->prot &&
4627             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
4628              wr->prot->addr != wr->wr.sg_list->addr  ||
4629              wr->prot->length != wr->wr.sg_list->length))
4630                 region_len += wr->prot->length;
4631
4632         /**
4633          * KLM octoword size - if protection was provided
4634          * then we use strided block format (3 octowords),
4635          * else we use single KLM (1 octoword)
4636          **/
4637         xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4638
4639         set_sig_umr_segment(*seg, xlt_size);
4640         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4641         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4642         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4643
4644         set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4645         *seg += sizeof(struct mlx5_mkey_seg);
4646         *size += sizeof(struct mlx5_mkey_seg) / 16;
4647         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4648
4649         ret = set_sig_data_segment(wr, qp, seg, size, cur_edge);
4650         if (ret)
4651                 return ret;
4652
4653         sig_mr->sig->sig_status_checked = false;
4654         return 0;
4655 }
4656
4657 static int set_psv_wr(struct ib_sig_domain *domain,
4658                       u32 psv_idx, void **seg, int *size)
4659 {
4660         struct mlx5_seg_set_psv *psv_seg = *seg;
4661
4662         memset(psv_seg, 0, sizeof(*psv_seg));
4663         psv_seg->psv_num = cpu_to_be32(psv_idx);
4664         switch (domain->sig_type) {
4665         case IB_SIG_TYPE_NONE:
4666                 break;
4667         case IB_SIG_TYPE_T10_DIF:
4668                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4669                                                      domain->sig.dif.app_tag);
4670                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4671                 break;
4672         default:
4673                 pr_err("Bad signature type (%d) is given.\n",
4674                        domain->sig_type);
4675                 return -EINVAL;
4676         }
4677
4678         *seg += sizeof(*psv_seg);
4679         *size += sizeof(*psv_seg) / 16;
4680
4681         return 0;
4682 }
4683
4684 static int set_reg_wr(struct mlx5_ib_qp *qp,
4685                       const struct ib_reg_wr *wr,
4686                       void **seg, int *size, void **cur_edge)
4687 {
4688         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4689         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4690         size_t mr_list_size = mr->ndescs * mr->desc_size;
4691         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4692
4693         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4694                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4695                              "Invalid IB_SEND_INLINE send flag\n");
4696                 return -EINVAL;
4697         }
4698
4699         set_reg_umr_seg(*seg, mr, umr_inline);
4700         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4701         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4702         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4703
4704         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4705         *seg += sizeof(struct mlx5_mkey_seg);
4706         *size += sizeof(struct mlx5_mkey_seg) / 16;
4707         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4708
4709         if (umr_inline) {
4710                 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4711                                 mr_list_size);
4712                 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
4713         } else {
4714                 set_reg_data_seg(*seg, mr, pd);
4715                 *seg += sizeof(struct mlx5_wqe_data_seg);
4716                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4717         }
4718         return 0;
4719 }
4720
4721 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4722                         void **cur_edge)
4723 {
4724         set_linv_umr_seg(*seg);
4725         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4726         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4727         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4728         set_linv_mkey_seg(*seg);
4729         *seg += sizeof(struct mlx5_mkey_seg);
4730         *size += sizeof(struct mlx5_mkey_seg) / 16;
4731         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4732 }
4733
4734 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
4735 {
4736         __be32 *p = NULL;
4737         int i, j;
4738
4739         pr_debug("dump WQE index %u:\n", idx);
4740         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4741                 if ((i & 0xf) == 0) {
4742                         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx);
4743                         pr_debug("WQBB at %p:\n", (void *)p);
4744                         j = 0;
4745                         idx = (idx + 1) & (qp->sq.wqe_cnt - 1);
4746                 }
4747                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4748                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4749                          be32_to_cpu(p[j + 3]));
4750         }
4751 }
4752
4753 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4754                        struct mlx5_wqe_ctrl_seg **ctrl,
4755                        const struct ib_send_wr *wr, unsigned int *idx,
4756                        int *size, void **cur_edge, int nreq,
4757                        bool send_signaled, bool solicited)
4758 {
4759         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4760                 return -ENOMEM;
4761
4762         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4763         *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
4764         *ctrl = *seg;
4765         *(uint32_t *)(*seg + 8) = 0;
4766         (*ctrl)->imm = send_ieth(wr);
4767         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4768                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4769                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4770
4771         *seg += sizeof(**ctrl);
4772         *size = sizeof(**ctrl) / 16;
4773         *cur_edge = qp->sq.cur_edge;
4774
4775         return 0;
4776 }
4777
4778 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4779                      struct mlx5_wqe_ctrl_seg **ctrl,
4780                      const struct ib_send_wr *wr, unsigned *idx,
4781                      int *size, void **cur_edge, int nreq)
4782 {
4783         return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
4784                            wr->send_flags & IB_SEND_SIGNALED,
4785                            wr->send_flags & IB_SEND_SOLICITED);
4786 }
4787
4788 static void finish_wqe(struct mlx5_ib_qp *qp,
4789                        struct mlx5_wqe_ctrl_seg *ctrl,
4790                        void *seg, u8 size, void *cur_edge,
4791                        unsigned int idx, u64 wr_id, int nreq, u8 fence,
4792                        u32 mlx5_opcode)
4793 {
4794         u8 opmod = 0;
4795
4796         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4797                                              mlx5_opcode | ((u32)opmod << 24));
4798         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4799         ctrl->fm_ce_se |= fence;
4800         if (unlikely(qp->wq_sig))
4801                 ctrl->signature = wq_sig(ctrl);
4802
4803         qp->sq.wrid[idx] = wr_id;
4804         qp->sq.w_list[idx].opcode = mlx5_opcode;
4805         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4806         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4807         qp->sq.w_list[idx].next = qp->sq.cur_post;
4808
4809         /* We save the edge which was possibly updated during the WQE
4810          * construction, into SQ's cache.
4811          */
4812         seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
4813         qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
4814                           get_sq_edge(&qp->sq, qp->sq.cur_post &
4815                                       (qp->sq.wqe_cnt - 1)) :
4816                           cur_edge;
4817 }
4818
4819 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4820                               const struct ib_send_wr **bad_wr, bool drain)
4821 {
4822         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
4823         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4824         struct mlx5_core_dev *mdev = dev->mdev;
4825         struct mlx5_ib_qp *qp;
4826         struct mlx5_ib_mr *mr;
4827         struct mlx5_wqe_xrc_seg *xrc;
4828         struct mlx5_bf *bf;
4829         void *cur_edge;
4830         int uninitialized_var(size);
4831         unsigned long flags;
4832         unsigned idx;
4833         int err = 0;
4834         int num_sge;
4835         void *seg;
4836         int nreq;
4837         int i;
4838         u8 next_fence = 0;
4839         u8 fence;
4840
4841         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4842                      !drain)) {
4843                 *bad_wr = wr;
4844                 return -EIO;
4845         }
4846
4847         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4848                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4849
4850         qp = to_mqp(ibqp);
4851         bf = &qp->bf;
4852
4853         spin_lock_irqsave(&qp->sq.lock, flags);
4854
4855         for (nreq = 0; wr; nreq++, wr = wr->next) {
4856                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4857                         mlx5_ib_warn(dev, "\n");
4858                         err = -EINVAL;
4859                         *bad_wr = wr;
4860                         goto out;
4861                 }
4862
4863                 num_sge = wr->num_sge;
4864                 if (unlikely(num_sge > qp->sq.max_gs)) {
4865                         mlx5_ib_warn(dev, "\n");
4866                         err = -EINVAL;
4867                         *bad_wr = wr;
4868                         goto out;
4869                 }
4870
4871                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
4872                                 nreq);
4873                 if (err) {
4874                         mlx5_ib_warn(dev, "\n");
4875                         err = -ENOMEM;
4876                         *bad_wr = wr;
4877                         goto out;
4878                 }
4879
4880                 if (wr->opcode == IB_WR_REG_MR) {
4881                         fence = dev->umr_fence;
4882                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4883                 } else  {
4884                         if (wr->send_flags & IB_SEND_FENCE) {
4885                                 if (qp->next_fence)
4886                                         fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4887                                 else
4888                                         fence = MLX5_FENCE_MODE_FENCE;
4889                         } else {
4890                                 fence = qp->next_fence;
4891                         }
4892                 }
4893
4894                 switch (ibqp->qp_type) {
4895                 case IB_QPT_XRC_INI:
4896                         xrc = seg;
4897                         seg += sizeof(*xrc);
4898                         size += sizeof(*xrc) / 16;
4899                         /* fall through */
4900                 case IB_QPT_RC:
4901                         switch (wr->opcode) {
4902                         case IB_WR_RDMA_READ:
4903                         case IB_WR_RDMA_WRITE:
4904                         case IB_WR_RDMA_WRITE_WITH_IMM:
4905                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4906                                               rdma_wr(wr)->rkey);
4907                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
4908                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4909                                 break;
4910
4911                         case IB_WR_ATOMIC_CMP_AND_SWP:
4912                         case IB_WR_ATOMIC_FETCH_AND_ADD:
4913                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4914                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4915                                 err = -ENOSYS;
4916                                 *bad_wr = wr;
4917                                 goto out;
4918
4919                         case IB_WR_LOCAL_INV:
4920                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4921                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4922                                 set_linv_wr(qp, &seg, &size, &cur_edge);
4923                                 num_sge = 0;
4924                                 break;
4925
4926                         case IB_WR_REG_MR:
4927                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4928                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4929                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
4930                                                  &cur_edge);
4931                                 if (err) {
4932                                         *bad_wr = wr;
4933                                         goto out;
4934                                 }
4935                                 num_sge = 0;
4936                                 break;
4937
4938                         case IB_WR_REG_SIG_MR:
4939                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4940                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4941
4942                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4943                                 err = set_sig_umr_wr(wr, qp, &seg, &size,
4944                                                      &cur_edge);
4945                                 if (err) {
4946                                         mlx5_ib_warn(dev, "\n");
4947                                         *bad_wr = wr;
4948                                         goto out;
4949                                 }
4950
4951                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4952                                            wr->wr_id, nreq, fence,
4953                                            MLX5_OPCODE_UMR);
4954                                 /*
4955                                  * SET_PSV WQEs are not signaled and solicited
4956                                  * on error
4957                                  */
4958                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4959                                                   &size, &cur_edge, nreq, false,
4960                                                   true);
4961                                 if (err) {
4962                                         mlx5_ib_warn(dev, "\n");
4963                                         err = -ENOMEM;
4964                                         *bad_wr = wr;
4965                                         goto out;
4966                                 }
4967
4968                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4969                                                  mr->sig->psv_memory.psv_idx, &seg,
4970                                                  &size);
4971                                 if (err) {
4972                                         mlx5_ib_warn(dev, "\n");
4973                                         *bad_wr = wr;
4974                                         goto out;
4975                                 }
4976
4977                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4978                                            wr->wr_id, nreq, fence,
4979                                            MLX5_OPCODE_SET_PSV);
4980                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4981                                                   &size, &cur_edge, nreq, false,
4982                                                   true);
4983                                 if (err) {
4984                                         mlx5_ib_warn(dev, "\n");
4985                                         err = -ENOMEM;
4986                                         *bad_wr = wr;
4987                                         goto out;
4988                                 }
4989
4990                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4991                                                  mr->sig->psv_wire.psv_idx, &seg,
4992                                                  &size);
4993                                 if (err) {
4994                                         mlx5_ib_warn(dev, "\n");
4995                                         *bad_wr = wr;
4996                                         goto out;
4997                                 }
4998
4999                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5000                                            wr->wr_id, nreq, fence,
5001                                            MLX5_OPCODE_SET_PSV);
5002                                 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
5003                                 num_sge = 0;
5004                                 goto skip_psv;
5005
5006                         default:
5007                                 break;
5008                         }
5009                         break;
5010
5011                 case IB_QPT_UC:
5012                         switch (wr->opcode) {
5013                         case IB_WR_RDMA_WRITE:
5014                         case IB_WR_RDMA_WRITE_WITH_IMM:
5015                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5016                                               rdma_wr(wr)->rkey);
5017                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
5018                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5019                                 break;
5020
5021                         default:
5022                                 break;
5023                         }
5024                         break;
5025
5026                 case IB_QPT_SMI:
5027                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
5028                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
5029                                 err = -EPERM;
5030                                 *bad_wr = wr;
5031                                 goto out;
5032                         }
5033                         /* fall through */
5034                 case MLX5_IB_QPT_HW_GSI:
5035                         set_datagram_seg(seg, wr);
5036                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5037                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5038                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5039
5040                         break;
5041                 case IB_QPT_UD:
5042                         set_datagram_seg(seg, wr);
5043                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5044                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5045                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5046
5047                         /* handle qp that supports ud offload */
5048                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
5049                                 struct mlx5_wqe_eth_pad *pad;
5050
5051                                 pad = seg;
5052                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
5053                                 seg += sizeof(struct mlx5_wqe_eth_pad);
5054                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
5055                                 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
5056                                 handle_post_send_edge(&qp->sq, &seg, size,
5057                                                       &cur_edge);
5058                         }
5059                         break;
5060                 case MLX5_IB_QPT_REG_UMR:
5061                         if (wr->opcode != MLX5_IB_WR_UMR) {
5062                                 err = -EINVAL;
5063                                 mlx5_ib_warn(dev, "bad opcode\n");
5064                                 goto out;
5065                         }
5066                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
5067                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
5068                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
5069                         if (unlikely(err))
5070                                 goto out;
5071                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5072                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
5073                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5074                         set_reg_mkey_segment(seg, wr);
5075                         seg += sizeof(struct mlx5_mkey_seg);
5076                         size += sizeof(struct mlx5_mkey_seg) / 16;
5077                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5078                         break;
5079
5080                 default:
5081                         break;
5082                 }
5083
5084                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
5085                         err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
5086                         if (unlikely(err)) {
5087                                 mlx5_ib_warn(dev, "\n");
5088                                 *bad_wr = wr;
5089                                 goto out;
5090                         }
5091                 } else {
5092                         for (i = 0; i < num_sge; i++) {
5093                                 handle_post_send_edge(&qp->sq, &seg, size,
5094                                                       &cur_edge);
5095                                 if (likely(wr->sg_list[i].length)) {
5096                                         set_data_ptr_seg
5097                                         ((struct mlx5_wqe_data_seg *)seg,
5098                                          wr->sg_list + i);
5099                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
5100                                         seg += sizeof(struct mlx5_wqe_data_seg);
5101                                 }
5102                         }
5103                 }
5104
5105                 qp->next_fence = next_fence;
5106                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
5107                            fence, mlx5_ib_opcode[wr->opcode]);
5108 skip_psv:
5109                 if (0)
5110                         dump_wqe(qp, idx, size);
5111         }
5112
5113 out:
5114         if (likely(nreq)) {
5115                 qp->sq.head += nreq;
5116
5117                 /* Make sure that descriptors are written before
5118                  * updating doorbell record and ringing the doorbell
5119                  */
5120                 wmb();
5121
5122                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5123
5124                 /* Make sure doorbell record is visible to the HCA before
5125                  * we hit doorbell */
5126                 wmb();
5127
5128                 /* currently we support only regular doorbells */
5129                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset);
5130                 /* Make sure doorbells don't leak out of SQ spinlock
5131                  * and reach the HCA out of order.
5132                  */
5133                 mmiowb();
5134                 bf->offset ^= bf->buf_size;
5135         }
5136
5137         spin_unlock_irqrestore(&qp->sq.lock, flags);
5138
5139         return err;
5140 }
5141
5142 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5143                       const struct ib_send_wr **bad_wr)
5144 {
5145         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5146 }
5147
5148 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5149 {
5150         sig->signature = calc_sig(sig, size);
5151 }
5152
5153 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5154                       const struct ib_recv_wr **bad_wr, bool drain)
5155 {
5156         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5157         struct mlx5_wqe_data_seg *scat;
5158         struct mlx5_rwqe_sig *sig;
5159         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5160         struct mlx5_core_dev *mdev = dev->mdev;
5161         unsigned long flags;
5162         int err = 0;
5163         int nreq;
5164         int ind;
5165         int i;
5166
5167         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5168                      !drain)) {
5169                 *bad_wr = wr;
5170                 return -EIO;
5171         }
5172
5173         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5174                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5175
5176         spin_lock_irqsave(&qp->rq.lock, flags);
5177
5178         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5179
5180         for (nreq = 0; wr; nreq++, wr = wr->next) {
5181                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5182                         err = -ENOMEM;
5183                         *bad_wr = wr;
5184                         goto out;
5185                 }
5186
5187                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5188                         err = -EINVAL;
5189                         *bad_wr = wr;
5190                         goto out;
5191                 }
5192
5193                 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
5194                 if (qp->wq_sig)
5195                         scat++;
5196
5197                 for (i = 0; i < wr->num_sge; i++)
5198                         set_data_ptr_seg(scat + i, wr->sg_list + i);
5199
5200                 if (i < qp->rq.max_gs) {
5201                         scat[i].byte_count = 0;
5202                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
5203                         scat[i].addr       = 0;
5204                 }
5205
5206                 if (qp->wq_sig) {
5207                         sig = (struct mlx5_rwqe_sig *)scat;
5208                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5209                 }
5210
5211                 qp->rq.wrid[ind] = wr->wr_id;
5212
5213                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5214         }
5215
5216 out:
5217         if (likely(nreq)) {
5218                 qp->rq.head += nreq;
5219
5220                 /* Make sure that descriptors are written before
5221                  * doorbell record.
5222                  */
5223                 wmb();
5224
5225                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5226         }
5227
5228         spin_unlock_irqrestore(&qp->rq.lock, flags);
5229
5230         return err;
5231 }
5232
5233 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5234                       const struct ib_recv_wr **bad_wr)
5235 {
5236         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5237 }
5238
5239 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5240 {
5241         switch (mlx5_state) {
5242         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
5243         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
5244         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
5245         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
5246         case MLX5_QP_STATE_SQ_DRAINING:
5247         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
5248         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
5249         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
5250         default:                     return -1;
5251         }
5252 }
5253
5254 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5255 {
5256         switch (mlx5_mig_state) {
5257         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
5258         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
5259         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
5260         default: return -1;
5261         }
5262 }
5263
5264 static int to_ib_qp_access_flags(int mlx5_flags)
5265 {
5266         int ib_flags = 0;
5267
5268         if (mlx5_flags & MLX5_QP_BIT_RRE)
5269                 ib_flags |= IB_ACCESS_REMOTE_READ;
5270         if (mlx5_flags & MLX5_QP_BIT_RWE)
5271                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5272         if (mlx5_flags & MLX5_QP_BIT_RAE)
5273                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5274
5275         return ib_flags;
5276 }
5277
5278 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5279                             struct rdma_ah_attr *ah_attr,
5280                             struct mlx5_qp_path *path)
5281 {
5282
5283         memset(ah_attr, 0, sizeof(*ah_attr));
5284
5285         if (!path->port || path->port > ibdev->num_ports)
5286                 return;
5287
5288         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5289
5290         rdma_ah_set_port_num(ah_attr, path->port);
5291         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5292
5293         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5294         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5295         rdma_ah_set_static_rate(ah_attr,
5296                                 path->static_rate ? path->static_rate - 5 : 0);
5297         if (path->grh_mlid & (1 << 7)) {
5298                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5299
5300                 rdma_ah_set_grh(ah_attr, NULL,
5301                                 tc_fl & 0xfffff,
5302                                 path->mgid_index,
5303                                 path->hop_limit,
5304                                 (tc_fl >> 20) & 0xff);
5305                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5306         }
5307 }
5308
5309 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5310                                         struct mlx5_ib_sq *sq,
5311                                         u8 *sq_state)
5312 {
5313         int err;
5314
5315         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5316         if (err)
5317                 goto out;
5318         sq->state = *sq_state;
5319
5320 out:
5321         return err;
5322 }
5323
5324 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5325                                         struct mlx5_ib_rq *rq,
5326                                         u8 *rq_state)
5327 {
5328         void *out;
5329         void *rqc;
5330         int inlen;
5331         int err;
5332
5333         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5334         out = kvzalloc(inlen, GFP_KERNEL);
5335         if (!out)
5336                 return -ENOMEM;
5337
5338         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5339         if (err)
5340                 goto out;
5341
5342         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5343         *rq_state = MLX5_GET(rqc, rqc, state);
5344         rq->state = *rq_state;
5345
5346 out:
5347         kvfree(out);
5348         return err;
5349 }
5350
5351 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5352                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5353 {
5354         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5355                 [MLX5_RQC_STATE_RST] = {
5356                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5357                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5358                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5359                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5360                 },
5361                 [MLX5_RQC_STATE_RDY] = {
5362                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5363                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5364                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5365                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5366                 },
5367                 [MLX5_RQC_STATE_ERR] = {
5368                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5369                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5370                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5371                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5372                 },
5373                 [MLX5_RQ_STATE_NA] = {
5374                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5375                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5376                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5377                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5378                 },
5379         };
5380
5381         *qp_state = sqrq_trans[rq_state][sq_state];
5382
5383         if (*qp_state == MLX5_QP_STATE_BAD) {
5384                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5385                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5386                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5387                 return -EINVAL;
5388         }
5389
5390         if (*qp_state == MLX5_QP_STATE)
5391                 *qp_state = qp->state;
5392
5393         return 0;
5394 }
5395
5396 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5397                                      struct mlx5_ib_qp *qp,
5398                                      u8 *raw_packet_qp_state)
5399 {
5400         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5401         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5402         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5403         int err;
5404         u8 sq_state = MLX5_SQ_STATE_NA;
5405         u8 rq_state = MLX5_RQ_STATE_NA;
5406
5407         if (qp->sq.wqe_cnt) {
5408                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5409                 if (err)
5410                         return err;
5411         }
5412
5413         if (qp->rq.wqe_cnt) {
5414                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5415                 if (err)
5416                         return err;
5417         }
5418
5419         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5420                                       raw_packet_qp_state);
5421 }
5422
5423 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5424                          struct ib_qp_attr *qp_attr)
5425 {
5426         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5427         struct mlx5_qp_context *context;
5428         int mlx5_state;
5429         u32 *outb;
5430         int err = 0;
5431
5432         outb = kzalloc(outlen, GFP_KERNEL);
5433         if (!outb)
5434                 return -ENOMEM;
5435
5436         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5437                                  outlen);
5438         if (err)
5439                 goto out;
5440
5441         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5442         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5443
5444         mlx5_state = be32_to_cpu(context->flags) >> 28;
5445
5446         qp->state                    = to_ib_qp_state(mlx5_state);
5447         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5448         qp_attr->path_mig_state      =
5449                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5450         qp_attr->qkey                = be32_to_cpu(context->qkey);
5451         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5452         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5453         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5454         qp_attr->qp_access_flags     =
5455                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5456
5457         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5458                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5459                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5460                 qp_attr->alt_pkey_index =
5461                         be16_to_cpu(context->alt_path.pkey_index);
5462                 qp_attr->alt_port_num   =
5463                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5464         }
5465
5466         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5467         qp_attr->port_num = context->pri_path.port;
5468
5469         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5470         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5471
5472         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5473
5474         qp_attr->max_dest_rd_atomic =
5475                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5476         qp_attr->min_rnr_timer      =
5477                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5478         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5479         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5480         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5481         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5482
5483 out:
5484         kfree(outb);
5485         return err;
5486 }
5487
5488 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5489                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5490                                 struct ib_qp_init_attr *qp_init_attr)
5491 {
5492         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5493         u32 *out;
5494         u32 access_flags = 0;
5495         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5496         void *dctc;
5497         int err;
5498         int supported_mask = IB_QP_STATE |
5499                              IB_QP_ACCESS_FLAGS |
5500                              IB_QP_PORT |
5501                              IB_QP_MIN_RNR_TIMER |
5502                              IB_QP_AV |
5503                              IB_QP_PATH_MTU |
5504                              IB_QP_PKEY_INDEX;
5505
5506         if (qp_attr_mask & ~supported_mask)
5507                 return -EINVAL;
5508         if (mqp->state != IB_QPS_RTR)
5509                 return -EINVAL;
5510
5511         out = kzalloc(outlen, GFP_KERNEL);
5512         if (!out)
5513                 return -ENOMEM;
5514
5515         err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5516         if (err)
5517                 goto out;
5518
5519         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5520
5521         if (qp_attr_mask & IB_QP_STATE)
5522                 qp_attr->qp_state = IB_QPS_RTR;
5523
5524         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5525                 if (MLX5_GET(dctc, dctc, rre))
5526                         access_flags |= IB_ACCESS_REMOTE_READ;
5527                 if (MLX5_GET(dctc, dctc, rwe))
5528                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5529                 if (MLX5_GET(dctc, dctc, rae))
5530                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5531                 qp_attr->qp_access_flags = access_flags;
5532         }
5533
5534         if (qp_attr_mask & IB_QP_PORT)
5535                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5536         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5537                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5538         if (qp_attr_mask & IB_QP_AV) {
5539                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5540                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5541                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5542                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5543         }
5544         if (qp_attr_mask & IB_QP_PATH_MTU)
5545                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5546         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5547                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5548 out:
5549         kfree(out);
5550         return err;
5551 }
5552
5553 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5554                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5555 {
5556         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5557         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5558         int err = 0;
5559         u8 raw_packet_qp_state;
5560
5561         if (ibqp->rwq_ind_tbl)
5562                 return -ENOSYS;
5563
5564         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5565                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5566                                             qp_init_attr);
5567
5568         /* Not all of output fields are applicable, make sure to zero them */
5569         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5570         memset(qp_attr, 0, sizeof(*qp_attr));
5571
5572         if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5573                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5574                                             qp_attr_mask, qp_init_attr);
5575
5576         mutex_lock(&qp->mutex);
5577
5578         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5579             qp->flags & MLX5_IB_QP_UNDERLAY) {
5580                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5581                 if (err)
5582                         goto out;
5583                 qp->state = raw_packet_qp_state;
5584                 qp_attr->port_num = 1;
5585         } else {
5586                 err = query_qp_attr(dev, qp, qp_attr);
5587                 if (err)
5588                         goto out;
5589         }
5590
5591         qp_attr->qp_state            = qp->state;
5592         qp_attr->cur_qp_state        = qp_attr->qp_state;
5593         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5594         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5595
5596         if (!ibqp->uobject) {
5597                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5598                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5599                 qp_init_attr->qp_context = ibqp->qp_context;
5600         } else {
5601                 qp_attr->cap.max_send_wr  = 0;
5602                 qp_attr->cap.max_send_sge = 0;
5603         }
5604
5605         qp_init_attr->qp_type = ibqp->qp_type;
5606         qp_init_attr->recv_cq = ibqp->recv_cq;
5607         qp_init_attr->send_cq = ibqp->send_cq;
5608         qp_init_attr->srq = ibqp->srq;
5609         qp_attr->cap.max_inline_data = qp->max_inline_data;
5610
5611         qp_init_attr->cap            = qp_attr->cap;
5612
5613         qp_init_attr->create_flags = 0;
5614         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5615                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5616
5617         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5618                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5619         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5620                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5621         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5622                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5623         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5624                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5625
5626         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5627                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5628
5629 out:
5630         mutex_unlock(&qp->mutex);
5631         return err;
5632 }
5633
5634 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5635                                    struct ib_udata *udata)
5636 {
5637         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5638         struct mlx5_ib_xrcd *xrcd;
5639         int err;
5640
5641         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5642                 return ERR_PTR(-ENOSYS);
5643
5644         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5645         if (!xrcd)
5646                 return ERR_PTR(-ENOMEM);
5647
5648         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
5649         if (err) {
5650                 kfree(xrcd);
5651                 return ERR_PTR(-ENOMEM);
5652         }
5653
5654         return &xrcd->ibxrcd;
5655 }
5656
5657 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
5658 {
5659         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5660         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5661         int err;
5662
5663         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
5664         if (err)
5665                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5666
5667         kfree(xrcd);
5668         return 0;
5669 }
5670
5671 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5672 {
5673         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5674         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5675         struct ib_event event;
5676
5677         if (rwq->ibwq.event_handler) {
5678                 event.device     = rwq->ibwq.device;
5679                 event.element.wq = &rwq->ibwq;
5680                 switch (type) {
5681                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5682                         event.event = IB_EVENT_WQ_FATAL;
5683                         break;
5684                 default:
5685                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5686                         return;
5687                 }
5688
5689                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5690         }
5691 }
5692
5693 static int set_delay_drop(struct mlx5_ib_dev *dev)
5694 {
5695         int err = 0;
5696
5697         mutex_lock(&dev->delay_drop.lock);
5698         if (dev->delay_drop.activate)
5699                 goto out;
5700
5701         err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5702         if (err)
5703                 goto out;
5704
5705         dev->delay_drop.activate = true;
5706 out:
5707         mutex_unlock(&dev->delay_drop.lock);
5708
5709         if (!err)
5710                 atomic_inc(&dev->delay_drop.rqs_cnt);
5711         return err;
5712 }
5713
5714 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5715                       struct ib_wq_init_attr *init_attr)
5716 {
5717         struct mlx5_ib_dev *dev;
5718         int has_net_offloads;
5719         __be64 *rq_pas0;
5720         void *in;
5721         void *rqc;
5722         void *wq;
5723         int inlen;
5724         int err;
5725
5726         dev = to_mdev(pd->device);
5727
5728         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5729         in = kvzalloc(inlen, GFP_KERNEL);
5730         if (!in)
5731                 return -ENOMEM;
5732
5733         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5734         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5735         MLX5_SET(rqc,  rqc, mem_rq_type,
5736                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5737         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5738         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5739         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5740         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5741         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5742         MLX5_SET(wq, wq, wq_type,
5743                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5744                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5745         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5746                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5747                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5748                         err = -EOPNOTSUPP;
5749                         goto out;
5750                 } else {
5751                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5752                 }
5753         }
5754         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5755         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5756                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5757                 MLX5_SET(wq, wq, log_wqe_stride_size,
5758                          rwq->single_stride_log_num_of_bytes -
5759                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5760                 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5761                          MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5762         }
5763         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5764         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5765         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5766         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5767         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5768         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5769         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5770         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5771                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5772                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5773                         err = -EOPNOTSUPP;
5774                         goto out;
5775                 }
5776         } else {
5777                 MLX5_SET(rqc, rqc, vsd, 1);
5778         }
5779         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5780                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5781                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5782                         err = -EOPNOTSUPP;
5783                         goto out;
5784                 }
5785                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5786         }
5787         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5788                 if (!(dev->ib_dev.attrs.raw_packet_caps &
5789                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
5790                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5791                         err = -EOPNOTSUPP;
5792                         goto out;
5793                 }
5794                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5795         }
5796         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5797         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5798         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5799         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5800                 err = set_delay_drop(dev);
5801                 if (err) {
5802                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5803                                      err);
5804                         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5805                 } else {
5806                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5807                 }
5808         }
5809 out:
5810         kvfree(in);
5811         return err;
5812 }
5813
5814 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5815                             struct ib_wq_init_attr *wq_init_attr,
5816                             struct mlx5_ib_create_wq *ucmd,
5817                             struct mlx5_ib_rwq *rwq)
5818 {
5819         /* Sanity check RQ size before proceeding */
5820         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5821                 return -EINVAL;
5822
5823         if (!ucmd->rq_wqe_count)
5824                 return -EINVAL;
5825
5826         rwq->wqe_count = ucmd->rq_wqe_count;
5827         rwq->wqe_shift = ucmd->rq_wqe_shift;
5828         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5829                 return -EINVAL;
5830
5831         rwq->log_rq_stride = rwq->wqe_shift;
5832         rwq->log_rq_size = ilog2(rwq->wqe_count);
5833         return 0;
5834 }
5835
5836 static int prepare_user_rq(struct ib_pd *pd,
5837                            struct ib_wq_init_attr *init_attr,
5838                            struct ib_udata *udata,
5839                            struct mlx5_ib_rwq *rwq)
5840 {
5841         struct mlx5_ib_dev *dev = to_mdev(pd->device);
5842         struct mlx5_ib_create_wq ucmd = {};
5843         int err;
5844         size_t required_cmd_sz;
5845
5846         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5847                 + sizeof(ucmd.single_stride_log_num_of_bytes);
5848         if (udata->inlen < required_cmd_sz) {
5849                 mlx5_ib_dbg(dev, "invalid inlen\n");
5850                 return -EINVAL;
5851         }
5852
5853         if (udata->inlen > sizeof(ucmd) &&
5854             !ib_is_udata_cleared(udata, sizeof(ucmd),
5855                                  udata->inlen - sizeof(ucmd))) {
5856                 mlx5_ib_dbg(dev, "inlen is not supported\n");
5857                 return -EOPNOTSUPP;
5858         }
5859
5860         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5861                 mlx5_ib_dbg(dev, "copy failed\n");
5862                 return -EFAULT;
5863         }
5864
5865         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5866                 mlx5_ib_dbg(dev, "invalid comp mask\n");
5867                 return -EOPNOTSUPP;
5868         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5869                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5870                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5871                         return -EOPNOTSUPP;
5872                 }
5873                 if ((ucmd.single_stride_log_num_of_bytes <
5874                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5875                     (ucmd.single_stride_log_num_of_bytes >
5876                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5877                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5878                                     ucmd.single_stride_log_num_of_bytes,
5879                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5880                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5881                         return -EINVAL;
5882                 }
5883                 if ((ucmd.single_wqe_log_num_of_strides >
5884                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5885                      (ucmd.single_wqe_log_num_of_strides <
5886                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5887                         mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5888                                     ucmd.single_wqe_log_num_of_strides,
5889                                     MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5890                                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5891                         return -EINVAL;
5892                 }
5893                 rwq->single_stride_log_num_of_bytes =
5894                         ucmd.single_stride_log_num_of_bytes;
5895                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5896                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5897                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5898         }
5899
5900         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5901         if (err) {
5902                 mlx5_ib_dbg(dev, "err %d\n", err);
5903                 return err;
5904         }
5905
5906         err = create_user_rq(dev, pd, udata, rwq, &ucmd);
5907         if (err) {
5908                 mlx5_ib_dbg(dev, "err %d\n", err);
5909                 return err;
5910         }
5911
5912         rwq->user_index = ucmd.user_index;
5913         return 0;
5914 }
5915
5916 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5917                                 struct ib_wq_init_attr *init_attr,
5918                                 struct ib_udata *udata)
5919 {
5920         struct mlx5_ib_dev *dev;
5921         struct mlx5_ib_rwq *rwq;
5922         struct mlx5_ib_create_wq_resp resp = {};
5923         size_t min_resp_len;
5924         int err;
5925
5926         if (!udata)
5927                 return ERR_PTR(-ENOSYS);
5928
5929         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5930         if (udata->outlen && udata->outlen < min_resp_len)
5931                 return ERR_PTR(-EINVAL);
5932
5933         dev = to_mdev(pd->device);
5934         switch (init_attr->wq_type) {
5935         case IB_WQT_RQ:
5936                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5937                 if (!rwq)
5938                         return ERR_PTR(-ENOMEM);
5939                 err = prepare_user_rq(pd, init_attr, udata, rwq);
5940                 if (err)
5941                         goto err;
5942                 err = create_rq(rwq, pd, init_attr);
5943                 if (err)
5944                         goto err_user_rq;
5945                 break;
5946         default:
5947                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5948                             init_attr->wq_type);
5949                 return ERR_PTR(-EINVAL);
5950         }
5951
5952         rwq->ibwq.wq_num = rwq->core_qp.qpn;
5953         rwq->ibwq.state = IB_WQS_RESET;
5954         if (udata->outlen) {
5955                 resp.response_length = offsetof(typeof(resp), response_length) +
5956                                 sizeof(resp.response_length);
5957                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5958                 if (err)
5959                         goto err_copy;
5960         }
5961
5962         rwq->core_qp.event = mlx5_ib_wq_event;
5963         rwq->ibwq.event_handler = init_attr->event_handler;
5964         return &rwq->ibwq;
5965
5966 err_copy:
5967         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5968 err_user_rq:
5969         destroy_user_rq(dev, pd, rwq, udata);
5970 err:
5971         kfree(rwq);
5972         return ERR_PTR(err);
5973 }
5974
5975 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
5976 {
5977         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5978         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5979
5980         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5981         destroy_user_rq(dev, wq->pd, rwq, udata);
5982         kfree(rwq);
5983
5984         return 0;
5985 }
5986
5987 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5988                                                       struct ib_rwq_ind_table_init_attr *init_attr,
5989                                                       struct ib_udata *udata)
5990 {
5991         struct mlx5_ib_dev *dev = to_mdev(device);
5992         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5993         int sz = 1 << init_attr->log_ind_tbl_size;
5994         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5995         size_t min_resp_len;
5996         int inlen;
5997         int err;
5998         int i;
5999         u32 *in;
6000         void *rqtc;
6001
6002         if (udata->inlen > 0 &&
6003             !ib_is_udata_cleared(udata, 0,
6004                                  udata->inlen))
6005                 return ERR_PTR(-EOPNOTSUPP);
6006
6007         if (init_attr->log_ind_tbl_size >
6008             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
6009                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
6010                             init_attr->log_ind_tbl_size,
6011                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
6012                 return ERR_PTR(-EINVAL);
6013         }
6014
6015         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6016         if (udata->outlen && udata->outlen < min_resp_len)
6017                 return ERR_PTR(-EINVAL);
6018
6019         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
6020         if (!rwq_ind_tbl)
6021                 return ERR_PTR(-ENOMEM);
6022
6023         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
6024         in = kvzalloc(inlen, GFP_KERNEL);
6025         if (!in) {
6026                 err = -ENOMEM;
6027                 goto err;
6028         }
6029
6030         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
6031
6032         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
6033         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
6034
6035         for (i = 0; i < sz; i++)
6036                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
6037
6038         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
6039         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
6040
6041         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
6042         kvfree(in);
6043
6044         if (err)
6045                 goto err;
6046
6047         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
6048         if (udata->outlen) {
6049                 resp.response_length = offsetof(typeof(resp), response_length) +
6050                                         sizeof(resp.response_length);
6051                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6052                 if (err)
6053                         goto err_copy;
6054         }
6055
6056         return &rwq_ind_tbl->ib_rwq_ind_tbl;
6057
6058 err_copy:
6059         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6060 err:
6061         kfree(rwq_ind_tbl);
6062         return ERR_PTR(err);
6063 }
6064
6065 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
6066 {
6067         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
6068         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
6069
6070         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6071
6072         kfree(rwq_ind_tbl);
6073         return 0;
6074 }
6075
6076 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
6077                       u32 wq_attr_mask, struct ib_udata *udata)
6078 {
6079         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6080         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6081         struct mlx5_ib_modify_wq ucmd = {};
6082         size_t required_cmd_sz;
6083         int curr_wq_state;
6084         int wq_state;
6085         int inlen;
6086         int err;
6087         void *rqc;
6088         void *in;
6089
6090         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
6091         if (udata->inlen < required_cmd_sz)
6092                 return -EINVAL;
6093
6094         if (udata->inlen > sizeof(ucmd) &&
6095             !ib_is_udata_cleared(udata, sizeof(ucmd),
6096                                  udata->inlen - sizeof(ucmd)))
6097                 return -EOPNOTSUPP;
6098
6099         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
6100                 return -EFAULT;
6101
6102         if (ucmd.comp_mask || ucmd.reserved)
6103                 return -EOPNOTSUPP;
6104
6105         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
6106         in = kvzalloc(inlen, GFP_KERNEL);
6107         if (!in)
6108                 return -ENOMEM;
6109
6110         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6111
6112         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6113                 wq_attr->curr_wq_state : wq->state;
6114         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6115                 wq_attr->wq_state : curr_wq_state;
6116         if (curr_wq_state == IB_WQS_ERR)
6117                 curr_wq_state = MLX5_RQC_STATE_ERR;
6118         if (wq_state == IB_WQS_ERR)
6119                 wq_state = MLX5_RQC_STATE_ERR;
6120         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
6121         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
6122         MLX5_SET(rqc, rqc, state, wq_state);
6123
6124         if (wq_attr_mask & IB_WQ_FLAGS) {
6125                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6126                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6127                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6128                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
6129                                             "supported\n");
6130                                 err = -EOPNOTSUPP;
6131                                 goto out;
6132                         }
6133                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6134                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6135                         MLX5_SET(rqc, rqc, vsd,
6136                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6137                 }
6138
6139                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6140                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6141                         err = -EOPNOTSUPP;
6142                         goto out;
6143                 }
6144         }
6145
6146         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6147                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6148                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6149                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
6150                         MLX5_SET(rqc, rqc, counter_set_id,
6151                                  dev->port->cnts.set_id);
6152                 } else
6153                         dev_info_once(
6154                                 &dev->ib_dev.dev,
6155                                 "Receive WQ counters are not supported on current FW\n");
6156         }
6157
6158         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
6159         if (!err)
6160                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6161
6162 out:
6163         kvfree(in);
6164         return err;
6165 }
6166
6167 struct mlx5_ib_drain_cqe {
6168         struct ib_cqe cqe;
6169         struct completion done;
6170 };
6171
6172 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6173 {
6174         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6175                                                      struct mlx5_ib_drain_cqe,
6176                                                      cqe);
6177
6178         complete(&cqe->done);
6179 }
6180
6181 /* This function returns only once the drained WR was completed */
6182 static void handle_drain_completion(struct ib_cq *cq,
6183                                     struct mlx5_ib_drain_cqe *sdrain,
6184                                     struct mlx5_ib_dev *dev)
6185 {
6186         struct mlx5_core_dev *mdev = dev->mdev;
6187
6188         if (cq->poll_ctx == IB_POLL_DIRECT) {
6189                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6190                         ib_process_cq_direct(cq, -1);
6191                 return;
6192         }
6193
6194         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6195                 struct mlx5_ib_cq *mcq = to_mcq(cq);
6196                 bool triggered = false;
6197                 unsigned long flags;
6198
6199                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6200                 /* Make sure that the CQ handler won't run if wasn't run yet */
6201                 if (!mcq->mcq.reset_notify_added)
6202                         mcq->mcq.reset_notify_added = 1;
6203                 else
6204                         triggered = true;
6205                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6206
6207                 if (triggered) {
6208                         /* Wait for any scheduled/running task to be ended */
6209                         switch (cq->poll_ctx) {
6210                         case IB_POLL_SOFTIRQ:
6211                                 irq_poll_disable(&cq->iop);
6212                                 irq_poll_enable(&cq->iop);
6213                                 break;
6214                         case IB_POLL_WORKQUEUE:
6215                                 cancel_work_sync(&cq->work);
6216                                 break;
6217                         default:
6218                                 WARN_ON_ONCE(1);
6219                         }
6220                 }
6221
6222                 /* Run the CQ handler - this makes sure that the drain WR will
6223                  * be processed if wasn't processed yet.
6224                  */
6225                 mcq->mcq.comp(&mcq->mcq);
6226         }
6227
6228         wait_for_completion(&sdrain->done);
6229 }
6230
6231 void mlx5_ib_drain_sq(struct ib_qp *qp)
6232 {
6233         struct ib_cq *cq = qp->send_cq;
6234         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6235         struct mlx5_ib_drain_cqe sdrain;
6236         const struct ib_send_wr *bad_swr;
6237         struct ib_rdma_wr swr = {
6238                 .wr = {
6239                         .next = NULL,
6240                         { .wr_cqe       = &sdrain.cqe, },
6241                         .opcode = IB_WR_RDMA_WRITE,
6242                 },
6243         };
6244         int ret;
6245         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6246         struct mlx5_core_dev *mdev = dev->mdev;
6247
6248         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6249         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6250                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6251                 return;
6252         }
6253
6254         sdrain.cqe.done = mlx5_ib_drain_qp_done;
6255         init_completion(&sdrain.done);
6256
6257         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6258         if (ret) {
6259                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6260                 return;
6261         }
6262
6263         handle_drain_completion(cq, &sdrain, dev);
6264 }
6265
6266 void mlx5_ib_drain_rq(struct ib_qp *qp)
6267 {
6268         struct ib_cq *cq = qp->recv_cq;
6269         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6270         struct mlx5_ib_drain_cqe rdrain;
6271         struct ib_recv_wr rwr = {};
6272         const struct ib_recv_wr *bad_rwr;
6273         int ret;
6274         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6275         struct mlx5_core_dev *mdev = dev->mdev;
6276
6277         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6278         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6279                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6280                 return;
6281         }
6282
6283         rwr.wr_cqe = &rdrain.cqe;
6284         rdrain.cqe.done = mlx5_ib_drain_qp_done;
6285         init_completion(&rdrain.done);
6286
6287         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6288         if (ret) {
6289                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6290                 return;
6291         }
6292
6293         handle_drain_completion(cq, &rdrain, dev);
6294 }