IB/mlx5: Allow future extension of libmlx5 input data
[sfrench/cifs-2.6.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include "mlx5_ib.h"
38
39 /* not supported currently */
40 static int wq_signature;
41
42 enum {
43         MLX5_IB_ACK_REQ_FREQ    = 8,
44 };
45
46 enum {
47         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
48         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
49         MLX5_IB_LINK_TYPE_IB            = 0,
50         MLX5_IB_LINK_TYPE_ETH           = 1
51 };
52
53 enum {
54         MLX5_IB_SQ_STRIDE       = 6,
55 };
56
57 static const u32 mlx5_ib_opcode[] = {
58         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
59         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
60         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
61         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
62         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
63         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
64         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
65         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
66         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
67         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
68         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
69         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
70         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
71         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
72 };
73
74 struct mlx5_wqe_eth_pad {
75         u8 rsvd0[16];
76 };
77
78 enum raw_qp_set_mask_map {
79         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
80         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
81 };
82
83 struct mlx5_modify_raw_qp_param {
84         u16 operation;
85
86         u32 set_mask; /* raw_qp_set_mask_map */
87         u32 rate_limit;
88         u8 rq_q_ctr_id;
89 };
90
91 static void get_cqs(enum ib_qp_type qp_type,
92                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
93                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
94
95 static int is_qp0(enum ib_qp_type qp_type)
96 {
97         return qp_type == IB_QPT_SMI;
98 }
99
100 static int is_sqp(enum ib_qp_type qp_type)
101 {
102         return is_qp0(qp_type) || is_qp1(qp_type);
103 }
104
105 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
106 {
107         return mlx5_buf_offset(&qp->buf, offset);
108 }
109
110 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
111 {
112         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
113 }
114
115 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
116 {
117         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
118 }
119
120 /**
121  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
122  *
123  * @qp: QP to copy from.
124  * @send: copy from the send queue when non-zero, use the receive queue
125  *        otherwise.
126  * @wqe_index:  index to start copying from. For send work queues, the
127  *              wqe_index is in units of MLX5_SEND_WQE_BB.
128  *              For receive work queue, it is the number of work queue
129  *              element in the queue.
130  * @buffer: destination buffer.
131  * @length: maximum number of bytes to copy.
132  *
133  * Copies at least a single WQE, but may copy more data.
134  *
135  * Return: the number of bytes copied, or an error code.
136  */
137 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
138                           void *buffer, u32 length,
139                           struct mlx5_ib_qp_base *base)
140 {
141         struct ib_device *ibdev = qp->ibqp.device;
142         struct mlx5_ib_dev *dev = to_mdev(ibdev);
143         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
144         size_t offset;
145         size_t wq_end;
146         struct ib_umem *umem = base->ubuffer.umem;
147         u32 first_copy_length;
148         int wqe_length;
149         int ret;
150
151         if (wq->wqe_cnt == 0) {
152                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
153                             qp->ibqp.qp_type);
154                 return -EINVAL;
155         }
156
157         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
158         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
159
160         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
161                 return -EINVAL;
162
163         if (offset > umem->length ||
164             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
165                 return -EINVAL;
166
167         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
168         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
169         if (ret)
170                 return ret;
171
172         if (send) {
173                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
174                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
175
176                 wqe_length = ds * MLX5_WQE_DS_UNITS;
177         } else {
178                 wqe_length = 1 << wq->wqe_shift;
179         }
180
181         if (wqe_length <= first_copy_length)
182                 return first_copy_length;
183
184         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
185                                 wqe_length - first_copy_length);
186         if (ret)
187                 return ret;
188
189         return wqe_length;
190 }
191
192 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
193 {
194         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
195         struct ib_event event;
196
197         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
198                 /* This event is only valid for trans_qps */
199                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
200         }
201
202         if (ibqp->event_handler) {
203                 event.device     = ibqp->device;
204                 event.element.qp = ibqp;
205                 switch (type) {
206                 case MLX5_EVENT_TYPE_PATH_MIG:
207                         event.event = IB_EVENT_PATH_MIG;
208                         break;
209                 case MLX5_EVENT_TYPE_COMM_EST:
210                         event.event = IB_EVENT_COMM_EST;
211                         break;
212                 case MLX5_EVENT_TYPE_SQ_DRAINED:
213                         event.event = IB_EVENT_SQ_DRAINED;
214                         break;
215                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
216                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
217                         break;
218                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
219                         event.event = IB_EVENT_QP_FATAL;
220                         break;
221                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
222                         event.event = IB_EVENT_PATH_MIG_ERR;
223                         break;
224                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
225                         event.event = IB_EVENT_QP_REQ_ERR;
226                         break;
227                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
228                         event.event = IB_EVENT_QP_ACCESS_ERR;
229                         break;
230                 default:
231                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
232                         return;
233                 }
234
235                 ibqp->event_handler(&event, ibqp->qp_context);
236         }
237 }
238
239 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
240                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
241 {
242         int wqe_size;
243         int wq_size;
244
245         /* Sanity check RQ size before proceeding */
246         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
247                 return -EINVAL;
248
249         if (!has_rq) {
250                 qp->rq.max_gs = 0;
251                 qp->rq.wqe_cnt = 0;
252                 qp->rq.wqe_shift = 0;
253                 cap->max_recv_wr = 0;
254                 cap->max_recv_sge = 0;
255         } else {
256                 if (ucmd) {
257                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
258                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
259                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
260                         qp->rq.max_post = qp->rq.wqe_cnt;
261                 } else {
262                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
263                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
264                         wqe_size = roundup_pow_of_two(wqe_size);
265                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
266                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
267                         qp->rq.wqe_cnt = wq_size / wqe_size;
268                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
269                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
270                                             wqe_size,
271                                             MLX5_CAP_GEN(dev->mdev,
272                                                          max_wqe_sz_rq));
273                                 return -EINVAL;
274                         }
275                         qp->rq.wqe_shift = ilog2(wqe_size);
276                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
277                         qp->rq.max_post = qp->rq.wqe_cnt;
278                 }
279         }
280
281         return 0;
282 }
283
284 static int sq_overhead(struct ib_qp_init_attr *attr)
285 {
286         int size = 0;
287
288         switch (attr->qp_type) {
289         case IB_QPT_XRC_INI:
290                 size += sizeof(struct mlx5_wqe_xrc_seg);
291                 /* fall through */
292         case IB_QPT_RC:
293                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
294                         max(sizeof(struct mlx5_wqe_atomic_seg) +
295                             sizeof(struct mlx5_wqe_raddr_seg),
296                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
297                             sizeof(struct mlx5_mkey_seg));
298                 break;
299
300         case IB_QPT_XRC_TGT:
301                 return 0;
302
303         case IB_QPT_UC:
304                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
305                         max(sizeof(struct mlx5_wqe_raddr_seg),
306                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
307                             sizeof(struct mlx5_mkey_seg));
308                 break;
309
310         case IB_QPT_UD:
311                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
312                         size += sizeof(struct mlx5_wqe_eth_pad) +
313                                 sizeof(struct mlx5_wqe_eth_seg);
314                 /* fall through */
315         case IB_QPT_SMI:
316         case MLX5_IB_QPT_HW_GSI:
317                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
318                         sizeof(struct mlx5_wqe_datagram_seg);
319                 break;
320
321         case MLX5_IB_QPT_REG_UMR:
322                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
323                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
324                         sizeof(struct mlx5_mkey_seg);
325                 break;
326
327         default:
328                 return -EINVAL;
329         }
330
331         return size;
332 }
333
334 static int calc_send_wqe(struct ib_qp_init_attr *attr)
335 {
336         int inl_size = 0;
337         int size;
338
339         size = sq_overhead(attr);
340         if (size < 0)
341                 return size;
342
343         if (attr->cap.max_inline_data) {
344                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
345                         attr->cap.max_inline_data;
346         }
347
348         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
349         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
350             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
351                         return MLX5_SIG_WQE_SIZE;
352         else
353                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
354 }
355
356 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
357 {
358         int max_sge;
359
360         if (attr->qp_type == IB_QPT_RC)
361                 max_sge = (min_t(int, wqe_size, 512) -
362                            sizeof(struct mlx5_wqe_ctrl_seg) -
363                            sizeof(struct mlx5_wqe_raddr_seg)) /
364                         sizeof(struct mlx5_wqe_data_seg);
365         else if (attr->qp_type == IB_QPT_XRC_INI)
366                 max_sge = (min_t(int, wqe_size, 512) -
367                            sizeof(struct mlx5_wqe_ctrl_seg) -
368                            sizeof(struct mlx5_wqe_xrc_seg) -
369                            sizeof(struct mlx5_wqe_raddr_seg)) /
370                         sizeof(struct mlx5_wqe_data_seg);
371         else
372                 max_sge = (wqe_size - sq_overhead(attr)) /
373                         sizeof(struct mlx5_wqe_data_seg);
374
375         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
376                      sizeof(struct mlx5_wqe_data_seg));
377 }
378
379 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
380                         struct mlx5_ib_qp *qp)
381 {
382         int wqe_size;
383         int wq_size;
384
385         if (!attr->cap.max_send_wr)
386                 return 0;
387
388         wqe_size = calc_send_wqe(attr);
389         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
390         if (wqe_size < 0)
391                 return wqe_size;
392
393         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
394                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
395                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
396                 return -EINVAL;
397         }
398
399         qp->max_inline_data = wqe_size - sq_overhead(attr) -
400                               sizeof(struct mlx5_wqe_inline_seg);
401         attr->cap.max_inline_data = qp->max_inline_data;
402
403         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
404                 qp->signature_en = true;
405
406         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
407         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
408         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
409                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
410                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
411                             qp->sq.wqe_cnt,
412                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
413                 return -ENOMEM;
414         }
415         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
416         qp->sq.max_gs = get_send_sge(attr, wqe_size);
417         if (qp->sq.max_gs < attr->cap.max_send_sge)
418                 return -ENOMEM;
419
420         attr->cap.max_send_sge = qp->sq.max_gs;
421         qp->sq.max_post = wq_size / wqe_size;
422         attr->cap.max_send_wr = qp->sq.max_post;
423
424         return wq_size;
425 }
426
427 static int set_user_buf_size(struct mlx5_ib_dev *dev,
428                             struct mlx5_ib_qp *qp,
429                             struct mlx5_ib_create_qp *ucmd,
430                             struct mlx5_ib_qp_base *base,
431                             struct ib_qp_init_attr *attr)
432 {
433         int desc_sz = 1 << qp->sq.wqe_shift;
434
435         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
436                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
437                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
438                 return -EINVAL;
439         }
440
441         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
442                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
443                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
444                 return -EINVAL;
445         }
446
447         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
448
449         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
450                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
451                              qp->sq.wqe_cnt,
452                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
453                 return -EINVAL;
454         }
455
456         if (attr->qp_type == IB_QPT_RAW_PACKET) {
457                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
458                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
459         } else {
460                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
461                                          (qp->sq.wqe_cnt << 6);
462         }
463
464         return 0;
465 }
466
467 static int qp_has_rq(struct ib_qp_init_attr *attr)
468 {
469         if (attr->qp_type == IB_QPT_XRC_INI ||
470             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
471             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
472             !attr->cap.max_recv_wr)
473                 return 0;
474
475         return 1;
476 }
477
478 static int first_med_bfreg(void)
479 {
480         return 1;
481 }
482
483 enum {
484         /* this is the first blue flame register in the array of bfregs assigned
485          * to a processes. Since we do not use it for blue flame but rather
486          * regular 64 bit doorbells, we do not need a lock for maintaiing
487          * "odd/even" order
488          */
489         NUM_NON_BLUE_FLAME_BFREGS = 1,
490 };
491
492 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
493 {
494         return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
495 }
496
497 static int num_med_bfreg(struct mlx5_ib_dev *dev,
498                          struct mlx5_bfreg_info *bfregi)
499 {
500         int n;
501
502         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
503             NUM_NON_BLUE_FLAME_BFREGS;
504
505         return n >= 0 ? n : 0;
506 }
507
508 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
509                           struct mlx5_bfreg_info *bfregi)
510 {
511         int med;
512
513         med = num_med_bfreg(dev, bfregi);
514         return ++med;
515 }
516
517 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
518                                   struct mlx5_bfreg_info *bfregi)
519 {
520         int i;
521
522         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
523                 if (!bfregi->count[i]) {
524                         bfregi->count[i]++;
525                         return i;
526                 }
527         }
528
529         return -ENOMEM;
530 }
531
532 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
533                                  struct mlx5_bfreg_info *bfregi)
534 {
535         int minidx = first_med_bfreg();
536         int i;
537
538         for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
539                 if (bfregi->count[i] < bfregi->count[minidx])
540                         minidx = i;
541                 if (!bfregi->count[minidx])
542                         break;
543         }
544
545         bfregi->count[minidx]++;
546         return minidx;
547 }
548
549 static int alloc_bfreg(struct mlx5_ib_dev *dev,
550                        struct mlx5_bfreg_info *bfregi,
551                        enum mlx5_ib_latency_class lat)
552 {
553         int bfregn = -EINVAL;
554
555         mutex_lock(&bfregi->lock);
556         switch (lat) {
557         case MLX5_IB_LATENCY_CLASS_LOW:
558                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
559                 bfregn = 0;
560                 bfregi->count[bfregn]++;
561                 break;
562
563         case MLX5_IB_LATENCY_CLASS_MEDIUM:
564                 if (bfregi->ver < 2)
565                         bfregn = -ENOMEM;
566                 else
567                         bfregn = alloc_med_class_bfreg(dev, bfregi);
568                 break;
569
570         case MLX5_IB_LATENCY_CLASS_HIGH:
571                 if (bfregi->ver < 2)
572                         bfregn = -ENOMEM;
573                 else
574                         bfregn = alloc_high_class_bfreg(dev, bfregi);
575                 break;
576         }
577         mutex_unlock(&bfregi->lock);
578
579         return bfregn;
580 }
581
582 static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
583 {
584         mutex_lock(&bfregi->lock);
585         bfregi->count[bfregn]--;
586         mutex_unlock(&bfregi->lock);
587 }
588
589 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
590 {
591         switch (state) {
592         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
593         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
594         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
595         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
596         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
597         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
598         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
599         default:                return -1;
600         }
601 }
602
603 static int to_mlx5_st(enum ib_qp_type type)
604 {
605         switch (type) {
606         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
607         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
608         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
609         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
610         case IB_QPT_XRC_INI:
611         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
612         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
613         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
614         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
615         case IB_QPT_RAW_PACKET:
616         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
617         case IB_QPT_MAX:
618         default:                return -EINVAL;
619         }
620 }
621
622 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
623                              struct mlx5_ib_cq *recv_cq);
624 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
625                                struct mlx5_ib_cq *recv_cq);
626
627 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
628                                struct mlx5_bfreg_info *bfregi, int bfregn)
629 {
630         int bfregs_per_sys_page;
631         int index_of_sys_page;
632         int offset;
633
634         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
635                                 MLX5_NON_FP_BFREGS_PER_UAR;
636         index_of_sys_page = bfregn / bfregs_per_sys_page;
637
638         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
639
640         return bfregi->sys_pages[index_of_sys_page] + offset;
641 }
642
643 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
644                             struct ib_pd *pd,
645                             unsigned long addr, size_t size,
646                             struct ib_umem **umem,
647                             int *npages, int *page_shift, int *ncont,
648                             u32 *offset)
649 {
650         int err;
651
652         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
653         if (IS_ERR(*umem)) {
654                 mlx5_ib_dbg(dev, "umem_get failed\n");
655                 return PTR_ERR(*umem);
656         }
657
658         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
659
660         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
661         if (err) {
662                 mlx5_ib_warn(dev, "bad offset\n");
663                 goto err_umem;
664         }
665
666         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
667                     addr, size, *npages, *page_shift, *ncont, *offset);
668
669         return 0;
670
671 err_umem:
672         ib_umem_release(*umem);
673         *umem = NULL;
674
675         return err;
676 }
677
678 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
679 {
680         struct mlx5_ib_ucontext *context;
681
682         context = to_mucontext(pd->uobject->context);
683         mlx5_ib_db_unmap_user(context, &rwq->db);
684         if (rwq->umem)
685                 ib_umem_release(rwq->umem);
686 }
687
688 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
689                           struct mlx5_ib_rwq *rwq,
690                           struct mlx5_ib_create_wq *ucmd)
691 {
692         struct mlx5_ib_ucontext *context;
693         int page_shift = 0;
694         int npages;
695         u32 offset = 0;
696         int ncont = 0;
697         int err;
698
699         if (!ucmd->buf_addr)
700                 return -EINVAL;
701
702         context = to_mucontext(pd->uobject->context);
703         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
704                                rwq->buf_size, 0, 0);
705         if (IS_ERR(rwq->umem)) {
706                 mlx5_ib_dbg(dev, "umem_get failed\n");
707                 err = PTR_ERR(rwq->umem);
708                 return err;
709         }
710
711         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
712                            &ncont, NULL);
713         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
714                                      &rwq->rq_page_offset);
715         if (err) {
716                 mlx5_ib_warn(dev, "bad offset\n");
717                 goto err_umem;
718         }
719
720         rwq->rq_num_pas = ncont;
721         rwq->page_shift = page_shift;
722         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
723         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
724
725         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
726                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
727                     npages, page_shift, ncont, offset);
728
729         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
730         if (err) {
731                 mlx5_ib_dbg(dev, "map failed\n");
732                 goto err_umem;
733         }
734
735         rwq->create_type = MLX5_WQ_USER;
736         return 0;
737
738 err_umem:
739         ib_umem_release(rwq->umem);
740         return err;
741 }
742
743 static int adjust_bfregn(struct mlx5_ib_dev *dev,
744                          struct mlx5_bfreg_info *bfregi, int bfregn)
745 {
746         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
747                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
748 }
749
750 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
751                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
752                           struct ib_qp_init_attr *attr,
753                           u32 **in,
754                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
755                           struct mlx5_ib_qp_base *base)
756 {
757         struct mlx5_ib_ucontext *context;
758         struct mlx5_ib_create_qp ucmd;
759         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
760         int page_shift = 0;
761         int uar_index;
762         int npages;
763         u32 offset = 0;
764         int bfregn;
765         int ncont = 0;
766         __be64 *pas;
767         void *qpc;
768         int err;
769
770         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
771         if (err) {
772                 mlx5_ib_dbg(dev, "copy failed\n");
773                 return err;
774         }
775
776         context = to_mucontext(pd->uobject->context);
777         /*
778          * TBD: should come from the verbs when we have the API
779          */
780         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
781                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
782                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
783         else {
784                 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
785                 if (bfregn < 0) {
786                         mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
787                         mlx5_ib_dbg(dev, "reverting to medium latency\n");
788                         bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
789                         if (bfregn < 0) {
790                                 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
791                                 mlx5_ib_dbg(dev, "reverting to high latency\n");
792                                 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
793                                 if (bfregn < 0) {
794                                         mlx5_ib_warn(dev, "bfreg allocation failed\n");
795                                         return bfregn;
796                                 }
797                         }
798                 }
799         }
800
801         uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
802         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
803
804         qp->rq.offset = 0;
805         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
806         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
807
808         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
809         if (err)
810                 goto err_bfreg;
811
812         if (ucmd.buf_addr && ubuffer->buf_size) {
813                 ubuffer->buf_addr = ucmd.buf_addr;
814                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
815                                        ubuffer->buf_size,
816                                        &ubuffer->umem, &npages, &page_shift,
817                                        &ncont, &offset);
818                 if (err)
819                         goto err_bfreg;
820         } else {
821                 ubuffer->umem = NULL;
822         }
823
824         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
825                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
826         *in = mlx5_vzalloc(*inlen);
827         if (!*in) {
828                 err = -ENOMEM;
829                 goto err_umem;
830         }
831
832         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
833         if (ubuffer->umem)
834                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
835
836         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
837
838         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
839         MLX5_SET(qpc, qpc, page_offset, offset);
840
841         MLX5_SET(qpc, qpc, uar_page, uar_index);
842         resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
843         qp->bfregn = bfregn;
844
845         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
846         if (err) {
847                 mlx5_ib_dbg(dev, "map failed\n");
848                 goto err_free;
849         }
850
851         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
852         if (err) {
853                 mlx5_ib_dbg(dev, "copy failed\n");
854                 goto err_unmap;
855         }
856         qp->create_type = MLX5_QP_USER;
857
858         return 0;
859
860 err_unmap:
861         mlx5_ib_db_unmap_user(context, &qp->db);
862
863 err_free:
864         kvfree(*in);
865
866 err_umem:
867         if (ubuffer->umem)
868                 ib_umem_release(ubuffer->umem);
869
870 err_bfreg:
871         free_bfreg(dev, &context->bfregi, bfregn);
872         return err;
873 }
874
875 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
876                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
877 {
878         struct mlx5_ib_ucontext *context;
879
880         context = to_mucontext(pd->uobject->context);
881         mlx5_ib_db_unmap_user(context, &qp->db);
882         if (base->ubuffer.umem)
883                 ib_umem_release(base->ubuffer.umem);
884         free_bfreg(dev, &context->bfregi, qp->bfregn);
885 }
886
887 static int create_kernel_qp(struct mlx5_ib_dev *dev,
888                             struct ib_qp_init_attr *init_attr,
889                             struct mlx5_ib_qp *qp,
890                             u32 **in, int *inlen,
891                             struct mlx5_ib_qp_base *base)
892 {
893         int uar_index;
894         void *qpc;
895         int err;
896
897         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
898                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
899                                         IB_QP_CREATE_IPOIB_UD_LSO |
900                                         mlx5_ib_create_qp_sqpn_qp1()))
901                 return -EINVAL;
902
903         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
904                 qp->bf.bfreg = &dev->fp_bfreg;
905         else
906                 qp->bf.bfreg = &dev->bfreg;
907
908         qp->bf.buf_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
909         uar_index = qp->bf.bfreg->index;
910
911         err = calc_sq_size(dev, init_attr, qp);
912         if (err < 0) {
913                 mlx5_ib_dbg(dev, "err %d\n", err);
914                 return err;
915         }
916
917         qp->rq.offset = 0;
918         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
919         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
920
921         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
922         if (err) {
923                 mlx5_ib_dbg(dev, "err %d\n", err);
924                 return err;
925         }
926
927         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
928         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
929                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
930         *in = mlx5_vzalloc(*inlen);
931         if (!*in) {
932                 err = -ENOMEM;
933                 goto err_buf;
934         }
935
936         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
937         MLX5_SET(qpc, qpc, uar_page, uar_index);
938         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
939
940         /* Set "fast registration enabled" for all kernel QPs */
941         MLX5_SET(qpc, qpc, fre, 1);
942         MLX5_SET(qpc, qpc, rlky, 1);
943
944         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
945                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
946                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
947         }
948
949         mlx5_fill_page_array(&qp->buf,
950                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
951
952         err = mlx5_db_alloc(dev->mdev, &qp->db);
953         if (err) {
954                 mlx5_ib_dbg(dev, "err %d\n", err);
955                 goto err_free;
956         }
957
958         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
959         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
960         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
961         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
962         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
963
964         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
965             !qp->sq.w_list || !qp->sq.wqe_head) {
966                 err = -ENOMEM;
967                 goto err_wrid;
968         }
969         qp->create_type = MLX5_QP_KERNEL;
970
971         return 0;
972
973 err_wrid:
974         kfree(qp->sq.wqe_head);
975         kfree(qp->sq.w_list);
976         kfree(qp->sq.wrid);
977         kfree(qp->sq.wr_data);
978         kfree(qp->rq.wrid);
979         mlx5_db_free(dev->mdev, &qp->db);
980
981 err_free:
982         kvfree(*in);
983
984 err_buf:
985         mlx5_buf_free(dev->mdev, &qp->buf);
986         return err;
987 }
988
989 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
990 {
991         kfree(qp->sq.wqe_head);
992         kfree(qp->sq.w_list);
993         kfree(qp->sq.wrid);
994         kfree(qp->sq.wr_data);
995         kfree(qp->rq.wrid);
996         mlx5_db_free(dev->mdev, &qp->db);
997         mlx5_buf_free(dev->mdev, &qp->buf);
998 }
999
1000 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1001 {
1002         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1003             (attr->qp_type == IB_QPT_XRC_INI))
1004                 return MLX5_SRQ_RQ;
1005         else if (!qp->has_rq)
1006                 return MLX5_ZERO_LEN_RQ;
1007         else
1008                 return MLX5_NON_ZERO_RQ;
1009 }
1010
1011 static int is_connected(enum ib_qp_type qp_type)
1012 {
1013         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1014                 return 1;
1015
1016         return 0;
1017 }
1018
1019 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1020                                     struct mlx5_ib_sq *sq, u32 tdn)
1021 {
1022         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1023         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1024
1025         MLX5_SET(tisc, tisc, transport_domain, tdn);
1026         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1027 }
1028
1029 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1030                                       struct mlx5_ib_sq *sq)
1031 {
1032         mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1033 }
1034
1035 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1036                                    struct mlx5_ib_sq *sq, void *qpin,
1037                                    struct ib_pd *pd)
1038 {
1039         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1040         __be64 *pas;
1041         void *in;
1042         void *sqc;
1043         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1044         void *wq;
1045         int inlen;
1046         int err;
1047         int page_shift = 0;
1048         int npages;
1049         int ncont = 0;
1050         u32 offset = 0;
1051
1052         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1053                                &sq->ubuffer.umem, &npages, &page_shift,
1054                                &ncont, &offset);
1055         if (err)
1056                 return err;
1057
1058         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1059         in = mlx5_vzalloc(inlen);
1060         if (!in) {
1061                 err = -ENOMEM;
1062                 goto err_umem;
1063         }
1064
1065         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1066         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1067         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1068         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1069         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1070         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1071         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1072
1073         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1074         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1075         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1076         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1077         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1078         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1079         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1080         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1081         MLX5_SET(wq, wq, page_offset, offset);
1082
1083         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1084         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1085
1086         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1087
1088         kvfree(in);
1089
1090         if (err)
1091                 goto err_umem;
1092
1093         return 0;
1094
1095 err_umem:
1096         ib_umem_release(sq->ubuffer.umem);
1097         sq->ubuffer.umem = NULL;
1098
1099         return err;
1100 }
1101
1102 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1103                                      struct mlx5_ib_sq *sq)
1104 {
1105         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1106         ib_umem_release(sq->ubuffer.umem);
1107 }
1108
1109 static int get_rq_pas_size(void *qpc)
1110 {
1111         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1112         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1113         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1114         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1115         u32 po_quanta     = 1 << (log_page_size - 6);
1116         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1117         u32 page_size     = 1 << log_page_size;
1118         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1119         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1120
1121         return rq_num_pas * sizeof(u64);
1122 }
1123
1124 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1125                                    struct mlx5_ib_rq *rq, void *qpin)
1126 {
1127         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1128         __be64 *pas;
1129         __be64 *qp_pas;
1130         void *in;
1131         void *rqc;
1132         void *wq;
1133         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1134         int inlen;
1135         int err;
1136         u32 rq_pas_size = get_rq_pas_size(qpc);
1137
1138         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1139         in = mlx5_vzalloc(inlen);
1140         if (!in)
1141                 return -ENOMEM;
1142
1143         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1144         MLX5_SET(rqc, rqc, vsd, 1);
1145         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1146         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1147         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1148         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1149         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1150
1151         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1152                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1153
1154         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1155         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1156         MLX5_SET(wq, wq, end_padding_mode,
1157                  MLX5_GET(qpc, qpc, end_padding_mode));
1158         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1159         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1160         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1161         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1162         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1163         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1164
1165         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1166         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1167         memcpy(pas, qp_pas, rq_pas_size);
1168
1169         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1170
1171         kvfree(in);
1172
1173         return err;
1174 }
1175
1176 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1177                                      struct mlx5_ib_rq *rq)
1178 {
1179         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1180 }
1181
1182 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1183                                     struct mlx5_ib_rq *rq, u32 tdn)
1184 {
1185         u32 *in;
1186         void *tirc;
1187         int inlen;
1188         int err;
1189
1190         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1191         in = mlx5_vzalloc(inlen);
1192         if (!in)
1193                 return -ENOMEM;
1194
1195         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1196         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1197         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1198         MLX5_SET(tirc, tirc, transport_domain, tdn);
1199
1200         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1201
1202         kvfree(in);
1203
1204         return err;
1205 }
1206
1207 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1208                                       struct mlx5_ib_rq *rq)
1209 {
1210         mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1211 }
1212
1213 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1214                                 u32 *in,
1215                                 struct ib_pd *pd)
1216 {
1217         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1218         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1219         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1220         struct ib_uobject *uobj = pd->uobject;
1221         struct ib_ucontext *ucontext = uobj->context;
1222         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1223         int err;
1224         u32 tdn = mucontext->tdn;
1225
1226         if (qp->sq.wqe_cnt) {
1227                 err = create_raw_packet_qp_tis(dev, sq, tdn);
1228                 if (err)
1229                         return err;
1230
1231                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1232                 if (err)
1233                         goto err_destroy_tis;
1234
1235                 sq->base.container_mibqp = qp;
1236         }
1237
1238         if (qp->rq.wqe_cnt) {
1239                 rq->base.container_mibqp = qp;
1240
1241                 err = create_raw_packet_qp_rq(dev, rq, in);
1242                 if (err)
1243                         goto err_destroy_sq;
1244
1245
1246                 err = create_raw_packet_qp_tir(dev, rq, tdn);
1247                 if (err)
1248                         goto err_destroy_rq;
1249         }
1250
1251         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1252                                                      rq->base.mqp.qpn;
1253
1254         return 0;
1255
1256 err_destroy_rq:
1257         destroy_raw_packet_qp_rq(dev, rq);
1258 err_destroy_sq:
1259         if (!qp->sq.wqe_cnt)
1260                 return err;
1261         destroy_raw_packet_qp_sq(dev, sq);
1262 err_destroy_tis:
1263         destroy_raw_packet_qp_tis(dev, sq);
1264
1265         return err;
1266 }
1267
1268 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1269                                   struct mlx5_ib_qp *qp)
1270 {
1271         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1272         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1273         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1274
1275         if (qp->rq.wqe_cnt) {
1276                 destroy_raw_packet_qp_tir(dev, rq);
1277                 destroy_raw_packet_qp_rq(dev, rq);
1278         }
1279
1280         if (qp->sq.wqe_cnt) {
1281                 destroy_raw_packet_qp_sq(dev, sq);
1282                 destroy_raw_packet_qp_tis(dev, sq);
1283         }
1284 }
1285
1286 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1287                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1288 {
1289         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1290         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1291
1292         sq->sq = &qp->sq;
1293         rq->rq = &qp->rq;
1294         sq->doorbell = &qp->db;
1295         rq->doorbell = &qp->db;
1296 }
1297
1298 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1299 {
1300         mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1301 }
1302
1303 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1304                                  struct ib_pd *pd,
1305                                  struct ib_qp_init_attr *init_attr,
1306                                  struct ib_udata *udata)
1307 {
1308         struct ib_uobject *uobj = pd->uobject;
1309         struct ib_ucontext *ucontext = uobj->context;
1310         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1311         struct mlx5_ib_create_qp_resp resp = {};
1312         int inlen;
1313         int err;
1314         u32 *in;
1315         void *tirc;
1316         void *hfso;
1317         u32 selected_fields = 0;
1318         size_t min_resp_len;
1319         u32 tdn = mucontext->tdn;
1320         struct mlx5_ib_create_qp_rss ucmd = {};
1321         size_t required_cmd_sz;
1322
1323         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1324                 return -EOPNOTSUPP;
1325
1326         if (init_attr->create_flags || init_attr->send_cq)
1327                 return -EINVAL;
1328
1329         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1330         if (udata->outlen < min_resp_len)
1331                 return -EINVAL;
1332
1333         required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1334         if (udata->inlen < required_cmd_sz) {
1335                 mlx5_ib_dbg(dev, "invalid inlen\n");
1336                 return -EINVAL;
1337         }
1338
1339         if (udata->inlen > sizeof(ucmd) &&
1340             !ib_is_udata_cleared(udata, sizeof(ucmd),
1341                                  udata->inlen - sizeof(ucmd))) {
1342                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1343                 return -EOPNOTSUPP;
1344         }
1345
1346         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1347                 mlx5_ib_dbg(dev, "copy failed\n");
1348                 return -EFAULT;
1349         }
1350
1351         if (ucmd.comp_mask) {
1352                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1353                 return -EOPNOTSUPP;
1354         }
1355
1356         if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1357                 mlx5_ib_dbg(dev, "invalid reserved\n");
1358                 return -EOPNOTSUPP;
1359         }
1360
1361         err = ib_copy_to_udata(udata, &resp, min_resp_len);
1362         if (err) {
1363                 mlx5_ib_dbg(dev, "copy failed\n");
1364                 return -EINVAL;
1365         }
1366
1367         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1368         in = mlx5_vzalloc(inlen);
1369         if (!in)
1370                 return -ENOMEM;
1371
1372         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1373         MLX5_SET(tirc, tirc, disp_type,
1374                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1375         MLX5_SET(tirc, tirc, indirect_table,
1376                  init_attr->rwq_ind_tbl->ind_tbl_num);
1377         MLX5_SET(tirc, tirc, transport_domain, tdn);
1378
1379         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1380         switch (ucmd.rx_hash_function) {
1381         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1382         {
1383                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1384                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1385
1386                 if (len != ucmd.rx_key_len) {
1387                         err = -EINVAL;
1388                         goto err;
1389                 }
1390
1391                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1392                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1393                 memcpy(rss_key, ucmd.rx_hash_key, len);
1394                 break;
1395         }
1396         default:
1397                 err = -EOPNOTSUPP;
1398                 goto err;
1399         }
1400
1401         if (!ucmd.rx_hash_fields_mask) {
1402                 /* special case when this TIR serves as steering entry without hashing */
1403                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1404                         goto create_tir;
1405                 err = -EINVAL;
1406                 goto err;
1407         }
1408
1409         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1410              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1411              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1412              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1413                 err = -EINVAL;
1414                 goto err;
1415         }
1416
1417         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1418         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1419             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1420                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1421                          MLX5_L3_PROT_TYPE_IPV4);
1422         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1423                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1424                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1425                          MLX5_L3_PROT_TYPE_IPV6);
1426
1427         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1428              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1429              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1430              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1431                 err = -EINVAL;
1432                 goto err;
1433         }
1434
1435         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1436         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1437             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1438                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1439                          MLX5_L4_PROT_TYPE_TCP);
1440         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1441                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1442                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1443                          MLX5_L4_PROT_TYPE_UDP);
1444
1445         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1446             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1447                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1448
1449         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1450             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1451                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1452
1453         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1454             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1455                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1456
1457         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1458             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1459                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1460
1461         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1462
1463 create_tir:
1464         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1465
1466         if (err)
1467                 goto err;
1468
1469         kvfree(in);
1470         /* qpn is reserved for that QP */
1471         qp->trans_qp.base.mqp.qpn = 0;
1472         qp->flags |= MLX5_IB_QP_RSS;
1473         return 0;
1474
1475 err:
1476         kvfree(in);
1477         return err;
1478 }
1479
1480 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1481                             struct ib_qp_init_attr *init_attr,
1482                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1483 {
1484         struct mlx5_ib_resources *devr = &dev->devr;
1485         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1486         struct mlx5_core_dev *mdev = dev->mdev;
1487         struct mlx5_ib_create_qp_resp resp;
1488         struct mlx5_ib_cq *send_cq;
1489         struct mlx5_ib_cq *recv_cq;
1490         unsigned long flags;
1491         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1492         struct mlx5_ib_create_qp ucmd;
1493         struct mlx5_ib_qp_base *base;
1494         void *qpc;
1495         u32 *in;
1496         int err;
1497
1498         base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1499                &qp->raw_packet_qp.rq.base :
1500                &qp->trans_qp.base;
1501
1502         mutex_init(&qp->mutex);
1503         spin_lock_init(&qp->sq.lock);
1504         spin_lock_init(&qp->rq.lock);
1505
1506         if (init_attr->rwq_ind_tbl) {
1507                 if (!udata)
1508                         return -ENOSYS;
1509
1510                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1511                 return err;
1512         }
1513
1514         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1515                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1516                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1517                         return -EINVAL;
1518                 } else {
1519                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1520                 }
1521         }
1522
1523         if (init_attr->create_flags &
1524                         (IB_QP_CREATE_CROSS_CHANNEL |
1525                          IB_QP_CREATE_MANAGED_SEND |
1526                          IB_QP_CREATE_MANAGED_RECV)) {
1527                 if (!MLX5_CAP_GEN(mdev, cd)) {
1528                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1529                         return -EINVAL;
1530                 }
1531                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1532                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1533                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1534                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1535                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1536                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1537         }
1538
1539         if (init_attr->qp_type == IB_QPT_UD &&
1540             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1541                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1542                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1543                         return -EOPNOTSUPP;
1544                 }
1545
1546         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1547                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1548                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1549                         return -EOPNOTSUPP;
1550                 }
1551                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1552                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1553                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1554                         return -EOPNOTSUPP;
1555                 }
1556                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1557         }
1558
1559         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1560                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1561
1562         if (pd && pd->uobject) {
1563                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1564                         mlx5_ib_dbg(dev, "copy failed\n");
1565                         return -EFAULT;
1566                 }
1567
1568                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1569                                         &ucmd, udata->inlen, &uidx);
1570                 if (err)
1571                         return err;
1572
1573                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1574                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1575         } else {
1576                 qp->wq_sig = !!wq_signature;
1577         }
1578
1579         qp->has_rq = qp_has_rq(init_attr);
1580         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1581                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1582         if (err) {
1583                 mlx5_ib_dbg(dev, "err %d\n", err);
1584                 return err;
1585         }
1586
1587         if (pd) {
1588                 if (pd->uobject) {
1589                         __u32 max_wqes =
1590                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1591                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1592                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1593                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1594                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1595                                 return -EINVAL;
1596                         }
1597                         if (ucmd.sq_wqe_count > max_wqes) {
1598                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1599                                             ucmd.sq_wqe_count, max_wqes);
1600                                 return -EINVAL;
1601                         }
1602                         if (init_attr->create_flags &
1603                             mlx5_ib_create_qp_sqpn_qp1()) {
1604                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1605                                 return -EINVAL;
1606                         }
1607                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1608                                              &resp, &inlen, base);
1609                         if (err)
1610                                 mlx5_ib_dbg(dev, "err %d\n", err);
1611                 } else {
1612                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1613                                                base);
1614                         if (err)
1615                                 mlx5_ib_dbg(dev, "err %d\n", err);
1616                 }
1617
1618                 if (err)
1619                         return err;
1620         } else {
1621                 in = mlx5_vzalloc(inlen);
1622                 if (!in)
1623                         return -ENOMEM;
1624
1625                 qp->create_type = MLX5_QP_EMPTY;
1626         }
1627
1628         if (is_sqp(init_attr->qp_type))
1629                 qp->port = init_attr->port_num;
1630
1631         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1632
1633         MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1634         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1635
1636         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1637                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1638         else
1639                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1640
1641
1642         if (qp->wq_sig)
1643                 MLX5_SET(qpc, qpc, wq_signature, 1);
1644
1645         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1646                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1647
1648         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1649                 MLX5_SET(qpc, qpc, cd_master, 1);
1650         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1651                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1652         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1653                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1654
1655         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1656                 int rcqe_sz;
1657                 int scqe_sz;
1658
1659                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1660                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1661
1662                 if (rcqe_sz == 128)
1663                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1664                 else
1665                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1666
1667                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1668                         if (scqe_sz == 128)
1669                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1670                         else
1671                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1672                 }
1673         }
1674
1675         if (qp->rq.wqe_cnt) {
1676                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1677                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1678         }
1679
1680         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1681
1682         if (qp->sq.wqe_cnt)
1683                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1684         else
1685                 MLX5_SET(qpc, qpc, no_sq, 1);
1686
1687         /* Set default resources */
1688         switch (init_attr->qp_type) {
1689         case IB_QPT_XRC_TGT:
1690                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1691                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1692                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1693                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1694                 break;
1695         case IB_QPT_XRC_INI:
1696                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1697                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1698                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1699                 break;
1700         default:
1701                 if (init_attr->srq) {
1702                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1703                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1704                 } else {
1705                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1706                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1707                 }
1708         }
1709
1710         if (init_attr->send_cq)
1711                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1712
1713         if (init_attr->recv_cq)
1714                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1715
1716         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1717
1718         /* 0xffffff means we ask to work with cqe version 0 */
1719         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1720                 MLX5_SET(qpc, qpc, user_index, uidx);
1721
1722         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1723         if (init_attr->qp_type == IB_QPT_UD &&
1724             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1725                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1726                 qp->flags |= MLX5_IB_QP_LSO;
1727         }
1728
1729         if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1730                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1731                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1732                 err = create_raw_packet_qp(dev, qp, in, pd);
1733         } else {
1734                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1735         }
1736
1737         if (err) {
1738                 mlx5_ib_dbg(dev, "create qp failed\n");
1739                 goto err_create;
1740         }
1741
1742         kvfree(in);
1743
1744         base->container_mibqp = qp;
1745         base->mqp.event = mlx5_ib_qp_event;
1746
1747         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1748                 &send_cq, &recv_cq);
1749         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1750         mlx5_ib_lock_cqs(send_cq, recv_cq);
1751         /* Maintain device to QPs access, needed for further handling via reset
1752          * flow
1753          */
1754         list_add_tail(&qp->qps_list, &dev->qp_list);
1755         /* Maintain CQ to QPs access, needed for further handling via reset flow
1756          */
1757         if (send_cq)
1758                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1759         if (recv_cq)
1760                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1761         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1762         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1763
1764         return 0;
1765
1766 err_create:
1767         if (qp->create_type == MLX5_QP_USER)
1768                 destroy_qp_user(dev, pd, qp, base);
1769         else if (qp->create_type == MLX5_QP_KERNEL)
1770                 destroy_qp_kernel(dev, qp);
1771
1772         kvfree(in);
1773         return err;
1774 }
1775
1776 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1777         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1778 {
1779         if (send_cq) {
1780                 if (recv_cq) {
1781                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1782                                 spin_lock(&send_cq->lock);
1783                                 spin_lock_nested(&recv_cq->lock,
1784                                                  SINGLE_DEPTH_NESTING);
1785                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1786                                 spin_lock(&send_cq->lock);
1787                                 __acquire(&recv_cq->lock);
1788                         } else {
1789                                 spin_lock(&recv_cq->lock);
1790                                 spin_lock_nested(&send_cq->lock,
1791                                                  SINGLE_DEPTH_NESTING);
1792                         }
1793                 } else {
1794                         spin_lock(&send_cq->lock);
1795                         __acquire(&recv_cq->lock);
1796                 }
1797         } else if (recv_cq) {
1798                 spin_lock(&recv_cq->lock);
1799                 __acquire(&send_cq->lock);
1800         } else {
1801                 __acquire(&send_cq->lock);
1802                 __acquire(&recv_cq->lock);
1803         }
1804 }
1805
1806 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1807         __releases(&send_cq->lock) __releases(&recv_cq->lock)
1808 {
1809         if (send_cq) {
1810                 if (recv_cq) {
1811                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1812                                 spin_unlock(&recv_cq->lock);
1813                                 spin_unlock(&send_cq->lock);
1814                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1815                                 __release(&recv_cq->lock);
1816                                 spin_unlock(&send_cq->lock);
1817                         } else {
1818                                 spin_unlock(&send_cq->lock);
1819                                 spin_unlock(&recv_cq->lock);
1820                         }
1821                 } else {
1822                         __release(&recv_cq->lock);
1823                         spin_unlock(&send_cq->lock);
1824                 }
1825         } else if (recv_cq) {
1826                 __release(&send_cq->lock);
1827                 spin_unlock(&recv_cq->lock);
1828         } else {
1829                 __release(&recv_cq->lock);
1830                 __release(&send_cq->lock);
1831         }
1832 }
1833
1834 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1835 {
1836         return to_mpd(qp->ibqp.pd);
1837 }
1838
1839 static void get_cqs(enum ib_qp_type qp_type,
1840                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1841                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1842 {
1843         switch (qp_type) {
1844         case IB_QPT_XRC_TGT:
1845                 *send_cq = NULL;
1846                 *recv_cq = NULL;
1847                 break;
1848         case MLX5_IB_QPT_REG_UMR:
1849         case IB_QPT_XRC_INI:
1850                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1851                 *recv_cq = NULL;
1852                 break;
1853
1854         case IB_QPT_SMI:
1855         case MLX5_IB_QPT_HW_GSI:
1856         case IB_QPT_RC:
1857         case IB_QPT_UC:
1858         case IB_QPT_UD:
1859         case IB_QPT_RAW_IPV6:
1860         case IB_QPT_RAW_ETHERTYPE:
1861         case IB_QPT_RAW_PACKET:
1862                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1863                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1864                 break;
1865
1866         case IB_QPT_MAX:
1867         default:
1868                 *send_cq = NULL;
1869                 *recv_cq = NULL;
1870                 break;
1871         }
1872 }
1873
1874 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1875                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1876                                 u8 lag_tx_affinity);
1877
1878 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1879 {
1880         struct mlx5_ib_cq *send_cq, *recv_cq;
1881         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1882         unsigned long flags;
1883         int err;
1884
1885         if (qp->ibqp.rwq_ind_tbl) {
1886                 destroy_rss_raw_qp_tir(dev, qp);
1887                 return;
1888         }
1889
1890         base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1891                &qp->raw_packet_qp.rq.base :
1892                &qp->trans_qp.base;
1893
1894         if (qp->state != IB_QPS_RESET) {
1895                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1896                         err = mlx5_core_qp_modify(dev->mdev,
1897                                                   MLX5_CMD_OP_2RST_QP, 0,
1898                                                   NULL, &base->mqp);
1899                 } else {
1900                         struct mlx5_modify_raw_qp_param raw_qp_param = {
1901                                 .operation = MLX5_CMD_OP_2RST_QP
1902                         };
1903
1904                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1905                 }
1906                 if (err)
1907                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1908                                      base->mqp.qpn);
1909         }
1910
1911         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1912                 &send_cq, &recv_cq);
1913
1914         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1915         mlx5_ib_lock_cqs(send_cq, recv_cq);
1916         /* del from lists under both locks above to protect reset flow paths */
1917         list_del(&qp->qps_list);
1918         if (send_cq)
1919                 list_del(&qp->cq_send_list);
1920
1921         if (recv_cq)
1922                 list_del(&qp->cq_recv_list);
1923
1924         if (qp->create_type == MLX5_QP_KERNEL) {
1925                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1926                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1927                 if (send_cq != recv_cq)
1928                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1929                                            NULL);
1930         }
1931         mlx5_ib_unlock_cqs(send_cq, recv_cq);
1932         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1933
1934         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1935                 destroy_raw_packet_qp(dev, qp);
1936         } else {
1937                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1938                 if (err)
1939                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1940                                      base->mqp.qpn);
1941         }
1942
1943         if (qp->create_type == MLX5_QP_KERNEL)
1944                 destroy_qp_kernel(dev, qp);
1945         else if (qp->create_type == MLX5_QP_USER)
1946                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
1947 }
1948
1949 static const char *ib_qp_type_str(enum ib_qp_type type)
1950 {
1951         switch (type) {
1952         case IB_QPT_SMI:
1953                 return "IB_QPT_SMI";
1954         case IB_QPT_GSI:
1955                 return "IB_QPT_GSI";
1956         case IB_QPT_RC:
1957                 return "IB_QPT_RC";
1958         case IB_QPT_UC:
1959                 return "IB_QPT_UC";
1960         case IB_QPT_UD:
1961                 return "IB_QPT_UD";
1962         case IB_QPT_RAW_IPV6:
1963                 return "IB_QPT_RAW_IPV6";
1964         case IB_QPT_RAW_ETHERTYPE:
1965                 return "IB_QPT_RAW_ETHERTYPE";
1966         case IB_QPT_XRC_INI:
1967                 return "IB_QPT_XRC_INI";
1968         case IB_QPT_XRC_TGT:
1969                 return "IB_QPT_XRC_TGT";
1970         case IB_QPT_RAW_PACKET:
1971                 return "IB_QPT_RAW_PACKET";
1972         case MLX5_IB_QPT_REG_UMR:
1973                 return "MLX5_IB_QPT_REG_UMR";
1974         case IB_QPT_MAX:
1975         default:
1976                 return "Invalid QP type";
1977         }
1978 }
1979
1980 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1981                                 struct ib_qp_init_attr *init_attr,
1982                                 struct ib_udata *udata)
1983 {
1984         struct mlx5_ib_dev *dev;
1985         struct mlx5_ib_qp *qp;
1986         u16 xrcdn = 0;
1987         int err;
1988
1989         if (pd) {
1990                 dev = to_mdev(pd->device);
1991
1992                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1993                         if (!pd->uobject) {
1994                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1995                                 return ERR_PTR(-EINVAL);
1996                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1997                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1998                                 return ERR_PTR(-EINVAL);
1999                         }
2000                 }
2001         } else {
2002                 /* being cautious here */
2003                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2004                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2005                         pr_warn("%s: no PD for transport %s\n", __func__,
2006                                 ib_qp_type_str(init_attr->qp_type));
2007                         return ERR_PTR(-EINVAL);
2008                 }
2009                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2010         }
2011
2012         switch (init_attr->qp_type) {
2013         case IB_QPT_XRC_TGT:
2014         case IB_QPT_XRC_INI:
2015                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2016                         mlx5_ib_dbg(dev, "XRC not supported\n");
2017                         return ERR_PTR(-ENOSYS);
2018                 }
2019                 init_attr->recv_cq = NULL;
2020                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2021                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2022                         init_attr->send_cq = NULL;
2023                 }
2024
2025                 /* fall through */
2026         case IB_QPT_RAW_PACKET:
2027         case IB_QPT_RC:
2028         case IB_QPT_UC:
2029         case IB_QPT_UD:
2030         case IB_QPT_SMI:
2031         case MLX5_IB_QPT_HW_GSI:
2032         case MLX5_IB_QPT_REG_UMR:
2033                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2034                 if (!qp)
2035                         return ERR_PTR(-ENOMEM);
2036
2037                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2038                 if (err) {
2039                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2040                         kfree(qp);
2041                         return ERR_PTR(err);
2042                 }
2043
2044                 if (is_qp0(init_attr->qp_type))
2045                         qp->ibqp.qp_num = 0;
2046                 else if (is_qp1(init_attr->qp_type))
2047                         qp->ibqp.qp_num = 1;
2048                 else
2049                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2050
2051                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2052                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2053                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2054                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2055
2056                 qp->trans_qp.xrcdn = xrcdn;
2057
2058                 break;
2059
2060         case IB_QPT_GSI:
2061                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2062
2063         case IB_QPT_RAW_IPV6:
2064         case IB_QPT_RAW_ETHERTYPE:
2065         case IB_QPT_MAX:
2066         default:
2067                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2068                             init_attr->qp_type);
2069                 /* Don't support raw QPs */
2070                 return ERR_PTR(-EINVAL);
2071         }
2072
2073         return &qp->ibqp;
2074 }
2075
2076 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2077 {
2078         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2079         struct mlx5_ib_qp *mqp = to_mqp(qp);
2080
2081         if (unlikely(qp->qp_type == IB_QPT_GSI))
2082                 return mlx5_ib_gsi_destroy_qp(qp);
2083
2084         destroy_qp_common(dev, mqp);
2085
2086         kfree(mqp);
2087
2088         return 0;
2089 }
2090
2091 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2092                                    int attr_mask)
2093 {
2094         u32 hw_access_flags = 0;
2095         u8 dest_rd_atomic;
2096         u32 access_flags;
2097
2098         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2099                 dest_rd_atomic = attr->max_dest_rd_atomic;
2100         else
2101                 dest_rd_atomic = qp->trans_qp.resp_depth;
2102
2103         if (attr_mask & IB_QP_ACCESS_FLAGS)
2104                 access_flags = attr->qp_access_flags;
2105         else
2106                 access_flags = qp->trans_qp.atomic_rd_en;
2107
2108         if (!dest_rd_atomic)
2109                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2110
2111         if (access_flags & IB_ACCESS_REMOTE_READ)
2112                 hw_access_flags |= MLX5_QP_BIT_RRE;
2113         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2114                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2115         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2116                 hw_access_flags |= MLX5_QP_BIT_RWE;
2117
2118         return cpu_to_be32(hw_access_flags);
2119 }
2120
2121 enum {
2122         MLX5_PATH_FLAG_FL       = 1 << 0,
2123         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2124         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2125 };
2126
2127 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2128 {
2129         if (rate == IB_RATE_PORT_CURRENT) {
2130                 return 0;
2131         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2132                 return -EINVAL;
2133         } else {
2134                 while (rate != IB_RATE_2_5_GBPS &&
2135                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2136                          MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2137                         --rate;
2138         }
2139
2140         return rate + MLX5_STAT_RATE_OFFSET;
2141 }
2142
2143 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2144                                       struct mlx5_ib_sq *sq, u8 sl)
2145 {
2146         void *in;
2147         void *tisc;
2148         int inlen;
2149         int err;
2150
2151         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2152         in = mlx5_vzalloc(inlen);
2153         if (!in)
2154                 return -ENOMEM;
2155
2156         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2157
2158         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2159         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2160
2161         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2162
2163         kvfree(in);
2164
2165         return err;
2166 }
2167
2168 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2169                                          struct mlx5_ib_sq *sq, u8 tx_affinity)
2170 {
2171         void *in;
2172         void *tisc;
2173         int inlen;
2174         int err;
2175
2176         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2177         in = mlx5_vzalloc(inlen);
2178         if (!in)
2179                 return -ENOMEM;
2180
2181         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2182
2183         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2184         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2185
2186         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2187
2188         kvfree(in);
2189
2190         return err;
2191 }
2192
2193 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2194                          const struct ib_ah_attr *ah,
2195                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2196                          u32 path_flags, const struct ib_qp_attr *attr,
2197                          bool alt)
2198 {
2199         enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2200         int err;
2201
2202         if (attr_mask & IB_QP_PKEY_INDEX)
2203                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2204                                                      attr->pkey_index);
2205
2206         if (ah->ah_flags & IB_AH_GRH) {
2207                 if (ah->grh.sgid_index >=
2208                     dev->mdev->port_caps[port - 1].gid_table_len) {
2209                         pr_err("sgid_index (%u) too large. max is %d\n",
2210                                ah->grh.sgid_index,
2211                                dev->mdev->port_caps[port - 1].gid_table_len);
2212                         return -EINVAL;
2213                 }
2214         }
2215
2216         if (ll == IB_LINK_LAYER_ETHERNET) {
2217                 if (!(ah->ah_flags & IB_AH_GRH))
2218                         return -EINVAL;
2219                 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2220                 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2221                                                           ah->grh.sgid_index);
2222                 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2223         } else {
2224                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2225                 path->fl_free_ar |=
2226                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2227                 path->rlid = cpu_to_be16(ah->dlid);
2228                 path->grh_mlid = ah->src_path_bits & 0x7f;
2229                 if (ah->ah_flags & IB_AH_GRH)
2230                         path->grh_mlid  |= 1 << 7;
2231                 path->dci_cfi_prio_sl = ah->sl & 0xf;
2232         }
2233
2234         if (ah->ah_flags & IB_AH_GRH) {
2235                 path->mgid_index = ah->grh.sgid_index;
2236                 path->hop_limit  = ah->grh.hop_limit;
2237                 path->tclass_flowlabel =
2238                         cpu_to_be32((ah->grh.traffic_class << 20) |
2239                                     (ah->grh.flow_label));
2240                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2241         }
2242
2243         err = ib_rate_to_mlx5(dev, ah->static_rate);
2244         if (err < 0)
2245                 return err;
2246         path->static_rate = err;
2247         path->port = port;
2248
2249         if (attr_mask & IB_QP_TIMEOUT)
2250                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2251
2252         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2253                 return modify_raw_packet_eth_prio(dev->mdev,
2254                                                   &qp->raw_packet_qp.sq,
2255                                                   ah->sl & 0xf);
2256
2257         return 0;
2258 }
2259
2260 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2261         [MLX5_QP_STATE_INIT] = {
2262                 [MLX5_QP_STATE_INIT] = {
2263                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2264                                           MLX5_QP_OPTPAR_RAE            |
2265                                           MLX5_QP_OPTPAR_RWE            |
2266                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2267                                           MLX5_QP_OPTPAR_PRI_PORT,
2268                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2269                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2270                                           MLX5_QP_OPTPAR_PRI_PORT,
2271                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2272                                           MLX5_QP_OPTPAR_Q_KEY          |
2273                                           MLX5_QP_OPTPAR_PRI_PORT,
2274                 },
2275                 [MLX5_QP_STATE_RTR] = {
2276                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2277                                           MLX5_QP_OPTPAR_RRE            |
2278                                           MLX5_QP_OPTPAR_RAE            |
2279                                           MLX5_QP_OPTPAR_RWE            |
2280                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2281                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2282                                           MLX5_QP_OPTPAR_RWE            |
2283                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2284                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2285                                           MLX5_QP_OPTPAR_Q_KEY,
2286                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2287                                            MLX5_QP_OPTPAR_Q_KEY,
2288                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2289                                           MLX5_QP_OPTPAR_RRE            |
2290                                           MLX5_QP_OPTPAR_RAE            |
2291                                           MLX5_QP_OPTPAR_RWE            |
2292                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2293                 },
2294         },
2295         [MLX5_QP_STATE_RTR] = {
2296                 [MLX5_QP_STATE_RTS] = {
2297                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2298                                           MLX5_QP_OPTPAR_RRE            |
2299                                           MLX5_QP_OPTPAR_RAE            |
2300                                           MLX5_QP_OPTPAR_RWE            |
2301                                           MLX5_QP_OPTPAR_PM_STATE       |
2302                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2303                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2304                                           MLX5_QP_OPTPAR_RWE            |
2305                                           MLX5_QP_OPTPAR_PM_STATE,
2306                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2307                 },
2308         },
2309         [MLX5_QP_STATE_RTS] = {
2310                 [MLX5_QP_STATE_RTS] = {
2311                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2312                                           MLX5_QP_OPTPAR_RAE            |
2313                                           MLX5_QP_OPTPAR_RWE            |
2314                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2315                                           MLX5_QP_OPTPAR_PM_STATE       |
2316                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2317                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2318                                           MLX5_QP_OPTPAR_PM_STATE       |
2319                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2320                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2321                                           MLX5_QP_OPTPAR_SRQN           |
2322                                           MLX5_QP_OPTPAR_CQN_RCV,
2323                 },
2324         },
2325         [MLX5_QP_STATE_SQER] = {
2326                 [MLX5_QP_STATE_RTS] = {
2327                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2328                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2329                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2330                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2331                                            MLX5_QP_OPTPAR_RWE           |
2332                                            MLX5_QP_OPTPAR_RAE           |
2333                                            MLX5_QP_OPTPAR_RRE,
2334                 },
2335         },
2336 };
2337
2338 static int ib_nr_to_mlx5_nr(int ib_mask)
2339 {
2340         switch (ib_mask) {
2341         case IB_QP_STATE:
2342                 return 0;
2343         case IB_QP_CUR_STATE:
2344                 return 0;
2345         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2346                 return 0;
2347         case IB_QP_ACCESS_FLAGS:
2348                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2349                         MLX5_QP_OPTPAR_RAE;
2350         case IB_QP_PKEY_INDEX:
2351                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2352         case IB_QP_PORT:
2353                 return MLX5_QP_OPTPAR_PRI_PORT;
2354         case IB_QP_QKEY:
2355                 return MLX5_QP_OPTPAR_Q_KEY;
2356         case IB_QP_AV:
2357                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2358                         MLX5_QP_OPTPAR_PRI_PORT;
2359         case IB_QP_PATH_MTU:
2360                 return 0;
2361         case IB_QP_TIMEOUT:
2362                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2363         case IB_QP_RETRY_CNT:
2364                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2365         case IB_QP_RNR_RETRY:
2366                 return MLX5_QP_OPTPAR_RNR_RETRY;
2367         case IB_QP_RQ_PSN:
2368                 return 0;
2369         case IB_QP_MAX_QP_RD_ATOMIC:
2370                 return MLX5_QP_OPTPAR_SRA_MAX;
2371         case IB_QP_ALT_PATH:
2372                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2373         case IB_QP_MIN_RNR_TIMER:
2374                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2375         case IB_QP_SQ_PSN:
2376                 return 0;
2377         case IB_QP_MAX_DEST_RD_ATOMIC:
2378                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2379                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2380         case IB_QP_PATH_MIG_STATE:
2381                 return MLX5_QP_OPTPAR_PM_STATE;
2382         case IB_QP_CAP:
2383                 return 0;
2384         case IB_QP_DEST_QPN:
2385                 return 0;
2386         }
2387         return 0;
2388 }
2389
2390 static int ib_mask_to_mlx5_opt(int ib_mask)
2391 {
2392         int result = 0;
2393         int i;
2394
2395         for (i = 0; i < 8 * sizeof(int); i++) {
2396                 if ((1 << i) & ib_mask)
2397                         result |= ib_nr_to_mlx5_nr(1 << i);
2398         }
2399
2400         return result;
2401 }
2402
2403 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2404                                    struct mlx5_ib_rq *rq, int new_state,
2405                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2406 {
2407         void *in;
2408         void *rqc;
2409         int inlen;
2410         int err;
2411
2412         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2413         in = mlx5_vzalloc(inlen);
2414         if (!in)
2415                 return -ENOMEM;
2416
2417         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2418
2419         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2420         MLX5_SET(rqc, rqc, state, new_state);
2421
2422         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2423                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2424                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2425                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2426                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2427                 } else
2428                         pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2429                                      dev->ib_dev.name);
2430         }
2431
2432         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2433         if (err)
2434                 goto out;
2435
2436         rq->state = new_state;
2437
2438 out:
2439         kvfree(in);
2440         return err;
2441 }
2442
2443 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2444                                    struct mlx5_ib_sq *sq,
2445                                    int new_state,
2446                                    const struct mlx5_modify_raw_qp_param *raw_qp_param)
2447 {
2448         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2449         u32 old_rate = ibqp->rate_limit;
2450         u32 new_rate = old_rate;
2451         u16 rl_index = 0;
2452         void *in;
2453         void *sqc;
2454         int inlen;
2455         int err;
2456
2457         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2458         in = mlx5_vzalloc(inlen);
2459         if (!in)
2460                 return -ENOMEM;
2461
2462         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2463
2464         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2465         MLX5_SET(sqc, sqc, state, new_state);
2466
2467         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2468                 if (new_state != MLX5_SQC_STATE_RDY)
2469                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2470                                 __func__);
2471                 else
2472                         new_rate = raw_qp_param->rate_limit;
2473         }
2474
2475         if (old_rate != new_rate) {
2476                 if (new_rate) {
2477                         err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2478                         if (err) {
2479                                 pr_err("Failed configuring rate %u: %d\n",
2480                                        new_rate, err);
2481                                 goto out;
2482                         }
2483                 }
2484
2485                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2486                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2487         }
2488
2489         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2490         if (err) {
2491                 /* Remove new rate from table if failed */
2492                 if (new_rate &&
2493                     old_rate != new_rate)
2494                         mlx5_rl_remove_rate(dev, new_rate);
2495                 goto out;
2496         }
2497
2498         /* Only remove the old rate after new rate was set */
2499         if ((old_rate &&
2500             (old_rate != new_rate)) ||
2501             (new_state != MLX5_SQC_STATE_RDY))
2502                 mlx5_rl_remove_rate(dev, old_rate);
2503
2504         ibqp->rate_limit = new_rate;
2505         sq->state = new_state;
2506
2507 out:
2508         kvfree(in);
2509         return err;
2510 }
2511
2512 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2513                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2514                                 u8 tx_affinity)
2515 {
2516         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2517         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2518         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2519         int modify_rq = !!qp->rq.wqe_cnt;
2520         int modify_sq = !!qp->sq.wqe_cnt;
2521         int rq_state;
2522         int sq_state;
2523         int err;
2524
2525         switch (raw_qp_param->operation) {
2526         case MLX5_CMD_OP_RST2INIT_QP:
2527                 rq_state = MLX5_RQC_STATE_RDY;
2528                 sq_state = MLX5_SQC_STATE_RDY;
2529                 break;
2530         case MLX5_CMD_OP_2ERR_QP:
2531                 rq_state = MLX5_RQC_STATE_ERR;
2532                 sq_state = MLX5_SQC_STATE_ERR;
2533                 break;
2534         case MLX5_CMD_OP_2RST_QP:
2535                 rq_state = MLX5_RQC_STATE_RST;
2536                 sq_state = MLX5_SQC_STATE_RST;
2537                 break;
2538         case MLX5_CMD_OP_RTR2RTS_QP:
2539         case MLX5_CMD_OP_RTS2RTS_QP:
2540                 if (raw_qp_param->set_mask ==
2541                     MLX5_RAW_QP_RATE_LIMIT) {
2542                         modify_rq = 0;
2543                         sq_state = sq->state;
2544                 } else {
2545                         return raw_qp_param->set_mask ? -EINVAL : 0;
2546                 }
2547                 break;
2548         case MLX5_CMD_OP_INIT2INIT_QP:
2549         case MLX5_CMD_OP_INIT2RTR_QP:
2550                 if (raw_qp_param->set_mask)
2551                         return -EINVAL;
2552                 else
2553                         return 0;
2554         default:
2555                 WARN_ON(1);
2556                 return -EINVAL;
2557         }
2558
2559         if (modify_rq) {
2560                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2561                 if (err)
2562                         return err;
2563         }
2564
2565         if (modify_sq) {
2566                 if (tx_affinity) {
2567                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2568                                                             tx_affinity);
2569                         if (err)
2570                                 return err;
2571                 }
2572
2573                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2574         }
2575
2576         return 0;
2577 }
2578
2579 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2580                                const struct ib_qp_attr *attr, int attr_mask,
2581                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
2582 {
2583         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2584                 [MLX5_QP_STATE_RST] = {
2585                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2586                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2587                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
2588                 },
2589                 [MLX5_QP_STATE_INIT]  = {
2590                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2591                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2592                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
2593                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
2594                 },
2595                 [MLX5_QP_STATE_RTR]   = {
2596                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2597                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2598                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
2599                 },
2600                 [MLX5_QP_STATE_RTS]   = {
2601                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2602                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2603                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
2604                 },
2605                 [MLX5_QP_STATE_SQD] = {
2606                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2607                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2608                 },
2609                 [MLX5_QP_STATE_SQER] = {
2610                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2611                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2612                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
2613                 },
2614                 [MLX5_QP_STATE_ERR] = {
2615                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
2616                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
2617                 }
2618         };
2619
2620         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2621         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2622         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2623         struct mlx5_ib_cq *send_cq, *recv_cq;
2624         struct mlx5_qp_context *context;
2625         struct mlx5_ib_pd *pd;
2626         struct mlx5_ib_port *mibport = NULL;
2627         enum mlx5_qp_state mlx5_cur, mlx5_new;
2628         enum mlx5_qp_optpar optpar;
2629         int mlx5_st;
2630         int err;
2631         u16 op;
2632         u8 tx_affinity = 0;
2633
2634         context = kzalloc(sizeof(*context), GFP_KERNEL);
2635         if (!context)
2636                 return -ENOMEM;
2637
2638         err = to_mlx5_st(ibqp->qp_type);
2639         if (err < 0) {
2640                 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2641                 goto out;
2642         }
2643
2644         context->flags = cpu_to_be32(err << 16);
2645
2646         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2647                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2648         } else {
2649                 switch (attr->path_mig_state) {
2650                 case IB_MIG_MIGRATED:
2651                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2652                         break;
2653                 case IB_MIG_REARM:
2654                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2655                         break;
2656                 case IB_MIG_ARMED:
2657                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2658                         break;
2659                 }
2660         }
2661
2662         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2663                 if ((ibqp->qp_type == IB_QPT_RC) ||
2664                     (ibqp->qp_type == IB_QPT_UD &&
2665                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2666                     (ibqp->qp_type == IB_QPT_UC) ||
2667                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2668                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
2669                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2670                         if (mlx5_lag_is_active(dev->mdev)) {
2671                                 tx_affinity = (unsigned int)atomic_add_return(1,
2672                                                 &dev->roce.next_port) %
2673                                                 MLX5_MAX_PORTS + 1;
2674                                 context->flags |= cpu_to_be32(tx_affinity << 24);
2675                         }
2676                 }
2677         }
2678
2679         if (is_sqp(ibqp->qp_type)) {
2680                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2681         } else if (ibqp->qp_type == IB_QPT_UD ||
2682                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2683                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2684         } else if (attr_mask & IB_QP_PATH_MTU) {
2685                 if (attr->path_mtu < IB_MTU_256 ||
2686                     attr->path_mtu > IB_MTU_4096) {
2687                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2688                         err = -EINVAL;
2689                         goto out;
2690                 }
2691                 context->mtu_msgmax = (attr->path_mtu << 5) |
2692                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2693         }
2694
2695         if (attr_mask & IB_QP_DEST_QPN)
2696                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2697
2698         if (attr_mask & IB_QP_PKEY_INDEX)
2699                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2700
2701         /* todo implement counter_index functionality */
2702
2703         if (is_sqp(ibqp->qp_type))
2704                 context->pri_path.port = qp->port;
2705
2706         if (attr_mask & IB_QP_PORT)
2707                 context->pri_path.port = attr->port_num;
2708
2709         if (attr_mask & IB_QP_AV) {
2710                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2711                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2712                                     attr_mask, 0, attr, false);
2713                 if (err)
2714                         goto out;
2715         }
2716
2717         if (attr_mask & IB_QP_TIMEOUT)
2718                 context->pri_path.ackto_lt |= attr->timeout << 3;
2719
2720         if (attr_mask & IB_QP_ALT_PATH) {
2721                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2722                                     &context->alt_path,
2723                                     attr->alt_port_num,
2724                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2725                                     0, attr, true);
2726                 if (err)
2727                         goto out;
2728         }
2729
2730         pd = get_pd(qp);
2731         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2732                 &send_cq, &recv_cq);
2733
2734         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2735         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2736         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2737         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2738
2739         if (attr_mask & IB_QP_RNR_RETRY)
2740                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2741
2742         if (attr_mask & IB_QP_RETRY_CNT)
2743                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2744
2745         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2746                 if (attr->max_rd_atomic)
2747                         context->params1 |=
2748                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2749         }
2750
2751         if (attr_mask & IB_QP_SQ_PSN)
2752                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2753
2754         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2755                 if (attr->max_dest_rd_atomic)
2756                         context->params2 |=
2757                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2758         }
2759
2760         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2761                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2762
2763         if (attr_mask & IB_QP_MIN_RNR_TIMER)
2764                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2765
2766         if (attr_mask & IB_QP_RQ_PSN)
2767                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2768
2769         if (attr_mask & IB_QP_QKEY)
2770                 context->qkey = cpu_to_be32(attr->qkey);
2771
2772         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2773                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2774
2775         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2776                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2777                                qp->port) - 1;
2778                 mibport = &dev->port[port_num];
2779                 context->qp_counter_set_usr_page |=
2780                         cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2781         }
2782
2783         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2784                 context->sq_crq_size |= cpu_to_be16(1 << 4);
2785
2786         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2787                 context->deth_sqpn = cpu_to_be32(1);
2788
2789         mlx5_cur = to_mlx5_state(cur_state);
2790         mlx5_new = to_mlx5_state(new_state);
2791         mlx5_st = to_mlx5_st(ibqp->qp_type);
2792         if (mlx5_st < 0)
2793                 goto out;
2794
2795         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2796             !optab[mlx5_cur][mlx5_new])
2797                 goto out;
2798
2799         op = optab[mlx5_cur][mlx5_new];
2800         optpar = ib_mask_to_mlx5_opt(attr_mask);
2801         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2802
2803         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2804                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2805
2806                 raw_qp_param.operation = op;
2807                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2808                         raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2809                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2810                 }
2811
2812                 if (attr_mask & IB_QP_RATE_LIMIT) {
2813                         raw_qp_param.rate_limit = attr->rate_limit;
2814                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2815                 }
2816
2817                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2818         } else {
2819                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2820                                           &base->mqp);
2821         }
2822
2823         if (err)
2824                 goto out;
2825
2826         qp->state = new_state;
2827
2828         if (attr_mask & IB_QP_ACCESS_FLAGS)
2829                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2830         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2831                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2832         if (attr_mask & IB_QP_PORT)
2833                 qp->port = attr->port_num;
2834         if (attr_mask & IB_QP_ALT_PATH)
2835                 qp->trans_qp.alt_port = attr->alt_port_num;
2836
2837         /*
2838          * If we moved a kernel QP to RESET, clean up all old CQ
2839          * entries and reinitialize the QP.
2840          */
2841         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2842                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2843                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2844                 if (send_cq != recv_cq)
2845                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2846
2847                 qp->rq.head = 0;
2848                 qp->rq.tail = 0;
2849                 qp->sq.head = 0;
2850                 qp->sq.tail = 0;
2851                 qp->sq.cur_post = 0;
2852                 qp->sq.last_poll = 0;
2853                 qp->db.db[MLX5_RCV_DBR] = 0;
2854                 qp->db.db[MLX5_SND_DBR] = 0;
2855         }
2856
2857 out:
2858         kfree(context);
2859         return err;
2860 }
2861
2862 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2863                       int attr_mask, struct ib_udata *udata)
2864 {
2865         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2866         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2867         enum ib_qp_type qp_type;
2868         enum ib_qp_state cur_state, new_state;
2869         int err = -EINVAL;
2870         int port;
2871         enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2872
2873         if (ibqp->rwq_ind_tbl)
2874                 return -ENOSYS;
2875
2876         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2877                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2878
2879         qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2880                 IB_QPT_GSI : ibqp->qp_type;
2881
2882         mutex_lock(&qp->mutex);
2883
2884         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2885         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2886
2887         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2888                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2889                 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2890         }
2891
2892         if (qp_type != MLX5_IB_QPT_REG_UMR &&
2893             !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2894                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2895                             cur_state, new_state, ibqp->qp_type, attr_mask);
2896                 goto out;
2897         }
2898
2899         if ((attr_mask & IB_QP_PORT) &&
2900             (attr->port_num == 0 ||
2901              attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2902                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2903                             attr->port_num, dev->num_ports);
2904                 goto out;
2905         }
2906
2907         if (attr_mask & IB_QP_PKEY_INDEX) {
2908                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2909                 if (attr->pkey_index >=
2910                     dev->mdev->port_caps[port - 1].pkey_table_len) {
2911                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2912                                     attr->pkey_index);
2913                         goto out;
2914                 }
2915         }
2916
2917         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2918             attr->max_rd_atomic >
2919             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2920                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2921                             attr->max_rd_atomic);
2922                 goto out;
2923         }
2924
2925         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2926             attr->max_dest_rd_atomic >
2927             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2928                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2929                             attr->max_dest_rd_atomic);
2930                 goto out;
2931         }
2932
2933         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2934                 err = 0;
2935                 goto out;
2936         }
2937
2938         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2939
2940 out:
2941         mutex_unlock(&qp->mutex);
2942         return err;
2943 }
2944
2945 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2946 {
2947         struct mlx5_ib_cq *cq;
2948         unsigned cur;
2949
2950         cur = wq->head - wq->tail;
2951         if (likely(cur + nreq < wq->max_post))
2952                 return 0;
2953
2954         cq = to_mcq(ib_cq);
2955         spin_lock(&cq->lock);
2956         cur = wq->head - wq->tail;
2957         spin_unlock(&cq->lock);
2958
2959         return cur + nreq >= wq->max_post;
2960 }
2961
2962 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2963                                           u64 remote_addr, u32 rkey)
2964 {
2965         rseg->raddr    = cpu_to_be64(remote_addr);
2966         rseg->rkey     = cpu_to_be32(rkey);
2967         rseg->reserved = 0;
2968 }
2969
2970 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2971                          struct ib_send_wr *wr, void *qend,
2972                          struct mlx5_ib_qp *qp, int *size)
2973 {
2974         void *seg = eseg;
2975
2976         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2977
2978         if (wr->send_flags & IB_SEND_IP_CSUM)
2979                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2980                                  MLX5_ETH_WQE_L4_CSUM;
2981
2982         seg += sizeof(struct mlx5_wqe_eth_seg);
2983         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2984
2985         if (wr->opcode == IB_WR_LSO) {
2986                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2987                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2988                 u64 left, leftlen, copysz;
2989                 void *pdata = ud_wr->header;
2990
2991                 left = ud_wr->hlen;
2992                 eseg->mss = cpu_to_be16(ud_wr->mss);
2993                 eseg->inline_hdr_sz = cpu_to_be16(left);
2994
2995                 /*
2996                  * check if there is space till the end of queue, if yes,
2997                  * copy all in one shot, otherwise copy till the end of queue,
2998                  * rollback and than the copy the left
2999                  */
3000                 leftlen = qend - (void *)eseg->inline_hdr_start;
3001                 copysz = min_t(u64, leftlen, left);
3002
3003                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3004
3005                 if (likely(copysz > size_of_inl_hdr_start)) {
3006                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3007                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3008                 }
3009
3010                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3011                         seg = mlx5_get_send_wqe(qp, 0);
3012                         left -= copysz;
3013                         pdata += copysz;
3014                         memcpy(seg, pdata, left);
3015                         seg += ALIGN(left, 16);
3016                         *size += ALIGN(left, 16) / 16;
3017                 }
3018         }
3019
3020         return seg;
3021 }
3022
3023 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3024                              struct ib_send_wr *wr)
3025 {
3026         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3027         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3028         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3029 }
3030
3031 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3032 {
3033         dseg->byte_count = cpu_to_be32(sg->length);
3034         dseg->lkey       = cpu_to_be32(sg->lkey);
3035         dseg->addr       = cpu_to_be64(sg->addr);
3036 }
3037
3038 static u64 get_xlt_octo(u64 bytes)
3039 {
3040         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3041                MLX5_IB_UMR_OCTOWORD;
3042 }
3043
3044 static __be64 frwr_mkey_mask(void)
3045 {
3046         u64 result;
3047
3048         result = MLX5_MKEY_MASK_LEN             |
3049                 MLX5_MKEY_MASK_PAGE_SIZE        |
3050