drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <rdma/rdma_counter.h>
  38 #include <linux/mlx5/fs.h>
  39 #include "mlx5_ib.h"
  40 #include "ib_rep.h"
  41 #include "cmd.h"
  42
  43 /* not supported currently */
  44 static int wq_signature;
  45
  46 enum {
  47         MLX5_IB_ACK_REQ_FREQ    = 8,
  48 };
  49
  50 enum {
  51         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  52         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  53         MLX5_IB_LINK_TYPE_IB            = 0,
  54         MLX5_IB_LINK_TYPE_ETH           = 1
  55 };
  56
  57 enum {
  58         MLX5_IB_SQ_STRIDE       = 6,
  59         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  60 };
  61
  62 static const u32 mlx5_ib_opcode[] = {
  63         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  64         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  65         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  66         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  67         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  68         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  69         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  70         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  71         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  72         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  73         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  74         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  75         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  76         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  77 };
  78
  79 struct mlx5_wqe_eth_pad {
  80         u8 rsvd0[16];
  81 };
  82
  83 enum raw_qp_set_mask_map {
  84         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  85         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  86 };
  87
  88 struct mlx5_modify_raw_qp_param {
  89         u16 operation;
  90
  91         u32 set_mask; /* raw_qp_set_mask_map */
  92
  93         struct mlx5_rate_limit rl;
  94
  95         u8 rq_q_ctr_id;
  96         u16 port;
  97 };
  98
  99 static void get_cqs(enum ib_qp_type qp_type,
 100                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
 101                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 102
 103 static int is_qp0(enum ib_qp_type qp_type)
 104 {
 105         return qp_type == IB_QPT_SMI;
 106 }
 107
 108 static int is_sqp(enum ib_qp_type qp_type)
 109 {
 110         return is_qp0(qp_type) || is_qp1(qp_type);
 111 }
 112
 113 /**
 114  * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
 115  * to kernel buffer
 116  *
 117  * @umem: User space memory where the WQ is
 118  * @buffer: buffer to copy to
 119  * @buflen: buffer length
 120  * @wqe_index: index of WQE to copy from
 121  * @wq_offset: offset to start of WQ
 122  * @wq_wqe_cnt: number of WQEs in WQ
 123  * @wq_wqe_shift: log2 of WQE size
 124  * @bcnt: number of bytes to copy
 125  * @bytes_copied: number of bytes to copy (return value)
 126  *
 127  * Copies from start of WQE bcnt or less bytes.
 128  * Does not gurantee to copy the entire WQE.
 129  *
 130  * Return: zero on success, or an error code.
 131  */
 132 static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem,
 133                                         void *buffer,
 134                                         u32 buflen,
 135                                         int wqe_index,
 136                                         int wq_offset,
 137                                         int wq_wqe_cnt,
 138                                         int wq_wqe_shift,
 139                                         int bcnt,
 140                                         size_t *bytes_copied)
 141 {
 142         size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
 143         size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
 144         size_t copy_length;
 145         int ret;
 146
 147         /* don't copy more than requested, more than buffer length or
 148          * beyond WQ end
 149          */
 150         copy_length = min_t(u32, buflen, wq_end - offset);
 151         copy_length = min_t(u32, copy_length, bcnt);
 152
 153         ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
 154         if (ret)
 155                 return ret;
 156
 157         if (!ret && bytes_copied)
 158                 *bytes_copied = copy_length;
 159
 160         return 0;
 161 }
 162
 163 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp,
 164                              int wqe_index,
 165                              void *buffer,
 166                              int buflen,
 167                              size_t *bc)
 168 {
 169         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 170         struct ib_umem *umem = base->ubuffer.umem;
 171         struct mlx5_ib_wq *wq = &qp->sq;
 172         struct mlx5_wqe_ctrl_seg *ctrl;
 173         size_t bytes_copied;
 174         size_t bytes_copied2;
 175         size_t wqe_length;
 176         int ret;
 177         int ds;
 178
 179         if (buflen < sizeof(*ctrl))
 180                 return -EINVAL;
 181
 182         /* at first read as much as possible */
 183         ret = mlx5_ib_read_user_wqe_common(umem,
 184                                            buffer,
 185                                            buflen,
 186                                            wqe_index,
 187                                            wq->offset,
 188                                            wq->wqe_cnt,
 189                                            wq->wqe_shift,
 190                                            buflen,
 191                                            &bytes_copied);
 192         if (ret)
 193                 return ret;
 194
 195         /* we need at least control segment size to proceed */
 196         if (bytes_copied < sizeof(*ctrl))
 197                 return -EINVAL;
 198
 199         ctrl = buffer;
 200         ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 201         wqe_length = ds * MLX5_WQE_DS_UNITS;
 202
 203         /* if we copied enough then we are done */
 204         if (bytes_copied >= wqe_length) {
 205                 *bc = bytes_copied;
 206                 return 0;
 207         }
 208
 209         /* otherwise this a wrapped around wqe
 210          * so read the remaining bytes starting
 211          * from  wqe_index 0
 212          */
 213         ret = mlx5_ib_read_user_wqe_common(umem,
 214                                            buffer + bytes_copied,
 215                                            buflen - bytes_copied,
 216                                            0,
 217                                            wq->offset,
 218                                            wq->wqe_cnt,
 219                                            wq->wqe_shift,
 220                                            wqe_length - bytes_copied,
 221                                            &bytes_copied2);
 222
 223         if (ret)
 224                 return ret;
 225         *bc = bytes_copied + bytes_copied2;
 226         return 0;
 227 }
 228
 229 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp,
 230                              int wqe_index,
 231                              void *buffer,
 232                              int buflen,
 233                              size_t *bc)
 234 {
 235         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
 236         struct ib_umem *umem = base->ubuffer.umem;
 237         struct mlx5_ib_wq *wq = &qp->rq;
 238         size_t bytes_copied;
 239         int ret;
 240
 241         ret = mlx5_ib_read_user_wqe_common(umem,
 242                                            buffer,
 243                                            buflen,
 244                                            wqe_index,
 245                                            wq->offset,
 246                                            wq->wqe_cnt,
 247                                            wq->wqe_shift,
 248                                            buflen,
 249                                            &bytes_copied);
 250
 251         if (ret)
 252                 return ret;
 253         *bc = bytes_copied;
 254         return 0;
 255 }
 256
 257 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq,
 258                               int wqe_index,
 259                               void *buffer,
 260                               int buflen,
 261                               size_t *bc)
 262 {
 263         struct ib_umem *umem = srq->umem;
 264         size_t bytes_copied;
 265         int ret;
 266
 267         ret = mlx5_ib_read_user_wqe_common(umem,
 268                                            buffer,
 269                                            buflen,
 270                                            wqe_index,
 271                                            0,
 272                                            srq->msrq.max,
 273                                            srq->msrq.wqe_shift,
 274                                            buflen,
 275                                            &bytes_copied);
 276
 277         if (ret)
 278                 return ret;
 279         *bc = bytes_copied;
 280         return 0;
 281 }
 282
 283 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 284 {
 285         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 286         struct ib_event event;
 287
 288         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 289                 /* This event is only valid for trans_qps */
 290                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 291         }
 292
 293         if (ibqp->event_handler) {
 294                 event.device     = ibqp->device;
 295                 event.element.qp = ibqp;
 296                 switch (type) {
 297                 case MLX5_EVENT_TYPE_PATH_MIG:
 298                         event.event = IB_EVENT_PATH_MIG;
 299                         break;
 300                 case MLX5_EVENT_TYPE_COMM_EST:
 301                         event.event = IB_EVENT_COMM_EST;
 302                         break;
 303                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 304                         event.event = IB_EVENT_SQ_DRAINED;
 305                         break;
 306                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 307                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 308                         break;
 309                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 310                         event.event = IB_EVENT_QP_FATAL;
 311                         break;
 312                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 313                         event.event = IB_EVENT_PATH_MIG_ERR;
 314                         break;
 315                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 316                         event.event = IB_EVENT_QP_REQ_ERR;
 317                         break;
 318                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 319                         event.event = IB_EVENT_QP_ACCESS_ERR;
 320                         break;
 321                 default:
 322                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 323                         return;
 324                 }
 325
 326                 ibqp->event_handler(&event, ibqp->qp_context);
 327         }
 328 }
 329
 330 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 331                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 332 {
 333         int wqe_size;
 334         int wq_size;
 335
 336         /* Sanity check RQ size before proceeding */
 337         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 338                 return -EINVAL;
 339
 340         if (!has_rq) {
 341                 qp->rq.max_gs = 0;
 342                 qp->rq.wqe_cnt = 0;
 343                 qp->rq.wqe_shift = 0;
 344                 cap->max_recv_wr = 0;
 345                 cap->max_recv_sge = 0;
 346         } else {
 347                 if (ucmd) {
 348                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 349                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 350                                 return -EINVAL;
 351                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 352                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 353                                 return -EINVAL;
 354                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 355                         qp->rq.max_post = qp->rq.wqe_cnt;
 356                 } else {
 357                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 358                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 359                         wqe_size = roundup_pow_of_two(wqe_size);
 360                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 361                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 362                         qp->rq.wqe_cnt = wq_size / wqe_size;
 363                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 364                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 365                                             wqe_size,
 366                                             MLX5_CAP_GEN(dev->mdev,
 367                                                          max_wqe_sz_rq));
 368                                 return -EINVAL;
 369                         }
 370                         qp->rq.wqe_shift = ilog2(wqe_size);
 371                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 372                         qp->rq.max_post = qp->rq.wqe_cnt;
 373                 }
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int sq_overhead(struct ib_qp_init_attr *attr)
 380 {
 381         int size = 0;
 382
 383         switch (attr->qp_type) {
 384         case IB_QPT_XRC_INI:
 385                 size += sizeof(struct mlx5_wqe_xrc_seg);
 386                 /* fall through */
 387         case IB_QPT_RC:
 388                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 389                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 390                             sizeof(struct mlx5_wqe_raddr_seg),
 391                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 392                             sizeof(struct mlx5_mkey_seg) +
 393                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 394                             MLX5_IB_UMR_OCTOWORD);
 395                 break;
 396
 397         case IB_QPT_XRC_TGT:
 398                 return 0;
 399
 400         case IB_QPT_UC:
 401                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 402                         max(sizeof(struct mlx5_wqe_raddr_seg),
 403                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 404                             sizeof(struct mlx5_mkey_seg));
 405                 break;
 406
 407         case IB_QPT_UD:
 408                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 409                         size += sizeof(struct mlx5_wqe_eth_pad) +
 410                                 sizeof(struct mlx5_wqe_eth_seg);
 411                 /* fall through */
 412         case IB_QPT_SMI:
 413         case MLX5_IB_QPT_HW_GSI:
 414                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 415                         sizeof(struct mlx5_wqe_datagram_seg);
 416                 break;
 417
 418         case MLX5_IB_QPT_REG_UMR:
 419                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 420                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 421                         sizeof(struct mlx5_mkey_seg);
 422                 break;
 423
 424         default:
 425                 return -EINVAL;
 426         }
 427
 428         return size;
 429 }
 430
 431 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 432 {
 433         int inl_size = 0;
 434         int size;
 435
 436         size = sq_overhead(attr);
 437         if (size < 0)
 438                 return size;
 439
 440         if (attr->cap.max_inline_data) {
 441                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 442                         attr->cap.max_inline_data;
 443         }
 444
 445         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 446         if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
 447             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 448                 return MLX5_SIG_WQE_SIZE;
 449         else
 450                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 451 }
 452
 453 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 454 {
 455         int max_sge;
 456
 457         if (attr->qp_type == IB_QPT_RC)
 458                 max_sge = (min_t(int, wqe_size, 512) -
 459                            sizeof(struct mlx5_wqe_ctrl_seg) -
 460                            sizeof(struct mlx5_wqe_raddr_seg)) /
 461                         sizeof(struct mlx5_wqe_data_seg);
 462         else if (attr->qp_type == IB_QPT_XRC_INI)
 463                 max_sge = (min_t(int, wqe_size, 512) -
 464                            sizeof(struct mlx5_wqe_ctrl_seg) -
 465                            sizeof(struct mlx5_wqe_xrc_seg) -
 466                            sizeof(struct mlx5_wqe_raddr_seg)) /
 467                         sizeof(struct mlx5_wqe_data_seg);
 468         else
 469                 max_sge = (wqe_size - sq_overhead(attr)) /
 470                         sizeof(struct mlx5_wqe_data_seg);
 471
 472         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 473                      sizeof(struct mlx5_wqe_data_seg));
 474 }
 475
 476 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 477                         struct mlx5_ib_qp *qp)
 478 {
 479         int wqe_size;
 480         int wq_size;
 481
 482         if (!attr->cap.max_send_wr)
 483                 return 0;
 484
 485         wqe_size = calc_send_wqe(attr);
 486         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 487         if (wqe_size < 0)
 488                 return wqe_size;
 489
 490         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 491                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 492                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 493                 return -EINVAL;
 494         }
 495
 496         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 497                               sizeof(struct mlx5_wqe_inline_seg);
 498         attr->cap.max_inline_data = qp->max_inline_data;
 499
 500         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 501         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 502         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 503                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 504                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 505                             qp->sq.wqe_cnt,
 506                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 507                 return -ENOMEM;
 508         }
 509         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 510         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 511         if (qp->sq.max_gs < attr->cap.max_send_sge)
 512                 return -ENOMEM;
 513
 514         attr->cap.max_send_sge = qp->sq.max_gs;
 515         qp->sq.max_post = wq_size / wqe_size;
 516         attr->cap.max_send_wr = qp->sq.max_post;
 517
 518         return wq_size;
 519 }
 520
 521 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 522                             struct mlx5_ib_qp *qp,
 523                             struct mlx5_ib_create_qp *ucmd,
 524                             struct mlx5_ib_qp_base *base,
 525                             struct ib_qp_init_attr *attr)
 526 {
 527         int desc_sz = 1 << qp->sq.wqe_shift;
 528
 529         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 530                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 531                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 532                 return -EINVAL;
 533         }
 534
 535         if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
 536                 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
 537                              ucmd->sq_wqe_count);
 538                 return -EINVAL;
 539         }
 540
 541         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 542
 543         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 544                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 545                              qp->sq.wqe_cnt,
 546                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 547                 return -EINVAL;
 548         }
 549
 550         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 551             qp->flags & MLX5_IB_QP_UNDERLAY) {
 552                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 553                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 554         } else {
 555                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 556                                          (qp->sq.wqe_cnt << 6);
 557         }
 558
 559         return 0;
 560 }
 561
 562 static int qp_has_rq(struct ib_qp_init_attr *attr)
 563 {
 564         if (attr->qp_type == IB_QPT_XRC_INI ||
 565             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 566             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 567             !attr->cap.max_recv_wr)
 568                 return 0;
 569
 570         return 1;
 571 }
 572
 573 enum {
 574         /* this is the first blue flame register in the array of bfregs assigned
 575          * to a processes. Since we do not use it for blue flame but rather
 576          * regular 64 bit doorbells, we do not need a lock for maintaiing
 577          * "odd/even" order
 578          */
 579         NUM_NON_BLUE_FLAME_BFREGS = 1,
 580 };
 581
 582 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 583 {
 584         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 585 }
 586
 587 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 588                          struct mlx5_bfreg_info *bfregi)
 589 {
 590         int n;
 591
 592         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 593             NUM_NON_BLUE_FLAME_BFREGS;
 594
 595         return n >= 0 ? n : 0;
 596 }
 597
 598 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 599                            struct mlx5_bfreg_info *bfregi)
 600 {
 601         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 602 }
 603
 604 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 605                           struct mlx5_bfreg_info *bfregi)
 606 {
 607         int med;
 608
 609         med = num_med_bfreg(dev, bfregi);
 610         return ++med;
 611 }
 612
 613 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 614                                   struct mlx5_bfreg_info *bfregi)
 615 {
 616         int i;
 617
 618         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 619                 if (!bfregi->count[i]) {
 620                         bfregi->count[i]++;
 621                         return i;
 622                 }
 623         }
 624
 625         return -ENOMEM;
 626 }
 627
 628 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 629                                  struct mlx5_bfreg_info *bfregi)
 630 {
 631         int minidx = first_med_bfreg(dev, bfregi);
 632         int i;
 633
 634         if (minidx < 0)
 635                 return minidx;
 636
 637         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 638                 if (bfregi->count[i] < bfregi->count[minidx])
 639                         minidx = i;
 640                 if (!bfregi->count[minidx])
 641                         break;
 642         }
 643
 644         bfregi->count[minidx]++;
 645         return minidx;
 646 }
 647
 648 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 649                        struct mlx5_bfreg_info *bfregi)
 650 {
 651         int bfregn = -ENOMEM;
 652
 653         mutex_lock(&bfregi->lock);
 654         if (bfregi->ver >= 2) {
 655                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 656                 if (bfregn < 0)
 657                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 658         }
 659
 660         if (bfregn < 0) {
 661                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 662                 bfregn = 0;
 663                 bfregi->count[bfregn]++;
 664         }
 665         mutex_unlock(&bfregi->lock);
 666
 667         return bfregn;
 668 }
 669
 670 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 671 {
 672         mutex_lock(&bfregi->lock);
 673         bfregi->count[bfregn]--;
 674         mutex_unlock(&bfregi->lock);
 675 }
 676
 677 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 678 {
 679         switch (state) {
 680         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 681         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 682         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 683         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 684         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 685         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 686         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 687         default:                return -1;
 688         }
 689 }
 690
 691 static int to_mlx5_st(enum ib_qp_type type)
 692 {
 693         switch (type) {
 694         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 695         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 696         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 697         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 698         case IB_QPT_XRC_INI:
 699         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 700         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 701         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 702         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 703         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 704         case IB_QPT_RAW_PACKET:
 705         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 706         case IB_QPT_MAX:
 707         default:                return -EINVAL;
 708         }
 709 }
 710
 711 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 712                              struct mlx5_ib_cq *recv_cq);
 713 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 714                                struct mlx5_ib_cq *recv_cq);
 715
 716 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 717                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 718                         bool dyn_bfreg)
 719 {
 720         unsigned int bfregs_per_sys_page;
 721         u32 index_of_sys_page;
 722         u32 offset;
 723
 724         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 725                                 MLX5_NON_FP_BFREGS_PER_UAR;
 726         index_of_sys_page = bfregn / bfregs_per_sys_page;
 727
 728         if (dyn_bfreg) {
 729                 index_of_sys_page += bfregi->num_static_sys_pages;
 730
 731                 if (index_of_sys_page >= bfregi->num_sys_pages)
 732                         return -EINVAL;
 733
 734                 if (bfregn > bfregi->num_dyn_bfregs ||
 735                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 736                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 737                         return -EINVAL;
 738                 }
 739         }
 740
 741         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 742         return bfregi->sys_pages[index_of_sys_page] + offset;
 743 }
 744
 745 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
 746                             unsigned long addr, size_t size,
 747                             struct ib_umem **umem, int *npages, int *page_shift,
 748                             int *ncont, u32 *offset)
 749 {
 750         int err;
 751
 752         *umem = ib_umem_get(udata, addr, size, 0, 0);
 753         if (IS_ERR(*umem)) {
 754                 mlx5_ib_dbg(dev, "umem_get failed\n");
 755                 return PTR_ERR(*umem);
 756         }
 757
 758         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 759
 760         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 761         if (err) {
 762                 mlx5_ib_warn(dev, "bad offset\n");
 763                 goto err_umem;
 764         }
 765
 766         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 767                     addr, size, *npages, *page_shift, *ncont, *offset);
 768
 769         return 0;
 770
 771 err_umem:
 772         ib_umem_release(*umem);
 773         *umem = NULL;
 774
 775         return err;
 776 }
 777
 778 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 779                             struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
 780 {
 781         struct mlx5_ib_ucontext *context =
 782                 rdma_udata_to_drv_context(
 783                         udata,
 784                         struct mlx5_ib_ucontext,
 785                         ibucontext);
 786
 787         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 788                 atomic_dec(&dev->delay_drop.rqs_cnt);
 789
 790         mlx5_ib_db_unmap_user(context, &rwq->db);
 791         ib_umem_release(rwq->umem);
 792 }
 793
 794 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 795                           struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
 796                           struct mlx5_ib_create_wq *ucmd)
 797 {
 798         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
 799                 udata, struct mlx5_ib_ucontext, ibucontext);
 800         int page_shift = 0;
 801         int npages;
 802         u32 offset = 0;
 803         int ncont = 0;
 804         int err;
 805
 806         if (!ucmd->buf_addr)
 807                 return -EINVAL;
 808
 809         rwq->umem = ib_umem_get(udata, ucmd->buf_addr, rwq->buf_size, 0, 0);
 810         if (IS_ERR(rwq->umem)) {
 811                 mlx5_ib_dbg(dev, "umem_get failed\n");
 812                 err = PTR_ERR(rwq->umem);
 813                 return err;
 814         }
 815
 816         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 817                            &ncont, NULL);
 818         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 819                                      &rwq->rq_page_offset);
 820         if (err) {
 821                 mlx5_ib_warn(dev, "bad offset\n");
 822                 goto err_umem;
 823         }
 824
 825         rwq->rq_num_pas = ncont;
 826         rwq->page_shift = page_shift;
 827         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 828         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 829
 830         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 831                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 832                     npages, page_shift, ncont, offset);
 833
 834         err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
 835         if (err) {
 836                 mlx5_ib_dbg(dev, "map failed\n");
 837                 goto err_umem;
 838         }
 839
 840         rwq->create_type = MLX5_WQ_USER;
 841         return 0;
 842
 843 err_umem:
 844         ib_umem_release(rwq->umem);
 845         return err;
 846 }
 847
 848 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 849                          struct mlx5_bfreg_info *bfregi, int bfregn)
 850 {
 851         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 852                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 853 }
 854
 855 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 856                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 857                           struct ib_qp_init_attr *attr,
 858                           u32 **in,
 859                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 860                           struct mlx5_ib_qp_base *base)
 861 {
 862         struct mlx5_ib_ucontext *context;
 863         struct mlx5_ib_create_qp ucmd;
 864         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 865         int page_shift = 0;
 866         int uar_index = 0;
 867         int npages;
 868         u32 offset = 0;
 869         int bfregn;
 870         int ncont = 0;
 871         __be64 *pas;
 872         void *qpc;
 873         int err;
 874         u16 uid;
 875
 876         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 877         if (err) {
 878                 mlx5_ib_dbg(dev, "copy failed\n");
 879                 return err;
 880         }
 881
 882         context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
 883                                             ibucontext);
 884         if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
 885                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 886                                                 ucmd.bfreg_index, true);
 887                 if (uar_index < 0)
 888                         return uar_index;
 889
 890                 bfregn = MLX5_IB_INVALID_BFREG;
 891         } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
 892                 /*
 893                  * TBD: should come from the verbs when we have the API
 894                  */
 895                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 896                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
 897         }
 898         else {
 899                 bfregn = alloc_bfreg(dev, &context->bfregi);
 900                 if (bfregn < 0)
 901                         return bfregn;
 902         }
 903
 904         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 905         if (bfregn != MLX5_IB_INVALID_BFREG)
 906                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 907                                                 false);
 908
 909         qp->rq.offset = 0;
 910         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 911         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 912
 913         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 914         if (err)
 915                 goto err_bfreg;
 916
 917         if (ucmd.buf_addr && ubuffer->buf_size) {
 918                 ubuffer->buf_addr = ucmd.buf_addr;
 919                 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
 920                                        ubuffer->buf_size, &ubuffer->umem,
 921                                        &npages, &page_shift, &ncont, &offset);
 922                 if (err)
 923                         goto err_bfreg;
 924         } else {
 925                 ubuffer->umem = NULL;
 926         }
 927
 928         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 929                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 930         *in = kvzalloc(*inlen, GFP_KERNEL);
 931         if (!*in) {
 932                 err = -ENOMEM;
 933                 goto err_umem;
 934         }
 935
 936         uid = (attr->qp_type != IB_QPT_XRC_TGT &&
 937                attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
 938         MLX5_SET(create_qp_in, *in, uid, uid);
 939         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 940         if (ubuffer->umem)
 941                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 942
 943         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 944
 945         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 946         MLX5_SET(qpc, qpc, page_offset, offset);
 947
 948         MLX5_SET(qpc, qpc, uar_page, uar_index);
 949         if (bfregn != MLX5_IB_INVALID_BFREG)
 950                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 951         else
 952                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
 953         qp->bfregn = bfregn;
 954
 955         err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db);
 956         if (err) {
 957                 mlx5_ib_dbg(dev, "map failed\n");
 958                 goto err_free;
 959         }
 960
 961         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
 962         if (err) {
 963                 mlx5_ib_dbg(dev, "copy failed\n");
 964                 goto err_unmap;
 965         }
 966         qp->create_type = MLX5_QP_USER;
 967
 968         return 0;
 969
 970 err_unmap:
 971         mlx5_ib_db_unmap_user(context, &qp->db);
 972
 973 err_free:
 974         kvfree(*in);
 975
 976 err_umem:
 977         ib_umem_release(ubuffer->umem);
 978
 979 err_bfreg:
 980         if (bfregn != MLX5_IB_INVALID_BFREG)
 981                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
 982         return err;
 983 }
 984
 985 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 986                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base,
 987                             struct ib_udata *udata)
 988 {
 989         struct mlx5_ib_ucontext *context =
 990                 rdma_udata_to_drv_context(
 991                         udata,
 992                         struct mlx5_ib_ucontext,
 993                         ibucontext);
 994
 995         mlx5_ib_db_unmap_user(context, &qp->db);
 996         ib_umem_release(base->ubuffer.umem);
 997
 998         /*
 999          * Free only the BFREGs which are handled by the kernel.
1000          * BFREGs of UARs allocated dynamically are handled by user.
1001          */
1002         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1003                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1004 }
1005
1006 /* get_sq_edge - Get the next nearby edge.
1007  *
1008  * An 'edge' is defined as the first following address after the end
1009  * of the fragment or the SQ. Accordingly, during the WQE construction
1010  * which repetitively increases the pointer to write the next data, it
1011  * simply should check if it gets to an edge.
1012  *
1013  * @sq - SQ buffer.
1014  * @idx - Stride index in the SQ buffer.
1015  *
1016  * Return:
1017  *      The new edge.
1018  */
1019 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
1020 {
1021         void *fragment_end;
1022
1023         fragment_end = mlx5_frag_buf_get_wqe
1024                 (&sq->fbc,
1025                  mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
1026
1027         return fragment_end + MLX5_SEND_WQE_BB;
1028 }
1029
1030 static int create_kernel_qp(struct mlx5_ib_dev *dev,
1031                             struct ib_qp_init_attr *init_attr,
1032                             struct mlx5_ib_qp *qp,
1033                             u32 **in, int *inlen,
1034                             struct mlx5_ib_qp_base *base)
1035 {
1036         int uar_index;
1037         void *qpc;
1038         int err;
1039
1040         if (init_attr->create_flags & ~(IB_QP_CREATE_INTEGRITY_EN |
1041                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
1042                                         IB_QP_CREATE_IPOIB_UD_LSO |
1043                                         IB_QP_CREATE_NETIF_QP |
1044                                         mlx5_ib_create_qp_sqpn_qp1()))
1045                 return -EINVAL;
1046
1047         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
1048                 qp->bf.bfreg = &dev->fp_bfreg;
1049         else
1050                 qp->bf.bfreg = &dev->bfreg;
1051
1052         /* We need to divide by two since each register is comprised of
1053          * two buffers of identical size, namely odd and even
1054          */
1055         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
1056         uar_index = qp->bf.bfreg->index;
1057
1058         err = calc_sq_size(dev, init_attr, qp);
1059         if (err < 0) {
1060                 mlx5_ib_dbg(dev, "err %d\n", err);
1061                 return err;
1062         }
1063
1064         qp->rq.offset = 0;
1065         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
1066         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
1067
1068         err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1069                                        &qp->buf, dev->mdev->priv.numa_node);
1070         if (err) {
1071                 mlx5_ib_dbg(dev, "err %d\n", err);
1072                 return err;
1073         }
1074
1075         if (qp->rq.wqe_cnt)
1076                 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1077                               ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1078
1079         if (qp->sq.wqe_cnt) {
1080                 int sq_strides_offset = (qp->sq.offset  & (PAGE_SIZE - 1)) /
1081                                         MLX5_SEND_WQE_BB;
1082                 mlx5_init_fbc_offset(qp->buf.frags +
1083                                      (qp->sq.offset / PAGE_SIZE),
1084                                      ilog2(MLX5_SEND_WQE_BB),
1085                                      ilog2(qp->sq.wqe_cnt),
1086                                      sq_strides_offset, &qp->sq.fbc);
1087
1088                 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1089         }
1090
1091         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1092                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1093         *in = kvzalloc(*inlen, GFP_KERNEL);
1094         if (!*in) {
1095                 err = -ENOMEM;
1096                 goto err_buf;
1097         }
1098
1099         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1100         MLX5_SET(qpc, qpc, uar_page, uar_index);
1101         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1102
1103         /* Set "fast registration enabled" for all kernel QPs */
1104         MLX5_SET(qpc, qpc, fre, 1);
1105         MLX5_SET(qpc, qpc, rlky, 1);
1106
1107         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
1108                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1109                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1110         }
1111
1112         mlx5_fill_page_frag_array(&qp->buf,
1113                                   (__be64 *)MLX5_ADDR_OF(create_qp_in,
1114                                                          *in, pas));
1115
1116         err = mlx5_db_alloc(dev->mdev, &qp->db);
1117         if (err) {
1118                 mlx5_ib_dbg(dev, "err %d\n", err);
1119                 goto err_free;
1120         }
1121
1122         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1123                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1124         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1125                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1126         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1127                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1128         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1129                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1130         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1131                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1132
1133         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1134             !qp->sq.w_list || !qp->sq.wqe_head) {
1135                 err = -ENOMEM;
1136                 goto err_wrid;
1137         }
1138         qp->create_type = MLX5_QP_KERNEL;
1139
1140         return 0;
1141
1142 err_wrid:
1143         kvfree(qp->sq.wqe_head);
1144         kvfree(qp->sq.w_list);
1145         kvfree(qp->sq.wrid);
1146         kvfree(qp->sq.wr_data);
1147         kvfree(qp->rq.wrid);
1148         mlx5_db_free(dev->mdev, &qp->db);
1149
1150 err_free:
1151         kvfree(*in);
1152
1153 err_buf:
1154         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1155         return err;
1156 }
1157
1158 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1159 {
1160         kvfree(qp->sq.wqe_head);
1161         kvfree(qp->sq.w_list);
1162         kvfree(qp->sq.wrid);
1163         kvfree(qp->sq.wr_data);
1164         kvfree(qp->rq.wrid);
1165         mlx5_db_free(dev->mdev, &qp->db);
1166         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1167 }
1168
1169 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1170 {
1171         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1172             (attr->qp_type == MLX5_IB_QPT_DCI) ||
1173             (attr->qp_type == IB_QPT_XRC_INI))
1174                 return MLX5_SRQ_RQ;
1175         else if (!qp->has_rq)
1176                 return MLX5_ZERO_LEN_RQ;
1177         else
1178                 return MLX5_NON_ZERO_RQ;
1179 }
1180
1181 static int is_connected(enum ib_qp_type qp_type)
1182 {
1183         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1184             qp_type == MLX5_IB_QPT_DCI)
1185                 return 1;
1186
1187         return 0;
1188 }
1189
1190 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1191                                     struct mlx5_ib_qp *qp,
1192                                     struct mlx5_ib_sq *sq, u32 tdn,
1193                                     struct ib_pd *pd)
1194 {
1195         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1196         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1197
1198         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1199         MLX5_SET(tisc, tisc, transport_domain, tdn);
1200         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1201                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1202
1203         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1204 }
1205
1206 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1207                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1208 {
1209         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1210 }
1211
1212 static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
1213 {
1214         if (sq->flow_rule)
1215                 mlx5_del_flow_rules(sq->flow_rule);
1216         sq->flow_rule = NULL;
1217 }
1218
1219 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1220                                    struct ib_udata *udata,
1221                                    struct mlx5_ib_sq *sq, void *qpin,
1222                                    struct ib_pd *pd)
1223 {
1224         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1225         __be64 *pas;
1226         void *in;
1227         void *sqc;
1228         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1229         void *wq;
1230         int inlen;
1231         int err;
1232         int page_shift = 0;
1233         int npages;
1234         int ncont = 0;
1235         u32 offset = 0;
1236
1237         err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1238                                &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1239                                &offset);
1240         if (err)
1241                 return err;
1242
1243         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1244         in = kvzalloc(inlen, GFP_KERNEL);
1245         if (!in) {
1246                 err = -ENOMEM;
1247                 goto err_umem;
1248         }
1249
1250         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1251         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1252         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1253         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1254                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1255         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1256         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1257         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1258         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1259         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1260         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1261             MLX5_CAP_ETH(dev->mdev, swp))
1262                 MLX5_SET(sqc, sqc, allow_swp, 1);
1263
1264         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1265         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1266         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1267         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1268         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1269         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1270         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1271         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1272         MLX5_SET(wq, wq, page_offset, offset);
1273
1274         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1275         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1276
1277         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1278
1279         kvfree(in);
1280
1281         if (err)
1282                 goto err_umem;
1283
1284         return 0;
1285
1286 err_umem:
1287         ib_umem_release(sq->ubuffer.umem);
1288         sq->ubuffer.umem = NULL;
1289
1290         return err;
1291 }
1292
1293 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1294                                      struct mlx5_ib_sq *sq)
1295 {
1296         destroy_flow_rule_vport_sq(sq);
1297         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1298         ib_umem_release(sq->ubuffer.umem);
1299 }
1300
1301 static size_t get_rq_pas_size(void *qpc)
1302 {
1303         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1304         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1305         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1306         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1307         u32 po_quanta     = 1 << (log_page_size - 6);
1308         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1309         u32 page_size     = 1 << log_page_size;
1310         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1311         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1312
1313         return rq_num_pas * sizeof(u64);
1314 }
1315
1316 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1317                                    struct mlx5_ib_rq *rq, void *qpin,
1318                                    size_t qpinlen, struct ib_pd *pd)
1319 {
1320         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1321         __be64 *pas;
1322         __be64 *qp_pas;
1323         void *in;
1324         void *rqc;
1325         void *wq;
1326         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1327         size_t rq_pas_size = get_rq_pas_size(qpc);
1328         size_t inlen;
1329         int err;
1330
1331         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1332                 return -EINVAL;
1333
1334         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1335         in = kvzalloc(inlen, GFP_KERNEL);
1336         if (!in)
1337                 return -ENOMEM;
1338
1339         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1340         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1341         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1342                 MLX5_SET(rqc, rqc, vsd, 1);
1343         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1344         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1345         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1346         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1347         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1348
1349         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1350                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1351
1352         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1353         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1354         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1355                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1356         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1357         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1358         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1359         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1360         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1361         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1362
1363         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1364         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1365         memcpy(pas, qp_pas, rq_pas_size);
1366
1367         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1368
1369         kvfree(in);
1370
1371         return err;
1372 }
1373
1374 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1375                                      struct mlx5_ib_rq *rq)
1376 {
1377         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1378 }
1379
1380 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1381 {
1382         return  (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1383                  MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1384                  MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1385 }
1386
1387 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1388                                       struct mlx5_ib_rq *rq,
1389                                       u32 qp_flags_en,
1390                                       struct ib_pd *pd)
1391 {
1392         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1393                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1394                 mlx5_ib_disable_lb(dev, false, true);
1395         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1396 }
1397
1398 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1399                                     struct mlx5_ib_rq *rq, u32 tdn,
1400                                     u32 *qp_flags_en,
1401                                     struct ib_pd *pd,
1402                                     u32 *out, int outlen)
1403 {
1404         u8 lb_flag = 0;
1405         u32 *in;
1406         void *tirc;
1407         int inlen;
1408         int err;
1409
1410         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1411         in = kvzalloc(inlen, GFP_KERNEL);
1412         if (!in)
1413                 return -ENOMEM;
1414
1415         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1416         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1417         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1418         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1419         MLX5_SET(tirc, tirc, transport_domain, tdn);
1420         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1421                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1422
1423         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1424                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1425
1426         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1427                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1428
1429         if (dev->is_rep) {
1430                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1431                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1432         }
1433
1434         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1435
1436         err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen);
1437
1438         rq->tirn = MLX5_GET(create_tir_out, out, tirn);
1439         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1440                 err = mlx5_ib_enable_lb(dev, false, true);
1441
1442                 if (err)
1443                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1444         }
1445         kvfree(in);
1446
1447         return err;
1448 }
1449
1450 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1451                                 u32 *in, size_t inlen,
1452                                 struct ib_pd *pd,
1453                                 struct ib_udata *udata,
1454                                 struct mlx5_ib_create_qp_resp *resp)
1455 {
1456         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1457         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1458         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1459         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1460                 udata, struct mlx5_ib_ucontext, ibucontext);
1461         int err;
1462         u32 tdn = mucontext->tdn;
1463         u16 uid = to_mpd(pd)->uid;
1464         u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
1465
1466         if (qp->sq.wqe_cnt) {
1467                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1468                 if (err)
1469                         return err;
1470
1471                 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
1472                 if (err)
1473                         goto err_destroy_tis;
1474
1475                 if (uid) {
1476                         resp->tisn = sq->tisn;
1477                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1478                         resp->sqn = sq->base.mqp.qpn;
1479                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1480                 }
1481
1482                 sq->base.container_mibqp = qp;
1483                 sq->base.mqp.event = mlx5_ib_qp_event;
1484         }
1485
1486         if (qp->rq.wqe_cnt) {
1487                 rq->base.container_mibqp = qp;
1488
1489                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1490                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1491                 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1492                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1493                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1494                 if (err)
1495                         goto err_destroy_sq;
1496
1497                 err = create_raw_packet_qp_tir(
1498                         dev, rq, tdn, &qp->flags_en, pd, out,
1499                         MLX5_ST_SZ_BYTES(create_tir_out));
1500                 if (err)
1501                         goto err_destroy_rq;
1502
1503                 if (uid) {
1504                         resp->rqn = rq->base.mqp.qpn;
1505                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1506                         resp->tirn = rq->tirn;
1507                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1508                         if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1509                                 resp->tir_icm_addr = MLX5_GET(
1510                                         create_tir_out, out, icm_address_31_0);
1511                                 resp->tir_icm_addr |=
1512                                         (u64)MLX5_GET(create_tir_out, out,
1513                                                       icm_address_39_32)
1514                                         << 32;
1515                                 resp->tir_icm_addr |=
1516                                         (u64)MLX5_GET(create_tir_out, out,
1517                                                       icm_address_63_40)
1518                                         << 40;
1519                                 resp->comp_mask |=
1520                                         MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1521                         }
1522                 }
1523         }
1524
1525         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1526                                                      rq->base.mqp.qpn;
1527         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1528         if (err)
1529                 goto err_destroy_tir;
1530
1531         return 0;
1532
1533 err_destroy_tir:
1534         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1535 err_destroy_rq:
1536         destroy_raw_packet_qp_rq(dev, rq);
1537 err_destroy_sq:
1538         if (!qp->sq.wqe_cnt)
1539                 return err;
1540         destroy_raw_packet_qp_sq(dev, sq);
1541 err_destroy_tis:
1542         destroy_raw_packet_qp_tis(dev, sq, pd);
1543
1544         return err;
1545 }
1546
1547 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1548                                   struct mlx5_ib_qp *qp)
1549 {
1550         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1551         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1552         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1553
1554         if (qp->rq.wqe_cnt) {
1555                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1556                 destroy_raw_packet_qp_rq(dev, rq);
1557         }
1558
1559         if (qp->sq.wqe_cnt) {
1560                 destroy_raw_packet_qp_sq(dev, sq);
1561                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1562         }
1563 }
1564
1565 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1566                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1567 {
1568         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1569         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1570
1571         sq->sq = &qp->sq;
1572         rq->rq = &qp->rq;
1573         sq->doorbell = &qp->db;
1574         rq->doorbell = &qp->db;
1575 }
1576
1577 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1578 {
1579         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1580                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1581                 mlx5_ib_disable_lb(dev, false, true);
1582         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1583                              to_mpd(qp->ibqp.pd)->uid);
1584 }
1585
1586 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1587                                  struct ib_pd *pd,
1588                                  struct ib_qp_init_attr *init_attr,
1589                                  struct ib_udata *udata)
1590 {
1591         struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1592                 udata, struct mlx5_ib_ucontext, ibucontext);
1593         struct mlx5_ib_create_qp_resp resp = {};
1594         int inlen;
1595         int outlen;
1596         int err;
1597         u32 *in;
1598         u32 *out;
1599         void *tirc;
1600         void *hfso;
1601         u32 selected_fields = 0;
1602         u32 outer_l4;
1603         size_t min_resp_len;
1604         u32 tdn = mucontext->tdn;
1605         struct mlx5_ib_create_qp_rss ucmd = {};
1606         size_t required_cmd_sz;
1607         u8 lb_flag = 0;
1608
1609         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1610                 return -EOPNOTSUPP;
1611
1612         if (init_attr->create_flags || init_attr->send_cq)
1613                 return -EINVAL;
1614
1615         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1616         if (udata->outlen < min_resp_len)
1617                 return -EINVAL;
1618
1619         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1620         if (udata->inlen < required_cmd_sz) {
1621                 mlx5_ib_dbg(dev, "invalid inlen\n");
1622                 return -EINVAL;
1623         }
1624
1625         if (udata->inlen > sizeof(ucmd) &&
1626             !ib_is_udata_cleared(udata, sizeof(ucmd),
1627                                  udata->inlen - sizeof(ucmd))) {
1628                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1629                 return -EOPNOTSUPP;
1630         }
1631
1632         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1633                 mlx5_ib_dbg(dev, "copy failed\n");
1634                 return -EFAULT;
1635         }
1636
1637         if (ucmd.comp_mask) {
1638                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1639                 return -EOPNOTSUPP;
1640         }
1641
1642         if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1643                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1644                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1645                 mlx5_ib_dbg(dev, "invalid flags\n");
1646                 return -EOPNOTSUPP;
1647         }
1648
1649         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1650             !tunnel_offload_supported(dev->mdev)) {
1651                 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1652                 return -EOPNOTSUPP;
1653         }
1654
1655         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1656             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1657                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1658                 return -EOPNOTSUPP;
1659         }
1660
1661         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->is_rep) {
1662                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1663                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1664         }
1665
1666         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1667                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1668                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1669         }
1670
1671         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1672         if (err) {
1673                 mlx5_ib_dbg(dev, "copy failed\n");
1674                 return -EINVAL;
1675         }
1676
1677         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1678         outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1679         in = kvzalloc(inlen + outlen, GFP_KERNEL);
1680         if (!in)
1681                 return -ENOMEM;
1682
1683         out = in + MLX5_ST_SZ_DW(create_tir_in);
1684         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1685         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1686         MLX5_SET(tirc, tirc, disp_type,
1687                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1688         MLX5_SET(tirc, tirc, indirect_table,
1689                  init_attr->rwq_ind_tbl->ind_tbl_num);
1690         MLX5_SET(tirc, tirc, transport_domain, tdn);
1691
1692         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1693
1694         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1695                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1696
1697         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1698
1699         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1700                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1701         else
1702                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1703
1704         switch (ucmd.rx_hash_function) {
1705         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1706         {
1707                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1708                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1709
1710                 if (len != ucmd.rx_key_len) {
1711                         err = -EINVAL;
1712                         goto err;
1713                 }
1714
1715                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1716                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1717                 memcpy(rss_key, ucmd.rx_hash_key, len);
1718                 break;
1719         }
1720         default:
1721                 err = -EOPNOTSUPP;
1722                 goto err;
1723         }
1724
1725         if (!ucmd.rx_hash_fields_mask) {
1726                 /* special case when this TIR serves as steering entry without hashing */
1727                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1728                         goto create_tir;
1729                 err = -EINVAL;
1730                 goto err;
1731         }
1732
1733         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1734              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1735              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1736              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1737                 err = -EINVAL;
1738                 goto err;
1739         }
1740
1741         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1742         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1743             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1744                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1745                          MLX5_L3_PROT_TYPE_IPV4);
1746         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1747                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1748                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1749                          MLX5_L3_PROT_TYPE_IPV6);
1750
1751         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1752                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1753                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1754                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1755                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1756
1757         /* Check that only one l4 protocol is set */
1758         if (outer_l4 & (outer_l4 - 1)) {
1759                 err = -EINVAL;
1760                 goto err;
1761         }
1762
1763         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1764         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1765             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1766                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1767                          MLX5_L4_PROT_TYPE_TCP);
1768         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1769                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1770                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1771                          MLX5_L4_PROT_TYPE_UDP);
1772
1773         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1774             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1775                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1776
1777         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1778             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1779                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1780
1781         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1782             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1783                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1784
1785         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1786             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1787                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1788
1789         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1790                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1791
1792         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1793
1794 create_tir:
1795         err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen);
1796
1797         qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
1798         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1799                 err = mlx5_ib_enable_lb(dev, false, true);
1800
1801                 if (err)
1802                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1803                                              to_mpd(pd)->uid);
1804         }
1805
1806         if (err)
1807                 goto err;
1808
1809         if (mucontext->devx_uid) {
1810                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1811                 resp.tirn = qp->rss_qp.tirn;
1812                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1813                         resp.tir_icm_addr =
1814                                 MLX5_GET(create_tir_out, out, icm_address_31_0);
1815                         resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1816                                                            icm_address_39_32)
1817                                              << 32;
1818                         resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out,
1819                                                            icm_address_63_40)
1820                                              << 40;
1821                         resp.comp_mask |=
1822                                 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1823                 }
1824         }
1825
1826         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1827         if (err)
1828                 goto err_copy;
1829
1830         kvfree(in);
1831         /* qpn is reserved for that QP */
1832         qp->trans_qp.base.mqp.qpn = 0;
1833         qp->flags |= MLX5_IB_QP_RSS;
1834         return 0;
1835
1836 err_copy:
1837         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1838 err:
1839         kvfree(in);
1840         return err;
1841 }
1842
1843 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1844                                          void *qpc)
1845 {
1846         int rcqe_sz;
1847
1848         if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1849                 return;
1850
1851         rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1852
1853         if (init_attr->qp_type == MLX5_IB_QPT_DCT) {
1854                 if (rcqe_sz == 128)
1855                         MLX5_SET(dctc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1856
1857                 return;
1858         }
1859
1860         MLX5_SET(qpc, qpc, cs_res,
1861                  rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
1862                                   MLX5_RES_SCAT_DATA32_CQE);
1863 }
1864
1865 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1866                                          struct ib_qp_init_attr *init_attr,
1867                                          struct mlx5_ib_create_qp *ucmd,
1868                                          void *qpc)
1869 {
1870         enum ib_qp_type qpt = init_attr->qp_type;
1871         int scqe_sz;
1872         bool allow_scat_cqe = 0;
1873
1874         if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1875                 return;
1876
1877         if (ucmd)
1878                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1879
1880         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1881                 return;
1882
1883         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1884         if (scqe_sz == 128) {
1885                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1886                 return;
1887         }
1888
1889         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1890             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1891                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1892 }
1893
1894 static int atomic_size_to_mode(int size_mask)
1895 {
1896         /* driver does not support atomic_size > 256B
1897          * and does not know how to translate bigger sizes
1898          */
1899         int supported_size_mask = size_mask & 0x1ff;
1900         int log_max_size;
1901
1902         if (!supported_size_mask)
1903                 return -EOPNOTSUPP;
1904
1905         log_max_size = __fls(supported_size_mask);
1906
1907         if (log_max_size > 3)
1908                 return log_max_size;
1909
1910         return MLX5_ATOMIC_MODE_8B;
1911 }
1912
1913 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1914                            enum ib_qp_type qp_type)
1915 {
1916         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1917         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1918         int atomic_mode = -EOPNOTSUPP;
1919         int atomic_size_mask;
1920
1921         if (!atomic)
1922                 return -EOPNOTSUPP;
1923
1924         if (qp_type == MLX5_IB_QPT_DCT)
1925                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1926         else
1927                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1928
1929         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1930             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1931                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1932
1933         if (atomic_mode <= 0 &&
1934             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1935              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1936                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1937
1938         return atomic_mode;
1939 }
1940
1941 static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1942 {
1943         return (input & ~supported) == 0;
1944 }
1945
1946 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1947                             struct ib_qp_init_attr *init_attr,
1948                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1949 {
1950         struct mlx5_ib_resources *devr = &dev->devr;
1951         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1952         struct mlx5_core_dev *mdev = dev->mdev;
1953         struct mlx5_ib_create_qp_resp resp = {};
1954         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
1955                 udata, struct mlx5_ib_ucontext, ibucontext);
1956         struct mlx5_ib_cq *send_cq;
1957         struct mlx5_ib_cq *recv_cq;
1958         unsigned long flags;
1959         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1960         struct mlx5_ib_create_qp ucmd;
1961         struct mlx5_ib_qp_base *base;
1962         int mlx5_st;
1963         void *qpc;
1964         u32 *in;
1965         int err;
1966
1967         mutex_init(&qp->mutex);
1968         spin_lock_init(&qp->sq.lock);
1969         spin_lock_init(&qp->rq.lock);
1970
1971         mlx5_st = to_mlx5_st(init_attr->qp_type);
1972         if (mlx5_st < 0)
1973                 return -EINVAL;
1974
1975         if (init_attr->rwq_ind_tbl) {
1976                 if (!udata)
1977                         return -ENOSYS;
1978
1979                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1980                 return err;
1981         }
1982
1983         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1984                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1985                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1986                         return -EINVAL;
1987                 } else {
1988                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1989                 }
1990         }
1991
1992         if (init_attr->create_flags &
1993                         (IB_QP_CREATE_CROSS_CHANNEL |
1994                          IB_QP_CREATE_MANAGED_SEND |
1995                          IB_QP_CREATE_MANAGED_RECV)) {
1996                 if (!MLX5_CAP_GEN(mdev, cd)) {
1997                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1998                         return -EINVAL;
1999                 }
2000                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
2001                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
2002                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
2003                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
2004                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
2005                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
2006         }
2007
2008         if (init_attr->qp_type == IB_QPT_UD &&
2009             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
2010                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
2011                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
2012                         return -EOPNOTSUPP;
2013                 }
2014
2015         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
2016                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2017                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
2018                         return -EOPNOTSUPP;
2019                 }
2020                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
2021                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
2022                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
2023                         return -EOPNOTSUPP;
2024                 }
2025                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
2026         }
2027
2028         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2029                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2030
2031         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
2032                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
2033                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
2034                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
2035                         return -EOPNOTSUPP;
2036                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
2037         }
2038
2039         if (udata) {
2040                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
2041                         mlx5_ib_dbg(dev, "copy failed\n");
2042                         return -EFAULT;
2043                 }
2044
2045                 if (!check_flags_mask(ucmd.flags,
2046                                       MLX5_QP_FLAG_ALLOW_SCATTER_CQE |
2047                                       MLX5_QP_FLAG_BFREG_INDEX |
2048                                       MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE |
2049                                       MLX5_QP_FLAG_SCATTER_CQE |
2050                                       MLX5_QP_FLAG_SIGNATURE |
2051                                       MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC |
2052                                       MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2053                                       MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2054                                       MLX5_QP_FLAG_TYPE_DCI |
2055                                       MLX5_QP_FLAG_TYPE_DCT))
2056                         return -EINVAL;
2057
2058                 err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx);
2059                 if (err)
2060                         return err;
2061
2062                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
2063                 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
2064                         qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
2065                 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
2066                         if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
2067                             !tunnel_offload_supported(mdev)) {
2068                                 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
2069                                 return -EOPNOTSUPP;
2070                         }
2071                         qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
2072                 }
2073
2074                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
2075                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2076                                 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
2077                                 return -EOPNOTSUPP;
2078                         }
2079                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
2080                 }
2081
2082                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
2083                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2084                                 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
2085                                 return -EOPNOTSUPP;
2086                         }
2087                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
2088                 }
2089
2090                 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) {
2091                         if (init_attr->qp_type != IB_QPT_RC ||
2092                                 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) {
2093                                 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n");
2094                                 return -EOPNOTSUPP;
2095                         }
2096                         qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT;
2097                 }
2098
2099                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
2100                         if (init_attr->qp_type != IB_QPT_UD ||
2101                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
2102                              MLX5_CAP_PORT_TYPE_IB) ||
2103                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
2104                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
2105                                 return -EOPNOTSUPP;
2106                         }
2107
2108                         qp->flags |= MLX5_IB_QP_UNDERLAY;
2109                         qp->underlay_qpn = init_attr->source_qpn;
2110                 }
2111         } else {
2112                 qp->wq_sig = !!wq_signature;
2113         }
2114
2115         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2116                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2117                &qp->raw_packet_qp.rq.base :
2118                &qp->trans_qp.base;
2119
2120         qp->has_rq = qp_has_rq(init_attr);
2121         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
2122                           qp, udata ? &ucmd : NULL);
2123         if (err) {
2124                 mlx5_ib_dbg(dev, "err %d\n", err);
2125                 return err;
2126         }
2127
2128         if (pd) {
2129                 if (udata) {
2130                         __u32 max_wqes =
2131                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
2132                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
2133                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
2134                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
2135                                 mlx5_ib_dbg(dev, "invalid rq params\n");
2136                                 return -EINVAL;
2137                         }
2138                         if (ucmd.sq_wqe_count > max_wqes) {
2139                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
2140                                             ucmd.sq_wqe_count, max_wqes);
2141                                 return -EINVAL;
2142                         }
2143                         if (init_attr->create_flags &
2144                             mlx5_ib_create_qp_sqpn_qp1()) {
2145                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
2146                                 return -EINVAL;
2147                         }
2148                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2149                                              &resp, &inlen, base);
2150                         if (err)
2151                                 mlx5_ib_dbg(dev, "err %d\n", err);
2152                 } else {
2153                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2154                                                base);
2155                         if (err)
2156                                 mlx5_ib_dbg(dev, "err %d\n", err);
2157                 }
2158
2159                 if (err)
2160                         return err;
2161         } else {
2162                 in = kvzalloc(inlen, GFP_KERNEL);
2163                 if (!in)
2164                         return -ENOMEM;
2165
2166                 qp->create_type = MLX5_QP_EMPTY;
2167         }
2168
2169         if (is_sqp(init_attr->qp_type))
2170                 qp->port = init_attr->port_num;
2171
2172         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2173
2174         MLX5_SET(qpc, qpc, st, mlx5_st);
2175         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2176
2177         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
2178                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2179         else
2180                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2181
2182
2183         if (qp->wq_sig)
2184                 MLX5_SET(qpc, qpc, wq_signature, 1);
2185
2186         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2187                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2188
2189         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
2190                 MLX5_SET(qpc, qpc, cd_master, 1);
2191         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
2192                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2193         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
2194                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2195         if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT)
2196                 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2197         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
2198                 configure_responder_scat_cqe(init_attr, qpc);
2199                 configure_requester_scat_cqe(dev, init_attr,
2200                                              udata ? &ucmd : NULL,
2201                                              qpc);
2202         }
2203
2204         if (qp->rq.wqe_cnt) {
2205                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2206                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2207         }
2208
2209         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2210
2211         if (qp->sq.wqe_cnt) {
2212                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2213         } else {
2214                 MLX5_SET(qpc, qpc, no_sq, 1);
2215                 if (init_attr->srq &&
2216                     init_attr->srq->srq_type == IB_SRQT_TM)
2217                         MLX5_SET(qpc, qpc, offload_type,
2218                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2219         }
2220
2221         /* Set default resources */
2222         switch (init_attr->qp_type) {
2223         case IB_QPT_XRC_TGT:
2224                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2225                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2226                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2227                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2228                 break;
2229         case IB_QPT_XRC_INI:
2230                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2231                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2232                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2233                 break;
2234         default:
2235                 if (init_attr->srq) {
2236                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2237                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2238                 } else {
2239                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2240                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2241                 }
2242         }
2243
2244         if (init_attr->send_cq)
2245                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2246
2247         if (init_attr->recv_cq)
2248                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2249
2250         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2251
2252         /* 0xffffff means we ask to work with cqe version 0 */
2253         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2254                 MLX5_SET(qpc, qpc, user_index, uidx);
2255
2256         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2257         if (init_attr->qp_type == IB_QPT_UD &&
2258             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
2259                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2260                 qp->flags |= MLX5_IB_QP_LSO;
2261         }
2262
2263         if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2264                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2265                         mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2266                         err = -EOPNOTSUPP;
2267                         goto err;
2268                 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2269                         MLX5_SET(qpc, qpc, end_padding_mode,
2270                                  MLX5_WQ_END_PAD_MODE_ALIGN);
2271                 } else {
2272                         qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2273                 }
2274         }
2275
2276         if (inlen < 0) {
2277                 err = -EINVAL;
2278                 goto err;
2279         }
2280
2281         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2282             qp->flags & MLX5_IB_QP_UNDERLAY) {
2283                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2284                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2285                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2286                                            &resp);
2287         } else {
2288                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2289         }
2290
2291         if (err) {
2292                 mlx5_ib_dbg(dev, "create qp failed\n");
2293                 goto err_create;
2294         }
2295
2296         kvfree(in);
2297
2298         base->container_mibqp = qp;
2299         base->mqp.event = mlx5_ib_qp_event;
2300
2301         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2302                 &send_cq, &recv_cq);
2303         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2304         mlx5_ib_lock_cqs(send_cq, recv_cq);
2305         /* Maintain device to QPs access, needed for further handling via reset
2306          * flow
2307          */
2308         list_add_tail(&qp->qps_list, &dev->qp_list);
2309         /* Maintain CQ to QPs access, needed for further handling via reset flow
2310          */
2311         if (send_cq)
2312                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2313         if (recv_cq)
2314                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2315         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2316         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2317
2318         return 0;
2319
2320 err_create:
2321         if (qp->create_type == MLX5_QP_USER)
2322                 destroy_qp_user(dev, pd, qp, base, udata);
2323         else if (qp->create_type == MLX5_QP_KERNEL)
2324                 destroy_qp_kernel(dev, qp);
2325
2326 err:
2327         kvfree(in);
2328         return err;
2329 }
2330
2331 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2332         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2333 {
2334         if (send_cq) {
2335                 if (recv_cq) {
2336                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2337                                 spin_lock(&send_cq->lock);
2338                                 spin_lock_nested(&recv_cq->lock,
2339                                                  SINGLE_DEPTH_NESTING);
2340                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2341                                 spin_lock(&send_cq->lock);
2342                                 __acquire(&recv_cq->lock);
2343                         } else {
2344                                 spin_lock(&recv_cq->lock);
2345                                 spin_lock_nested(&send_cq->lock,
2346                                                  SINGLE_DEPTH_NESTING);
2347                         }
2348                 } else {
2349                         spin_lock(&send_cq->lock);
2350                         __acquire(&recv_cq->lock);
2351                 }
2352         } else if (recv_cq) {
2353                 spin_lock(&recv_cq->lock);
2354                 __acquire(&send_cq->lock);
2355         } else {
2356                 __acquire(&send_cq->lock);
2357                 __acquire(&recv_cq->lock);
2358         }
2359 }
2360
2361 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2362         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2363 {
2364         if (send_cq) {
2365                 if (recv_cq) {
2366                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2367                                 spin_unlock(&recv_cq->lock);
2368                                 spin_unlock(&send_cq->lock);
2369                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2370                                 __release(&recv_cq->lock);
2371                                 spin_unlock(&send_cq->lock);
2372                         } else {
2373                                 spin_unlock(&send_cq->lock);
2374                                 spin_unlock(&recv_cq->lock);
2375                         }
2376                 } else {
2377                         __release(&recv_cq->lock);
2378                         spin_unlock(&send_cq->lock);
2379                 }
2380         } else if (recv_cq) {
2381                 __release(&send_cq->lock);
2382                 spin_unlock(&recv_cq->lock);
2383         } else {
2384                 __release(&recv_cq->lock);
2385                 __release(&send_cq->lock);
2386         }
2387 }
2388
2389 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2390 {
2391         return to_mpd(qp->ibqp.pd);
2392 }
2393
2394 static void get_cqs(enum ib_qp_type qp_type,
2395                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2396                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2397 {
2398         switch (qp_type) {
2399         case IB_QPT_XRC_TGT:
2400                 *send_cq = NULL;
2401                 *recv_cq = NULL;
2402                 break;
2403         case MLX5_IB_QPT_REG_UMR:
2404         case IB_QPT_XRC_INI:
2405                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2406                 *recv_cq = NULL;
2407                 break;
2408
2409         case IB_QPT_SMI:
2410         case MLX5_IB_QPT_HW_GSI:
2411         case IB_QPT_RC:
2412         case IB_QPT_UC:
2413         case IB_QPT_UD:
2414         case IB_QPT_RAW_IPV6:
2415         case IB_QPT_RAW_ETHERTYPE:
2416         case IB_QPT_RAW_PACKET:
2417                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2418                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2419                 break;
2420
2421         case IB_QPT_MAX:
2422         default:
2423                 *send_cq = NULL;
2424                 *recv_cq = NULL;
2425                 break;
2426         }
2427 }
2428
2429 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2430                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2431                                 u8 lag_tx_affinity);
2432
2433 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2434                               struct ib_udata *udata)
2435 {
2436         struct mlx5_ib_cq *send_cq, *recv_cq;
2437         struct mlx5_ib_qp_base *base;
2438         unsigned long flags;
2439         int err;
2440
2441         if (qp->ibqp.rwq_ind_tbl) {
2442                 destroy_rss_raw_qp_tir(dev, qp);
2443                 return;
2444         }
2445
2446         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2447                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2448                &qp->raw_packet_qp.rq.base :
2449                &qp->trans_qp.base;
2450
2451         if (qp->state != IB_QPS_RESET) {
2452                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2453                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2454                         err = mlx5_core_qp_modify(dev->mdev,
2455                                                   MLX5_CMD_OP_2RST_QP, 0,
2456                                                   NULL, &base->mqp);
2457                 } else {
2458                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2459                                 .operation = MLX5_CMD_OP_2RST_QP
2460                         };
2461
2462                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2463                 }
2464                 if (err)
2465                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2466                                      base->mqp.qpn);
2467         }
2468
2469         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2470                 &send_cq, &recv_cq);
2471
2472         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2473         mlx5_ib_lock_cqs(send_cq, recv_cq);
2474         /* del from lists under both locks above to protect reset flow paths */
2475         list_del(&qp->qps_list);
2476         if (send_cq)
2477                 list_del(&qp->cq_send_list);
2478
2479         if (recv_cq)
2480                 list_del(&qp->cq_recv_list);
2481
2482         if (qp->create_type == MLX5_QP_KERNEL) {
2483                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2484                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2485                 if (send_cq != recv_cq)
2486                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2487                                            NULL);
2488         }
2489         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2490         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2491
2492         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2493             qp->flags & MLX5_IB_QP_UNDERLAY) {
2494                 destroy_raw_packet_qp(dev, qp);
2495         } else {
2496                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2497                 if (err)
2498                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2499                                      base->mqp.qpn);
2500         }
2501
2502         if (qp->create_type == MLX5_QP_KERNEL)
2503                 destroy_qp_kernel(dev, qp);
2504         else if (qp->create_type == MLX5_QP_USER)
2505                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata);
2506 }
2507
2508 static const char *ib_qp_type_str(enum ib_qp_type type)
2509 {
2510         switch (type) {
2511         case IB_QPT_SMI:
2512                 return "IB_QPT_SMI";
2513         case IB_QPT_GSI:
2514                 return "IB_QPT_GSI";
2515         case IB_QPT_RC:
2516                 return "IB_QPT_RC";
2517         case IB_QPT_UC:
2518                 return "IB_QPT_UC";
2519         case IB_QPT_UD:
2520                 return "IB_QPT_UD";
2521         case IB_QPT_RAW_IPV6:
2522                 return "IB_QPT_RAW_IPV6";
2523         case IB_QPT_RAW_ETHERTYPE:
2524                 return "IB_QPT_RAW_ETHERTYPE";
2525         case IB_QPT_XRC_INI:
2526                 return "IB_QPT_XRC_INI";
2527         case IB_QPT_XRC_TGT:
2528                 return "IB_QPT_XRC_TGT";
2529         case IB_QPT_RAW_PACKET:
2530                 return "IB_QPT_RAW_PACKET";
2531         case MLX5_IB_QPT_REG_UMR:
2532                 return "MLX5_IB_QPT_REG_UMR";
2533         case IB_QPT_DRIVER:
2534                 return "IB_QPT_DRIVER";
2535         case IB_QPT_MAX:
2536         default:
2537                 return "Invalid QP type";
2538         }
2539 }
2540
2541 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2542                                         struct ib_qp_init_attr *attr,
2543                                         struct mlx5_ib_create_qp *ucmd,
2544                                         struct ib_udata *udata)
2545 {
2546         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2547                 udata, struct mlx5_ib_ucontext, ibucontext);
2548         struct mlx5_ib_qp *qp;
2549         int err = 0;
2550         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2551         void *dctc;
2552
2553         if (!attr->srq || !attr->recv_cq)
2554                 return ERR_PTR(-EINVAL);
2555
2556         err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx);
2557         if (err)
2558                 return ERR_PTR(err);
2559
2560         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2561         if (!qp)
2562                 return ERR_PTR(-ENOMEM);
2563
2564         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2565         if (!qp->dct.in) {
2566                 err = -ENOMEM;
2567                 goto err_free;
2568         }
2569
2570         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2571         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2572         qp->qp_sub_type = MLX5_IB_QPT_DCT;
2573         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2574         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2575         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2576         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2577         MLX5_SET(dctc, dctc, user_index, uidx);
2578
2579         if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2580                 configure_responder_scat_cqe(attr, dctc);
2581
2582         qp->state = IB_QPS_RESET;
2583
2584         return &qp->ibqp;
2585 err_free:
2586         kfree(qp);
2587         return ERR_PTR(err);
2588 }
2589
2590 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2591                            struct ib_qp_init_attr *init_attr,
2592                            struct mlx5_ib_create_qp *ucmd,
2593                            struct ib_udata *udata)
2594 {
2595         enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2596         int err;
2597
2598         if (!udata)
2599                 return -EINVAL;
2600
2601         if (udata->inlen < sizeof(*ucmd)) {
2602                 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2603                 return -EINVAL;
2604         }
2605         err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2606         if (err)
2607                 return err;
2608
2609         if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2610                 init_attr->qp_type = MLX5_IB_QPT_DCI;
2611         } else {
2612                 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2613                         init_attr->qp_type = MLX5_IB_QPT_DCT;
2614                 } else {
2615                         mlx5_ib_dbg(dev, "Invalid QP flags\n");
2616                         return -EINVAL;
2617                 }
2618         }
2619
2620         if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2621                 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2622                 return -EOPNOTSUPP;
2623         }
2624
2625         return 0;
2626 }
2627
2628 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2629                                 struct ib_qp_init_attr *verbs_init_attr,
2630                                 struct ib_udata *udata)
2631 {
2632         struct mlx5_ib_dev *dev;
2633         struct mlx5_ib_qp *qp;
2634         u16 xrcdn = 0;
2635         int err;
2636         struct ib_qp_init_attr mlx_init_attr;
2637         struct ib_qp_init_attr *init_attr = verbs_init_attr;
2638         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2639                 udata, struct mlx5_ib_ucontext, ibucontext);
2640
2641         if (pd) {
2642                 dev = to_mdev(pd->device);
2643
2644                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2645                         if (!ucontext) {
2646                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2647                                 return ERR_PTR(-EINVAL);
2648                         } else if (!ucontext->cqe_version) {
2649                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2650                                 return ERR_PTR(-EINVAL);
2651                         }
2652                 }
2653         } else {
2654                 /* being cautious here */
2655                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2656                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2657                         pr_warn("%s: no PD for transport %s\n", __func__,
2658                                 ib_qp_type_str(init_attr->qp_type));
2659                         return ERR_PTR(-EINVAL);
2660                 }
2661                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2662         }
2663
2664         if (init_attr->qp_type == IB_QPT_DRIVER) {
2665                 struct mlx5_ib_create_qp ucmd;
2666
2667                 init_attr = &mlx_init_attr;
2668                 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2669                 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2670                 if (err)
2671                         return ERR_PTR(err);
2672
2673                 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2674                         if (init_attr->cap.max_recv_wr ||
2675                             init_attr->cap.max_recv_sge) {
2676                                 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2677                                 return ERR_PTR(-EINVAL);
2678                         }
2679                 } else {
2680                         return mlx5_ib_create_dct(pd, init_attr, &ucmd, udata);
2681                 }
2682         }
2683
2684         switch (init_attr->qp_type) {
2685         case IB_QPT_XRC_TGT:
2686         case IB_QPT_XRC_INI:
2687                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2688                         mlx5_ib_dbg(dev, "XRC not supported\n");
2689                         return ERR_PTR(-ENOSYS);
2690                 }
2691                 init_attr->recv_cq = NULL;
2692                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2693                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2694                         init_attr->send_cq = NULL;
2695                 }
2696
2697                 /* fall through */
2698         case IB_QPT_RAW_PACKET:
2699         case IB_QPT_RC:
2700         case IB_QPT_UC:
2701         case IB_QPT_UD:
2702         case IB_QPT_SMI:
2703         case MLX5_IB_QPT_HW_GSI:
2704         case MLX5_IB_QPT_REG_UMR:
2705         case MLX5_IB_QPT_DCI:
2706                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2707                 if (!qp)
2708                         return ERR_PTR(-ENOMEM);
2709
2710                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2711                 if (err) {
2712                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2713                         kfree(qp);
2714                         return ERR_PTR(err);
2715                 }
2716
2717                 if (is_qp0(init_attr->qp_type))
2718                         qp->ibqp.qp_num = 0;
2719                 else if (is_qp1(init_attr->qp_type))
2720                         qp->ibqp.qp_num = 1;
2721                 else
2722                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2723
2724                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2725                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2726                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2727                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2728
2729                 qp->trans_qp.xrcdn = xrcdn;
2730
2731                 break;
2732
2733         case IB_QPT_GSI:
2734                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2735
2736         case IB_QPT_RAW_IPV6:
2737         case IB_QPT_RAW_ETHERTYPE:
2738         case IB_QPT_MAX:
2739         default:
2740                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2741                             init_attr->qp_type);
2742                 /* Don't support raw QPs */
2743                 return ERR_PTR(-EINVAL);
2744         }
2745
2746         if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2747                 qp->qp_sub_type = init_attr->qp_type;
2748
2749         return &qp->ibqp;
2750 }
2751
2752 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2753 {
2754         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2755
2756         if (mqp->state == IB_QPS_RTR) {
2757                 int err;
2758
2759                 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2760                 if (err) {
2761                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2762                         return err;
2763                 }
2764         }
2765
2766         kfree(mqp->dct.in);
2767         kfree(mqp);
2768         return 0;
2769 }
2770
2771 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
2772 {
2773         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2774         struct mlx5_ib_qp *mqp = to_mqp(qp);
2775
2776         if (unlikely(qp->qp_type == IB_QPT_GSI))
2777                 return mlx5_ib_gsi_destroy_qp(qp);
2778
2779         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2780                 return mlx5_ib_destroy_dct(mqp);
2781
2782         destroy_qp_common(dev, mqp, udata);
2783
2784         kfree(mqp);
2785
2786         return 0;
2787 }
2788
2789 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2790                                 const struct ib_qp_attr *attr,
2791                                 int attr_mask, __be32 *hw_access_flags_be)
2792 {
2793         u8 dest_rd_atomic;
2794         u32 access_flags, hw_access_flags = 0;
2795
2796         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2797
2798         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2799                 dest_rd_atomic = attr->max_dest_rd_atomic;
2800         else
2801                 dest_rd_atomic = qp->trans_qp.resp_depth;
2802
2803         if (attr_mask & IB_QP_ACCESS_FLAGS)
2804                 access_flags = attr->qp_access_flags;
2805         else
2806                 access_flags = qp->trans_qp.atomic_rd_en;
2807
2808         if (!dest_rd_atomic)
2809                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2810
2811         if (access_flags & IB_ACCESS_REMOTE_READ)
2812                 hw_access_flags |= MLX5_QP_BIT_RRE;
2813         if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
2814                 int atomic_mode;
2815
2816                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2817                 if (atomic_mode < 0)
2818                         return -EOPNOTSUPP;
2819
2820                 hw_access_flags |= MLX5_QP_BIT_RAE;
2821                 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2822         }
2823
2824         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2825                 hw_access_flags |= MLX5_QP_BIT_RWE;
2826
2827         *hw_access_flags_be = cpu_to_be32(hw_access_flags);
2828
2829         return 0;
2830 }
2831
2832 enum {
2833         MLX5_PATH_FLAG_FL       = 1 << 0,
2834         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2835         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2836 };
2837
2838 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2839 {
2840         if (rate == IB_RATE_PORT_CURRENT)
2841                 return 0;
2842
2843         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
2844                 return -EINVAL;
2845
2846         while (rate != IB_RATE_PORT_CURRENT &&
2847                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2848                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2849                 --rate;
2850
2851         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2852 }
2853
2854 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2855                                       struct mlx5_ib_sq *sq, u8 sl,
2856                                       struct ib_pd *pd)
2857 {
2858         void *in;
2859         void *tisc;
2860         int inlen;
2861         int err;
2862
2863         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2864         in = kvzalloc(inlen, GFP_KERNEL);
2865         if (!in)
2866                 return -ENOMEM;
2867
2868         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2869         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2870
2871         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2872         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2873
2874         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2875
2876         kvfree(in);
2877
2878         return err;
2879 }
2880
2881 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2882                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
2883                                          struct ib_pd *pd)
2884 {
2885         void *in;
2886         void *tisc;
2887         int inlen;
2888         int err;
2889
2890         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2891         in = kvzalloc(inlen, GFP_KERNEL);
2892         if (!in)
2893                 return -ENOMEM;
2894
2895         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2896         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2897
2898         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2899         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2900
2901         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2902
2903         kvfree(in);
2904
2905         return err;
2906 }
2907
2908 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2909                          const struct rdma_ah_attr *ah,
2910                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2911                          u32 path_flags, const struct ib_qp_attr *attr,
2912                          bool alt)
2913 {
2914         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2915         int err;
2916         enum ib_gid_type gid_type;
2917         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2918         u8 sl = rdma_ah_get_sl(ah);
2919
2920         if (attr_mask & IB_QP_PKEY_INDEX)
2921                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2922                                                      attr->pkey_index);
2923
2924         if (ah_flags & IB_AH_GRH) {
2925                 if (grh->sgid_index >=
2926                     dev->mdev->port_caps[port - 1].gid_table_len) {
2927                         pr_err("sgid_index (%u) too large. max is %d\n",
2928                                grh->sgid_index,
2929                                dev->mdev->port_caps[port - 1].gid_table_len);
2930                         return -EINVAL;
2931                 }
2932         }
2933
2934         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2935                 if (!(ah_flags & IB_AH_GRH))
2936                         return -EINVAL;
2937
2938                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2939                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2940                     qp->ibqp.qp_type == IB_QPT_UC ||
2941                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2942                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2943                         path->udp_sport =
2944                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2945                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2946                 gid_type = ah->grh.sgid_attr->gid_type;
2947                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2948                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2949         } else {
2950                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2951                 path->fl_free_ar |=
2952                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2953                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2954                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2955                 if (ah_flags & IB_AH_GRH)
2956                         path->grh_mlid  |= 1 << 7;
2957                 path->dci_cfi_prio_sl = sl & 0xf;
2958         }
2959
2960         if (ah_flags & IB_AH_GRH) {
2961                 path->mgid_index = grh->sgid_index;
2962                 path->hop_limit  = grh->hop_limit;
2963                 path->tclass_flowlabel =
2964                         cpu_to_be32((grh->traffic_class << 20) |
2965                                     (grh->flow_label));
2966                 memcpy(path->rgid, grh->dgid.raw, 16);
2967         }
2968
2969         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2970         if (err < 0)
2971                 return err;
2972         path->static_rate = err;
2973         path->port = port;
2974
2975         if (attr_mask & IB_QP_TIMEOUT)
2976                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2977
2978         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2979                 return modify_raw_packet_eth_prio(dev->mdev,
2980                                                   &qp->raw_packet_qp.sq,
2981                                                   sl & 0xf, qp->ibqp.pd);
2982
2983         return 0;
2984 }
2985
2986 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2987         [MLX5_QP_STATE_INIT] = {
2988                 [MLX5_QP_STATE_INIT] = {
2989                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2990                                           MLX5_QP_OPTPAR_RAE            |
2991                                           MLX5_QP_OPTPAR_RWE            |
2992                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2993                                           MLX5_QP_OPTPAR_PRI_PORT,
2994                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2995                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2996                                           MLX5_QP_OPTPAR_PRI_PORT,
2997                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2998                                           MLX5_QP_OPTPAR_Q_KEY          |
2999                                           MLX5_QP_OPTPAR_PRI_PORT,
3000                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3001                                           MLX5_QP_OPTPAR_RAE            |
3002                                           MLX5_QP_OPTPAR_RWE            |
3003                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
3004                                           MLX5_QP_OPTPAR_PRI_PORT,
3005                 },
3006                 [MLX5_QP_STATE_RTR] = {
3007                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3008                                           MLX5_QP_OPTPAR_RRE            |
3009                                           MLX5_QP_OPTPAR_RAE            |
3010                                           MLX5_QP_OPTPAR_RWE            |
3011                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3012                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3013                                           MLX5_QP_OPTPAR_RWE            |
3014                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3015                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
3016                                           MLX5_QP_OPTPAR_Q_KEY,
3017                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
3018                                            MLX5_QP_OPTPAR_Q_KEY,
3019                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3020                                           MLX5_QP_OPTPAR_RRE            |
3021                                           MLX5_QP_OPTPAR_RAE            |
3022                                           MLX5_QP_OPTPAR_RWE            |
3023                                           MLX5_QP_OPTPAR_PKEY_INDEX,
3024                 },
3025         },
3026         [MLX5_QP_STATE_RTR] = {
3027                 [MLX5_QP_STATE_RTS] = {
3028                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3029                                           MLX5_QP_OPTPAR_RRE            |
3030                                           MLX5_QP_OPTPAR_RAE            |
3031                                           MLX5_QP_OPTPAR_RWE            |
3032                                           MLX5_QP_OPTPAR_PM_STATE       |
3033                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3034                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
3035                                           MLX5_QP_OPTPAR_RWE            |
3036                                           MLX5_QP_OPTPAR_PM_STATE,
3037                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3038                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3039                                           MLX5_QP_OPTPAR_RRE            |
3040                                           MLX5_QP_OPTPAR_RAE            |
3041                                           MLX5_QP_OPTPAR_RWE            |
3042                                           MLX5_QP_OPTPAR_PM_STATE       |
3043                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
3044                 },
3045         },
3046         [MLX5_QP_STATE_RTS] = {
3047                 [MLX5_QP_STATE_RTS] = {
3048                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
3049                                           MLX5_QP_OPTPAR_RAE            |
3050                                           MLX5_QP_OPTPAR_RWE            |
3051                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3052                                           MLX5_QP_OPTPAR_PM_STATE       |
3053                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3054                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
3055                                           MLX5_QP_OPTPAR_PM_STATE       |
3056                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3057                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
3058                                           MLX5_QP_OPTPAR_SRQN           |
3059                                           MLX5_QP_OPTPAR_CQN_RCV,
3060                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE           |
3061                                           MLX5_QP_OPTPAR_RAE            |
3062                                           MLX5_QP_OPTPAR_RWE            |
3063                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
3064                                           MLX5_QP_OPTPAR_PM_STATE       |
3065                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
3066                 },
3067         },
3068         [MLX5_QP_STATE_SQER] = {
3069                 [MLX5_QP_STATE_RTS] = {
3070                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
3071                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
3072                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
3073                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
3074                                            MLX5_QP_OPTPAR_RWE           |
3075                                            MLX5_QP_OPTPAR_RAE           |
3076                                            MLX5_QP_OPTPAR_RRE,
3077                         [MLX5_QP_ST_XRC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT  |
3078                                            MLX5_QP_OPTPAR_RWE           |
3079                                            MLX5_QP_OPTPAR_RAE           |
3080                                            MLX5_QP_OPTPAR_RRE,
3081                 },
3082         },
3083 };
3084
3085 static int ib_nr_to_mlx5_nr(int ib_mask)
3086 {
3087         switch (ib_mask) {
3088         case IB_QP_STATE:
3089                 return 0;
3090         case IB_QP_CUR_STATE:
3091                 return 0;
3092         case IB_QP_EN_SQD_ASYNC_NOTIFY:
3093                 return 0;
3094         case IB_QP_ACCESS_FLAGS:
3095                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3096                         MLX5_QP_OPTPAR_RAE;
3097         case IB_QP_PKEY_INDEX:
3098                 return MLX5_QP_OPTPAR_PKEY_INDEX;
3099         case IB_QP_PORT:
3100                 return MLX5_QP_OPTPAR_PRI_PORT;
3101         case IB_QP_QKEY:
3102                 return MLX5_QP_OPTPAR_Q_KEY;
3103         case IB_QP_AV:
3104                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3105                         MLX5_QP_OPTPAR_PRI_PORT;
3106         case IB_QP_PATH_MTU:
3107                 return 0;
3108         case IB_QP_TIMEOUT:
3109                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3110         case IB_QP_RETRY_CNT:
3111                 return MLX5_QP_OPTPAR_RETRY_COUNT;
3112         case IB_QP_RNR_RETRY:
3113                 return MLX5_QP_OPTPAR_RNR_RETRY;
3114         case IB_QP_RQ_PSN:
3115                 return 0;
3116         case IB_QP_MAX_QP_RD_ATOMIC:
3117                 return MLX5_QP_OPTPAR_SRA_MAX;
3118         case IB_QP_ALT_PATH:
3119                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3120         case IB_QP_MIN_RNR_TIMER:
3121                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3122         case IB_QP_SQ_PSN:
3123                 return 0;
3124         case IB_QP_MAX_DEST_RD_ATOMIC:
3125                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3126                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3127         case IB_QP_PATH_MIG_STATE:
3128                 return MLX5_QP_OPTPAR_PM_STATE;
3129         case IB_QP_CAP:
3130                 return 0;
3131         case IB_QP_DEST_QPN:
3132                 return 0;
3133         }
3134         return 0;
3135 }
3136
3137 static int ib_mask_to_mlx5_opt(int ib_mask)
3138 {
3139         int result = 0;
3140         int i;
3141
3142         for (i = 0; i < 8 * sizeof(int); i++) {
3143                 if ((1 << i) & ib_mask)
3144                         result |= ib_nr_to_mlx5_nr(1 << i);
3145         }
3146
3147         return result;
3148 }
3149
3150 static int modify_raw_packet_qp_rq(
3151         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3152         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3153 {
3154         void *in;
3155         void *rqc;
3156         int inlen;
3157         int err;
3158
3159         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3160         in = kvzalloc(inlen, GFP_KERNEL);
3161         if (!in)
3162                 return -ENOMEM;
3163
3164         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3165         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3166
3167         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3168         MLX5_SET(rqc, rqc, state, new_state);
3169
3170         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3171                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3172                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
3173                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3174                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3175                 } else
3176                         dev_info_once(
3177                                 &dev->ib_dev.dev,
3178                                 "RAW PACKET QP counters are not supported on current FW\n");
3179         }
3180
3181         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
3182         if (err)
3183                 goto out;
3184
3185         rq->state = new_state;
3186
3187 out:
3188         kvfree(in);
3189         return err;
3190 }
3191
3192 static int modify_raw_packet_qp_sq(
3193         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3194         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3195 {
3196         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3197         struct mlx5_rate_limit old_rl = ibqp->rl;
3198         struct mlx5_rate_limit new_rl = old_rl;
3199         bool new_rate_added = false;
3200         u16 rl_index = 0;
3201         void *in;
3202         void *sqc;
3203         int inlen;
3204         int err;
3205
3206         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3207         in = kvzalloc(inlen, GFP_KERNEL);
3208         if (!in)
3209                 return -ENOMEM;
3210
3211         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3212         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3213
3214         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3215         MLX5_SET(sqc, sqc, state, new_state);
3216
3217         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3218                 if (new_state != MLX5_SQC_STATE_RDY)
3219                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3220                                 __func__);
3221                 else
3222                         new_rl = raw_qp_param->rl;
3223         }
3224
3225         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3226                 if (new_rl.rate) {
3227                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3228                         if (err) {
3229                                 pr_err("Failed configuring rate limit(err %d): \
3230                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3231                                        err, new_rl.rate, new_rl.max_burst_sz,
3232                                        new_rl.typical_pkt_sz);
3233
3234                                 goto out;
3235                         }
3236                         new_rate_added = true;
3237                 }
3238
3239                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3240                 /* index 0 means no limit */
3241                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3242         }
3243
3244         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
3245         if (err) {
3246                 /* Remove new rate from table if failed */
3247                 if (new_rate_added)
3248                         mlx5_rl_remove_rate(dev, &new_rl);
3249                 goto out;
3250         }
3251
3252         /* Only remove the old rate after new rate was set */
3253         if ((old_rl.rate &&
3254              !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3255             (new_state != MLX5_SQC_STATE_RDY))
3256                 mlx5_rl_remove_rate(dev, &old_rl);
3257
3258         ibqp->rl = new_rl;
3259         sq->state = new_state;
3260
3261 out:
3262         kvfree(in);
3263         return err;
3264 }
3265
3266 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3267                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3268                                 u8 tx_affinity)
3269 {
3270         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3271         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3272         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3273         int modify_rq = !!qp->rq.wqe_cnt;
3274         int modify_sq = !!qp->sq.wqe_cnt;
3275         int rq_state;
3276         int sq_state;
3277         int err;
3278
3279         switch (raw_qp_param->operation) {
3280         case MLX5_CMD_OP_RST2INIT_QP:
3281                 rq_state = MLX5_RQC_STATE_RDY;
3282                 sq_state = MLX5_SQC_STATE_RDY;
3283                 break;
3284         case MLX5_CMD_OP_2ERR_QP:
3285                 rq_state = MLX5_RQC_STATE_ERR;
3286                 sq_state = MLX5_SQC_STATE_ERR;
3287                 break;
3288         case MLX5_CMD_OP_2RST_QP:
3289                 rq_state = MLX5_RQC_STATE_RST;
3290                 sq_state = MLX5_SQC_STATE_RST;
3291                 break;
3292         case MLX5_CMD_OP_RTR2RTS_QP:
3293         case MLX5_CMD_OP_RTS2RTS_QP:
3294                 if (raw_qp_param->set_mask ==
3295                     MLX5_RAW_QP_RATE_LIMIT) {
3296                         modify_rq = 0;
3297                         sq_state = sq->state;
3298                 } else {
3299                         return raw_qp_param->set_mask ? -EINVAL : 0;
3300                 }
3301                 break;
3302         case MLX5_CMD_OP_INIT2INIT_QP:
3303         case MLX5_CMD_OP_INIT2RTR_QP:
3304                 if (raw_qp_param->set_mask)
3305                         return -EINVAL;
3306                 else
3307                         return 0;
3308         default:
3309                 WARN_ON(1);
3310                 return -EINVAL;
3311         }
3312
3313         if (modify_rq) {
3314                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3315                                                qp->ibqp.pd);
3316                 if (err)
3317                         return err;
3318         }
3319
3320         if (modify_sq) {
3321                 struct mlx5_flow_handle *flow_rule;
3322
3323                 if (tx_affinity) {
3324                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3325                                                             tx_affinity,
3326                                                             qp->ibqp.pd);
3327                         if (err)
3328                                 return err;
3329                 }
3330
3331                 flow_rule = create_flow_rule_vport_sq(dev, sq,
3332                                                       raw_qp_param->port);
3333                 if (IS_ERR(flow_rule))
3334                         return PTR_ERR(flow_rule);
3335
3336                 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3337                                               raw_qp_param, qp->ibqp.pd);
3338                 if (err) {
3339                         if (flow_rule)
3340                                 mlx5_del_flow_rules(flow_rule);
3341                         return err;
3342                 }
3343
3344                 if (flow_rule) {
3345                         destroy_flow_rule_vport_sq(sq);
3346                         sq->flow_rule = flow_rule;
3347                 }
3348
3349                 return err;
3350         }
3351
3352         return 0;
3353 }
3354
3355 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3356                                     struct mlx5_ib_pd *pd,
3357                                     struct mlx5_ib_qp_base *qp_base,
3358                                     u8 port_num, struct ib_udata *udata)
3359 {
3360         struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3361                 udata, struct mlx5_ib_ucontext, ibucontext);
3362         unsigned int tx_port_affinity;
3363
3364         if (ucontext) {
3365                 tx_port_affinity = (unsigned int)atomic_add_return(
3366                                            1, &ucontext->tx_port_affinity) %
3367                                            MLX5_MAX_PORTS +
3368                                    1;
3369                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3370                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3371         } else {
3372                 tx_port_affinity =
3373                         (unsigned int)atomic_add_return(
3374                                 1, &dev->port[port_num].roce.tx_port_affinity) %
3375                                 MLX5_MAX_PORTS +
3376                         1;
3377                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3378                                 tx_port_affinity, qp_base->mqp.qpn);
3379         }
3380
3381         return tx_port_affinity;
3382 }
3383
3384 static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3385                                     struct rdma_counter *counter)
3386 {
3387         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3388         struct mlx5_ib_qp *mqp = to_mqp(qp);
3389         struct mlx5_qp_context context = {};
3390         struct mlx5_ib_port *mibport = NULL;
3391         struct mlx5_ib_qp_base *base;
3392         u32 set_id;
3393
3394         if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id))
3395                 return 0;
3396
3397         if (counter) {
3398                 set_id = counter->id;
3399         } else {
3400                 mibport = &dev->port[mqp->port - 1];
3401                 set_id = mibport->cnts.set_id;
3402         }
3403
3404         base = &mqp->trans_qp.base;
3405         context.qp_counter_set_usr_page &= cpu_to_be32(0xffffff);
3406         context.qp_counter_set_usr_page |= cpu_to_be32(set_id << 24);
3407         return mlx5_core_qp_modify(dev->mdev,
3408                                    MLX5_CMD_OP_RTS2RTS_QP,
3409                                    MLX5_QP_OPTPAR_COUNTER_SET_ID,
3410                                    &context, &base->mqp);
3411 }
3412
3413 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3414                                const struct ib_qp_attr *attr, int attr_mask,
3415                                enum ib_qp_state cur_state,
3416                                enum ib_qp_state new_state,
3417                                const struct mlx5_ib_modify_qp *ucmd,
3418                                struct ib_udata *udata)
3419 {
3420         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3421                 [MLX5_QP_STATE_RST] = {
3422                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3423                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3424                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3425                 },
3426                 [MLX5_QP_STATE_INIT]  = {
3427                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3428                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3429                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3430                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3431                 },
3432                 [MLX5_QP_STATE_RTR]   = {
3433                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3434                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3435                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3436                 },
3437                 [MLX5_QP_STATE_RTS]   = {
3438                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3439                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3440                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3441                 },
3442                 [MLX5_QP_STATE_SQD] = {
3443                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3444                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3445                 },
3446                 [MLX5_QP_STATE_SQER] = {
3447                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3448                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3449                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3450                 },
3451                 [MLX5_QP_STATE_ERR] = {
3452                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3453                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3454                 }
3455         };
3456
3457         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3458         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3459         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3460         struct mlx5_ib_cq *send_cq, *recv_cq;
3461         struct mlx5_qp_context *context;
3462         struct mlx5_ib_pd *pd;
3463         struct mlx5_ib_port *mibport = NULL;
3464         enum mlx5_qp_state mlx5_cur, mlx5_new;
3465         enum mlx5_qp_optpar optpar;
3466         u32 set_id = 0;
3467         int mlx5_st;
3468         int err;
3469         u16 op;
3470         u8 tx_affinity = 0;
3471
3472         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3473                              qp->qp_sub_type : ibqp->qp_type);
3474         if (mlx5_st < 0)
3475                 return -EINVAL;
3476
3477         context = kzalloc(sizeof(*context), GFP_KERNEL);
3478         if (!context)
3479                 return -ENOMEM;
3480
3481         pd = get_pd(qp);
3482         context->flags = cpu_to_be32(mlx5_st << 16);
3483
3484         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3485                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3486         } else {
3487                 switch (attr->path_mig_state) {
3488                 case IB_MIG_MIGRATED:
3489                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3490                         break;
3491                 case IB_MIG_REARM:
3492                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3493                         break;
3494                 case IB_MIG_ARMED:
3495                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3496                         break;
3497                 }
3498         }
3499
3500         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3501                 if ((ibqp->qp_type == IB_QPT_RC) ||
3502                     (ibqp->qp_type == IB_QPT_UD &&
3503                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3504                     (ibqp->qp_type == IB_QPT_UC) ||
3505                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3506                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3507                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3508                         if (dev->lag_active) {
3509                                 u8 p = mlx5_core_native_port_num(dev->mdev) - 1;
3510                                 tx_affinity = get_tx_affinity(dev, pd, base, p,
3511                                                               udata);
3512                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3513                         }
3514                 }
3515         }
3516
3517         if (is_sqp(ibqp->qp_type)) {
3518                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3519         } else if ((ibqp->qp_type == IB_QPT_UD &&
3520                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3521                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3522                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3523         } else if (attr_mask & IB_QP_PATH_MTU) {
3524                 if (attr->path_mtu < IB_MTU_256 ||
3525                     attr->path_mtu > IB_MTU_4096) {
3526                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3527                         err = -EINVAL;
3528                         goto out;
3529                 }
3530                 context->mtu_msgmax = (attr->path_mtu << 5) |
3531                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3532         }
3533
3534         if (attr_mask & IB_QP_DEST_QPN)
3535                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3536
3537         if (attr_mask & IB_QP_PKEY_INDEX)
3538                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3539
3540         /* todo implement counter_index functionality */
3541
3542         if (is_sqp(ibqp->qp_type))
3543                 context->pri_path.port = qp->port;
3544
3545         if (attr_mask & IB_QP_PORT)
3546                 context->pri_path.port = attr->port_num;
3547
3548         if (attr_mask & IB_QP_AV) {
3549                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3550                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3551                                     attr_mask, 0, attr, false);
3552                 if (err)
3553                         goto out;
3554         }
3555
3556         if (attr_mask & IB_QP_TIMEOUT)
3557                 context->pri_path.ackto_lt |= attr->timeout << 3;
3558
3559         if (attr_mask & IB_QP_ALT_PATH) {
3560                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3561                                     &context->alt_path,
3562                                     attr->alt_port_num,
3563                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3564                                     0, attr, true);
3565                 if (err)
3566                         goto out;
3567         }
3568
3569         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3570                 &send_cq, &recv_cq);
3571
3572         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3573         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3574         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3575         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3576
3577         if (attr_mask & IB_QP_RNR_RETRY)
3578                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3579
3580         if (attr_mask & IB_QP_RETRY_CNT)
3581                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3582
3583         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3584                 if (attr->max_rd_atomic)
3585                         context->params1 |=
3586                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3587         }
3588
3589         if (attr_mask & IB_QP_SQ_PSN)
3590                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3591
3592         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3593                 if (attr->max_dest_rd_atomic)
3594                         context->params2 |=
3595                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3596         }
3597
3598         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3599                 __be32 access_flags;
3600
3601                 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3602                 if (err)
3603                         goto out;
3604
3605                 context->params2 |= access_flags;
3606         }
3607
3608         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3609                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3610
3611         if (attr_mask & IB_QP_RQ_PSN)
3612                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3613
3614         if (attr_mask & IB_QP_QKEY)
3615                 context->qkey = cpu_to_be32(attr->qkey);
3616
3617         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3618                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3619
3620         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3621                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3622                                qp->port) - 1;
3623
3624                 /* Underlay port should be used - index 0 function per port */
3625                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3626                         port_num = 0;
3627
3628                 mibport = &dev->port[port_num];
3629                 if (ibqp->counter)
3630                         set_id = ibqp->counter->id;
3631                 else
3632                         set_id = mibport->cnts.set_id;
3633                 context->qp_counter_set_usr_page |=
3634                         cpu_to_be32(set_id << 24);
3635         }
3636
3637         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3638                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3639
3640         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3641                 context->deth_sqpn = cpu_to_be32(1);
3642
3643         mlx5_cur = to_mlx5_state(cur_state);
3644         mlx5_new = to_mlx5_state(new_state);
3645
3646         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3647             !optab[mlx5_cur][mlx5_new]) {
3648                 err = -EINVAL;
3649                 goto out;
3650         }
3651
3652         op = optab[mlx5_cur][mlx5_new];
3653         optpar = ib_mask_to_mlx5_opt(attr_mask);
3654         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3655
3656         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3657             qp->flags & MLX5_IB_QP_UNDERLAY) {
3658                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3659
3660                 raw_qp_param.operation = op;
3661                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3662                         raw_qp_param.rq_q_ctr_id = set_id;
3663                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3664                 }
3665
3666                 if (attr_mask & IB_QP_PORT)
3667                         raw_qp_param.port = attr->port_num;
3668
3669                 if (attr_mask & IB_QP_RATE_LIMIT) {
3670                         raw_qp_param.rl.rate = attr->rate_limit;
3671
3672                         if (ucmd->burst_info.max_burst_sz) {
3673                                 if (attr->rate_limit &&
3674                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3675                                         raw_qp_param.rl.max_burst_sz =
3676                                                 ucmd->burst_info.max_burst_sz;
3677                                 } else {
3678                                         err = -EINVAL;
3679                                         goto out;
3680                                 }
3681                         }
3682
3683                         if (ucmd->burst_info.typical_pkt_sz) {
3684                                 if (attr->rate_limit &&
3685                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3686                                         raw_qp_param.rl.typical_pkt_sz =
3687                                                 ucmd->burst_info.typical_pkt_sz;
3688                                 } else {
3689                                         err = -EINVAL;
3690                                         goto out;
3691                                 }
3692                         }
3693
3694                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3695                 }
3696
3697                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3698         } else {
3699                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3700                                           &base->mqp);
3701         }
3702
3703         if (err)
3704                 goto out;
3705
3706         qp->state = new_state;
3707
3708         if (attr_mask & IB_QP_ACCESS_FLAGS)
3709                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3710         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3711                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3712         if (attr_mask & IB_QP_PORT)
3713                 qp->port = attr->port_num;
3714         if (attr_mask & IB_QP_ALT_PATH)
3715                 qp->trans_qp.alt_port = attr->alt_port_num;
3716
3717         /*
3718          * If we moved a kernel QP to RESET, clean up all old CQ
3719          * entries and reinitialize the QP.
3720          */
3721         if (new_state == IB_QPS_RESET &&
3722             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3723                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3724                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3725                 if (send_cq != recv_cq)
3726                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3727
3728                 qp->rq.head = 0;
3729                 qp->rq.tail = 0;
3730                 qp->sq.head = 0;
3731                 qp->sq.tail = 0;
3732                 qp->sq.cur_post = 0;
3733                 if (qp->sq.wqe_cnt)
3734                         qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
3735                 qp->db.db[MLX5_RCV_DBR] = 0;
3736                 qp->db.db[MLX5_SND_DBR] = 0;
3737         }
3738
3739         if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
3740                 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
3741                 if (!err)
3742                         qp->counter_pending = 0;
3743         }
3744
3745 out:
3746         kfree(context);
3747         return err;
3748 }
3749
3750 static inline bool is_valid_mask(int mask, int req, int opt)
3751 {
3752         if ((mask & req) != req)
3753                 return false;
3754
3755         if (mask & ~(req | opt))
3756                 return false;
3757
3758         return true;
3759 }
3760
3761 /* check valid transition for driver QP types
3762  * for now the only QP type that this function supports is DCI
3763  */
3764 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3765                                 enum ib_qp_attr_mask attr_mask)
3766 {
3767         int req = IB_QP_STATE;
3768         int opt = 0;
3769
3770         if (new_state == IB_QPS_RESET) {
3771                 return is_valid_mask(attr_mask, req, opt);
3772         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3773                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3774                 return is_valid_mask(attr_mask, req, opt);
3775         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3776                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3777                 return is_valid_mask(attr_mask, req, opt);
3778         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3779                 req |= IB_QP_PATH_MTU;
3780                 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
3781                 return is_valid_mask(attr_mask, req, opt);
3782         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3783                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3784                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3785                 opt = IB_QP_MIN_RNR_TIMER;
3786                 return is_valid_mask(attr_mask, req, opt);
3787         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3788                 opt = IB_QP_MIN_RNR_TIMER;
3789                 return is_valid_mask(attr_mask, req, opt);
3790         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3791                 return is_valid_mask(attr_mask, req, opt);
3792         }
3793         return false;
3794 }
3795
3796 /* mlx5_ib_modify_dct: modify a DCT QP
3797  * valid transitions are:
3798  * RESET to INIT: must set access_flags, pkey_index and port
3799  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3800  *                         mtu, gid_index and hop_limit
3801  * Other transitions and attributes are illegal
3802  */
3803 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3804                               int attr_mask, struct ib_udata *udata)
3805 {
3806         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3807         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3808         enum ib_qp_state cur_state, new_state;
3809         int err = 0;
3810         int required = IB_QP_STATE;
3811         void *dctc;
3812
3813         if (!(attr_mask & IB_QP_STATE))
3814                 return -EINVAL;
3815
3816         cur_state = qp->state;
3817         new_state = attr->qp_state;
3818
3819         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3820         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3821                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3822                 if (!is_valid_mask(attr_mask, required, 0))
3823                         return -EINVAL;
3824
3825                 if (attr->port_num == 0 ||
3826                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3827                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3828                                     attr->port_num, dev->num_ports);
3829                         return -EINVAL;
3830                 }
3831                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3832                         MLX5_SET(dctc, dctc, rre, 1);
3833                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3834                         MLX5_SET(dctc, dctc, rwe, 1);
3835                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3836                         int atomic_mode;
3837
3838                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3839                         if (atomic_mode < 0)
3840                                 return -EOPNOTSUPP;
3841
3842                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
3843                         MLX5_SET(dctc, dctc, rae, 1);
3844                 }
3845                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3846                 MLX5_SET(dctc, dctc, port, attr->port_num);
3847                 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3848
3849         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3850                 struct mlx5_ib_modify_qp_resp resp = {};
3851                 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0};
3852                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3853                                    sizeof(resp.dctn);
3854
3855                 if (udata->outlen < min_resp_len)
3856                         return -EINVAL;
3857                 resp.response_length = min_resp_len;
3858
3859                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3860                 if (!is_valid_mask(attr_mask, required, 0))
3861                         return -EINVAL;
3862                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3863                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3864                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3865                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3866                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3867                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3868
3869                 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3870                                            MLX5_ST_SZ_BYTES(create_dct_in), out,
3871                                            sizeof(out));
3872                 if (err)
3873                         return err;
3874                 resp.dctn = qp->dct.mdct.mqp.qpn;
3875                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3876                 if (err) {
3877                         mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3878                         return err;
3879                 }
3880         } else {
3881                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3882                 return -EINVAL;
3883         }
3884         if (err)
3885                 qp->state = IB_QPS_ERR;
3886         else
3887                 qp->state = new_state;
3888         return err;
3889 }
3890
3891 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3892                       int attr_mask, struct ib_udata *udata)
3893 {
3894         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3895         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3896         struct mlx5_ib_modify_qp ucmd = {};
3897         enum ib_qp_type qp_type;
3898         enum ib_qp_state cur_state, new_state;
3899         size_t required_cmd_sz;
3900         int err = -EINVAL;
3901         int port;
3902
3903         if (ibqp->rwq_ind_tbl)
3904                 return -ENOSYS;
3905
3906         if (udata && udata->inlen) {
3907                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3908                         sizeof(ucmd.reserved);
3909                 if (udata->inlen < required_cmd_sz)
3910                         return -EINVAL;
3911
3912                 if (udata->inlen > sizeof(ucmd) &&
3913                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3914                                          udata->inlen - sizeof(ucmd)))
3915                         return -EOPNOTSUPP;
3916
3917                 if (ib_copy_from_udata(&ucmd, udata,
3918                                        min(udata->inlen, sizeof(ucmd))))
3919                         return -EFAULT;
3920
3921                 if (ucmd.comp_mask ||
3922                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3923                     memchr_inv(&ucmd.burst_info.reserved, 0,
3924                                sizeof(ucmd.burst_info.reserved)))
3925                         return -EOPNOTSUPP;
3926         }
3927
3928         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3929                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3930
3931         if (ibqp->qp_type == IB_QPT_DRIVER)
3932                 qp_type = qp->qp_sub_type;
3933         else
3934                 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3935                         IB_QPT_GSI : ibqp->qp_type;
3936
3937         if (qp_type == MLX5_IB_QPT_DCT)
3938                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3939
3940         mutex_lock(&qp->mutex);
3941
3942         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3943         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3944
3945         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3946                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3947         }
3948
3949         if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3950                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3951                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3952                                     attr_mask);
3953                         goto out;
3954                 }
3955         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3956                    qp_type != MLX5_IB_QPT_DCI &&
3957                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3958                                        attr_mask)) {
3959                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3960                             cur_state, new_state, ibqp->qp_type, attr_mask);
3961                 goto out;
3962         } else if (qp_type == MLX5_IB_QPT_DCI &&
3963                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3964                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3965                             cur_state, new_state, qp_type, attr_mask);
3966                 goto out;
3967         }
3968
3969         if ((attr_mask & IB_QP_PORT) &&
3970             (attr->port_num == 0 ||
3971              attr->port_num > dev->num_ports)) {
3972                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3973                             attr->port_num, dev->num_ports);
3974                 goto out;
3975         }
3976
3977         if (attr_mask & IB_QP_PKEY_INDEX) {
3978                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3979                 if (attr->pkey_index >=
3980                     dev->mdev->port_caps[port - 1].pkey_table_len) {
3981                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3982                                     attr->pkey_index);
3983                         goto out;
3984                 }
3985         }
3986
3987         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3988             attr->max_rd_atomic >
3989             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3990                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3991                             attr->max_rd_atomic);
3992                 goto out;
3993         }
3994
3995         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3996             attr->max_dest_rd_atomic >
3997             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3998                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3999                             attr->max_dest_rd_atomic);
4000                 goto out;
4001         }
4002
4003         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4004                 err = 0;
4005                 goto out;
4006         }
4007
4008         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
4009                                   new_state, &ucmd, udata);
4010
4011 out:
4012         mutex_unlock(&qp->mutex);
4013         return err;
4014 }
4015
4016 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4017                                    u32 wqe_sz, void **cur_edge)
4018 {
4019         u32 idx;
4020
4021         idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
4022         *cur_edge = get_sq_edge(sq, idx);
4023
4024         *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
4025 }
4026
4027 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
4028  * next nearby edge and get new address translation for current WQE position.
4029  * @sq - SQ buffer.
4030  * @seg: Current WQE position (16B aligned).
4031  * @wqe_sz: Total current WQE size [16B].
4032  * @cur_edge: Updated current edge.
4033  */
4034 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
4035                                          u32 wqe_sz, void **cur_edge)
4036 {
4037         if (likely(*seg != *cur_edge))
4038                 return;
4039
4040         _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
4041 }
4042
4043 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
4044  * pointers. At the end @seg is aligned to 16B regardless the copied size.
4045  * @sq - SQ buffer.
4046  * @cur_edge: Updated current edge.
4047  * @seg: Current WQE position (16B aligned).
4048  * @wqe_sz: Total current WQE size [16B].
4049  * @src: Pointer to copy from.
4050  * @n: Number of bytes to copy.
4051  */
4052 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
4053                                    void **seg, u32 *wqe_sz, const void *src,
4054                                    size_t n)
4055 {
4056         while (likely(n)) {
4057                 size_t leftlen = *cur_edge - *seg;
4058                 size_t copysz = min_t(size_t, leftlen, n);
4059                 size_t stride;
4060
4061                 memcpy(*seg, src, copysz);
4062
4063                 n -= copysz;
4064                 src += copysz;
4065                 stride = !n ? ALIGN(copysz, 16) : copysz;
4066                 *seg += stride;
4067                 *wqe_sz += stride >> 4;
4068                 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
4069         }
4070 }
4071
4072 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
4073 {
4074         struct mlx5_ib_cq *cq;
4075         unsigned cur;
4076
4077         cur = wq->head - wq->tail;
4078         if (likely(cur + nreq < wq->max_post))
4079                 return 0;
4080
4081         cq = to_mcq(ib_cq);
4082         spin_lock(&cq->lock);
4083         cur = wq->head - wq->tail;
4084         spin_unlock(&cq->lock);
4085
4086         return cur + nreq >= wq->max_post;
4087 }
4088
4089 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
4090                                           u64 remote_addr, u32 rkey)
4091 {
4092         rseg->raddr    = cpu_to_be64(remote_addr);
4093         rseg->rkey     = cpu_to_be32(rkey);
4094         rseg->reserved = 0;
4095 }
4096
4097 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
4098                         void **seg, int *size, void **cur_edge)
4099 {
4100         struct mlx5_wqe_eth_seg *eseg = *seg;
4101
4102         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
4103
4104         if (wr->send_flags & IB_SEND_IP_CSUM)
4105                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
4106                                  MLX5_ETH_WQE_L4_CSUM;
4107
4108         if (wr->opcode == IB_WR_LSO) {
4109                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
4110                 size_t left, copysz;
4111                 void *pdata = ud_wr->header;
4112                 size_t stride;
4113
4114                 left = ud_wr->hlen;
4115                 eseg->mss = cpu_to_be16(ud_wr->mss);
4116                 eseg->inline_hdr.sz = cpu_to_be16(left);
4117
4118                 /* memcpy_send_wqe should get a 16B align address. Hence, we
4119                  * first copy up to the current edge and then, if needed,
4120                  * fall-through to memcpy_send_wqe.
4121                  */
4122                 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
4123                                left);
4124                 memcpy(eseg->inline_hdr.start, pdata, copysz);
4125                 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
4126                                sizeof(eseg->inline_hdr.start) + copysz, 16);
4127                 *size += stride / 16;
4128                 *seg += stride;
4129
4130                 if (copysz < left) {
4131                         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4132                         left -= copysz;
4133                         pdata += copysz;
4134                         memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
4135                                         left);
4136                 }
4137
4138                 return;
4139         }
4140
4141         *seg += sizeof(struct mlx5_wqe_eth_seg);
4142         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
4143 }
4144
4145 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
4146                              const struct ib_send_wr *wr)
4147 {
4148         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
4149         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
4150         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
4151 }
4152
4153 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
4154 {
4155         dseg->byte_count = cpu_to_be32(sg->length);
4156         dseg->lkey       = cpu_to_be32(sg->lkey);
4157         dseg->addr       = cpu_to_be64(sg->addr);
4158 }
4159
4160 static u64 get_xlt_octo(u64 bytes)
4161 {
4162         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
4163                MLX5_IB_UMR_OCTOWORD;
4164 }
4165
4166 static __be64 frwr_mkey_mask(void)
4167 {
4168         u64 result;
4169
4170         result = MLX5_MKEY_MASK_LEN             |
4171                 MLX5_MKEY_MASK_PAGE_SIZE        |
4172                 MLX5_MKEY_MASK_START_ADDR       |
4173                 MLX5_MKEY_MASK_EN_RINVAL        |
4174                 MLX5_MKEY_MASK_KEY              |
4175                 MLX5_MKEY_MASK_LR               |
4176                 MLX5_MKEY_MASK_LW               |
4177                 MLX5_MKEY_MASK_RR               |
4178                 MLX5_MKEY_MASK_RW               |
4179                 MLX5_MKEY_MASK_A                |
4180                 MLX5_MKEY_MASK_SMALL_FENCE      |
4181                 MLX5_MKEY_MASK_FREE;
4182
4183         return cpu_to_be64(result);
4184 }
4185
4186 static __be64 sig_mkey_mask(void)
4187 {
4188         u64 result;
4189
4190         result = MLX5_MKEY_MASK_LEN             |
4191                 MLX5_MKEY_MASK_PAGE_SIZE        |
4192                 MLX5_MKEY_MASK_START_ADDR       |
4193                 MLX5_MKEY_MASK_EN_SIGERR        |
4194                 MLX5_MKEY_MASK_EN_RINVAL        |
4195                 MLX5_MKEY_MASK_KEY              |
4196                 MLX5_MKEY_MASK_LR               |
4197                 MLX5_MKEY_MASK_LW               |
4198                 MLX5_MKEY_MASK_RR               |
4199                 MLX5_MKEY_MASK_RW               |
4200                 MLX5_MKEY_MASK_SMALL_FENCE      |
4201                 MLX5_MKEY_MASK_FREE             |
4202                 MLX5_MKEY_MASK_BSF_EN;
4203
4204         return cpu_to_be64(result);
4205 }
4206
4207 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
4208                             struct mlx5_ib_mr *mr, u8 flags)
4209 {
4210         int size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4211
4212         memset(umr, 0, sizeof(*umr));
4213
4214         umr->flags = flags;
4215         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4216         umr->mkey_mask = frwr_mkey_mask();
4217 }
4218
4219 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
4220 {
4221         memset(umr, 0, sizeof(*umr));
4222         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
4223         umr->flags = MLX5_UMR_INLINE;
4224 }
4225
4226 static __be64 get_umr_enable_mr_mask(void)
4227 {
4228         u64 result;
4229
4230         result = MLX5_MKEY_MASK_KEY |
4231                  MLX5_MKEY_MASK_FREE;
4232
4233         return cpu_to_be64(result);
4234 }
4235
4236 static __be64 get_umr_disable_mr_mask(void)
4237 {
4238         u64 result;
4239
4240         result = MLX5_MKEY_MASK_FREE;
4241
4242         return cpu_to_be64(result);
4243 }
4244
4245 static __be64 get_umr_update_translation_mask(void)
4246 {
4247         u64 result;
4248
4249         result = MLX5_MKEY_MASK_LEN |
4250                  MLX5_MKEY_MASK_PAGE_SIZE |
4251                  MLX5_MKEY_MASK_START_ADDR;
4252
4253         return cpu_to_be64(result);
4254 }
4255
4256 static __be64 get_umr_update_access_mask(int atomic)
4257 {
4258         u64 result;
4259
4260         result = MLX5_MKEY_MASK_LR |
4261                  MLX5_MKEY_MASK_LW |
4262                  MLX5_MKEY_MASK_RR |
4263                  MLX5_MKEY_MASK_RW;
4264
4265         if (atomic)
4266                 result |= MLX5_MKEY_MASK_A;
4267
4268         return cpu_to_be64(result);
4269 }
4270
4271 static __be64 get_umr_update_pd_mask(void)
4272 {
4273         u64 result;
4274
4275         result = MLX5_MKEY_MASK_PD;
4276
4277         return cpu_to_be64(result);
4278 }
4279
4280 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4281 {
4282         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4283              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4284             (mask & MLX5_MKEY_MASK_A &&
4285              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4286                 return -EPERM;
4287         return 0;
4288 }
4289
4290 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4291                                struct mlx5_wqe_umr_ctrl_seg *umr,
4292                                const struct ib_send_wr *wr, int atomic)
4293 {
4294         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4295
4296         memset(umr, 0, sizeof(*umr));
4297
4298         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4299                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
4300         else
4301                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
4302
4303         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4304         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4305                 u64 offset = get_xlt_octo(umrwr->offset);
4306
4307                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4308                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4309                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
4310         }
4311         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4312                 umr->mkey_mask |= get_umr_update_translation_mask();
4313         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4314                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4315                 umr->mkey_mask |= get_umr_update_pd_mask();
4316         }
4317         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4318                 umr->mkey_mask |= get_umr_enable_mr_mask();
4319         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4320                 umr->mkey_mask |= get_umr_disable_mr_mask();
4321
4322         if (!wr->num_sge)
4323                 umr->flags |= MLX5_UMR_INLINE;
4324
4325         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4326 }
4327
4328 static u8 get_umr_flags(int acc)
4329 {
4330         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
4331                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
4332                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
4333                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
4334                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4335 }
4336
4337 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4338                              struct mlx5_ib_mr *mr,
4339                              u32 key, int access)
4340 {
4341         int ndescs = ALIGN(mr->ndescs + mr->meta_ndescs, 8) >> 1;
4342
4343         memset(seg, 0, sizeof(*seg));
4344
4345         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4346                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4347         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4348                 /* KLMs take twice the size of MTTs */
4349                 ndescs *= 2;
4350
4351         seg->flags = get_umr_flags(access) | mr->access_mode;
4352         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4353         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4354         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4355         seg->len = cpu_to_be64(mr->ibmr.length);
4356         seg->xlt_oct_size = cpu_to_be32(ndescs);
4357 }
4358
4359 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4360 {
4361         memset(seg, 0, sizeof(*seg));
4362         seg->status = MLX5_MKEY_STATUS_FREE;
4363 }
4364
4365 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4366                                  const struct ib_send_wr *wr)
4367 {
4368         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4369
4370         memset(seg, 0, sizeof(*seg));
4371         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4372                 seg->status = MLX5_MKEY_STATUS_FREE;
4373
4374         seg->flags = convert_access(umrwr->access_flags);
4375         if (umrwr->pd)
4376                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4377         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4378             !umrwr->length)
4379                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4380
4381         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4382         seg->len = cpu_to_be64(umrwr->length);
4383         seg->log2_page_size = umrwr->page_shift;
4384         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4385                                        mlx5_mkey_variant(umrwr->mkey));
4386 }
4387
4388 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4389                              struct mlx5_ib_mr *mr,
4390                              struct mlx5_ib_pd *pd)
4391 {
4392         int bcount = mr->desc_size * (mr->ndescs + mr->meta_ndescs);
4393
4394         dseg->addr = cpu_to_be64(mr->desc_map);
4395         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4396         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4397 }
4398
4399 static __be32 send_ieth(const struct ib_send_wr *wr)
4400 {
4401         switch (wr->opcode) {
4402         case IB_WR_SEND_WITH_IMM:
4403         case IB_WR_RDMA_WRITE_WITH_IMM:
4404                 return wr->ex.imm_data;
4405
4406         case IB_WR_SEND_WITH_INV:
4407                 return cpu_to_be32(wr->ex.invalidate_rkey);
4408
4409         default:
4410                 return 0;
4411         }
4412 }
4413
4414 static u8 calc_sig(void *wqe, int size)
4415 {
4416         u8 *p = wqe;
4417         u8 res = 0;
4418         int i;
4419
4420         for (i = 0; i < size; i++)
4421                 res ^= p[i];
4422
4423         return ~res;
4424 }
4425
4426 static u8 wq_sig(void *wqe)
4427 {
4428         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4429 }
4430
4431 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4432                             void **wqe, int *wqe_sz, void **cur_edge)
4433 {
4434         struct mlx5_wqe_inline_seg *seg;
4435         size_t offset;
4436         int inl = 0;
4437         int i;
4438
4439         seg = *wqe;
4440         *wqe += sizeof(*seg);
4441         offset = sizeof(*seg);
4442
4443         for (i = 0; i < wr->num_sge; i++) {
4444                 size_t len  = wr->sg_list[i].length;
4445                 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4446
4447                 inl += len;
4448
4449                 if (unlikely(inl > qp->max_inline_data))
4450                         return -ENOMEM;
4451
4452                 while (likely(len)) {
4453                         size_t leftlen;
4454                         size_t copysz;
4455
4456                         handle_post_send_edge(&qp->sq, wqe,
4457                                               *wqe_sz + (offset >> 4),
4458                                               cur_edge);
4459
4460                         leftlen = *cur_edge - *wqe;
4461                         copysz = min_t(size_t, leftlen, len);
4462
4463                         memcpy(*wqe, addr, copysz);
4464                         len -= copysz;
4465                         addr += copysz;
4466                         *wqe += copysz;
4467                         offset += copysz;
4468                 }
4469         }
4470
4471         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4472
4473         *wqe_sz +=  ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4474
4475         return 0;
4476 }
4477
4478 static u16 prot_field_size(enum ib_signature_type type)
4479 {
4480         switch (type) {
4481         case IB_SIG_TYPE_T10_DIF:
4482                 return MLX5_DIF_SIZE;
4483         default:
4484                 return 0;
4485         }
4486 }
4487
4488 static u8 bs_selector(int block_size)
4489 {
4490         switch (block_size) {
4491         case 512:           return 0x1;
4492         case 520:           return 0x2;
4493         case 4096:          return 0x3;
4494         case 4160:          return 0x4;
4495         case 1073741824:    return 0x5;
4496         default:            return 0;
4497         }
4498 }
4499
4500 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4501                               struct mlx5_bsf_inl *inl)
4502 {
4503         /* Valid inline section and allow BSF refresh */
4504         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4505                                        MLX5_BSF_REFRESH_DIF);
4506         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4507         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4508         /* repeating block */
4509         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4510         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4511                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4512
4513         if (domain->sig.dif.ref_remap)
4514                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4515
4516         if (domain->sig.dif.app_escape) {
4517                 if (domain->sig.dif.ref_escape)
4518                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4519                 else
4520                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4521         }
4522
4523         inl->dif_app_bitmask_check =
4524                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4525 }
4526
4527 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4528                         struct ib_sig_attrs *sig_attrs,
4529                         struct mlx5_bsf *bsf, u32 data_size)
4530 {
4531         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4532         struct mlx5_bsf_basic *basic = &bsf->basic;
4533         struct ib_sig_domain *mem = &sig_attrs->mem;
4534         struct ib_sig_domain *wire = &sig_attrs->wire;
4535
4536         memset(bsf, 0, sizeof(*bsf));
4537
4538         /* Basic + Extended + Inline */
4539         basic->bsf_size_sbs = 1 << 7;
4540         /* Input domain check byte mask */
4541         basic->check_byte_mask = sig_attrs->check_mask;
4542         basic->raw_data_size = cpu_to_be32(data_size);
4543
4544         /* Memory domain */
4545         switch (sig_attrs->mem.sig_type) {
4546         case IB_SIG_TYPE_NONE:
4547                 break;
4548         case IB_SIG_TYPE_T10_DIF:
4549                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4550                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4551                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4552                 break;
4553         default:
4554                 return -EINVAL;
4555         }
4556
4557         /* Wire domain */
4558         switch (sig_attrs->wire.sig_type) {
4559         case IB_SIG_TYPE_NONE:
4560                 break;
4561         case IB_SIG_TYPE_T10_DIF:
4562                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4563                     mem->sig_type == wire->sig_type) {
4564                         /* Same block structure */
4565                         basic->bsf_size_sbs |= 1 << 4;
4566                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4567                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4568                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4569                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4570                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4571                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4572                 } else
4573                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4574
4575                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4576                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4577                 break;
4578         default:
4579                 return -EINVAL;
4580         }
4581
4582         return 0;
4583 }
4584
4585 static int set_sig_data_segment(const struct ib_send_wr *send_wr,
4586                                 struct ib_mr *sig_mr,
4587                                 struct ib_sig_attrs *sig_attrs,
4588                                 struct mlx5_ib_qp *qp, void **seg, int *size,
4589                                 void **cur_edge)
4590 {
4591         struct mlx5_bsf *bsf;
4592         u32 data_len;
4593         u32 data_key;
4594         u64 data_va;
4595         u32 prot_len = 0;
4596         u32 prot_key = 0;
4597         u64 prot_va = 0;
4598         bool prot = false;
4599         int ret;
4600         int wqe_size;
4601         struct mlx5_ib_mr *mr = to_mmr(sig_mr);
4602         struct mlx5_ib_mr *pi_mr = mr->pi_mr;
4603
4604         data_len = pi_mr->data_length;
4605         data_key = pi_mr->ibmr.lkey;
4606         data_va = pi_mr->data_iova;
4607         if (pi_mr->meta_ndescs) {
4608                 prot_len = pi_mr->meta_length;
4609                 prot_key = pi_mr->ibmr.lkey;
4610                 prot_va = pi_mr->pi_iova;
4611                 prot = true;
4612         }
4613
4614         if (!prot || (data_key == prot_key && data_va == prot_va &&
4615                       data_len == prot_len)) {
4616                 /**
4617                  * Source domain doesn't contain signature information
4618                  * or data and protection are interleaved in memory.
4619                  * So need construct:
4620                  *                  ------------------
4621                  *                 |     data_klm     |
4622                  *                  ------------------
4623                  *                 |       BSF        |
4624                  *                  ------------------
4625                  **/
4626                 struct mlx5_klm *data_klm = *seg;
4627
4628                 data_klm->bcount = cpu_to_be32(data_len);
4629                 data_klm->key = cpu_to_be32(data_key);
4630                 data_klm->va = cpu_to_be64(data_va);
4631                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4632         } else {
4633                 /**
4634                  * Source domain contains signature information
4635                  * So need construct a strided block format:
4636                  *               ---------------------------
4637                  *              |     stride_block_ctrl     |
4638                  *               ---------------------------
4639                  *              |          data_klm         |
4640                  *               ---------------------------
4641                  *              |          prot_klm         |
4642                  *               ---------------------------
4643                  *              |             BSF           |
4644                  *               ---------------------------
4645                  **/
4646                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4647                 struct mlx5_stride_block_entry *data_sentry;
4648                 struct mlx5_stride_block_entry *prot_sentry;
4649                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4650                 int prot_size;
4651
4652                 sblock_ctrl = *seg;
4653                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4654                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4655
4656                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4657                 if (!prot_size) {
4658                         pr_err("Bad block size given: %u\n", block_size);
4659                         return -EINVAL;
4660                 }
4661                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4662                                                             prot_size);
4663                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4664                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4665                 sblock_ctrl->num_entries = cpu_to_be16(2);
4666
4667                 data_sentry->bcount = cpu_to_be16(block_size);
4668                 data_sentry->key = cpu_to_be32(data_key);
4669                 data_sentry->va = cpu_to_be64(data_va);
4670                 data_sentry->stride = cpu_to_be16(block_size);
4671
4672                 prot_sentry->bcount = cpu_to_be16(prot_size);
4673                 prot_sentry->key = cpu_to_be32(prot_key);
4674                 prot_sentry->va = cpu_to_be64(prot_va);
4675                 prot_sentry->stride = cpu_to_be16(prot_size);
4676
4677                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4678                                  sizeof(*prot_sentry), 64);
4679         }
4680
4681         *seg += wqe_size;
4682         *size += wqe_size / 16;
4683         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4684
4685         bsf = *seg;
4686         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4687         if (ret)
4688                 return -EINVAL;
4689
4690         *seg += sizeof(*bsf);
4691         *size += sizeof(*bsf) / 16;
4692         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4693
4694         return 0;
4695 }
4696
4697 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4698                                  struct ib_mr *sig_mr, int access_flags,
4699                                  u32 size, u32 length, u32 pdn)
4700 {
4701         u32 sig_key = sig_mr->rkey;
4702         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4703
4704         memset(seg, 0, sizeof(*seg));
4705
4706         seg->flags = get_umr_flags(access_flags) | MLX5_MKC_ACCESS_MODE_KLMS;
4707         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4708         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4709                                     MLX5_MKEY_BSF_EN | pdn);
4710         seg->len = cpu_to_be64(length);
4711         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4712         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4713 }
4714
4715 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4716                                 u32 size)
4717 {
4718         memset(umr, 0, sizeof(*umr));
4719
4720         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4721         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4722         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4723         umr->mkey_mask = sig_mkey_mask();
4724 }
4725
4726 static int set_pi_umr_wr(const struct ib_send_wr *send_wr,
4727                          struct mlx5_ib_qp *qp, void **seg, int *size,
4728                          void **cur_edge)
4729 {
4730         const struct ib_reg_wr *wr = reg_wr(send_wr);
4731         struct mlx5_ib_mr *sig_mr = to_mmr(wr->mr);
4732         struct mlx5_ib_mr *pi_mr = sig_mr->pi_mr;
4733         struct ib_sig_attrs *sig_attrs = sig_mr->ibmr.sig_attrs;
4734         u32 pdn = get_pd(qp)->pdn;
4735         u32 xlt_size;
4736         int region_len, ret;
4737
4738         if (unlikely(send_wr->num_sge != 0) ||
4739             unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) ||
4740             unlikely(!sig_mr->sig) || unlikely(!qp->ibqp.integrity_en) ||
4741             unlikely(!sig_mr->sig->sig_status_checked))
4742                 return -EINVAL;
4743
4744         /* length of the protected region, data + protection */
4745         region_len = pi_mr->ibmr.length;
4746
4747         /**
4748          * KLM octoword size - if protection was provided
4749          * then we use strided block format (3 octowords),
4750          * else we use single KLM (1 octoword)
4751          **/
4752         if (sig_attrs->mem.sig_type != IB_SIG_TYPE_NONE)
4753                 xlt_size = 0x30;
4754         else
4755                 xlt_size = sizeof(struct mlx5_klm);
4756
4757         set_sig_umr_segment(*seg, xlt_size);
4758         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4759         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4760         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4761
4762         set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len,
4763                              pdn);
4764         *seg += sizeof(struct mlx5_mkey_seg);
4765         *size += sizeof(struct mlx5_mkey_seg) / 16;
4766         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4767
4768         ret = set_sig_data_segment(send_wr, wr->mr, sig_attrs, qp, seg, size,
4769                                    cur_edge);
4770         if (ret)
4771                 return ret;
4772
4773         sig_mr->sig->sig_status_checked = false;
4774         return 0;
4775 }
4776
4777 static int set_psv_wr(struct ib_sig_domain *domain,
4778                       u32 psv_idx, void **seg, int *size)
4779 {
4780         struct mlx5_seg_set_psv *psv_seg = *seg;
4781
4782         memset(psv_seg, 0, sizeof(*psv_seg));
4783         psv_seg->psv_num = cpu_to_be32(psv_idx);
4784         switch (domain->sig_type) {
4785         case IB_SIG_TYPE_NONE:
4786                 break;
4787         case IB_SIG_TYPE_T10_DIF:
4788                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4789                                                      domain->sig.dif.app_tag);
4790                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4791                 break;
4792         default:
4793                 pr_err("Bad signature type (%d) is given.\n",
4794                        domain->sig_type);
4795                 return -EINVAL;
4796         }
4797
4798         *seg += sizeof(*psv_seg);
4799         *size += sizeof(*psv_seg) / 16;
4800
4801         return 0;
4802 }
4803
4804 static int set_reg_wr(struct mlx5_ib_qp *qp,
4805                       const struct ib_reg_wr *wr,
4806                       void **seg, int *size, void **cur_edge,
4807                       bool check_not_free)
4808 {
4809         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4810         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4811         int mr_list_size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
4812         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4813         u8 flags = 0;
4814
4815         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4816                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4817                              "Invalid IB_SEND_INLINE send flag\n");
4818                 return -EINVAL;
4819         }
4820
4821         if (check_not_free)
4822                 flags |= MLX5_UMR_CHECK_NOT_FREE;
4823         if (umr_inline)
4824                 flags |= MLX5_UMR_INLINE;
4825
4826         set_reg_umr_seg(*seg, mr, flags);
4827         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4828         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4829         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4830
4831         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4832         *seg += sizeof(struct mlx5_mkey_seg);
4833         *size += sizeof(struct mlx5_mkey_seg) / 16;
4834         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4835
4836         if (umr_inline) {
4837                 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4838                                 mr_list_size);
4839                 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
4840         } else {
4841                 set_reg_data_seg(*seg, mr, pd);
4842                 *seg += sizeof(struct mlx5_wqe_data_seg);
4843                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4844         }
4845         return 0;
4846 }
4847
4848 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4849                         void **cur_edge)
4850 {
4851         set_linv_umr_seg(*seg);
4852         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4853         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4854         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4855         set_linv_mkey_seg(*seg);
4856         *seg += sizeof(struct mlx5_mkey_seg);
4857         *size += sizeof(struct mlx5_mkey_seg) / 16;
4858         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4859 }
4860
4861 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
4862 {
4863         __be32 *p = NULL;
4864         int i, j;
4865
4866         pr_debug("dump WQE index %u:\n", idx);
4867         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4868                 if ((i & 0xf) == 0) {
4869                         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx);
4870                         pr_debug("WQBB at %p:\n", (void *)p);
4871                         j = 0;
4872                         idx = (idx + 1) & (qp->sq.wqe_cnt - 1);
4873                 }
4874                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4875                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4876                          be32_to_cpu(p[j + 3]));
4877         }
4878 }
4879
4880 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4881                        struct mlx5_wqe_ctrl_seg **ctrl,
4882                        const struct ib_send_wr *wr, unsigned int *idx,
4883                        int *size, void **cur_edge, int nreq,
4884                        bool send_signaled, bool solicited)
4885 {
4886         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4887                 return -ENOMEM;
4888
4889         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4890         *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
4891         *ctrl = *seg;
4892         *(uint32_t *)(*seg + 8) = 0;
4893         (*ctrl)->imm = send_ieth(wr);
4894         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4895                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4896                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4897
4898         *seg += sizeof(**ctrl);
4899         *size = sizeof(**ctrl) / 16;
4900         *cur_edge = qp->sq.cur_edge;
4901
4902         return 0;
4903 }
4904
4905 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4906                      struct mlx5_wqe_ctrl_seg **ctrl,
4907                      const struct ib_send_wr *wr, unsigned *idx,
4908                      int *size, void **cur_edge, int nreq)
4909 {
4910         return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
4911                            wr->send_flags & IB_SEND_SIGNALED,
4912                            wr->send_flags & IB_SEND_SOLICITED);
4913 }
4914
4915 static void finish_wqe(struct mlx5_ib_qp *qp,
4916                        struct mlx5_wqe_ctrl_seg *ctrl,
4917                        void *seg, u8 size, void *cur_edge,
4918                        unsigned int idx, u64 wr_id, int nreq, u8 fence,
4919                        u32 mlx5_opcode)
4920 {
4921         u8 opmod = 0;
4922
4923         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4924                                              mlx5_opcode | ((u32)opmod << 24));
4925         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4926         ctrl->fm_ce_se |= fence;
4927         if (unlikely(qp->wq_sig))
4928                 ctrl->signature = wq_sig(ctrl);
4929
4930         qp->sq.wrid[idx] = wr_id;
4931         qp->sq.w_list[idx].opcode = mlx5_opcode;
4932         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4933         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4934         qp->sq.w_list[idx].next = qp->sq.cur_post;
4935
4936         /* We save the edge which was possibly updated during the WQE
4937          * construction, into SQ's cache.
4938          */
4939         seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
4940         qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
4941                           get_sq_edge(&qp->sq, qp->sq.cur_post &
4942                                       (qp->sq.wqe_cnt - 1)) :
4943                           cur_edge;
4944 }
4945
4946 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4947                               const struct ib_send_wr **bad_wr, bool drain)
4948 {
4949         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
4950         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4951         struct mlx5_core_dev *mdev = dev->mdev;
4952         struct ib_reg_wr reg_pi_wr;
4953         struct mlx5_ib_qp *qp;
4954         struct mlx5_ib_mr *mr;
4955         struct mlx5_ib_mr *pi_mr;
4956         struct mlx5_ib_mr pa_pi_mr;
4957         struct ib_sig_attrs *sig_attrs;
4958         struct mlx5_wqe_xrc_seg *xrc;
4959         struct mlx5_bf *bf;
4960         void *cur_edge;
4961         int uninitialized_var(size);
4962         unsigned long flags;
4963         unsigned idx;
4964         int err = 0;
4965         int num_sge;
4966         void *seg;
4967         int nreq;
4968         int i;
4969         u8 next_fence = 0;
4970         u8 fence;
4971
4972         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4973                      !drain)) {
4974                 *bad_wr = wr;
4975                 return -EIO;
4976         }
4977
4978         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4979                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4980
4981         qp = to_mqp(ibqp);
4982         bf = &qp->bf;
4983
4984         spin_lock_irqsave(&qp->sq.lock, flags);
4985
4986         for (nreq = 0; wr; nreq++, wr = wr->next) {
4987                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4988                         mlx5_ib_warn(dev, "\n");
4989                         err = -EINVAL;
4990                         *bad_wr = wr;
4991                         goto out;
4992                 }
4993
4994                 num_sge = wr->num_sge;
4995                 if (unlikely(num_sge > qp->sq.max_gs)) {
4996                         mlx5_ib_warn(dev, "\n");
4997                         err = -EINVAL;
4998                         *bad_wr = wr;
4999                         goto out;
5000                 }
5001
5002                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
5003                                 nreq);
5004                 if (err) {
5005                         mlx5_ib_warn(dev, "\n");
5006                         err = -ENOMEM;
5007                         *bad_wr = wr;
5008                         goto out;
5009                 }
5010
5011                 if (wr->opcode == IB_WR_REG_MR ||
5012                     wr->opcode == IB_WR_REG_MR_INTEGRITY) {
5013                         fence = dev->umr_fence;
5014                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
5015                 } else  {
5016                         if (wr->send_flags & IB_SEND_FENCE) {
5017                                 if (qp->next_fence)
5018                                         fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
5019                                 else
5020                                         fence = MLX5_FENCE_MODE_FENCE;
5021                         } else {
5022                                 fence = qp->next_fence;
5023                         }
5024                 }
5025
5026                 switch (ibqp->qp_type) {
5027                 case IB_QPT_XRC_INI:
5028                         xrc = seg;
5029                         seg += sizeof(*xrc);
5030                         size += sizeof(*xrc) / 16;
5031                         /* fall through */
5032                 case IB_QPT_RC:
5033                         switch (wr->opcode) {
5034                         case IB_WR_RDMA_READ:
5035                         case IB_WR_RDMA_WRITE:
5036                         case IB_WR_RDMA_WRITE_WITH_IMM:
5037                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5038                                               rdma_wr(wr)->rkey);
5039                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
5040                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5041                                 break;
5042
5043                         case IB_WR_ATOMIC_CMP_AND_SWP:
5044                         case IB_WR_ATOMIC_FETCH_AND_ADD:
5045                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
5046                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
5047                                 err = -ENOSYS;
5048                                 *bad_wr = wr;
5049                                 goto out;
5050
5051                         case IB_WR_LOCAL_INV:
5052                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
5053                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
5054                                 set_linv_wr(qp, &seg, &size, &cur_edge);
5055                                 num_sge = 0;
5056                                 break;
5057
5058                         case IB_WR_REG_MR:
5059                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
5060                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
5061                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
5062                                                  &cur_edge, true);
5063                                 if (err) {
5064                                         *bad_wr = wr;
5065                                         goto out;
5066                                 }
5067                                 num_sge = 0;
5068                                 break;
5069
5070                         case IB_WR_REG_MR_INTEGRITY:
5071                                 qp->sq.wr_data[idx] = IB_WR_REG_MR_INTEGRITY;
5072
5073                                 mr = to_mmr(reg_wr(wr)->mr);
5074                                 pi_mr = mr->pi_mr;
5075
5076                                 if (pi_mr) {
5077                                         memset(&reg_pi_wr, 0,
5078                                                sizeof(struct ib_reg_wr));
5079
5080                                         reg_pi_wr.mr = &pi_mr->ibmr;
5081                                         reg_pi_wr.access = reg_wr(wr)->access;
5082                                         reg_pi_wr.key = pi_mr->ibmr.rkey;
5083
5084                                         ctrl->imm = cpu_to_be32(reg_pi_wr.key);
5085                                         /* UMR for data + prot registration */
5086                                         err = set_reg_wr(qp, &reg_pi_wr, &seg,
5087                                                          &size, &cur_edge,
5088                                                          false);
5089                                         if (err) {
5090                                                 *bad_wr = wr;
5091                                                 goto out;
5092                                         }
5093                                         finish_wqe(qp, ctrl, seg, size,
5094                                                    cur_edge, idx, wr->wr_id,
5095                                                    nreq, fence,
5096                                                    MLX5_OPCODE_UMR);
5097
5098                                         err = begin_wqe(qp, &seg, &ctrl, wr,
5099                                                         &idx, &size, &cur_edge,
5100                                                         nreq);
5101                                         if (err) {
5102                                                 mlx5_ib_warn(dev, "\n");
5103                                                 err = -ENOMEM;
5104                                                 *bad_wr = wr;
5105                                                 goto out;
5106                                         }
5107                                 } else {
5108                                         memset(&pa_pi_mr, 0,
5109                                                sizeof(struct mlx5_ib_mr));
5110                                         /* No UMR, use local_dma_lkey */
5111                                         pa_pi_mr.ibmr.lkey =
5112                                                 mr->ibmr.pd->local_dma_lkey;
5113
5114                                         pa_pi_mr.ndescs = mr->ndescs;
5115                                         pa_pi_mr.data_length = mr->data_length;
5116                                         pa_pi_mr.data_iova = mr->data_iova;
5117                                         if (mr->meta_ndescs) {
5118                                                 pa_pi_mr.meta_ndescs =
5119                                                         mr->meta_ndescs;
5120                                                 pa_pi_mr.meta_length =
5121                                                         mr->meta_length;
5122                                                 pa_pi_mr.pi_iova = mr->pi_iova;
5123                                         }
5124
5125                                         pa_pi_mr.ibmr.length = mr->ibmr.length;
5126                                         mr->pi_mr = &pa_pi_mr;
5127                                 }
5128                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
5129                                 /* UMR for sig MR */
5130                                 err = set_pi_umr_wr(wr, qp, &seg, &size,
5131                                                     &cur_edge);
5132                                 if (err) {
5133                                         mlx5_ib_warn(dev, "\n");
5134                                         *bad_wr = wr;
5135                                         goto out;
5136                                 }
5137                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5138                                            wr->wr_id, nreq, fence,
5139                                            MLX5_OPCODE_UMR);
5140
5141                                 /*
5142                                  * SET_PSV WQEs are not signaled and solicited
5143                                  * on error
5144                                  */
5145                                 sig_attrs = mr->ibmr.sig_attrs;
5146                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5147                                                   &size, &cur_edge, nreq, false,
5148                                                   true);
5149                                 if (err) {
5150                                         mlx5_ib_warn(dev, "\n");
5151                                         err = -ENOMEM;
5152                                         *bad_wr = wr;
5153                                         goto out;
5154                                 }
5155                                 err = set_psv_wr(&sig_attrs->mem,
5156                                                  mr->sig->psv_memory.psv_idx,
5157                                                  &seg, &size);
5158                                 if (err) {
5159                                         mlx5_ib_warn(dev, "\n");
5160                                         *bad_wr = wr;
5161                                         goto out;
5162                                 }
5163                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5164                                            wr->wr_id, nreq, next_fence,
5165                                            MLX5_OPCODE_SET_PSV);
5166
5167                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
5168                                                   &size, &cur_edge, nreq, false,
5169                                                   true);
5170                                 if (err) {
5171                                         mlx5_ib_warn(dev, "\n");
5172                                         err = -ENOMEM;
5173                                         *bad_wr = wr;
5174                                         goto out;
5175                                 }
5176                                 err = set_psv_wr(&sig_attrs->wire,
5177                                                  mr->sig->psv_wire.psv_idx,
5178                                                  &seg, &size);
5179                                 if (err) {
5180                                         mlx5_ib_warn(dev, "\n");
5181                                         *bad_wr = wr;
5182                                         goto out;
5183                                 }
5184                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5185                                            wr->wr_id, nreq, next_fence,
5186                                            MLX5_OPCODE_SET_PSV);
5187
5188                                 qp->next_fence =
5189                                         MLX5_FENCE_MODE_INITIATOR_SMALL;
5190                                 num_sge = 0;
5191                                 goto skip_psv;
5192
5193                         default:
5194                                 break;
5195                         }
5196                         break;
5197
5198                 case IB_QPT_UC:
5199                         switch (wr->opcode) {
5200                         case IB_WR_RDMA_WRITE:
5201                         case IB_WR_RDMA_WRITE_WITH_IMM:
5202                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5203                                               rdma_wr(wr)->rkey);
5204                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
5205                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5206                                 break;
5207
5208                         default:
5209                                 break;
5210                         }
5211                         break;
5212
5213                 case IB_QPT_SMI:
5214                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
5215                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
5216                                 err = -EPERM;
5217                                 *bad_wr = wr;
5218                                 goto out;
5219                         }
5220                         /* fall through */
5221                 case MLX5_IB_QPT_HW_GSI:
5222                         set_datagram_seg(seg, wr);
5223                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5224                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5225                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5226
5227                         break;
5228                 case IB_QPT_UD:
5229                         set_datagram_seg(seg, wr);
5230                         seg += sizeof(struct mlx5_wqe_datagram_seg);
5231                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
5232                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5233
5234                         /* handle qp that supports ud offload */
5235                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
5236                                 struct mlx5_wqe_eth_pad *pad;
5237
5238                                 pad = seg;
5239                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
5240                                 seg += sizeof(struct mlx5_wqe_eth_pad);
5241                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
5242                                 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
5243                                 handle_post_send_edge(&qp->sq, &seg, size,
5244                                                       &cur_edge);
5245                         }
5246                         break;
5247                 case MLX5_IB_QPT_REG_UMR:
5248                         if (wr->opcode != MLX5_IB_WR_UMR) {
5249                                 err = -EINVAL;
5250                                 mlx5_ib_warn(dev, "bad opcode\n");
5251                                 goto out;
5252                         }
5253                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
5254                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
5255                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
5256                         if (unlikely(err))
5257                                 goto out;
5258                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5259                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
5260                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5261                         set_reg_mkey_segment(seg, wr);
5262                         seg += sizeof(struct mlx5_mkey_seg);
5263                         size += sizeof(struct mlx5_mkey_seg) / 16;
5264                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5265                         break;
5266
5267                 default:
5268                         break;
5269                 }
5270
5271                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
5272                         err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
5273                         if (unlikely(err)) {
5274                                 mlx5_ib_warn(dev, "\n");
5275                                 *bad_wr = wr;
5276                                 goto out;
5277                         }
5278                 } else {
5279                         for (i = 0; i < num_sge; i++) {
5280                                 handle_post_send_edge(&qp->sq, &seg, size,
5281                                                       &cur_edge);
5282                                 if (likely(wr->sg_list[i].length)) {
5283                                         set_data_ptr_seg
5284                                         ((struct mlx5_wqe_data_seg *)seg,
5285                                          wr->sg_list + i);
5286                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
5287                                         seg += sizeof(struct mlx5_wqe_data_seg);
5288                                 }
5289                         }
5290                 }
5291
5292                 qp->next_fence = next_fence;
5293                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
5294                            fence, mlx5_ib_opcode[wr->opcode]);
5295 skip_psv:
5296                 if (0)
5297                         dump_wqe(qp, idx, size);
5298         }
5299
5300 out:
5301         if (likely(nreq)) {
5302                 qp->sq.head += nreq;
5303
5304                 /* Make sure that descriptors are written before
5305                  * updating doorbell record and ringing the doorbell
5306                  */
5307                 wmb();
5308
5309                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5310
5311                 /* Make sure doorbell record is visible to the HCA before
5312                  * we hit doorbell */
5313                 wmb();
5314
5315                 /* currently we support only regular doorbells */
5316                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset);
5317                 /* Make sure doorbells don't leak out of SQ spinlock
5318                  * and reach the HCA out of order.
5319                  */
5320                 bf->offset ^= bf->buf_size;
5321         }
5322
5323         spin_unlock_irqrestore(&qp->sq.lock, flags);
5324
5325         return err;
5326 }
5327
5328 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5329                       const struct ib_send_wr **bad_wr)
5330 {
5331         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5332 }
5333
5334 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5335 {
5336         sig->signature = calc_sig(sig, size);
5337 }
5338
5339 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5340                       const struct ib_recv_wr **bad_wr, bool drain)
5341 {
5342         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5343         struct mlx5_wqe_data_seg *scat;
5344         struct mlx5_rwqe_sig *sig;
5345         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5346         struct mlx5_core_dev *mdev = dev->mdev;
5347         unsigned long flags;
5348         int err = 0;
5349         int nreq;
5350         int ind;
5351         int i;
5352
5353         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5354                      !drain)) {
5355                 *bad_wr = wr;
5356                 return -EIO;
5357         }
5358
5359         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5360                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5361
5362         spin_lock_irqsave(&qp->rq.lock, flags);
5363
5364         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5365
5366         for (nreq = 0; wr; nreq++, wr = wr->next) {
5367                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5368                         err = -ENOMEM;
5369                         *bad_wr = wr;
5370                         goto out;
5371                 }
5372
5373                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5374                         err = -EINVAL;
5375                         *bad_wr = wr;
5376                         goto out;
5377                 }
5378
5379                 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
5380                 if (qp->wq_sig)
5381                         scat++;
5382
5383                 for (i = 0; i < wr->num_sge; i++)
5384                         set_data_ptr_seg(scat + i, wr->sg_list + i);
5385
5386                 if (i < qp->rq.max_gs) {
5387                         scat[i].byte_count = 0;
5388                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
5389                         scat[i].addr       = 0;
5390                 }
5391
5392                 if (qp->wq_sig) {
5393                         sig = (struct mlx5_rwqe_sig *)scat;
5394                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5395                 }
5396
5397                 qp->rq.wrid[ind] = wr->wr_id;
5398
5399                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5400         }
5401
5402 out:
5403         if (likely(nreq)) {
5404                 qp->rq.head += nreq;
5405
5406                 /* Make sure that descriptors are written before
5407                  * doorbell record.
5408                  */
5409                 wmb();
5410
5411                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5412         }
5413
5414         spin_unlock_irqrestore(&qp->rq.lock, flags);
5415
5416         return err;
5417 }
5418
5419 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5420                       const struct ib_recv_wr **bad_wr)
5421 {
5422         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5423 }
5424
5425 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5426 {
5427         switch (mlx5_state) {
5428         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
5429         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
5430         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
5431         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
5432         case MLX5_QP_STATE_SQ_DRAINING:
5433         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
5434         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
5435         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
5436         default:                     return -1;
5437         }
5438 }
5439
5440 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5441 {
5442         switch (mlx5_mig_state) {
5443         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
5444         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
5445         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
5446         default: return -1;
5447         }
5448 }
5449
5450 static int to_ib_qp_access_flags(int mlx5_flags)
5451 {
5452         int ib_flags = 0;
5453
5454         if (mlx5_flags & MLX5_QP_BIT_RRE)
5455                 ib_flags |= IB_ACCESS_REMOTE_READ;
5456         if (mlx5_flags & MLX5_QP_BIT_RWE)
5457                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5458         if (mlx5_flags & MLX5_QP_BIT_RAE)
5459                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5460
5461         return ib_flags;
5462 }
5463
5464 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5465                             struct rdma_ah_attr *ah_attr,
5466                             struct mlx5_qp_path *path)
5467 {
5468
5469         memset(ah_attr, 0, sizeof(*ah_attr));
5470
5471         if (!path->port || path->port > ibdev->num_ports)
5472                 return;
5473
5474         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5475
5476         rdma_ah_set_port_num(ah_attr, path->port);
5477         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5478
5479         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5480         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5481         rdma_ah_set_static_rate(ah_attr,
5482                                 path->static_rate ? path->static_rate - 5 : 0);
5483         if (path->grh_mlid & (1 << 7)) {
5484                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5485
5486                 rdma_ah_set_grh(ah_attr, NULL,
5487                                 tc_fl & 0xfffff,
5488                                 path->mgid_index,
5489                                 path->hop_limit,
5490                                 (tc_fl >> 20) & 0xff);
5491                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5492         }
5493 }
5494
5495 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5496                                         struct mlx5_ib_sq *sq,
5497                                         u8 *sq_state)
5498 {
5499         int err;
5500
5501         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5502         if (err)
5503                 goto out;
5504         sq->state = *sq_state;
5505
5506 out:
5507         return err;
5508 }
5509
5510 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5511                                         struct mlx5_ib_rq *rq,
5512                                         u8 *rq_state)
5513 {
5514         void *out;
5515         void *rqc;
5516         int inlen;
5517         int err;
5518
5519         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5520         out = kvzalloc(inlen, GFP_KERNEL);
5521         if (!out)
5522                 return -ENOMEM;
5523
5524         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5525         if (err)
5526                 goto out;
5527
5528         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5529         *rq_state = MLX5_GET(rqc, rqc, state);
5530         rq->state = *rq_state;
5531
5532 out:
5533         kvfree(out);
5534         return err;
5535 }
5536
5537 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5538                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5539 {
5540         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5541                 [MLX5_RQC_STATE_RST] = {
5542                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5543                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5544                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5545                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5546                 },
5547                 [MLX5_RQC_STATE_RDY] = {
5548                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5549                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5550                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5551                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5552                 },
5553                 [MLX5_RQC_STATE_ERR] = {
5554                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5555                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5556                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5557                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5558                 },
5559                 [MLX5_RQ_STATE_NA] = {
5560                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5561                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5562                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5563                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5564                 },
5565         };
5566
5567         *qp_state = sqrq_trans[rq_state][sq_state];
5568
5569         if (*qp_state == MLX5_QP_STATE_BAD) {
5570                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5571                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5572                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5573                 return -EINVAL;
5574         }
5575
5576         if (*qp_state == MLX5_QP_STATE)
5577                 *qp_state = qp->state;
5578
5579         return 0;
5580 }
5581
5582 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5583                                      struct mlx5_ib_qp *qp,
5584                                      u8 *raw_packet_qp_state)
5585 {
5586         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5587         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5588         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5589         int err;
5590         u8 sq_state = MLX5_SQ_STATE_NA;
5591         u8 rq_state = MLX5_RQ_STATE_NA;
5592
5593         if (qp->sq.wqe_cnt) {
5594                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5595                 if (err)
5596                         return err;
5597         }
5598
5599         if (qp->rq.wqe_cnt) {
5600                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5601                 if (err)
5602                         return err;
5603         }
5604
5605         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5606                                       raw_packet_qp_state);
5607 }
5608
5609 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5610                          struct ib_qp_attr *qp_attr)
5611 {
5612         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5613         struct mlx5_qp_context *context;
5614         int mlx5_state;
5615         u32 *outb;
5616         int err = 0;
5617
5618         outb = kzalloc(outlen, GFP_KERNEL);
5619         if (!outb)
5620                 return -ENOMEM;
5621
5622         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5623                                  outlen);
5624         if (err)
5625                 goto out;
5626
5627         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5628         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5629
5630         mlx5_state = be32_to_cpu(context->flags) >> 28;
5631
5632         qp->state                    = to_ib_qp_state(mlx5_state);
5633         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5634         qp_attr->path_mig_state      =
5635                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5636         qp_attr->qkey                = be32_to_cpu(context->qkey);
5637         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5638         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5639         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5640         qp_attr->qp_access_flags     =
5641                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5642
5643         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5644                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5645                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5646                 qp_attr->alt_pkey_index =
5647                         be16_to_cpu(context->alt_path.pkey_index);
5648                 qp_attr->alt_port_num   =
5649                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5650         }
5651
5652         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5653         qp_attr->port_num = context->pri_path.port;
5654
5655         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5656         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5657
5658         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5659
5660         qp_attr->max_dest_rd_atomic =
5661                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5662         qp_attr->min_rnr_timer      =
5663                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5664         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5665         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5666         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5667         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5668
5669 out:
5670         kfree(outb);
5671         return err;
5672 }
5673
5674 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5675                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5676                                 struct ib_qp_init_attr *qp_init_attr)
5677 {
5678         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5679         u32 *out;
5680         u32 access_flags = 0;
5681         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5682         void *dctc;
5683         int err;
5684         int supported_mask = IB_QP_STATE |
5685                              IB_QP_ACCESS_FLAGS |
5686                              IB_QP_PORT |
5687                              IB_QP_MIN_RNR_TIMER |
5688                              IB_QP_AV |
5689                              IB_QP_PATH_MTU |
5690                              IB_QP_PKEY_INDEX;
5691
5692         if (qp_attr_mask & ~supported_mask)
5693                 return -EINVAL;
5694         if (mqp->state != IB_QPS_RTR)
5695                 return -EINVAL;
5696
5697         out = kzalloc(outlen, GFP_KERNEL);
5698         if (!out)
5699                 return -ENOMEM;
5700
5701         err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5702         if (err)
5703                 goto out;
5704
5705         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5706
5707         if (qp_attr_mask & IB_QP_STATE)
5708                 qp_attr->qp_state = IB_QPS_RTR;
5709
5710         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5711                 if (MLX5_GET(dctc, dctc, rre))
5712                         access_flags |= IB_ACCESS_REMOTE_READ;
5713                 if (MLX5_GET(dctc, dctc, rwe))
5714                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5715                 if (MLX5_GET(dctc, dctc, rae))
5716                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5717                 qp_attr->qp_access_flags = access_flags;
5718         }
5719
5720         if (qp_attr_mask & IB_QP_PORT)
5721                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5722         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5723                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5724         if (qp_attr_mask & IB_QP_AV) {
5725                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5726                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5727                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5728                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5729         }
5730         if (qp_attr_mask & IB_QP_PATH_MTU)
5731                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5732         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5733                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5734 out:
5735         kfree(out);
5736         return err;
5737 }
5738
5739 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5740                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5741 {
5742         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5743         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5744         int err = 0;
5745         u8 raw_packet_qp_state;
5746
5747         if (ibqp->rwq_ind_tbl)
5748                 return -ENOSYS;
5749
5750         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5751                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5752                                             qp_init_attr);
5753
5754         /* Not all of output fields are applicable, make sure to zero them */
5755         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5756         memset(qp_attr, 0, sizeof(*qp_attr));
5757
5758         if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5759                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5760                                             qp_attr_mask, qp_init_attr);
5761
5762         mutex_lock(&qp->mutex);
5763
5764         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5765             qp->flags & MLX5_IB_QP_UNDERLAY) {
5766                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5767                 if (err)
5768                         goto out;
5769                 qp->state = raw_packet_qp_state;
5770                 qp_attr->port_num = 1;
5771         } else {
5772                 err = query_qp_attr(dev, qp, qp_attr);
5773                 if (err)
5774                         goto out;
5775         }
5776
5777         qp_attr->qp_state            = qp->state;
5778         qp_attr->cur_qp_state        = qp_attr->qp_state;
5779         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5780         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5781
5782         if (!ibqp->uobject) {
5783                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5784                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5785                 qp_init_attr->qp_context = ibqp->qp_context;
5786         } else {
5787                 qp_attr->cap.max_send_wr  = 0;
5788                 qp_attr->cap.max_send_sge = 0;
5789         }
5790
5791         qp_init_attr->qp_type = ibqp->qp_type;
5792         qp_init_attr->recv_cq = ibqp->recv_cq;
5793         qp_init_attr->send_cq = ibqp->send_cq;
5794         qp_init_attr->srq = ibqp->srq;
5795         qp_attr->cap.max_inline_data = qp->max_inline_data;
5796
5797         qp_init_attr->cap            = qp_attr->cap;
5798
5799         qp_init_attr->create_flags = 0;
5800         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5801                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5802
5803         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5804                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5805         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5806                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5807         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5808                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5809         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5810                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5811
5812         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5813                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5814
5815 out:
5816         mutex_unlock(&qp->mutex);
5817         return err;
5818 }
5819
5820 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5821                                    struct ib_udata *udata)
5822 {
5823         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5824         struct mlx5_ib_xrcd *xrcd;
5825         int err;
5826
5827         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5828                 return ERR_PTR(-ENOSYS);
5829
5830         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5831         if (!xrcd)
5832                 return ERR_PTR(-ENOMEM);
5833
5834         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
5835         if (err) {
5836                 kfree(xrcd);
5837                 return ERR_PTR(-ENOMEM);
5838         }
5839
5840         return &xrcd->ibxrcd;
5841 }
5842
5843 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
5844 {
5845         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5846         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5847         int err;
5848
5849         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
5850         if (err)
5851                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5852
5853         kfree(xrcd);
5854         return 0;
5855 }
5856
5857 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5858 {
5859         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5860         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5861         struct ib_event event;
5862
5863         if (rwq->ibwq.event_handler) {
5864                 event.device     = rwq->ibwq.device;
5865                 event.element.wq = &rwq->ibwq;
5866                 switch (type) {
5867                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5868                         event.event = IB_EVENT_WQ_FATAL;
5869                         break;
5870                 default:
5871                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5872                         return;
5873                 }
5874
5875                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5876         }
5877 }
5878
5879 static int set_delay_drop(struct mlx5_ib_dev *dev)
5880 {
5881         int err = 0;
5882
5883         mutex_lock(&dev->delay_drop.lock);
5884         if (dev->delay_drop.activate)
5885                 goto out;
5886
5887         err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5888         if (err)
5889                 goto out;
5890
5891         dev->delay_drop.activate = true;
5892 out:
5893         mutex_unlock(&dev->delay_drop.lock);
5894
5895         if (!err)
5896                 atomic_inc(&dev->delay_drop.rqs_cnt);
5897         return err;
5898 }
5899
5900 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5901                       struct ib_wq_init_attr *init_attr)
5902 {
5903         struct mlx5_ib_dev *dev;
5904         int has_net_offloads;
5905         __be64 *rq_pas0;
5906         void *in;
5907         void *rqc;
5908         void *wq;
5909         int inlen;
5910         int err;
5911
5912         dev = to_mdev(pd->device);
5913
5914         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5915         in = kvzalloc(inlen, GFP_KERNEL);
5916         if (!in)
5917                 return -ENOMEM;
5918
5919         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5920         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5921         MLX5_SET(rqc,  rqc, mem_rq_type,
5922                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5923         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5924         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5925         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5926         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5927         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5928         MLX5_SET(wq, wq, wq_type,
5929                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5930                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5931         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5932                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5933                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5934                         err = -EOPNOTSUPP;
5935                         goto out;
5936                 } else {
5937                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5938                 }
5939         }
5940         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5941         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5942                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5943                 MLX5_SET(wq, wq, log_wqe_stride_size,
5944                          rwq->single_stride_log_num_of_bytes -
5945                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5946                 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5947                          MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5948         }
5949         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5950         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5951         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5952         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5953         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5954         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5955         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5956         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5957                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5958                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5959                         err = -EOPNOTSUPP;
5960                         goto out;
5961                 }
5962         } else {
5963                 MLX5_SET(rqc, rqc, vsd, 1);
5964         }
5965         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5966                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5967                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5968                         err = -EOPNOTSUPP;
5969                         goto out;
5970                 }
5971                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5972         }
5973         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5974                 if (!(dev->ib_dev.attrs.raw_packet_caps &
5975                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
5976                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5977                         err = -EOPNOTSUPP;
5978                         goto out;
5979                 }
5980                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5981         }
5982         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5983         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5984         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5985         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5986                 err = set_delay_drop(dev);
5987                 if (err) {
5988                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5989                                      err);
5990                         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5991                 } else {
5992                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5993                 }
5994         }
5995 out:
5996         kvfree(in);
5997         return err;
5998 }
5999
6000 static int set_user_rq_size(struct mlx5_ib_dev *dev,
6001                             struct ib_wq_init_attr *wq_init_attr,
6002                             struct mlx5_ib_create_wq *ucmd,
6003                             struct mlx5_ib_rwq *rwq)
6004 {
6005         /* Sanity check RQ size before proceeding */
6006         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
6007                 return -EINVAL;
6008
6009         if (!ucmd->rq_wqe_count)
6010                 return -EINVAL;
6011
6012         rwq->wqe_count = ucmd->rq_wqe_count;
6013         rwq->wqe_shift = ucmd->rq_wqe_shift;
6014         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
6015                 return -EINVAL;
6016
6017         rwq->log_rq_stride = rwq->wqe_shift;
6018         rwq->log_rq_size = ilog2(rwq->wqe_count);
6019         return 0;
6020 }
6021
6022 static int prepare_user_rq(struct ib_pd *pd,
6023                            struct ib_wq_init_attr *init_attr,
6024                            struct ib_udata *udata,
6025                            struct mlx5_ib_rwq *rwq)
6026 {
6027         struct mlx5_ib_dev *dev = to_mdev(pd->device);
6028         struct mlx5_ib_create_wq ucmd = {};
6029         int err;
6030         size_t required_cmd_sz;
6031
6032         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
6033                 + sizeof(ucmd.single_stride_log_num_of_bytes);
6034         if (udata->inlen < required_cmd_sz) {
6035                 mlx5_ib_dbg(dev, "invalid inlen\n");
6036                 return -EINVAL;
6037         }
6038
6039         if (udata->inlen > sizeof(ucmd) &&
6040             !ib_is_udata_cleared(udata, sizeof(ucmd),
6041                                  udata->inlen - sizeof(ucmd))) {
6042                 mlx5_ib_dbg(dev, "inlen is not supported\n");
6043                 return -EOPNOTSUPP;
6044         }
6045
6046         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
6047                 mlx5_ib_dbg(dev, "copy failed\n");
6048                 return -EFAULT;
6049         }
6050
6051         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
6052                 mlx5_ib_dbg(dev, "invalid comp mask\n");
6053                 return -EOPNOTSUPP;
6054         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
6055                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
6056                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
6057                         return -EOPNOTSUPP;
6058                 }
6059                 if ((ucmd.single_stride_log_num_of_bytes <
6060                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
6061                     (ucmd.single_stride_log_num_of_bytes >
6062                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
6063                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
6064                                     ucmd.single_stride_log_num_of_bytes,
6065                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
6066                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
6067                         return -EINVAL;
6068                 }
6069                 if ((ucmd.single_wqe_log_num_of_strides >
6070                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
6071                      (ucmd.single_wqe_log_num_of_strides <
6072                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
6073                         mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
6074                                     ucmd.single_wqe_log_num_of_strides,
6075                                     MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
6076                                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
6077                         return -EINVAL;
6078                 }
6079                 rwq->single_stride_log_num_of_bytes =
6080                         ucmd.single_stride_log_num_of_bytes;
6081                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
6082                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
6083                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
6084         }
6085
6086         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
6087         if (err) {
6088                 mlx5_ib_dbg(dev, "err %d\n", err);
6089                 return err;
6090         }
6091
6092         err = create_user_rq(dev, pd, udata, rwq, &ucmd);
6093         if (err) {
6094                 mlx5_ib_dbg(dev, "err %d\n", err);
6095                 return err;
6096         }
6097
6098         rwq->user_index = ucmd.user_index;
6099         return 0;
6100 }
6101
6102 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
6103                                 struct ib_wq_init_attr *init_attr,
6104                                 struct ib_udata *udata)
6105 {
6106         struct mlx5_ib_dev *dev;
6107         struct mlx5_ib_rwq *rwq;
6108         struct mlx5_ib_create_wq_resp resp = {};
6109         size_t min_resp_len;
6110         int err;
6111
6112         if (!udata)
6113                 return ERR_PTR(-ENOSYS);
6114
6115         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6116         if (udata->outlen && udata->outlen < min_resp_len)
6117                 return ERR_PTR(-EINVAL);
6118
6119         dev = to_mdev(pd->device);
6120         switch (init_attr->wq_type) {
6121         case IB_WQT_RQ:
6122                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
6123                 if (!rwq)
6124                         return ERR_PTR(-ENOMEM);
6125                 err = prepare_user_rq(pd, init_attr, udata, rwq);
6126                 if (err)
6127                         goto err;
6128                 err = create_rq(rwq, pd, init_attr);
6129                 if (err)
6130                         goto err_user_rq;
6131                 break;
6132         default:
6133                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
6134                             init_attr->wq_type);
6135                 return ERR_PTR(-EINVAL);
6136         }
6137
6138         rwq->ibwq.wq_num = rwq->core_qp.qpn;
6139         rwq->ibwq.state = IB_WQS_RESET;
6140         if (udata->outlen) {
6141                 resp.response_length = offsetof(typeof(resp), response_length) +
6142                                 sizeof(resp.response_length);
6143                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6144                 if (err)
6145                         goto err_copy;
6146         }
6147
6148         rwq->core_qp.event = mlx5_ib_wq_event;
6149         rwq->ibwq.event_handler = init_attr->event_handler;
6150         return &rwq->ibwq;
6151
6152 err_copy:
6153         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
6154 err_user_rq:
6155         destroy_user_rq(dev, pd, rwq, udata);
6156 err:
6157         kfree(rwq);
6158         return ERR_PTR(err);
6159 }
6160
6161 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
6162 {
6163         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6164         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6165
6166         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
6167         destroy_user_rq(dev, wq->pd, rwq, udata);
6168         kfree(rwq);
6169 }
6170
6171 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
6172                                                       struct ib_rwq_ind_table_init_attr *init_attr,
6173                                                       struct ib_udata *udata)
6174 {
6175         struct mlx5_ib_dev *dev = to_mdev(device);
6176         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
6177         int sz = 1 << init_attr->log_ind_tbl_size;
6178         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
6179         size_t min_resp_len;
6180         int inlen;
6181         int err;
6182         int i;
6183         u32 *in;
6184         void *rqtc;
6185
6186         if (udata->inlen > 0 &&
6187             !ib_is_udata_cleared(udata, 0,
6188                                  udata->inlen))
6189                 return ERR_PTR(-EOPNOTSUPP);
6190
6191         if (init_attr->log_ind_tbl_size >
6192             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
6193                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
6194                             init_attr->log_ind_tbl_size,
6195                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
6196                 return ERR_PTR(-EINVAL);
6197         }
6198
6199         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6200         if (udata->outlen && udata->outlen < min_resp_len)
6201                 return ERR_PTR(-EINVAL);
6202
6203         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
6204         if (!rwq_ind_tbl)
6205                 return ERR_PTR(-ENOMEM);
6206
6207         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
6208         in = kvzalloc(inlen, GFP_KERNEL);
6209         if (!in) {
6210                 err = -ENOMEM;
6211                 goto err;
6212         }
6213
6214         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
6215
6216         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
6217         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
6218
6219         for (i = 0; i < sz; i++)
6220                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
6221
6222         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
6223         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
6224
6225         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
6226         kvfree(in);
6227
6228         if (err)
6229                 goto err;
6230
6231         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
6232         if (udata->outlen) {
6233                 resp.response_length = offsetof(typeof(resp), response_length) +
6234                                         sizeof(resp.response_length);
6235                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6236                 if (err)
6237                         goto err_copy;
6238         }
6239
6240         return &rwq_ind_tbl->ib_rwq_ind_tbl;
6241
6242 err_copy:
6243         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6244 err:
6245         kfree(rwq_ind_tbl);
6246         return ERR_PTR(err);
6247 }
6248
6249 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
6250 {
6251         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
6252         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
6253
6254         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
6255
6256         kfree(rwq_ind_tbl);
6257         return 0;
6258 }
6259
6260 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
6261                       u32 wq_attr_mask, struct ib_udata *udata)
6262 {
6263         struct mlx5_ib_dev *dev = to_mdev(wq->device);
6264         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6265         struct mlx5_ib_modify_wq ucmd = {};
6266         size_t required_cmd_sz;
6267         int curr_wq_state;
6268         int wq_state;
6269         int inlen;
6270         int err;
6271         void *rqc;
6272         void *in;
6273
6274         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
6275         if (udata->inlen < required_cmd_sz)
6276                 return -EINVAL;
6277
6278         if (udata->inlen > sizeof(ucmd) &&
6279             !ib_is_udata_cleared(udata, sizeof(ucmd),
6280                                  udata->inlen - sizeof(ucmd)))
6281                 return -EOPNOTSUPP;
6282
6283         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
6284                 return -EFAULT;
6285
6286         if (ucmd.comp_mask || ucmd.reserved)
6287                 return -EOPNOTSUPP;
6288
6289         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
6290         in = kvzalloc(inlen, GFP_KERNEL);
6291         if (!in)
6292                 return -ENOMEM;
6293
6294         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6295
6296         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6297                 wq_attr->curr_wq_state : wq->state;
6298         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6299                 wq_attr->wq_state : curr_wq_state;
6300         if (curr_wq_state == IB_WQS_ERR)
6301                 curr_wq_state = MLX5_RQC_STATE_ERR;
6302         if (wq_state == IB_WQS_ERR)
6303                 wq_state = MLX5_RQC_STATE_ERR;
6304         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
6305         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
6306         MLX5_SET(rqc, rqc, state, wq_state);
6307
6308         if (wq_attr_mask & IB_WQ_FLAGS) {
6309                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6310                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6311                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6312                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
6313                                             "supported\n");
6314                                 err = -EOPNOTSUPP;
6315                                 goto out;
6316                         }
6317                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6318                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6319                         MLX5_SET(rqc, rqc, vsd,
6320                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6321                 }
6322
6323                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6324                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6325                         err = -EOPNOTSUPP;
6326                         goto out;
6327                 }
6328         }
6329
6330         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6331                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6332                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6333                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
6334                         MLX5_SET(rqc, rqc, counter_set_id,
6335                                  dev->port->cnts.set_id);
6336                 } else
6337                         dev_info_once(
6338                                 &dev->ib_dev.dev,
6339                                 "Receive WQ counters are not supported on current FW\n");
6340         }
6341
6342         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
6343         if (!err)
6344                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6345
6346 out:
6347         kvfree(in);
6348         return err;
6349 }
6350
6351 struct mlx5_ib_drain_cqe {
6352         struct ib_cqe cqe;
6353         struct completion done;
6354 };
6355
6356 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6357 {
6358         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6359                                                      struct mlx5_ib_drain_cqe,
6360                                                      cqe);
6361
6362         complete(&cqe->done);
6363 }
6364
6365 /* This function returns only once the drained WR was completed */
6366 static void handle_drain_completion(struct ib_cq *cq,
6367                                     struct mlx5_ib_drain_cqe *sdrain,
6368                                     struct mlx5_ib_dev *dev)
6369 {
6370         struct mlx5_core_dev *mdev = dev->mdev;
6371
6372         if (cq->poll_ctx == IB_POLL_DIRECT) {
6373                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6374                         ib_process_cq_direct(cq, -1);
6375                 return;
6376         }
6377
6378         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6379                 struct mlx5_ib_cq *mcq = to_mcq(cq);
6380                 bool triggered = false;
6381                 unsigned long flags;
6382
6383                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6384                 /* Make sure that the CQ handler won't run if wasn't run yet */
6385                 if (!mcq->mcq.reset_notify_added)
6386                         mcq->mcq.reset_notify_added = 1;
6387                 else
6388                         triggered = true;
6389                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6390
6391                 if (triggered) {
6392                         /* Wait for any scheduled/running task to be ended */
6393                         switch (cq->poll_ctx) {
6394                         case IB_POLL_SOFTIRQ:
6395                                 irq_poll_disable(&cq->iop);
6396                                 irq_poll_enable(&cq->iop);
6397                                 break;
6398                         case IB_POLL_WORKQUEUE:
6399                                 cancel_work_sync(&cq->work);
6400                                 break;
6401                         default:
6402                                 WARN_ON_ONCE(1);
6403                         }
6404                 }
6405
6406                 /* Run the CQ handler - this makes sure that the drain WR will
6407                  * be processed if wasn't processed yet.
6408                  */
6409                 mcq->mcq.comp(&mcq->mcq, NULL);
6410         }
6411
6412         wait_for_completion(&sdrain->done);
6413 }
6414
6415 void mlx5_ib_drain_sq(struct ib_qp *qp)
6416 {
6417         struct ib_cq *cq = qp->send_cq;
6418         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6419         struct mlx5_ib_drain_cqe sdrain;
6420         const struct ib_send_wr *bad_swr;
6421         struct ib_rdma_wr swr = {
6422                 .wr = {
6423                         .next = NULL,
6424                         { .wr_cqe       = &sdrain.cqe, },
6425                         .opcode = IB_WR_RDMA_WRITE,
6426                 },
6427         };
6428         int ret;
6429         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6430         struct mlx5_core_dev *mdev = dev->mdev;
6431
6432         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6433         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6434                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6435                 return;
6436         }
6437
6438         sdrain.cqe.done = mlx5_ib_drain_qp_done;
6439         init_completion(&sdrain.done);
6440
6441         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6442         if (ret) {
6443                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6444                 return;
6445         }
6446
6447         handle_drain_completion(cq, &sdrain, dev);
6448 }
6449
6450 void mlx5_ib_drain_rq(struct ib_qp *qp)
6451 {
6452         struct ib_cq *cq = qp->recv_cq;
6453         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6454         struct mlx5_ib_drain_cqe rdrain;
6455         struct ib_recv_wr rwr = {};
6456         const struct ib_recv_wr *bad_rwr;
6457         int ret;
6458         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6459         struct mlx5_core_dev *mdev = dev->mdev;
6460
6461         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6462         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6463                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6464                 return;
6465         }
6466
6467         rwr.wr_cqe = &rdrain.cqe;
6468         rdrain.cqe.done = mlx5_ib_drain_qp_done;
6469         init_completion(&rdrain.done);
6470
6471         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6472         if (ret) {
6473                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6474                 return;
6475         }
6476
6477         handle_drain_completion(cq, &rdrain, dev);
6478 }
6479
6480 /**
6481  * Bind a qp to a counter. If @counter is NULL then bind the qp to
6482  * the default counter
6483  */
6484 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
6485 {
6486         struct mlx5_ib_qp *mqp = to_mqp(qp);
6487         int err = 0;
6488
6489         mutex_lock(&mqp->mutex);
6490         if (mqp->state == IB_QPS_RESET) {
6491                 qp->counter = counter;
6492                 goto out;
6493         }
6494
6495         if (mqp->state == IB_QPS_RTS) {
6496                 err = __mlx5_ib_qp_set_counter(qp, counter);
6497                 if (!err)
6498                         qp->counter = counter;
6499
6500                 goto out;
6501         }
6502
6503         mqp->counter_pending = 1;
6504         qp->counter = counter;
6505
6506 out:
6507         mutex_unlock(&mqp->mutex);
6508         return err;
6509 }