2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_umem.h>
40 #include <rdma/ib_smi.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/fs.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/types.h>
46 #include <linux/mlx5/transobj.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/mlx5-abi.h>
49 #include <rdma/uverbs_ioctl.h>
50 #include <rdma/mlx5_user_ioctl_cmds.h>
51 #include <rdma/mlx5_user_ioctl_verbs.h>
55 #define mlx5_ib_dbg(_dev, format, arg...) \
56 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
57 __LINE__, current->pid, ##arg)
59 #define mlx5_ib_err(_dev, format, arg...) \
60 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
61 __LINE__, current->pid, ##arg)
63 #define mlx5_ib_warn(_dev, format, arg...) \
64 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
65 __LINE__, current->pid, ##arg)
67 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
68 sizeof(((type *)0)->fld) <= (sz))
69 #define MLX5_IB_DEFAULT_UIDX 0xffffff
70 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
72 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
75 MLX5_IB_MMAP_CMD_SHIFT = 8,
76 MLX5_IB_MMAP_CMD_MASK = 0xff,
80 MLX5_RES_SCAT_DATA32_CQE = 0x1,
81 MLX5_RES_SCAT_DATA64_CQE = 0x2,
82 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
83 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
86 enum mlx5_ib_mad_ifc_flags {
87 MLX5_MAD_IFC_IGNORE_MKEY = 1,
88 MLX5_MAD_IFC_IGNORE_BKEY = 2,
89 MLX5_MAD_IFC_NET_VIEW = 4,
93 MLX5_CROSS_CHANNEL_BFREG = 0,
102 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
107 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
108 MLX5_IB_INVALID_BFREG = BIT(31),
112 MLX5_MAX_MEMIC_PAGES = 0x100,
113 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
117 MLX5_MEMIC_BASE_ALIGN = 6,
118 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
121 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) \
122 (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
123 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
125 struct mlx5_ib_ucontext {
126 struct ib_ucontext ibucontext;
127 struct list_head db_page_list;
129 /* protect doorbell record alloc/free
131 struct mutex db_page_mutex;
132 struct mlx5_bfreg_info bfregi;
134 /* Transport Domain number */
138 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES);
140 /* For RoCE LAG TX affinity */
141 atomic_t tx_port_affinity;
144 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
146 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
156 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
157 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
158 MLX5_IB_FLOW_ACTION_DECAP,
161 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
162 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
163 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
164 #error "Invalid number of bypass priorities"
166 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
168 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
169 #define MLX5_IB_NUM_SNIFFER_FTS 2
170 #define MLX5_IB_NUM_EGRESS_FTS 1
171 struct mlx5_ib_flow_prio {
172 struct mlx5_flow_table *flow_table;
173 unsigned int refcount;
176 struct mlx5_ib_flow_handler {
177 struct list_head list;
178 struct ib_flow ibflow;
179 struct mlx5_ib_flow_prio *prio;
180 struct mlx5_flow_handle *rule;
181 struct ib_counters *ibcounters;
182 struct mlx5_ib_dev *dev;
183 struct mlx5_ib_flow_matcher *flow_matcher;
186 struct mlx5_ib_flow_matcher {
187 struct mlx5_ib_match_params matcher_mask;
189 enum mlx5_ib_flow_type flow_type;
190 enum mlx5_flow_namespace_type ns_type;
192 struct mlx5_core_dev *mdev;
194 u8 match_criteria_enable;
197 struct mlx5_ib_flow_db {
198 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
199 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
200 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
201 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
202 struct mlx5_ib_flow_prio fdb;
203 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT];
204 struct mlx5_flow_table *lag_demux_ft;
205 /* Protect flow steering bypass flow tables
206 * when add/del flow rules.
207 * only single add/removal of flow steering rule could be done
213 /* Use macros here so that don't have to duplicate
214 * enum ib_send_flags and enum ib_qp_type for low-level driver
217 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
218 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
219 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
220 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
221 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
222 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
224 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
226 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
227 * creates the actual hardware QP.
229 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
230 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
231 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
232 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
234 #define MLX5_IB_UMR_OCTOWORD 16
235 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
237 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
238 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
239 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
240 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
241 #define MLX5_IB_UPD_XLT_PD BIT(4)
242 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
243 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
245 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
247 * These flags are intended for internal use by the mlx5_ib driver, and they
248 * rely on the range reserved for that use in the ib_qp_create_flags enum.
251 /* Create a UD QP whose source QP number is 1 */
252 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void)
254 return IB_QP_CREATE_RESERVED_START;
262 enum mlx5_ib_rq_flags {
263 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
264 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
268 struct mlx5_frag_buf_ctrl fbc;
271 struct wr_list *w_list;
275 /* serialize post to the work queue
289 enum mlx5_ib_wq_flags {
290 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
291 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
294 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
295 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
296 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
297 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
301 struct mlx5_core_qp core_qp;
308 u32 two_byte_shift_en;
309 u32 single_stride_log_num_of_bytes;
310 struct ib_umem *umem;
312 unsigned int page_shift;
319 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
333 struct mlx5_ib_rwq_ind_table {
334 struct ib_rwq_ind_table ib_rwq_ind_tbl;
339 struct mlx5_ib_ubuffer {
340 struct ib_umem *umem;
345 struct mlx5_ib_qp_base {
346 struct mlx5_ib_qp *container_mibqp;
347 struct mlx5_core_qp mqp;
348 struct mlx5_ib_ubuffer ubuffer;
351 struct mlx5_ib_qp_trans {
352 struct mlx5_ib_qp_base base;
359 struct mlx5_ib_rss_qp {
364 struct mlx5_ib_qp_base base;
365 struct mlx5_ib_wq *rq;
366 struct mlx5_ib_ubuffer ubuffer;
367 struct mlx5_db *doorbell;
374 struct mlx5_ib_qp_base base;
375 struct mlx5_ib_wq *sq;
376 struct mlx5_ib_ubuffer ubuffer;
377 struct mlx5_db *doorbell;
378 struct mlx5_flow_handle *flow_rule;
383 struct mlx5_ib_raw_packet_qp {
384 struct mlx5_ib_sq sq;
385 struct mlx5_ib_rq rq;
390 unsigned long offset;
391 struct mlx5_sq_bfreg *bfreg;
395 struct mlx5_core_dct mdct;
402 struct mlx5_ib_qp_trans trans_qp;
403 struct mlx5_ib_raw_packet_qp raw_packet_qp;
404 struct mlx5_ib_rss_qp rss_qp;
405 struct mlx5_ib_dct dct;
407 struct mlx5_frag_buf buf;
410 struct mlx5_ib_wq rq;
414 struct mlx5_ib_wq sq;
416 /* serialize qp state modifications
428 /* only for user space QPs. For kernel
429 * we have it from the bf object
435 struct list_head qps_list;
436 struct list_head cq_recv_list;
437 struct list_head cq_send_list;
438 struct mlx5_rate_limit rl;
441 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */
442 enum ib_qp_type qp_sub_type;
443 /* A flag to indicate if there's a new counter is configured
444 * but not take effective
449 struct mlx5_ib_cq_buf {
450 struct mlx5_frag_buf_ctrl fbc;
451 struct mlx5_frag_buf frag_buf;
452 struct ib_umem *umem;
457 enum mlx5_ib_qp_flags {
458 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
459 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
460 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL,
461 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND,
462 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV,
463 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5,
464 /* QP uses 1 as its source QP number */
465 MLX5_IB_QP_SQPN_QP1 = 1 << 6,
466 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7,
467 MLX5_IB_QP_RSS = 1 << 8,
468 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9,
469 MLX5_IB_QP_UNDERLAY = 1 << 10,
470 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11,
471 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12,
472 MLX5_IB_QP_PACKET_BASED_CREDIT = 1 << 13,
476 struct ib_send_wr wr;
480 unsigned int page_shift;
481 unsigned int xlt_size;
485 u8 ignore_free_state:1;
488 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr)
490 return container_of(wr, struct mlx5_umr_wr, wr);
493 struct mlx5_shared_mr_info {
495 struct ib_umem *umem;
498 enum mlx5_ib_cq_pr_flags {
499 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
504 struct mlx5_core_cq mcq;
505 struct mlx5_ib_cq_buf buf;
508 /* serialize access to the CQ
514 struct mutex resize_mutex;
515 struct mlx5_ib_cq_buf *resize_buf;
516 struct ib_umem *resize_umem;
518 struct list_head list_send_qp;
519 struct list_head list_recv_qp;
521 struct list_head wc_list;
522 enum ib_cq_notify_flags notify_flags;
523 struct work_struct notify_work;
524 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
529 struct list_head list;
534 struct mlx5_core_srq msrq;
535 struct mlx5_frag_buf buf;
537 struct mlx5_frag_buf_ctrl fbc;
539 /* protect SRQ hanlding
545 struct ib_umem *umem;
546 /* serialize arming a SRQ
552 struct mlx5_ib_xrcd {
553 struct ib_xrcd ibxrcd;
557 enum mlx5_ib_mtt_access_flags {
558 MLX5_IB_MTT_READ = (1 << 0),
559 MLX5_IB_MTT_WRITE = (1 << 1),
564 phys_addr_t dev_addr;
571 /* other dm types specific params should be added here */
575 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
577 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
578 IB_ACCESS_REMOTE_WRITE |\
579 IB_ACCESS_REMOTE_READ |\
580 IB_ACCESS_REMOTE_ATOMIC |\
583 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
584 IB_ACCESS_REMOTE_WRITE |\
585 IB_ACCESS_REMOTE_READ |\
599 struct mlx5_core_mkey mmkey;
600 struct ib_umem *umem;
601 struct mlx5_shared_mr_info *smr_info;
602 struct list_head list;
604 bool allocated_from_cache;
606 struct mlx5_ib_dev *dev;
607 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
608 struct mlx5_core_sig_ctx *sig;
611 int access_flags; /* Needed for rereg MR */
613 struct mlx5_ib_mr *parent;
614 /* Needed for IB_MR_TYPE_INTEGRITY */
615 struct mlx5_ib_mr *pi_mr;
616 struct mlx5_ib_mr *klm_mr;
617 struct mlx5_ib_mr *mtt_mr;
621 atomic_t num_leaf_free;
622 wait_queue_head_t q_leaf_free;
623 struct mlx5_async_work cb_work;
624 atomic_t num_pending_prefetch;
627 static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
629 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
635 struct mlx5_core_mkey mmkey;
639 struct mlx5_ib_devx_mr {
640 struct mlx5_core_mkey mmkey;
644 struct mlx5_ib_umr_context {
646 enum ib_wc_status status;
647 struct completion done;
654 /* control access to UMR QP
656 struct semaphore sem;
665 struct mlx5_cache_ent {
666 struct list_head head;
667 /* sync access to the cahce entry
683 struct mlx5_ib_dev *dev;
684 struct work_struct work;
685 struct delayed_work dwork;
687 struct completion compl;
690 struct mlx5_mr_cache {
691 struct workqueue_struct *wq;
692 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
695 unsigned long last_add;
698 struct mlx5_ib_gsi_qp;
700 struct mlx5_ib_port_resources {
701 struct mlx5_ib_resources *devr;
702 struct mlx5_ib_gsi_qp *gsi;
703 struct work_struct pkey_change_work;
706 struct mlx5_ib_resources {
713 struct mlx5_ib_port_resources ports[2];
714 /* Protects changes to the port resources */
718 struct mlx5_ib_counters {
722 u32 num_cong_counters;
723 u32 num_ext_ppcnt_counters;
728 struct mlx5_ib_multiport_info;
730 struct mlx5_ib_multiport {
731 struct mlx5_ib_multiport_info *mpi;
732 /* To be held when accessing the multiport info */
737 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
740 rwlock_t netdev_lock;
741 struct net_device *netdev;
742 struct notifier_block nb;
743 atomic_t tx_port_affinity;
744 enum ib_port_state last_port_state;
745 struct mlx5_ib_dev *dev;
749 struct mlx5_ib_port {
750 struct mlx5_ib_counters cnts;
751 struct mlx5_ib_multiport mp;
752 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
753 struct mlx5_roce roce;
754 struct mlx5_eswitch_rep *rep;
757 struct mlx5_ib_dbg_param {
759 struct mlx5_ib_dev *dev;
760 struct dentry *dentry;
764 enum mlx5_ib_dbg_cc_types {
765 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
766 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
767 MLX5_IB_DBG_CC_RP_TIME_RESET,
768 MLX5_IB_DBG_CC_RP_BYTE_RESET,
769 MLX5_IB_DBG_CC_RP_THRESHOLD,
770 MLX5_IB_DBG_CC_RP_AI_RATE,
771 MLX5_IB_DBG_CC_RP_HAI_RATE,
772 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
773 MLX5_IB_DBG_CC_RP_MIN_RATE,
774 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
775 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
776 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
777 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
778 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
779 MLX5_IB_DBG_CC_RP_GD,
780 MLX5_IB_DBG_CC_NP_CNP_DSCP,
781 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
782 MLX5_IB_DBG_CC_NP_CNP_PRIO,
786 struct mlx5_ib_dbg_cc_params {
788 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
792 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
795 struct mlx5_ib_delay_drop {
796 struct mlx5_ib_dev *dev;
797 struct work_struct delay_drop_work;
798 /* serialize setting of delay drop */
804 struct dentry *dir_debugfs;
807 enum mlx5_ib_stages {
809 MLX5_IB_STAGE_FLOW_DB,
811 MLX5_IB_STAGE_NON_DEFAULT_CB,
814 MLX5_IB_STAGE_DEVICE_RESOURCES,
815 MLX5_IB_STAGE_DEVICE_NOTIFIER,
817 MLX5_IB_STAGE_COUNTERS,
818 MLX5_IB_STAGE_CONG_DEBUGFS,
821 MLX5_IB_STAGE_PRE_IB_REG_UMR,
822 MLX5_IB_STAGE_WHITELIST_UID,
823 MLX5_IB_STAGE_IB_REG,
824 MLX5_IB_STAGE_POST_IB_REG_UMR,
825 MLX5_IB_STAGE_DELAY_DROP,
826 MLX5_IB_STAGE_CLASS_ATTR,
830 struct mlx5_ib_stage {
831 int (*init)(struct mlx5_ib_dev *dev);
832 void (*cleanup)(struct mlx5_ib_dev *dev);
835 #define STAGE_CREATE(_stage, _init, _cleanup) \
836 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
838 struct mlx5_ib_profile {
839 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
842 struct mlx5_ib_multiport_info {
843 struct list_head list;
844 struct mlx5_ib_dev *ibdev;
845 struct mlx5_core_dev *mdev;
846 struct notifier_block mdev_events;
847 struct completion unref_comp;
854 struct mlx5_ib_flow_action {
855 struct ib_flow_action ib_action;
859 struct mlx5_accel_esp_xfrm *ctx;
862 struct mlx5_ib_dev *dev;
865 struct mlx5_modify_hdr *modify_hdr;
866 struct mlx5_pkt_reformat *pkt_reformat;
873 struct mlx5_core_dev *dev;
874 /* This lock is used to protect the access to the shared
875 * allocation map when concurrent requests by different
876 * processes are handled.
879 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
882 struct mlx5_read_counters_attr {
883 struct mlx5_fc *hw_cntrs_hndl;
888 enum mlx5_ib_counters_type {
889 MLX5_IB_COUNTERS_FLOW,
892 struct mlx5_ib_mcounters {
893 struct ib_counters ibcntrs;
894 enum mlx5_ib_counters_type type;
895 /* number of counters supported for this counters type */
897 struct mlx5_fc *hw_cntrs_hndl;
898 /* read function for this counters type */
899 int (*read_counters)(struct ib_device *ibdev,
900 struct mlx5_read_counters_attr *read_attr);
901 /* max index set as part of create_flow */
903 /* number of counters data entries (<description,index> pair) */
905 /* counters data array for descriptions and indexes */
906 struct mlx5_ib_flow_counters_desc *counters_data;
907 /* protects access to mcounters internal data */
908 struct mutex mcntrs_mutex;
911 static inline struct mlx5_ib_mcounters *
912 to_mcounters(struct ib_counters *ibcntrs)
914 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
917 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
919 struct mlx5_flow_act *action);
920 struct mlx5_ib_lb_state {
921 /* protect the user_td */
928 struct mlx5_ib_pf_eq {
929 struct notifier_block irq_nb;
930 struct mlx5_ib_dev *dev;
931 struct mlx5_eq *core;
932 struct work_struct work;
933 spinlock_t lock; /* Pagefaults spinlock */
934 struct workqueue_struct *wq;
938 struct mlx5_devx_event_table {
939 struct mlx5_nb devx_nb;
940 /* serialize updating the event_xa */
941 struct mutex event_xa_lock;
942 struct xarray event_xa;
946 struct ib_device ib_dev;
947 struct mlx5_core_dev *mdev;
948 struct notifier_block mdev_events;
950 /* serialize update of capability mask
952 struct mutex cap_mask_mutex;
954 struct umr_common umrc;
955 /* sync used page count stats
957 struct mlx5_ib_resources devr;
958 struct mlx5_mr_cache cache;
959 struct timer_list delay_timer;
960 /* Prevents soft lock on massive reg MRs */
961 struct mutex slow_path_mutex;
963 struct ib_odp_caps odp_caps;
965 struct mlx5_ib_pf_eq odp_pf_eq;
968 * Sleepable RCU that prevents destruction of MRs while they are still
969 * being used by a page fault handler.
971 struct srcu_struct mr_srcu;
973 struct mlx5_ib_flow_db *flow_db;
974 /* protect resources needed as part of reset flow */
975 spinlock_t reset_flow_resource_lock;
976 struct list_head qp_list;
977 /* Array with num_ports elements */
978 struct mlx5_ib_port *port;
979 struct mlx5_sq_bfreg bfreg;
980 struct mlx5_sq_bfreg fp_bfreg;
981 struct mlx5_ib_delay_drop delay_drop;
982 const struct mlx5_ib_profile *profile;
986 struct mlx5_ib_lb_state lb;
988 struct list_head ib_dev_list;
991 u16 devx_whitelist_uid;
992 struct mlx5_srq_table srq_table;
993 struct mlx5_async_ctx async_ctx;
994 struct mlx5_devx_event_table devx_event_table;
997 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
999 return container_of(mcq, struct mlx5_ib_cq, mcq);
1002 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1004 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1007 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1009 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1012 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1014 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1015 udata, struct mlx5_ib_ucontext, ibucontext);
1017 return to_mdev(context->ibucontext.device);
1020 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1022 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1025 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1027 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1030 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1032 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1035 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey)
1037 return container_of(mmkey, struct mlx5_ib_mr, mmkey);
1040 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1042 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1045 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1047 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1050 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1052 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1055 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1057 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1060 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1062 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1065 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1067 return container_of(msrq, struct mlx5_ib_srq, msrq);
1070 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
1072 return container_of(ibdm, struct mlx5_ib_dm, ibdm);
1075 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1077 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1080 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1082 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1085 static inline struct mlx5_ib_flow_action *
1086 to_mflow_act(struct ib_flow_action *ibact)
1088 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1091 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context,
1092 struct ib_udata *udata, unsigned long virt,
1093 struct mlx5_db *db);
1094 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1095 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1096 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1097 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1098 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, u32 flags,
1099 struct ib_udata *udata);
1100 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1101 void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags);
1102 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1103 struct ib_udata *udata);
1104 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1105 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1106 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1107 void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1108 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1109 const struct ib_recv_wr **bad_wr);
1110 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1111 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1112 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1113 struct ib_qp_init_attr *init_attr,
1114 struct ib_udata *udata);
1115 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1116 int attr_mask, struct ib_udata *udata);
1117 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1118 struct ib_qp_init_attr *qp_init_attr);
1119 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1120 void mlx5_ib_drain_sq(struct ib_qp *qp);
1121 void mlx5_ib_drain_rq(struct ib_qp *qp);
1122 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1123 const struct ib_send_wr **bad_wr);
1124 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1125 const struct ib_recv_wr **bad_wr);
1126 int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1127 int buflen, size_t *bc);
1128 int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1129 int buflen, size_t *bc);
1130 int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
1131 void *buffer, int buflen, size_t *bc);
1132 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1133 struct ib_udata *udata);
1134 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1135 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1136 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1137 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1138 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1139 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1140 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1141 u64 virt_addr, int access_flags,
1142 struct ib_udata *udata);
1143 int mlx5_ib_advise_mr(struct ib_pd *pd,
1144 enum ib_uverbs_advise_mr_advice advice,
1146 struct ib_sge *sg_list,
1148 struct uverbs_attr_bundle *attrs);
1149 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1150 struct ib_udata *udata);
1151 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1152 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1153 int page_shift, int flags);
1154 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1155 struct ib_udata *udata,
1157 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1158 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1159 u64 length, u64 virt_addr, int access_flags,
1160 struct ib_pd *pd, struct ib_udata *udata);
1161 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1162 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1163 u32 max_num_sg, struct ib_udata *udata);
1164 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1166 u32 max_num_meta_sg);
1167 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1168 unsigned int *sg_offset);
1169 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1170 int data_sg_nents, unsigned int *data_sg_offset,
1171 struct scatterlist *meta_sg, int meta_sg_nents,
1172 unsigned int *meta_sg_offset);
1173 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
1174 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1175 const struct ib_mad_hdr *in, size_t in_mad_size,
1176 struct ib_mad_hdr *out, size_t *out_mad_size,
1177 u16 *out_mad_pkey_index);
1178 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
1179 struct ib_udata *udata);
1180 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1181 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
1182 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
1183 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
1184 struct ib_smp *out_mad);
1185 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1186 __be64 *sys_image_guid);
1187 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1189 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1191 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1192 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1193 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
1195 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
1197 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
1198 struct ib_port_attr *props);
1199 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1200 struct ib_port_attr *props);
1201 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
1202 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
1203 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
1204 unsigned long max_page_shift,
1205 int *count, int *shift,
1206 int *ncont, int *order);
1207 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1208 int page_shift, size_t offset, size_t num_pages,
1209 __be64 *pas, int access_flags);
1210 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1211 int page_shift, __be64 *pas, int access_flags);
1212 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1213 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1214 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1215 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1217 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry);
1218 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
1219 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1220 struct ib_mr_status *mr_status);
1221 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1222 struct ib_wq_init_attr *init_attr,
1223 struct ib_udata *udata);
1224 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1225 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1226 u32 wq_attr_mask, struct ib_udata *udata);
1227 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
1228 struct ib_rwq_ind_table_init_attr *init_attr,
1229 struct ib_udata *udata);
1230 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1231 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev);
1232 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
1233 struct ib_ucontext *context,
1234 struct ib_dm_alloc_attr *attr,
1235 struct uverbs_attr_bundle *attrs);
1236 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs);
1237 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1238 struct ib_dm_mr_attr *attr,
1239 struct uverbs_attr_bundle *attrs);
1241 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1242 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
1243 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1244 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1245 int __init mlx5_ib_odp_init(void);
1246 void mlx5_ib_odp_cleanup(void);
1247 void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp, unsigned long start,
1249 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1250 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1251 size_t nentries, struct mlx5_ib_mr *mr, int flags);
1253 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1254 enum ib_uverbs_advise_mr_advice advice,
1255 u32 flags, struct ib_sge *sg_list, u32 num_sge);
1256 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1257 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
1262 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
1263 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
1264 static inline int mlx5_ib_odp_init(void) { return 0; }
1265 static inline void mlx5_ib_odp_cleanup(void) {}
1266 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
1267 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1268 size_t nentries, struct mlx5_ib_mr *mr,
1272 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1273 enum ib_uverbs_advise_mr_advice advice, u32 flags,
1274 struct ib_sge *sg_list, u32 num_sge)
1278 static inline void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp,
1279 unsigned long start,
1280 unsigned long end){};
1281 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1283 /* Needed for rep profile */
1284 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1285 const struct mlx5_ib_profile *profile,
1287 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
1288 const struct mlx5_ib_profile *profile);
1290 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1291 u8 port, struct ifla_vf_info *info);
1292 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1293 u8 port, int state);
1294 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1295 u8 port, struct ifla_vf_stats *stats);
1296 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
1297 u64 guid, int type);
1299 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
1300 const struct ib_gid_attr *attr);
1302 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1303 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1305 /* GSI QP helper functions */
1306 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
1307 struct ib_qp_init_attr *init_attr);
1308 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp);
1309 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1311 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1313 struct ib_qp_init_attr *qp_init_attr);
1314 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1315 const struct ib_send_wr **bad_wr);
1316 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1317 const struct ib_recv_wr **bad_wr);
1318 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1320 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1322 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1324 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1325 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1327 u8 *native_port_num);
1328 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1331 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
1332 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user);
1333 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid);
1334 void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev);
1335 void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev);
1336 const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void);
1337 extern const struct uapi_definition mlx5_ib_devx_defs[];
1338 extern const struct uapi_definition mlx5_ib_flow_defs[];
1339 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add(
1340 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher,
1341 struct mlx5_flow_context *flow_context,
1342 struct mlx5_flow_act *flow_act, u32 counter_id,
1343 void *cmd_in, int inlen, int dest_id, int dest_type);
1344 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type);
1345 bool mlx5_ib_devx_is_flow_counter(void *obj, u32 *counter_id);
1346 int mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root);
1347 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction);
1350 mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1351 bool is_user) { return -EOPNOTSUPP; }
1352 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {}
1353 static inline void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev) {}
1354 static inline void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev) {}
1355 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id,
1361 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction)
1366 static inline void init_query_mad(struct ib_smp *mad)
1368 mad->base_version = 1;
1369 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1370 mad->class_version = 1;
1371 mad->method = IB_MGMT_METHOD_GET;
1374 static inline u8 convert_access(int acc)
1376 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1377 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1378 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1379 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1380 MLX5_PERM_LOCAL_READ;
1383 static inline int is_qp1(enum ib_qp_type qp_type)
1385 return qp_type == MLX5_IB_QPT_HW_GSI;
1388 #define MLX5_MAX_UMR_SHIFT 16
1389 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1391 static inline u32 check_cq_create_flags(u32 flags)
1394 * It returns non-zero value for unsupported CQ
1395 * create flags, otherwise it returns zero.
1397 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1398 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1401 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1405 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1406 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1408 *user_index = cmd_uidx;
1410 *user_index = MLX5_IB_DEFAULT_UIDX;
1416 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1417 struct mlx5_ib_create_qp *ucmd,
1421 u8 cqe_version = ucontext->cqe_version;
1423 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) &&
1424 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1427 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) !=
1431 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1434 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1435 struct mlx5_ib_create_srq *ucmd,
1439 u8 cqe_version = ucontext->cqe_version;
1441 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) &&
1442 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1445 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) !=
1449 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1452 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1454 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1455 MLX5_UARS_IN_PAGE : 1;
1458 static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1459 struct mlx5_bfreg_info *bfregi)
1461 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1464 unsigned long mlx5_ib_get_xlt_emergency_page(void);
1465 void mlx5_ib_put_xlt_emergency_page(void);
1467 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1468 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1471 int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter);
1472 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num);
1474 static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev,
1475 bool do_modify_atomic)
1477 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
1480 if (do_modify_atomic &&
1481 MLX5_CAP_GEN(dev->mdev, atomic) &&
1482 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
1487 #endif /* MLX5_IB_H */