2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/bitmap.h>
42 #if defined(CONFIG_X86)
45 #include <linux/sched.h>
46 #include <linux/sched/mm.h>
47 #include <linux/sched/task.h>
48 #include <linux/delay.h>
49 #include <rdma/ib_user_verbs.h>
50 #include <rdma/ib_addr.h>
51 #include <rdma/ib_cache.h>
52 #include <linux/mlx5/port.h>
53 #include <linux/mlx5/vport.h>
54 #include <linux/mlx5/fs.h>
55 #include <linux/mlx5/eswitch.h>
56 #include <linux/list.h>
57 #include <rdma/ib_smi.h>
58 #include <rdma/ib_umem.h>
60 #include <linux/etherdevice.h>
65 #include <linux/mlx5/fs_helpers.h>
66 #include <linux/mlx5/accel.h>
67 #include <rdma/uverbs_std_types.h>
68 #include <rdma/mlx5_user_ioctl_verbs.h>
69 #include <rdma/mlx5_user_ioctl_cmds.h>
70 #include <rdma/ib_umem_odp.h>
72 #define UVERBS_MODULE_NAME mlx5_ib
73 #include <rdma/uverbs_named_ioctl.h>
75 #define DRIVER_NAME "mlx5_ib"
76 #define DRIVER_VERSION "5.0-0"
78 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
79 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
80 MODULE_LICENSE("Dual BSD/GPL");
82 static char mlx5_version[] =
83 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
86 struct mlx5_ib_event_work {
87 struct work_struct work;
89 struct mlx5_ib_dev *dev;
90 struct mlx5_ib_multiport_info *mpi;
98 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
101 static struct workqueue_struct *mlx5_ib_event_wq;
102 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
103 static LIST_HEAD(mlx5_ib_dev_list);
105 * This mutex should be held when accessing either of the above lists
107 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
109 /* We can't use an array for xlt_emergency_page because dma_map_single
110 * doesn't work on kernel modules memory
112 static unsigned long xlt_emergency_page;
113 static struct mutex xlt_emergency_page_mutex;
115 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
117 struct mlx5_ib_dev *dev;
119 mutex_lock(&mlx5_ib_multiport_mutex);
121 mutex_unlock(&mlx5_ib_multiport_mutex);
125 static enum rdma_link_layer
126 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
128 switch (port_type_cap) {
129 case MLX5_CAP_PORT_TYPE_IB:
130 return IB_LINK_LAYER_INFINIBAND;
131 case MLX5_CAP_PORT_TYPE_ETH:
132 return IB_LINK_LAYER_ETHERNET;
134 return IB_LINK_LAYER_UNSPECIFIED;
138 static enum rdma_link_layer
139 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
141 struct mlx5_ib_dev *dev = to_mdev(device);
142 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
144 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
147 static int get_port_state(struct ib_device *ibdev,
149 enum ib_port_state *state)
151 struct ib_port_attr attr;
154 memset(&attr, 0, sizeof(attr));
155 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
161 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
162 struct net_device *ndev,
165 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
166 struct net_device *rep_ndev;
167 struct mlx5_ib_port *port;
170 for (i = 0; i < dev->num_ports; i++) {
171 port = &dev->port[i];
175 read_lock(&port->roce.netdev_lock);
176 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 if (rep_ndev == ndev) {
179 read_unlock(&port->roce.netdev_lock);
183 read_unlock(&port->roce.netdev_lock);
189 static int mlx5_netdev_event(struct notifier_block *this,
190 unsigned long event, void *ptr)
192 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
193 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
194 u8 port_num = roce->native_port_num;
195 struct mlx5_core_dev *mdev;
196 struct mlx5_ib_dev *ibdev;
199 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
204 case NETDEV_REGISTER:
205 /* Should already be registered during the load */
208 write_lock(&roce->netdev_lock);
209 if (ndev->dev.parent == mdev->device)
211 write_unlock(&roce->netdev_lock);
214 case NETDEV_UNREGISTER:
215 /* In case of reps, ib device goes away before the netdevs */
216 write_lock(&roce->netdev_lock);
217 if (roce->netdev == ndev)
219 write_unlock(&roce->netdev_lock);
225 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
226 struct net_device *upper = NULL;
229 upper = netdev_master_upper_dev_get(lag_ndev);
234 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
237 if ((upper == ndev || (!upper && ndev == roce->netdev))
238 && ibdev->ib_active) {
239 struct ib_event ibev = { };
240 enum ib_port_state port_state;
242 if (get_port_state(&ibdev->ib_dev, port_num,
246 if (roce->last_port_state == port_state)
249 roce->last_port_state = port_state;
250 ibev.device = &ibdev->ib_dev;
251 if (port_state == IB_PORT_DOWN)
252 ibev.event = IB_EVENT_PORT_ERR;
253 else if (port_state == IB_PORT_ACTIVE)
254 ibev.event = IB_EVENT_PORT_ACTIVE;
258 ibev.element.port_num = port_num;
259 ib_dispatch_event(&ibev);
268 mlx5_ib_put_native_port_mdev(ibdev, port_num);
272 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
275 struct mlx5_ib_dev *ibdev = to_mdev(device);
276 struct net_device *ndev;
277 struct mlx5_core_dev *mdev;
279 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
283 ndev = mlx5_lag_get_roce_netdev(mdev);
287 /* Ensure ndev does not disappear before we invoke dev_hold()
289 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
290 ndev = ibdev->port[port_num - 1].roce.netdev;
293 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
296 mlx5_ib_put_native_port_mdev(ibdev, port_num);
300 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
306 struct mlx5_core_dev *mdev = NULL;
307 struct mlx5_ib_multiport_info *mpi;
308 struct mlx5_ib_port *port;
310 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
311 ll != IB_LINK_LAYER_ETHERNET) {
313 *native_port_num = ib_port_num;
318 *native_port_num = 1;
320 port = &ibdev->port[ib_port_num - 1];
324 spin_lock(&port->mp.mpi_lock);
325 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
326 if (mpi && !mpi->unaffiliate) {
328 /* If it's the master no need to refcount, it'll exist
329 * as long as the ib_dev exists.
334 spin_unlock(&port->mp.mpi_lock);
339 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
341 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
343 struct mlx5_ib_multiport_info *mpi;
344 struct mlx5_ib_port *port;
346 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
349 port = &ibdev->port[port_num - 1];
351 spin_lock(&port->mp.mpi_lock);
352 mpi = ibdev->port[port_num - 1].mp.mpi;
357 if (mpi->unaffiliate)
358 complete(&mpi->unref_comp);
360 spin_unlock(&port->mp.mpi_lock);
363 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
366 switch (eth_proto_oper) {
367 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
368 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
369 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
370 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
371 *active_width = IB_WIDTH_1X;
372 *active_speed = IB_SPEED_SDR;
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
378 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
379 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
380 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
381 *active_width = IB_WIDTH_1X;
382 *active_speed = IB_SPEED_QDR;
384 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
385 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
386 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
387 *active_width = IB_WIDTH_1X;
388 *active_speed = IB_SPEED_EDR;
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
391 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
392 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
393 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
394 *active_width = IB_WIDTH_4X;
395 *active_speed = IB_SPEED_QDR;
397 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
398 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
399 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
400 *active_width = IB_WIDTH_1X;
401 *active_speed = IB_SPEED_HDR;
403 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
404 *active_width = IB_WIDTH_4X;
405 *active_speed = IB_SPEED_FDR;
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
408 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
409 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
410 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
411 *active_width = IB_WIDTH_4X;
412 *active_speed = IB_SPEED_EDR;
421 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
424 switch (eth_proto_oper) {
425 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
426 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
427 *active_width = IB_WIDTH_1X;
428 *active_speed = IB_SPEED_SDR;
430 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
431 *active_width = IB_WIDTH_1X;
432 *active_speed = IB_SPEED_DDR;
434 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
435 *active_width = IB_WIDTH_1X;
436 *active_speed = IB_SPEED_QDR;
438 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
439 *active_width = IB_WIDTH_4X;
440 *active_speed = IB_SPEED_QDR;
442 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
443 *active_width = IB_WIDTH_1X;
444 *active_speed = IB_SPEED_EDR;
446 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
447 *active_width = IB_WIDTH_2X;
448 *active_speed = IB_SPEED_EDR;
450 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
451 *active_width = IB_WIDTH_1X;
452 *active_speed = IB_SPEED_HDR;
454 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
455 *active_width = IB_WIDTH_4X;
456 *active_speed = IB_SPEED_EDR;
458 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
459 *active_width = IB_WIDTH_2X;
460 *active_speed = IB_SPEED_HDR;
462 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
463 *active_width = IB_WIDTH_4X;
464 *active_speed = IB_SPEED_HDR;
473 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
474 u8 *active_width, bool ext)
477 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
479 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
483 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
484 struct ib_port_attr *props)
486 struct mlx5_ib_dev *dev = to_mdev(device);
487 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
488 struct mlx5_core_dev *mdev;
489 struct net_device *ndev, *upper;
490 enum ib_mtu ndev_ib_mtu;
491 bool put_mdev = true;
498 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
500 /* This means the port isn't affiliated yet. Get the
501 * info for the master port instead.
509 /* Possible bad flows are checked before filling out props so in case
510 * of an error it will still be zeroed out.
511 * Use native port in case of reps
514 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
517 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
521 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
522 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
524 props->active_width = IB_WIDTH_4X;
525 props->active_speed = IB_SPEED_QDR;
527 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
528 &props->active_width, ext);
530 props->port_cap_flags |= IB_PORT_CM_SUP;
531 props->ip_gids = true;
533 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
534 roce_address_table_size);
535 props->max_mtu = IB_MTU_4096;
536 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
537 props->pkey_tbl_len = 1;
538 props->state = IB_PORT_DOWN;
539 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
541 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
542 props->qkey_viol_cntr = qkey_viol_cntr;
544 /* If this is a stub query for an unaffiliated port stop here */
548 ndev = mlx5_ib_get_netdev(device, port_num);
552 if (dev->lag_active) {
554 upper = netdev_master_upper_dev_get_rcu(ndev);
563 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
564 props->state = IB_PORT_ACTIVE;
565 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
568 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
572 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
575 mlx5_ib_put_native_port_mdev(dev, port_num);
579 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
580 unsigned int index, const union ib_gid *gid,
581 const struct ib_gid_attr *attr)
583 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
584 u16 vlan_id = 0xffff;
591 gid_type = attr->gid_type;
592 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
599 roce_version = MLX5_ROCE_VERSION_1;
601 case IB_GID_TYPE_ROCE_UDP_ENCAP:
602 roce_version = MLX5_ROCE_VERSION_2;
603 if (ipv6_addr_v4mapped((void *)gid))
604 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
606 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
610 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
613 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
614 roce_l3_type, gid->raw, mac,
615 vlan_id < VLAN_CFI_MASK, vlan_id,
619 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
620 __always_unused void **context)
622 return set_roce_addr(to_mdev(attr->device), attr->port_num,
623 attr->index, &attr->gid, attr);
626 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
627 __always_unused void **context)
629 return set_roce_addr(to_mdev(attr->device), attr->port_num,
630 attr->index, NULL, NULL);
633 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
634 const struct ib_gid_attr *attr)
636 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
639 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
642 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
644 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
645 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
650 MLX5_VPORT_ACCESS_METHOD_MAD,
651 MLX5_VPORT_ACCESS_METHOD_HCA,
652 MLX5_VPORT_ACCESS_METHOD_NIC,
655 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
657 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
658 return MLX5_VPORT_ACCESS_METHOD_MAD;
660 if (mlx5_ib_port_link_layer(ibdev, 1) ==
661 IB_LINK_LAYER_ETHERNET)
662 return MLX5_VPORT_ACCESS_METHOD_NIC;
664 return MLX5_VPORT_ACCESS_METHOD_HCA;
667 static void get_atomic_caps(struct mlx5_ib_dev *dev,
669 struct ib_device_attr *props)
672 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
673 u8 atomic_req_8B_endianness_mode =
674 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
676 /* Check if HW supports 8 bytes standard atomic operations and capable
677 * of host endianness respond
679 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
680 if (((atomic_operations & tmp) == tmp) &&
681 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
682 (atomic_req_8B_endianness_mode)) {
683 props->atomic_cap = IB_ATOMIC_HCA;
685 props->atomic_cap = IB_ATOMIC_NONE;
689 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
690 struct ib_device_attr *props)
692 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
694 get_atomic_caps(dev, atomic_size_qp, props);
697 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
698 __be64 *sys_image_guid)
700 struct mlx5_ib_dev *dev = to_mdev(ibdev);
701 struct mlx5_core_dev *mdev = dev->mdev;
705 switch (mlx5_get_vport_access_method(ibdev)) {
706 case MLX5_VPORT_ACCESS_METHOD_MAD:
707 return mlx5_query_mad_ifc_system_image_guid(ibdev,
710 case MLX5_VPORT_ACCESS_METHOD_HCA:
711 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
714 case MLX5_VPORT_ACCESS_METHOD_NIC:
715 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
723 *sys_image_guid = cpu_to_be64(tmp);
729 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
732 struct mlx5_ib_dev *dev = to_mdev(ibdev);
733 struct mlx5_core_dev *mdev = dev->mdev;
735 switch (mlx5_get_vport_access_method(ibdev)) {
736 case MLX5_VPORT_ACCESS_METHOD_MAD:
737 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
739 case MLX5_VPORT_ACCESS_METHOD_HCA:
740 case MLX5_VPORT_ACCESS_METHOD_NIC:
741 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
750 static int mlx5_query_vendor_id(struct ib_device *ibdev,
753 struct mlx5_ib_dev *dev = to_mdev(ibdev);
755 switch (mlx5_get_vport_access_method(ibdev)) {
756 case MLX5_VPORT_ACCESS_METHOD_MAD:
757 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
759 case MLX5_VPORT_ACCESS_METHOD_HCA:
760 case MLX5_VPORT_ACCESS_METHOD_NIC:
761 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
768 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
774 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
775 case MLX5_VPORT_ACCESS_METHOD_MAD:
776 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
778 case MLX5_VPORT_ACCESS_METHOD_HCA:
779 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
782 case MLX5_VPORT_ACCESS_METHOD_NIC:
783 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
791 *node_guid = cpu_to_be64(tmp);
796 struct mlx5_reg_node_desc {
797 u8 desc[IB_DEVICE_NODE_DESC_MAX];
800 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
802 struct mlx5_reg_node_desc in;
804 if (mlx5_use_mad_ifc(dev))
805 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
807 memset(&in, 0, sizeof(in));
809 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
810 sizeof(struct mlx5_reg_node_desc),
811 MLX5_REG_NODE_DESC, 0, 0);
814 static int mlx5_ib_query_device(struct ib_device *ibdev,
815 struct ib_device_attr *props,
816 struct ib_udata *uhw)
818 struct mlx5_ib_dev *dev = to_mdev(ibdev);
819 struct mlx5_core_dev *mdev = dev->mdev;
824 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
825 bool raw_support = !mlx5_core_mp_enabled(mdev);
826 struct mlx5_ib_query_device_resp resp = {};
830 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
831 if (uhw->outlen && uhw->outlen < resp_len)
834 resp.response_length = resp_len;
836 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
839 memset(props, 0, sizeof(*props));
840 err = mlx5_query_system_image_guid(ibdev,
841 &props->sys_image_guid);
845 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
849 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
853 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
854 (fw_rev_min(dev->mdev) << 16) |
855 fw_rev_sub(dev->mdev);
856 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
857 IB_DEVICE_PORT_ACTIVE_EVENT |
858 IB_DEVICE_SYS_IMAGE_GUID |
859 IB_DEVICE_RC_RNR_NAK_GEN;
861 if (MLX5_CAP_GEN(mdev, pkv))
862 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
863 if (MLX5_CAP_GEN(mdev, qkv))
864 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
865 if (MLX5_CAP_GEN(mdev, apm))
866 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
867 if (MLX5_CAP_GEN(mdev, xrc))
868 props->device_cap_flags |= IB_DEVICE_XRC;
869 if (MLX5_CAP_GEN(mdev, imaicl)) {
870 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
871 IB_DEVICE_MEM_WINDOW_TYPE_2B;
872 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
873 /* We support 'Gappy' memory registration too */
874 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
876 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
877 if (MLX5_CAP_GEN(mdev, sho)) {
878 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
879 /* At this stage no support for signature handover */
880 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
881 IB_PROT_T10DIF_TYPE_2 |
882 IB_PROT_T10DIF_TYPE_3;
883 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
884 IB_GUARD_T10DIF_CSUM;
886 if (MLX5_CAP_GEN(mdev, block_lb_mc))
887 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
889 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
890 if (MLX5_CAP_ETH(mdev, csum_cap)) {
891 /* Legacy bit to support old userspace libraries */
892 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
893 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
896 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
897 props->raw_packet_caps |=
898 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
900 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
901 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
903 resp.tso_caps.max_tso = 1 << max_tso;
904 resp.tso_caps.supported_qpts |=
905 1 << IB_QPT_RAW_PACKET;
906 resp.response_length += sizeof(resp.tso_caps);
910 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
911 resp.rss_caps.rx_hash_function =
912 MLX5_RX_HASH_FUNC_TOEPLITZ;
913 resp.rss_caps.rx_hash_fields_mask =
914 MLX5_RX_HASH_SRC_IPV4 |
915 MLX5_RX_HASH_DST_IPV4 |
916 MLX5_RX_HASH_SRC_IPV6 |
917 MLX5_RX_HASH_DST_IPV6 |
918 MLX5_RX_HASH_SRC_PORT_TCP |
919 MLX5_RX_HASH_DST_PORT_TCP |
920 MLX5_RX_HASH_SRC_PORT_UDP |
921 MLX5_RX_HASH_DST_PORT_UDP |
923 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
924 MLX5_ACCEL_IPSEC_CAP_DEVICE)
925 resp.rss_caps.rx_hash_fields_mask |=
926 MLX5_RX_HASH_IPSEC_SPI;
927 resp.response_length += sizeof(resp.rss_caps);
930 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
931 resp.response_length += sizeof(resp.tso_caps);
932 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
933 resp.response_length += sizeof(resp.rss_caps);
936 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
937 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
938 props->device_cap_flags |= IB_DEVICE_UD_TSO;
941 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
942 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
944 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
946 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
947 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
948 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
950 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
951 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
953 /* Legacy bit to support old userspace libraries */
954 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
955 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
958 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
960 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
963 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
964 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
966 if (MLX5_CAP_GEN(mdev, end_pad))
967 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
969 props->vendor_part_id = mdev->pdev->device;
970 props->hw_ver = mdev->pdev->revision;
972 props->max_mr_size = ~0ull;
973 props->page_size_cap = ~(min_page_size - 1);
974 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
975 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
976 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
977 sizeof(struct mlx5_wqe_data_seg);
978 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
979 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
980 sizeof(struct mlx5_wqe_raddr_seg)) /
981 sizeof(struct mlx5_wqe_data_seg);
982 props->max_send_sge = max_sq_sg;
983 props->max_recv_sge = max_rq_sg;
984 props->max_sge_rd = MLX5_MAX_SGE_RD;
985 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
986 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
987 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
988 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
989 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
990 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
991 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
992 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
993 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
994 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
995 props->max_srq_sge = max_rq_sg - 1;
996 props->max_fast_reg_page_list_len =
997 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
998 props->max_pi_fast_reg_page_list_len =
999 props->max_fast_reg_page_list_len / 2;
1001 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
1002 get_atomic_caps_qp(dev, props);
1003 props->masked_atomic_cap = IB_ATOMIC_NONE;
1004 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1005 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1006 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1007 props->max_mcast_grp;
1008 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
1009 props->max_ah = INT_MAX;
1010 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1011 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1013 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1014 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
1015 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1016 props->odp_caps = dev->odp_caps;
1019 if (MLX5_CAP_GEN(mdev, cd))
1020 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1022 if (!mlx5_core_is_pf(mdev))
1023 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1025 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1026 IB_LINK_LAYER_ETHERNET && raw_support) {
1027 props->rss_caps.max_rwq_indirection_tables =
1028 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1029 props->rss_caps.max_rwq_indirection_table_size =
1030 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1031 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1032 props->max_wq_type_rq =
1033 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1036 if (MLX5_CAP_GEN(mdev, tag_matching)) {
1037 props->tm_caps.max_num_tags =
1038 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1039 props->tm_caps.max_ops =
1040 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1041 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1044 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1045 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1046 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1047 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1050 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1051 props->cq_caps.max_cq_moderation_count =
1053 props->cq_caps.max_cq_moderation_period =
1057 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
1058 resp.response_length += sizeof(resp.cqe_comp_caps);
1060 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1061 resp.cqe_comp_caps.max_num =
1062 MLX5_CAP_GEN(dev->mdev,
1063 cqe_compression_max_num);
1065 resp.cqe_comp_caps.supported_format =
1066 MLX5_IB_CQE_RES_FORMAT_HASH |
1067 MLX5_IB_CQE_RES_FORMAT_CSUM;
1069 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1070 resp.cqe_comp_caps.supported_format |=
1071 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1075 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1077 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1078 MLX5_CAP_GEN(mdev, qos)) {
1079 resp.packet_pacing_caps.qp_rate_limit_max =
1080 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1081 resp.packet_pacing_caps.qp_rate_limit_min =
1082 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1083 resp.packet_pacing_caps.supported_qpts |=
1084 1 << IB_QPT_RAW_PACKET;
1085 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1086 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1087 resp.packet_pacing_caps.cap_flags |=
1088 MLX5_IB_PP_SUPPORT_BURST;
1090 resp.response_length += sizeof(resp.packet_pacing_caps);
1093 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1095 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1096 resp.mlx5_ib_support_multi_pkt_send_wqes =
1099 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1100 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1101 MLX5_IB_SUPPORT_EMPW;
1103 resp.response_length +=
1104 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1107 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1108 resp.response_length += sizeof(resp.flags);
1110 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1112 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1114 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1115 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1116 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1118 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1120 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1123 if (field_avail(typeof(resp), sw_parsing_caps,
1125 resp.response_length += sizeof(resp.sw_parsing_caps);
1126 if (MLX5_CAP_ETH(mdev, swp)) {
1127 resp.sw_parsing_caps.sw_parsing_offloads |=
1130 if (MLX5_CAP_ETH(mdev, swp_csum))
1131 resp.sw_parsing_caps.sw_parsing_offloads |=
1132 MLX5_IB_SW_PARSING_CSUM;
1134 if (MLX5_CAP_ETH(mdev, swp_lso))
1135 resp.sw_parsing_caps.sw_parsing_offloads |=
1136 MLX5_IB_SW_PARSING_LSO;
1138 if (resp.sw_parsing_caps.sw_parsing_offloads)
1139 resp.sw_parsing_caps.supported_qpts =
1140 BIT(IB_QPT_RAW_PACKET);
1144 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1146 resp.response_length += sizeof(resp.striding_rq_caps);
1147 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1148 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1149 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1150 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1151 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1152 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1153 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1154 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1155 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1156 resp.striding_rq_caps.supported_qpts =
1157 BIT(IB_QPT_RAW_PACKET);
1161 if (field_avail(typeof(resp), tunnel_offloads_caps,
1163 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1164 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1165 resp.tunnel_offloads_caps |=
1166 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1167 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1168 resp.tunnel_offloads_caps |=
1169 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1170 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1171 resp.tunnel_offloads_caps |=
1172 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1173 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1174 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1175 resp.tunnel_offloads_caps |=
1176 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1177 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1178 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1179 resp.tunnel_offloads_caps |=
1180 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1184 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1193 enum mlx5_ib_width {
1194 MLX5_IB_WIDTH_1X = 1 << 0,
1195 MLX5_IB_WIDTH_2X = 1 << 1,
1196 MLX5_IB_WIDTH_4X = 1 << 2,
1197 MLX5_IB_WIDTH_8X = 1 << 3,
1198 MLX5_IB_WIDTH_12X = 1 << 4
1201 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1204 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1206 if (active_width & MLX5_IB_WIDTH_1X)
1207 *ib_width = IB_WIDTH_1X;
1208 else if (active_width & MLX5_IB_WIDTH_2X)
1209 *ib_width = IB_WIDTH_2X;
1210 else if (active_width & MLX5_IB_WIDTH_4X)
1211 *ib_width = IB_WIDTH_4X;
1212 else if (active_width & MLX5_IB_WIDTH_8X)
1213 *ib_width = IB_WIDTH_8X;
1214 else if (active_width & MLX5_IB_WIDTH_12X)
1215 *ib_width = IB_WIDTH_12X;
1217 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1219 *ib_width = IB_WIDTH_4X;
1225 static int mlx5_mtu_to_ib_mtu(int mtu)
1230 case 1024: return 3;
1231 case 2048: return 4;
1232 case 4096: return 5;
1234 pr_warn("invalid mtu\n");
1239 enum ib_max_vl_num {
1241 __IB_MAX_VL_0_1 = 2,
1242 __IB_MAX_VL_0_3 = 3,
1243 __IB_MAX_VL_0_7 = 4,
1244 __IB_MAX_VL_0_14 = 5,
1247 enum mlx5_vl_hw_cap {
1256 MLX5_VL_HW_0_14 = 15
1259 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1262 switch (vl_hw_cap) {
1264 *max_vl_num = __IB_MAX_VL_0;
1266 case MLX5_VL_HW_0_1:
1267 *max_vl_num = __IB_MAX_VL_0_1;
1269 case MLX5_VL_HW_0_3:
1270 *max_vl_num = __IB_MAX_VL_0_3;
1272 case MLX5_VL_HW_0_7:
1273 *max_vl_num = __IB_MAX_VL_0_7;
1275 case MLX5_VL_HW_0_14:
1276 *max_vl_num = __IB_MAX_VL_0_14;
1286 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1287 struct ib_port_attr *props)
1289 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1290 struct mlx5_core_dev *mdev = dev->mdev;
1291 struct mlx5_hca_vport_context *rep;
1295 u8 ib_link_width_oper;
1298 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1304 /* props being zeroed by the caller, avoid zeroing it here */
1306 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1310 props->lid = rep->lid;
1311 props->lmc = rep->lmc;
1312 props->sm_lid = rep->sm_lid;
1313 props->sm_sl = rep->sm_sl;
1314 props->state = rep->vport_state;
1315 props->phys_state = rep->port_physical_state;
1316 props->port_cap_flags = rep->cap_mask1;
1317 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1318 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1319 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1320 props->bad_pkey_cntr = rep->pkey_violation_counter;
1321 props->qkey_viol_cntr = rep->qkey_violation_counter;
1322 props->subnet_timeout = rep->subnet_timeout;
1323 props->init_type_reply = rep->init_type_reply;
1325 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1326 props->port_cap_flags2 = rep->cap_mask2;
1328 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1332 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1334 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1338 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1340 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1342 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1344 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1346 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1350 err = translate_max_vl_num(ibdev, vl_hw_cap,
1351 &props->max_vl_num);
1357 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1358 struct ib_port_attr *props)
1363 switch (mlx5_get_vport_access_method(ibdev)) {
1364 case MLX5_VPORT_ACCESS_METHOD_MAD:
1365 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1368 case MLX5_VPORT_ACCESS_METHOD_HCA:
1369 ret = mlx5_query_hca_port(ibdev, port, props);
1372 case MLX5_VPORT_ACCESS_METHOD_NIC:
1373 ret = mlx5_query_port_roce(ibdev, port, props);
1380 if (!ret && props) {
1381 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1382 struct mlx5_core_dev *mdev;
1383 bool put_mdev = true;
1385 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1387 /* If the port isn't affiliated yet query the master.
1388 * The master and slave will have the same values.
1394 count = mlx5_core_reserved_gids_count(mdev);
1396 mlx5_ib_put_native_port_mdev(dev, port);
1397 props->gid_tbl_len -= count;
1402 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1403 struct ib_port_attr *props)
1407 /* Only link layer == ethernet is valid for representors
1408 * and we always use port 1
1410 ret = mlx5_query_port_roce(ibdev, port, props);
1414 /* We don't support GIDS */
1415 props->gid_tbl_len = 0;
1420 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1423 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1424 struct mlx5_core_dev *mdev = dev->mdev;
1426 switch (mlx5_get_vport_access_method(ibdev)) {
1427 case MLX5_VPORT_ACCESS_METHOD_MAD:
1428 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1430 case MLX5_VPORT_ACCESS_METHOD_HCA:
1431 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1439 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1440 u16 index, u16 *pkey)
1442 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1443 struct mlx5_core_dev *mdev;
1444 bool put_mdev = true;
1448 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1450 /* The port isn't affiliated yet, get the PKey from the master
1451 * port. For RoCE the PKey tables will be the same.
1458 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1461 mlx5_ib_put_native_port_mdev(dev, port);
1466 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1469 switch (mlx5_get_vport_access_method(ibdev)) {
1470 case MLX5_VPORT_ACCESS_METHOD_MAD:
1471 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1473 case MLX5_VPORT_ACCESS_METHOD_HCA:
1474 case MLX5_VPORT_ACCESS_METHOD_NIC:
1475 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1481 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1482 struct ib_device_modify *props)
1484 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1485 struct mlx5_reg_node_desc in;
1486 struct mlx5_reg_node_desc out;
1489 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1492 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1496 * If possible, pass node desc to FW, so it can generate
1497 * a 144 trap. If cmd fails, just ignore.
1499 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1500 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1501 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1505 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1510 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1513 struct mlx5_hca_vport_context ctx = {};
1514 struct mlx5_core_dev *mdev;
1518 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1522 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1526 if (~ctx.cap_mask1_perm & mask) {
1527 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1528 mask, ctx.cap_mask1_perm);
1533 ctx.cap_mask1 = value;
1534 ctx.cap_mask1_perm = mask;
1535 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1539 mlx5_ib_put_native_port_mdev(dev, port_num);
1544 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1545 struct ib_port_modify *props)
1547 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1548 struct ib_port_attr attr;
1553 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1554 IB_LINK_LAYER_INFINIBAND);
1556 /* CM layer calls ib_modify_port() regardless of the link layer. For
1557 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1562 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1563 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1564 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1565 return set_port_caps_atomic(dev, port, change_mask, value);
1568 mutex_lock(&dev->cap_mask_mutex);
1570 err = ib_query_port(ibdev, port, &attr);
1574 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1575 ~props->clr_port_cap_mask;
1577 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1580 mutex_unlock(&dev->cap_mask_mutex);
1584 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1586 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1587 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1590 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1592 /* Large page with non 4k uar support might limit the dynamic size */
1593 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1594 return MLX5_MIN_DYN_BFREGS;
1596 return MLX5_MAX_DYN_BFREGS;
1599 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1600 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1601 struct mlx5_bfreg_info *bfregi)
1603 int uars_per_sys_page;
1604 int bfregs_per_sys_page;
1605 int ref_bfregs = req->total_num_bfregs;
1607 if (req->total_num_bfregs == 0)
1610 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1611 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1613 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1616 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1617 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1618 /* This holds the required static allocation asked by the user */
1619 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1620 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1623 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1624 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1625 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1626 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1628 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1629 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1630 lib_uar_4k ? "yes" : "no", ref_bfregs,
1631 req->total_num_bfregs, bfregi->total_num_bfregs,
1632 bfregi->num_sys_pages);
1637 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1639 struct mlx5_bfreg_info *bfregi;
1643 bfregi = &context->bfregi;
1644 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1645 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1649 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1652 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1653 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1658 for (--i; i >= 0; i--)
1659 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1660 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1665 static void deallocate_uars(struct mlx5_ib_dev *dev,
1666 struct mlx5_ib_ucontext *context)
1668 struct mlx5_bfreg_info *bfregi;
1671 bfregi = &context->bfregi;
1672 for (i = 0; i < bfregi->num_sys_pages; i++)
1673 if (i < bfregi->num_static_sys_pages ||
1674 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1675 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1678 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1682 mutex_lock(&dev->lb.mutex);
1688 if (dev->lb.user_td == 2 ||
1690 if (!dev->lb.enabled) {
1691 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1692 dev->lb.enabled = true;
1696 mutex_unlock(&dev->lb.mutex);
1701 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1703 mutex_lock(&dev->lb.mutex);
1709 if (dev->lb.user_td == 1 &&
1711 if (dev->lb.enabled) {
1712 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1713 dev->lb.enabled = false;
1717 mutex_unlock(&dev->lb.mutex);
1720 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1725 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1728 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1732 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1733 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1734 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1737 return mlx5_ib_enable_lb(dev, true, false);
1740 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1743 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1746 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1748 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1749 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1750 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1753 mlx5_ib_disable_lb(dev, true, false);
1756 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1757 struct ib_udata *udata)
1759 struct ib_device *ibdev = uctx->device;
1760 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1761 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1762 struct mlx5_ib_alloc_ucontext_resp resp = {};
1763 struct mlx5_core_dev *mdev = dev->mdev;
1764 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1765 struct mlx5_bfreg_info *bfregi;
1768 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1773 if (!dev->ib_active)
1776 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1778 else if (udata->inlen >= min_req_v2)
1783 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1787 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1790 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1793 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1794 MLX5_NON_FP_BFREGS_PER_UAR);
1795 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1798 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1799 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1800 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1801 resp.cache_line_size = cache_line_size();
1802 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1803 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1804 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1805 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1806 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1807 resp.cqe_version = min_t(__u8,
1808 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1809 req.max_cqe_version);
1810 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1811 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1812 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1813 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1814 resp.response_length = min(offsetof(typeof(resp), response_length) +
1815 sizeof(resp.response_length), udata->outlen);
1817 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1818 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1819 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1820 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1821 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1822 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1823 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1824 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1825 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1826 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1829 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1830 bfregi = &context->bfregi;
1832 /* updates req->total_num_bfregs */
1833 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1837 mutex_init(&bfregi->lock);
1838 bfregi->lib_uar_4k = lib_uar_4k;
1839 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1841 if (!bfregi->count) {
1846 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1847 sizeof(*bfregi->sys_pages),
1849 if (!bfregi->sys_pages) {
1854 err = allocate_uars(dev, context);
1858 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1859 err = mlx5_ib_devx_create(dev, true);
1862 context->devx_uid = err;
1865 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1870 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1871 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1876 INIT_LIST_HEAD(&context->db_page_list);
1877 mutex_init(&context->db_page_mutex);
1879 resp.tot_bfregs = req.total_num_bfregs;
1880 resp.num_ports = dev->num_ports;
1882 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1883 resp.response_length += sizeof(resp.cqe_version);
1885 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1886 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1887 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1888 resp.response_length += sizeof(resp.cmds_supp_uhw);
1891 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1892 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1893 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1894 resp.eth_min_inline++;
1896 resp.response_length += sizeof(resp.eth_min_inline);
1899 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1900 if (mdev->clock_info)
1901 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1902 resp.response_length += sizeof(resp.clock_info_versions);
1906 * We don't want to expose information from the PCI bar that is located
1907 * after 4096 bytes, so if the arch only supports larger pages, let's
1908 * pretend we don't support reading the HCA's core clock. This is also
1909 * forced by mmap function.
1911 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1912 if (PAGE_SIZE <= 4096) {
1914 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1915 resp.hca_core_clock_offset =
1916 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1918 resp.response_length += sizeof(resp.hca_core_clock_offset);
1921 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1922 resp.response_length += sizeof(resp.log_uar_size);
1924 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1925 resp.response_length += sizeof(resp.num_uars_per_page);
1927 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1928 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1929 resp.response_length += sizeof(resp.num_dyn_bfregs);
1932 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1933 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1934 resp.dump_fill_mkey = dump_fill_mkey;
1936 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1938 resp.response_length += sizeof(resp.dump_fill_mkey);
1941 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1946 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1947 context->cqe_version = resp.cqe_version;
1948 context->lib_caps = req.lib_caps;
1949 print_lib_caps(dev, context->lib_caps);
1951 if (dev->lag_active) {
1952 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
1954 atomic_set(&context->tx_port_affinity,
1956 1, &dev->port[port].roce.tx_port_affinity));
1962 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1964 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1965 mlx5_ib_devx_destroy(dev, context->devx_uid);
1968 deallocate_uars(dev, context);
1971 kfree(bfregi->sys_pages);
1974 kfree(bfregi->count);
1980 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1982 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1983 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1984 struct mlx5_bfreg_info *bfregi;
1986 bfregi = &context->bfregi;
1987 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1989 if (context->devx_uid)
1990 mlx5_ib_devx_destroy(dev, context->devx_uid);
1992 deallocate_uars(dev, context);
1993 kfree(bfregi->sys_pages);
1994 kfree(bfregi->count);
1997 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2000 int fw_uars_per_page;
2002 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2004 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2007 static int get_command(unsigned long offset)
2009 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2012 static int get_arg(unsigned long offset)
2014 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2017 static int get_index(unsigned long offset)
2019 return get_arg(offset);
2022 /* Index resides in an extra byte to enable larger values than 255 */
2023 static int get_extended_index(unsigned long offset)
2025 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2029 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2033 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2036 case MLX5_IB_MMAP_WC_PAGE:
2038 case MLX5_IB_MMAP_REGULAR_PAGE:
2039 return "best effort WC";
2040 case MLX5_IB_MMAP_NC_PAGE:
2042 case MLX5_IB_MMAP_DEVICE_MEM:
2043 return "Device Memory";
2049 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2050 struct vm_area_struct *vma,
2051 struct mlx5_ib_ucontext *context)
2053 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2054 !(vma->vm_flags & VM_SHARED))
2057 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2060 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2062 vma->vm_flags &= ~VM_MAYWRITE;
2064 if (!dev->mdev->clock_info)
2067 return vm_insert_page(vma, vma->vm_start,
2068 virt_to_page(dev->mdev->clock_info));
2071 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2072 struct vm_area_struct *vma,
2073 struct mlx5_ib_ucontext *context)
2075 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2080 u32 bfreg_dyn_idx = 0;
2082 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2083 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2084 bfregi->num_static_sys_pages;
2086 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2090 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2092 idx = get_index(vma->vm_pgoff);
2094 if (idx >= max_valid_idx) {
2095 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2096 idx, max_valid_idx);
2101 case MLX5_IB_MMAP_WC_PAGE:
2102 case MLX5_IB_MMAP_ALLOC_WC:
2103 /* Some architectures don't support WC memory */
2104 #if defined(CONFIG_X86)
2107 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2111 case MLX5_IB_MMAP_REGULAR_PAGE:
2112 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2113 prot = pgprot_writecombine(vma->vm_page_prot);
2115 case MLX5_IB_MMAP_NC_PAGE:
2116 prot = pgprot_noncached(vma->vm_page_prot);
2125 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2126 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2127 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2128 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2129 bfreg_dyn_idx, bfregi->total_num_bfregs);
2133 mutex_lock(&bfregi->lock);
2134 /* Fail if uar already allocated, first bfreg index of each
2135 * page holds its count.
2137 if (bfregi->count[bfreg_dyn_idx]) {
2138 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2139 mutex_unlock(&bfregi->lock);
2143 bfregi->count[bfreg_dyn_idx]++;
2144 mutex_unlock(&bfregi->lock);
2146 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2148 mlx5_ib_warn(dev, "UAR alloc failed\n");
2152 uar_index = bfregi->sys_pages[idx];
2155 pfn = uar_index2pfn(dev, uar_index);
2156 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2158 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2162 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2163 err, mmap_cmd2str(cmd));
2168 bfregi->sys_pages[idx] = uar_index;
2175 mlx5_cmd_free_uar(dev->mdev, idx);
2178 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2183 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2185 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2186 struct mlx5_ib_dev *dev = to_mdev(context->device);
2187 u16 page_idx = get_extended_index(vma->vm_pgoff);
2188 size_t map_size = vma->vm_end - vma->vm_start;
2189 u32 npages = map_size >> PAGE_SHIFT;
2192 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2196 pfn = ((dev->mdev->bar_addr +
2197 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2200 return rdma_user_mmap_io(context, vma, pfn, map_size,
2201 pgprot_writecombine(vma->vm_page_prot));
2204 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2206 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2207 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2208 unsigned long command;
2211 command = get_command(vma->vm_pgoff);
2213 case MLX5_IB_MMAP_WC_PAGE:
2214 case MLX5_IB_MMAP_NC_PAGE:
2215 case MLX5_IB_MMAP_REGULAR_PAGE:
2216 case MLX5_IB_MMAP_ALLOC_WC:
2217 return uar_mmap(dev, command, vma, context);
2219 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2222 case MLX5_IB_MMAP_CORE_CLOCK:
2223 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2226 if (vma->vm_flags & VM_WRITE)
2228 vma->vm_flags &= ~VM_MAYWRITE;
2230 /* Don't expose to user-space information it shouldn't have */
2231 if (PAGE_SIZE > 4096)
2234 pfn = (dev->mdev->iseg_base +
2235 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2237 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2239 pgprot_noncached(vma->vm_page_prot));
2240 case MLX5_IB_MMAP_CLOCK_INFO:
2241 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2243 case MLX5_IB_MMAP_DEVICE_MEM:
2244 return dm_mmap(ibcontext, vma);
2253 static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2257 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2258 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2261 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2262 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2263 if (!capable(CAP_SYS_RAWIO) ||
2264 !capable(CAP_NET_RAW))
2267 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2268 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2276 static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2277 struct mlx5_ib_dm *dm,
2278 struct ib_dm_alloc_attr *attr,
2279 struct uverbs_attr_bundle *attrs)
2281 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2286 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2288 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2289 dm->size, attr->alignment);
2293 page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2294 MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
2297 err = uverbs_copy_to(attrs,
2298 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2299 &page_idx, sizeof(page_idx));
2303 start_offset = dm->dev_addr & ~PAGE_MASK;
2304 err = uverbs_copy_to(attrs,
2305 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2306 &start_offset, sizeof(start_offset));
2310 bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2311 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2316 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2321 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2322 struct mlx5_ib_dm *dm,
2323 struct ib_dm_alloc_attr *attr,
2324 struct uverbs_attr_bundle *attrs,
2327 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
2331 /* Allocation size must a multiple of the basic block size
2334 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
2335 act_size = roundup_pow_of_two(act_size);
2337 dm->size = act_size;
2338 err = mlx5_dm_sw_icm_alloc(dev, type, act_size,
2339 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2340 &dm->icm_dm.obj_id);
2344 err = uverbs_copy_to(attrs,
2345 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2346 &dm->dev_addr, sizeof(dm->dev_addr));
2348 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2349 to_mucontext(ctx)->devx_uid, dm->dev_addr,
2355 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2356 struct ib_ucontext *context,
2357 struct ib_dm_alloc_attr *attr,
2358 struct uverbs_attr_bundle *attrs)
2360 struct mlx5_ib_dm *dm;
2361 enum mlx5_ib_uapi_dm_type type;
2364 err = uverbs_get_const_default(&type, attrs,
2365 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2366 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2368 return ERR_PTR(err);
2370 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2371 type, attr->length, attr->alignment);
2373 err = check_dm_type_support(to_mdev(ibdev), type);
2375 return ERR_PTR(err);
2377 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2379 return ERR_PTR(-ENOMEM);
2384 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2385 err = handle_alloc_dm_memic(context, dm,
2389 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2390 err = handle_alloc_dm_sw_icm(context, dm,
2392 MLX5_SW_ICM_TYPE_STEERING);
2394 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2395 err = handle_alloc_dm_sw_icm(context, dm,
2397 MLX5_SW_ICM_TYPE_HEADER_MODIFY);
2410 return ERR_PTR(err);
2413 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
2415 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2416 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2417 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
2418 struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
2419 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2424 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2425 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2429 page_idx = (dm->dev_addr - pci_resource_start(dev->pdev, 0) -
2430 MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr)) >>
2432 bitmap_clear(ctx->dm_pages, page_idx,
2433 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2435 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2436 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2437 dm->size, ctx->devx_uid, dm->dev_addr,
2442 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2443 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2444 dm->size, ctx->devx_uid, dm->dev_addr,
2458 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2460 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2461 struct ib_device *ibdev = ibpd->device;
2462 struct mlx5_ib_alloc_pd_resp resp;
2464 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2465 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2467 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2468 udata, struct mlx5_ib_ucontext, ibucontext);
2470 uid = context ? context->devx_uid : 0;
2471 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2472 MLX5_SET(alloc_pd_in, in, uid, uid);
2473 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2478 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2482 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2483 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2491 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2493 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2494 struct mlx5_ib_pd *mpd = to_mpd(pd);
2496 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2500 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2501 MATCH_CRITERIA_ENABLE_MISC_BIT,
2502 MATCH_CRITERIA_ENABLE_INNER_BIT,
2503 MATCH_CRITERIA_ENABLE_MISC2_BIT
2506 #define HEADER_IS_ZERO(match_criteria, headers) \
2507 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2508 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2510 static u8 get_match_criteria_enable(u32 *match_criteria)
2512 u8 match_criteria_enable;
2514 match_criteria_enable =
2515 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2516 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2517 match_criteria_enable |=
2518 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2519 MATCH_CRITERIA_ENABLE_MISC_BIT;
2520 match_criteria_enable |=
2521 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2522 MATCH_CRITERIA_ENABLE_INNER_BIT;
2523 match_criteria_enable |=
2524 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2525 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2527 return match_criteria_enable;
2530 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2539 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2541 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2544 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2545 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2548 /* Don't override existing ip protocol */
2549 if (mask != entry_mask || val != entry_val)
2555 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2559 MLX5_SET(fte_match_set_misc,
2560 misc_c, inner_ipv6_flow_label, mask);
2561 MLX5_SET(fte_match_set_misc,
2562 misc_v, inner_ipv6_flow_label, val);
2564 MLX5_SET(fte_match_set_misc,
2565 misc_c, outer_ipv6_flow_label, mask);
2566 MLX5_SET(fte_match_set_misc,
2567 misc_v, outer_ipv6_flow_label, val);
2571 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2573 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2574 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2575 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2576 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2579 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2581 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2582 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2585 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2586 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2589 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2590 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2593 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2594 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2600 #define LAST_ETH_FIELD vlan_tag
2601 #define LAST_IB_FIELD sl
2602 #define LAST_IPV4_FIELD tos
2603 #define LAST_IPV6_FIELD traffic_class
2604 #define LAST_TCP_UDP_FIELD src_port
2605 #define LAST_TUNNEL_FIELD tunnel_id
2606 #define LAST_FLOW_TAG_FIELD tag_id
2607 #define LAST_DROP_FIELD size
2608 #define LAST_COUNTERS_FIELD counters
2610 /* Field is the last supported field */
2611 #define FIELDS_NOT_SUPPORTED(filter, field)\
2612 memchr_inv((void *)&filter.field +\
2613 sizeof(filter.field), 0,\
2615 offsetof(typeof(filter), field) -\
2616 sizeof(filter.field))
2618 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2620 struct mlx5_flow_act *action)
2623 switch (maction->ib_action.type) {
2624 case IB_FLOW_ACTION_ESP:
2625 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2626 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2628 /* Currently only AES_GCM keymat is supported by the driver */
2629 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2630 action->action |= is_egress ?
2631 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2632 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2634 case IB_FLOW_ACTION_UNSPECIFIED:
2635 if (maction->flow_action_raw.sub_type ==
2636 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2637 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2639 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2640 action->modify_hdr =
2641 maction->flow_action_raw.modify_hdr;
2644 if (maction->flow_action_raw.sub_type ==
2645 MLX5_IB_FLOW_ACTION_DECAP) {
2646 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2648 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2651 if (maction->flow_action_raw.sub_type ==
2652 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
2653 if (action->action &
2654 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2657 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2658 action->pkt_reformat =
2659 maction->flow_action_raw.pkt_reformat;
2668 static int parse_flow_attr(struct mlx5_core_dev *mdev,
2669 struct mlx5_flow_spec *spec,
2670 const union ib_flow_spec *ib_spec,
2671 const struct ib_flow_attr *flow_attr,
2672 struct mlx5_flow_act *action, u32 prev_type)
2674 struct mlx5_flow_context *flow_context = &spec->flow_context;
2675 u32 *match_c = spec->match_criteria;
2676 u32 *match_v = spec->match_value;
2677 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2679 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2681 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2683 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2690 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2691 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2693 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2695 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2696 ft_field_support.inner_ip_version);
2698 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2700 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2702 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2703 ft_field_support.outer_ip_version);
2706 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2707 case IB_FLOW_SPEC_ETH:
2708 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2711 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2713 ib_spec->eth.mask.dst_mac);
2714 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2716 ib_spec->eth.val.dst_mac);
2718 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2720 ib_spec->eth.mask.src_mac);
2721 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2723 ib_spec->eth.val.src_mac);
2725 if (ib_spec->eth.mask.vlan_tag) {
2726 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2728 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2731 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2732 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2733 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2734 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2736 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2738 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2739 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2741 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2743 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2745 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2746 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2748 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2750 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2751 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2752 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2753 ethertype, ntohs(ib_spec->eth.val.ether_type));
2755 case IB_FLOW_SPEC_IPV4:
2756 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2760 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2762 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2763 ip_version, MLX5_FS_IPV4_VERSION);
2765 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2767 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2768 ethertype, ETH_P_IP);
2771 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2772 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2773 &ib_spec->ipv4.mask.src_ip,
2774 sizeof(ib_spec->ipv4.mask.src_ip));
2775 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2776 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2777 &ib_spec->ipv4.val.src_ip,
2778 sizeof(ib_spec->ipv4.val.src_ip));
2779 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2780 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2781 &ib_spec->ipv4.mask.dst_ip,
2782 sizeof(ib_spec->ipv4.mask.dst_ip));
2783 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2784 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2785 &ib_spec->ipv4.val.dst_ip,
2786 sizeof(ib_spec->ipv4.val.dst_ip));
2788 set_tos(headers_c, headers_v,
2789 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2791 if (set_proto(headers_c, headers_v,
2792 ib_spec->ipv4.mask.proto,
2793 ib_spec->ipv4.val.proto))
2796 case IB_FLOW_SPEC_IPV6:
2797 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2801 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2803 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2804 ip_version, MLX5_FS_IPV6_VERSION);
2806 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2808 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2809 ethertype, ETH_P_IPV6);
2812 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2813 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2814 &ib_spec->ipv6.mask.src_ip,
2815 sizeof(ib_spec->ipv6.mask.src_ip));
2816 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2817 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2818 &ib_spec->ipv6.val.src_ip,
2819 sizeof(ib_spec->ipv6.val.src_ip));
2820 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2821 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2822 &ib_spec->ipv6.mask.dst_ip,
2823 sizeof(ib_spec->ipv6.mask.dst_ip));
2824 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2825 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2826 &ib_spec->ipv6.val.dst_ip,
2827 sizeof(ib_spec->ipv6.val.dst_ip));
2829 set_tos(headers_c, headers_v,
2830 ib_spec->ipv6.mask.traffic_class,
2831 ib_spec->ipv6.val.traffic_class);
2833 if (set_proto(headers_c, headers_v,
2834 ib_spec->ipv6.mask.next_hdr,
2835 ib_spec->ipv6.val.next_hdr))
2838 set_flow_label(misc_params_c, misc_params_v,
2839 ntohl(ib_spec->ipv6.mask.flow_label),
2840 ntohl(ib_spec->ipv6.val.flow_label),
2841 ib_spec->type & IB_FLOW_SPEC_INNER);
2843 case IB_FLOW_SPEC_ESP:
2844 if (ib_spec->esp.mask.seq)
2847 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2848 ntohl(ib_spec->esp.mask.spi));
2849 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2850 ntohl(ib_spec->esp.val.spi));
2852 case IB_FLOW_SPEC_TCP:
2853 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2854 LAST_TCP_UDP_FIELD))
2857 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2860 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2861 ntohs(ib_spec->tcp_udp.mask.src_port));
2862 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2863 ntohs(ib_spec->tcp_udp.val.src_port));
2865 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2866 ntohs(ib_spec->tcp_udp.mask.dst_port));
2867 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2868 ntohs(ib_spec->tcp_udp.val.dst_port));
2870 case IB_FLOW_SPEC_UDP:
2871 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2872 LAST_TCP_UDP_FIELD))
2875 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2878 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2879 ntohs(ib_spec->tcp_udp.mask.src_port));
2880 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2881 ntohs(ib_spec->tcp_udp.val.src_port));
2883 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2884 ntohs(ib_spec->tcp_udp.mask.dst_port));
2885 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2886 ntohs(ib_spec->tcp_udp.val.dst_port));
2888 case IB_FLOW_SPEC_GRE:
2889 if (ib_spec->gre.mask.c_ks_res0_ver)
2892 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2895 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2897 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2900 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2901 ntohs(ib_spec->gre.mask.protocol));
2902 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2903 ntohs(ib_spec->gre.val.protocol));
2905 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2907 &ib_spec->gre.mask.key,
2908 sizeof(ib_spec->gre.mask.key));
2909 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2911 &ib_spec->gre.val.key,
2912 sizeof(ib_spec->gre.val.key));
2914 case IB_FLOW_SPEC_MPLS:
2915 switch (prev_type) {
2916 case IB_FLOW_SPEC_UDP:
2917 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2918 ft_field_support.outer_first_mpls_over_udp),
2919 &ib_spec->mpls.mask.tag))
2922 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2923 outer_first_mpls_over_udp),
2924 &ib_spec->mpls.val.tag,
2925 sizeof(ib_spec->mpls.val.tag));
2926 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2927 outer_first_mpls_over_udp),
2928 &ib_spec->mpls.mask.tag,
2929 sizeof(ib_spec->mpls.mask.tag));
2931 case IB_FLOW_SPEC_GRE:
2932 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2933 ft_field_support.outer_first_mpls_over_gre),
2934 &ib_spec->mpls.mask.tag))
2937 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2938 outer_first_mpls_over_gre),
2939 &ib_spec->mpls.val.tag,
2940 sizeof(ib_spec->mpls.val.tag));
2941 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2942 outer_first_mpls_over_gre),
2943 &ib_spec->mpls.mask.tag,
2944 sizeof(ib_spec->mpls.mask.tag));
2947 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2948 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2949 ft_field_support.inner_first_mpls),
2950 &ib_spec->mpls.mask.tag))
2953 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2955 &ib_spec->mpls.val.tag,
2956 sizeof(ib_spec->mpls.val.tag));
2957 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2959 &ib_spec->mpls.mask.tag,
2960 sizeof(ib_spec->mpls.mask.tag));
2962 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2963 ft_field_support.outer_first_mpls),
2964 &ib_spec->mpls.mask.tag))
2967 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2969 &ib_spec->mpls.val.tag,
2970 sizeof(ib_spec->mpls.val.tag));
2971 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2973 &ib_spec->mpls.mask.tag,
2974 sizeof(ib_spec->mpls.mask.tag));
2978 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2979 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2983 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2984 ntohl(ib_spec->tunnel.mask.tunnel_id));
2985 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2986 ntohl(ib_spec->tunnel.val.tunnel_id));
2988 case IB_FLOW_SPEC_ACTION_TAG:
2989 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2990 LAST_FLOW_TAG_FIELD))
2992 if (ib_spec->flow_tag.tag_id >= BIT(24))
2995 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
2996 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
2998 case IB_FLOW_SPEC_ACTION_DROP:
2999 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3002 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3004 case IB_FLOW_SPEC_ACTION_HANDLE:
3005 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3006 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
3010 case IB_FLOW_SPEC_ACTION_COUNT:
3011 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3012 LAST_COUNTERS_FIELD))
3015 /* for now support only one counters spec per flow */
3016 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3019 action->counters = ib_spec->flow_count.counters;
3020 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3029 /* If a flow could catch both multicast and unicast packets,
3030 * it won't fall into the multicast flow steering table and this rule
3031 * could steal other multicast packets.
3033 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
3035 union ib_flow_spec *flow_spec;
3037 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
3038 ib_attr->num_of_specs < 1)
3041 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3042 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3043 struct ib_flow_spec_ipv4 *ipv4_spec;
3045 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3046 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3052 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3053 struct ib_flow_spec_eth *eth_spec;
3055 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3056 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3057 is_multicast_ether_addr(eth_spec->val.dst_mac);
3069 static enum valid_spec
3070 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3071 const struct mlx5_flow_spec *spec,
3072 const struct mlx5_flow_act *flow_act,
3075 const u32 *match_c = spec->match_criteria;
3077 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3078 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3079 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3080 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3083 * Currently only crypto is supported in egress, when regular egress
3084 * rules would be supported, always return VALID_SPEC_NA.
3087 return VALID_SPEC_NA;
3089 return is_crypto && is_ipsec &&
3090 (!egress || (!is_drop &&
3091 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
3092 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3095 static bool is_valid_spec(struct mlx5_core_dev *mdev,
3096 const struct mlx5_flow_spec *spec,
3097 const struct mlx5_flow_act *flow_act,
3100 /* We curretly only support ipsec egress flow */
3101 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3104 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3105 const struct ib_flow_attr *flow_attr,
3108 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
3109 int match_ipv = check_inner ?
3110 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3111 ft_field_support.inner_ip_version) :
3112 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3113 ft_field_support.outer_ip_version);
3114 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3115 bool ipv4_spec_valid, ipv6_spec_valid;
3116 unsigned int ip_spec_type = 0;
3117 bool has_ethertype = false;
3118 unsigned int spec_index;
3119 bool mask_valid = true;
3123 /* Validate that ethertype is correct */
3124 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3125 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
3126 ib_spec->eth.mask.ether_type) {
3127 mask_valid = (ib_spec->eth.mask.ether_type ==
3129 has_ethertype = true;
3130 eth_type = ntohs(ib_spec->eth.val.ether_type);
3131 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3132 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3133 ip_spec_type = ib_spec->type;
3135 ib_spec = (void *)ib_spec + ib_spec->size;
3138 type_valid = (!has_ethertype) || (!ip_spec_type);
3139 if (!type_valid && mask_valid) {
3140 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3141 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3142 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3143 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
3145 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3146 (((eth_type == ETH_P_MPLS_UC) ||
3147 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
3153 static bool is_valid_attr(struct mlx5_core_dev *mdev,
3154 const struct ib_flow_attr *flow_attr)
3156 return is_valid_ethertype(mdev, flow_attr, false) &&
3157 is_valid_ethertype(mdev, flow_attr, true);
3160 static void put_flow_table(struct mlx5_ib_dev *dev,
3161 struct mlx5_ib_flow_prio *prio, bool ft_added)
3163 prio->refcount -= !!ft_added;
3164 if (!prio->refcount) {
3165 mlx5_destroy_flow_table(prio->flow_table);
3166 prio->flow_table = NULL;
3170 static void counters_clear_description(struct ib_counters *counters)
3172 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3174 mutex_lock(&mcounters->mcntrs_mutex);
3175 kfree(mcounters->counters_data);
3176 mcounters->counters_data = NULL;
3177 mcounters->cntrs_max_index = 0;
3178 mutex_unlock(&mcounters->mcntrs_mutex);
3181 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3183 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3184 struct mlx5_ib_flow_handler,
3186 struct mlx5_ib_flow_handler *iter, *tmp;
3187 struct mlx5_ib_dev *dev = handler->dev;
3189 mutex_lock(&dev->flow_db->lock);
3191 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3192 mlx5_del_flow_rules(iter->rule);
3193 put_flow_table(dev, iter->prio, true);
3194 list_del(&iter->list);
3198 mlx5_del_flow_rules(handler->rule);
3199 put_flow_table(dev, handler->prio, true);
3200 if (handler->ibcounters &&
3201 atomic_read(&handler->ibcounters->usecnt) == 1)
3202 counters_clear_description(handler->ibcounters);
3204 mutex_unlock(&dev->flow_db->lock);
3205 if (handler->flow_matcher)
3206 atomic_dec(&handler->flow_matcher->usecnt);
3212 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3220 enum flow_table_type {
3225 #define MLX5_FS_MAX_TYPES 6
3226 #define MLX5_FS_MAX_ENTRIES BIT(16)
3228 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3229 struct mlx5_ib_flow_prio *prio,
3231 int num_entries, int num_groups,
3234 struct mlx5_flow_table *ft;
3236 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3241 return ERR_CAST(ft);
3243 prio->flow_table = ft;
3248 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3249 struct ib_flow_attr *flow_attr,
3250 enum flow_table_type ft_type)
3252 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3253 struct mlx5_flow_namespace *ns = NULL;
3254 struct mlx5_ib_flow_prio *prio;
3255 struct mlx5_flow_table *ft;
3263 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3265 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3266 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3267 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3268 enum mlx5_flow_namespace_type fn_type;
3270 if (flow_is_multicast_only(flow_attr) &&
3272 priority = MLX5_IB_FLOW_MCAST_PRIO;
3274 priority = ib_prio_to_core_prio(flow_attr->priority,
3276 if (ft_type == MLX5_IB_FT_RX) {
3277 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3278 prio = &dev->flow_db->prios[priority];
3279 if (!dev->is_rep && !esw_encap &&
3280 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3281 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3282 if (!dev->is_rep && !esw_encap &&
3283 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3284 reformat_l3_tunnel_to_l2))
3285 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3288 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3290 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3291 prio = &dev->flow_db->egress_prios[priority];
3292 if (!dev->is_rep && !esw_encap &&
3293 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3294 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3296 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3297 num_entries = MLX5_FS_MAX_ENTRIES;
3298 num_groups = MLX5_FS_MAX_TYPES;
3299 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3300 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3301 ns = mlx5_get_flow_namespace(dev->mdev,
3302 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3303 build_leftovers_ft_param(&priority,
3306 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3307 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3308 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3309 allow_sniffer_and_nic_rx_shared_tir))
3310 return ERR_PTR(-ENOTSUPP);
3312 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3313 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3314 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3316 prio = &dev->flow_db->sniffer[ft_type];
3323 return ERR_PTR(-ENOTSUPP);
3325 max_table_size = min_t(int, num_entries, max_table_size);
3327 ft = prio->flow_table;
3329 return _get_prio(ns, prio, priority, max_table_size, num_groups,
3335 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3336 struct mlx5_flow_spec *spec,
3339 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3340 spec->match_criteria,
3342 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3346 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3347 ft_field_support.bth_dst_qp)) {
3348 MLX5_SET(fte_match_set_misc,
3349 misc_params_v, bth_dst_qp, underlay_qpn);
3350 MLX5_SET(fte_match_set_misc,
3351 misc_params_c, bth_dst_qp, 0xffffff);
3355 static int read_flow_counters(struct ib_device *ibdev,
3356 struct mlx5_read_counters_attr *read_attr)
3358 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3359 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3361 return mlx5_fc_query(dev->mdev, fc,
3362 &read_attr->out[IB_COUNTER_PACKETS],
3363 &read_attr->out[IB_COUNTER_BYTES]);
3366 /* flow counters currently expose two counters packets and bytes */
3367 #define FLOW_COUNTERS_NUM 2
3368 static int counters_set_description(struct ib_counters *counters,
3369 enum mlx5_ib_counters_type counters_type,
3370 struct mlx5_ib_flow_counters_desc *desc_data,
3373 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3374 u32 cntrs_max_index = 0;
3377 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3380 /* init the fields for the object */
3381 mcounters->type = counters_type;
3382 mcounters->read_counters = read_flow_counters;
3383 mcounters->counters_num = FLOW_COUNTERS_NUM;
3384 mcounters->ncounters = ncounters;
3385 /* each counter entry have both description and index pair */
3386 for (i = 0; i < ncounters; i++) {
3387 if (desc_data[i].description > IB_COUNTER_BYTES)
3390 if (cntrs_max_index <= desc_data[i].index)
3391 cntrs_max_index = desc_data[i].index + 1;
3394 mutex_lock(&mcounters->mcntrs_mutex);
3395 mcounters->counters_data = desc_data;
3396 mcounters->cntrs_max_index = cntrs_max_index;
3397 mutex_unlock(&mcounters->mcntrs_mutex);
3402 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3403 static int flow_counters_set_data(struct ib_counters *ibcounters,
3404 struct mlx5_ib_create_flow *ucmd)
3406 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3407 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3408 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3409 bool hw_hndl = false;
3412 if (ucmd && ucmd->ncounters_data != 0) {
3413 cntrs_data = ucmd->data;
3414 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3417 desc_data = kcalloc(cntrs_data->ncounters,
3423 if (copy_from_user(desc_data,
3424 u64_to_user_ptr(cntrs_data->counters_data),
3425 sizeof(*desc_data) * cntrs_data->ncounters)) {
3431 if (!mcounters->hw_cntrs_hndl) {
3432 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3433 to_mdev(ibcounters->device)->mdev, false);
3434 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3435 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3442 /* counters already bound to at least one flow */
3443 if (mcounters->cntrs_max_index) {
3448 ret = counters_set_description(ibcounters,
3449 MLX5_IB_COUNTERS_FLOW,
3451 cntrs_data->ncounters);
3455 } else if (!mcounters->cntrs_max_index) {
3456 /* counters not bound yet, must have udata passed */
3465 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3466 mcounters->hw_cntrs_hndl);
3467 mcounters->hw_cntrs_hndl = NULL;
3474 static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3475 struct mlx5_flow_spec *spec,
3476 struct mlx5_eswitch_rep *rep)
3478 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3481 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3482 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3485 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3486 mlx5_eswitch_get_vport_metadata_for_match(esw,
3488 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3491 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
3493 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3496 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3498 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3501 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3505 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3506 struct mlx5_ib_flow_prio *ft_prio,
3507 const struct ib_flow_attr *flow_attr,
3508 struct mlx5_flow_destination *dst,
3510 struct mlx5_ib_create_flow *ucmd)
3512 struct mlx5_flow_table *ft = ft_prio->flow_table;
3513 struct mlx5_ib_flow_handler *handler;
3514 struct mlx5_flow_act flow_act = {};
3515 struct mlx5_flow_spec *spec;
3516 struct mlx5_flow_destination dest_arr[2] = {};
3517 struct mlx5_flow_destination *rule_dst = dest_arr;
3518 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3519 unsigned int spec_index;
3523 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3525 if (!is_valid_attr(dev->mdev, flow_attr))
3526 return ERR_PTR(-EINVAL);
3528 if (dev->is_rep && is_egress)
3529 return ERR_PTR(-EINVAL);
3531 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3532 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3533 if (!handler || !spec) {
3538 INIT_LIST_HEAD(&handler->list);
3540 memcpy(&dest_arr[0], dst, sizeof(*dst));
3544 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3545 err = parse_flow_attr(dev->mdev, spec,
3546 ib_flow, flow_attr, &flow_act,
3551 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3552 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3555 if (!flow_is_multicast_only(flow_attr))
3556 set_underlay_qp(dev, spec, underlay_qpn);
3559 struct mlx5_eswitch_rep *rep;
3561 rep = dev->port[flow_attr->port - 1].rep;
3567 mlx5_ib_set_rule_source_port(dev, spec, rep);
3570 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3573 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3578 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3579 struct mlx5_ib_mcounters *mcounters;
3581 err = flow_counters_set_data(flow_act.counters, ucmd);
3585 mcounters = to_mcounters(flow_act.counters);
3586 handler->ibcounters = flow_act.counters;
3587 dest_arr[dest_num].type =
3588 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3589 dest_arr[dest_num].counter_id =
3590 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3594 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3595 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3601 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3604 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3605 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3608 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
3609 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3610 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3611 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3612 spec->flow_context.flow_tag, flow_attr->type);
3616 handler->rule = mlx5_add_flow_rules(ft, spec,
3618 rule_dst, dest_num);
3620 if (IS_ERR(handler->rule)) {
3621 err = PTR_ERR(handler->rule);
3625 ft_prio->refcount++;
3626 handler->prio = ft_prio;
3629 ft_prio->flow_table = ft;
3631 if (err && handler) {
3632 if (handler->ibcounters &&
3633 atomic_read(&handler->ibcounters->usecnt) == 1)
3634 counters_clear_description(handler->ibcounters);
3638 return err ? ERR_PTR(err) : handler;
3641 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3642 struct mlx5_ib_flow_prio *ft_prio,
3643 const struct ib_flow_attr *flow_attr,
3644 struct mlx5_flow_destination *dst)
3646 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3649 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3650 struct mlx5_ib_flow_prio *ft_prio,
3651 struct ib_flow_attr *flow_attr,
3652 struct mlx5_flow_destination *dst)
3654 struct mlx5_ib_flow_handler *handler_dst = NULL;
3655 struct mlx5_ib_flow_handler *handler = NULL;
3657 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3658 if (!IS_ERR(handler)) {
3659 handler_dst = create_flow_rule(dev, ft_prio,
3661 if (IS_ERR(handler_dst)) {
3662 mlx5_del_flow_rules(handler->rule);
3663 ft_prio->refcount--;
3665 handler = handler_dst;
3667 list_add(&handler_dst->list, &handler->list);
3678 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3679 struct mlx5_ib_flow_prio *ft_prio,
3680 struct ib_flow_attr *flow_attr,
3681 struct mlx5_flow_destination *dst)
3683 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3684 struct mlx5_ib_flow_handler *handler = NULL;
3687 struct ib_flow_attr flow_attr;
3688 struct ib_flow_spec_eth eth_flow;
3689 } leftovers_specs[] = {
3693 .size = sizeof(leftovers_specs[0])
3696 .type = IB_FLOW_SPEC_ETH,
3697 .size = sizeof(struct ib_flow_spec_eth),
3698 .mask = {.dst_mac = {0x1} },
3699 .val = {.dst_mac = {0x1} }
3705 .size = sizeof(leftovers_specs[0])
3708 .type = IB_FLOW_SPEC_ETH,
3709 .size = sizeof(struct ib_flow_spec_eth),
3710 .mask = {.dst_mac = {0x1} },
3711 .val = {.dst_mac = {} }
3716 handler = create_flow_rule(dev, ft_prio,
3717 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3719 if (!IS_ERR(handler) &&
3720 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3721 handler_ucast = create_flow_rule(dev, ft_prio,
3722 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3724 if (IS_ERR(handler_ucast)) {
3725 mlx5_del_flow_rules(handler->rule);
3726 ft_prio->refcount--;
3728 handler = handler_ucast;
3730 list_add(&handler_ucast->list, &handler->list);
3737 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3738 struct mlx5_ib_flow_prio *ft_rx,
3739 struct mlx5_ib_flow_prio *ft_tx,
3740 struct mlx5_flow_destination *dst)
3742 struct mlx5_ib_flow_handler *handler_rx;
3743 struct mlx5_ib_flow_handler *handler_tx;
3745 static const struct ib_flow_attr flow_attr = {
3747 .size = sizeof(flow_attr)
3750 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3751 if (IS_ERR(handler_rx)) {
3752 err = PTR_ERR(handler_rx);
3756 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3757 if (IS_ERR(handler_tx)) {
3758 err = PTR_ERR(handler_tx);
3762 list_add(&handler_tx->list, &handler_rx->list);
3767 mlx5_del_flow_rules(handler_rx->rule);
3771 return ERR_PTR(err);
3774 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3775 struct ib_flow_attr *flow_attr,
3777 struct ib_udata *udata)
3779 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3780 struct mlx5_ib_qp *mqp = to_mqp(qp);
3781 struct mlx5_ib_flow_handler *handler = NULL;
3782 struct mlx5_flow_destination *dst = NULL;
3783 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3784 struct mlx5_ib_flow_prio *ft_prio;
3785 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3786 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3787 size_t min_ucmd_sz, required_ucmd_sz;
3791 if (udata && udata->inlen) {
3792 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3793 sizeof(ucmd_hdr.reserved);
3794 if (udata->inlen < min_ucmd_sz)
3795 return ERR_PTR(-EOPNOTSUPP);
3797 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3799 return ERR_PTR(err);
3801 /* currently supports only one counters data */
3802 if (ucmd_hdr.ncounters_data > 1)
3803 return ERR_PTR(-EINVAL);
3805 required_ucmd_sz = min_ucmd_sz +
3806 sizeof(struct mlx5_ib_flow_counters_data) *
3807 ucmd_hdr.ncounters_data;
3808 if (udata->inlen > required_ucmd_sz &&
3809 !ib_is_udata_cleared(udata, required_ucmd_sz,
3810 udata->inlen - required_ucmd_sz))
3811 return ERR_PTR(-EOPNOTSUPP);
3813 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3815 return ERR_PTR(-ENOMEM);
3817 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3822 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3827 if (domain != IB_FLOW_DOMAIN_USER ||
3828 flow_attr->port > dev->num_ports ||
3829 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3830 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3836 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3837 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3842 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3848 mutex_lock(&dev->flow_db->lock);
3850 ft_prio = get_flow_table(dev, flow_attr,
3851 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3852 if (IS_ERR(ft_prio)) {
3853 err = PTR_ERR(ft_prio);
3856 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3857 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3858 if (IS_ERR(ft_prio_tx)) {
3859 err = PTR_ERR(ft_prio_tx);
3866 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3868 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3869 if (mqp->flags & MLX5_IB_QP_RSS)
3870 dst->tir_num = mqp->rss_qp.tirn;
3872 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3875 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3876 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3877 handler = create_dont_trap_rule(dev, ft_prio,
3880 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3881 mqp->underlay_qpn : 0;
3882 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3883 dst, underlay_qpn, ucmd);
3885 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3886 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3887 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3889 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3890 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3896 if (IS_ERR(handler)) {
3897 err = PTR_ERR(handler);
3902 mutex_unlock(&dev->flow_db->lock);
3906 return &handler->ibflow;
3909 put_flow_table(dev, ft_prio, false);
3911 put_flow_table(dev, ft_prio_tx, false);
3913 mutex_unlock(&dev->flow_db->lock);
3917 return ERR_PTR(err);
3920 static struct mlx5_ib_flow_prio *
3921 _get_flow_table(struct mlx5_ib_dev *dev,
3922 struct mlx5_ib_flow_matcher *fs_matcher,
3925 struct mlx5_flow_namespace *ns = NULL;
3926 struct mlx5_ib_flow_prio *prio = NULL;
3927 int max_table_size = 0;
3933 priority = MLX5_IB_FLOW_MCAST_PRIO;
3935 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3937 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3938 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3939 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3940 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3942 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
3943 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3944 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3945 reformat_l3_tunnel_to_l2) &&
3947 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3948 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3949 max_table_size = BIT(
3950 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
3951 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
3952 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3953 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3954 max_table_size = BIT(
3955 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
3956 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3957 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3958 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3960 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3961 priority = FDB_BYPASS_PATH;
3962 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX) {
3964 BIT(MLX5_CAP_FLOWTABLE_RDMA_RX(dev->mdev,
3966 priority = fs_matcher->priority;
3969 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
3971 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
3973 return ERR_PTR(-ENOTSUPP);
3975 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3976 prio = &dev->flow_db->prios[priority];
3977 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
3978 prio = &dev->flow_db->egress_prios[priority];
3979 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3980 prio = &dev->flow_db->fdb;
3981 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX)
3982 prio = &dev->flow_db->rdma_rx[priority];
3985 return ERR_PTR(-EINVAL);
3987 if (prio->flow_table)
3990 return _get_prio(ns, prio, priority, max_table_size,
3991 MLX5_FS_MAX_TYPES, flags);
3994 static struct mlx5_ib_flow_handler *
3995 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
3996 struct mlx5_ib_flow_prio *ft_prio,
3997 struct mlx5_flow_destination *dst,
3998 struct mlx5_ib_flow_matcher *fs_matcher,
3999 struct mlx5_flow_context *flow_context,
4000 struct mlx5_flow_act *flow_act,
4001 void *cmd_in, int inlen,
4004 struct mlx5_ib_flow_handler *handler;
4005 struct mlx5_flow_spec *spec;
4006 struct mlx5_flow_table *ft = ft_prio->flow_table;
4009 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4010 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4011 if (!handler || !spec) {
4016 INIT_LIST_HEAD(&handler->list);
4018 memcpy(spec->match_value, cmd_in, inlen);
4019 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4020 fs_matcher->mask_len);
4021 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
4022 spec->flow_context = *flow_context;
4024 handler->rule = mlx5_add_flow_rules(ft, spec,
4025 flow_act, dst, dst_num);
4027 if (IS_ERR(handler->rule)) {
4028 err = PTR_ERR(handler->rule);
4032 ft_prio->refcount++;
4033 handler->prio = ft_prio;
4035 ft_prio->flow_table = ft;
4041 return err ? ERR_PTR(err) : handler;
4044 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4048 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4049 void *dmac, *dmac_mask;
4050 void *ipv4, *ipv4_mask;
4052 if (!(fs_matcher->match_criteria_enable &
4053 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4056 match_c = fs_matcher->matcher_mask.match_params;
4057 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4059 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4062 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4064 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4067 if (is_multicast_ether_addr(dmac) &&
4068 is_multicast_ether_addr(dmac_mask))
4071 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4072 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4074 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4075 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4077 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4078 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4084 struct mlx5_ib_flow_handler *
4085 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4086 struct mlx5_ib_flow_matcher *fs_matcher,
4087 struct mlx5_flow_context *flow_context,
4088 struct mlx5_flow_act *flow_act,
4090 void *cmd_in, int inlen, int dest_id,
4093 struct mlx5_flow_destination *dst;
4094 struct mlx5_ib_flow_prio *ft_prio;
4095 struct mlx5_ib_flow_handler *handler;
4100 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4101 return ERR_PTR(-EOPNOTSUPP);
4103 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4104 return ERR_PTR(-ENOMEM);
4106 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
4108 return ERR_PTR(-ENOMEM);
4110 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4111 mutex_lock(&dev->flow_db->lock);
4113 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
4114 if (IS_ERR(ft_prio)) {
4115 err = PTR_ERR(ft_prio);
4119 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
4120 dst[dst_num].type = dest_type;
4121 dst[dst_num].tir_num = dest_id;
4122 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4123 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
4124 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4125 dst[dst_num].ft_num = dest_id;
4126 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4128 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
4129 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
4134 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4135 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4136 dst[dst_num].counter_id = counter_id;
4140 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4141 flow_context, flow_act,
4142 cmd_in, inlen, dst_num);
4144 if (IS_ERR(handler)) {
4145 err = PTR_ERR(handler);
4149 mutex_unlock(&dev->flow_db->lock);
4150 atomic_inc(&fs_matcher->usecnt);
4151 handler->flow_matcher = fs_matcher;
4158 put_flow_table(dev, ft_prio, false);
4160 mutex_unlock(&dev->flow_db->lock);
4163 return ERR_PTR(err);
4166 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4170 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4171 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4176 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4177 static struct ib_flow_action *
4178 mlx5_ib_create_flow_action_esp(struct ib_device *device,
4179 const struct ib_flow_action_attrs_esp *attr,
4180 struct uverbs_attr_bundle *attrs)
4182 struct mlx5_ib_dev *mdev = to_mdev(device);
4183 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4184 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4185 struct mlx5_ib_flow_action *action;
4190 err = uverbs_get_flags64(
4191 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4192 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4194 return ERR_PTR(err);
4196 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4198 /* We current only support a subset of the standard features. Only a
4199 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4200 * (with overlap). Full offload mode isn't supported.
4202 if (!attr->keymat || attr->replay || attr->encap ||
4203 attr->spi || attr->seq || attr->tfc_pad ||
4204 attr->hard_limit_pkts ||
4205 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4206 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4207 return ERR_PTR(-EOPNOTSUPP);
4209 if (attr->keymat->protocol !=
4210 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4211 return ERR_PTR(-EOPNOTSUPP);
4213 aes_gcm = &attr->keymat->keymat.aes_gcm;
4215 if (aes_gcm->icv_len != 16 ||
4216 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4217 return ERR_PTR(-EOPNOTSUPP);
4219 action = kmalloc(sizeof(*action), GFP_KERNEL);
4221 return ERR_PTR(-ENOMEM);
4223 action->esp_aes_gcm.ib_flags = attr->flags;
4224 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4225 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4226 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4227 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4228 sizeof(accel_attrs.keymat.aes_gcm.salt));
4229 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4230 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4231 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4232 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4233 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4235 accel_attrs.esn = attr->esn;
4236 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4237 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4238 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4239 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4241 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4242 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4244 action->esp_aes_gcm.ctx =
4245 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4246 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4247 err = PTR_ERR(action->esp_aes_gcm.ctx);
4251 action->esp_aes_gcm.ib_flags = attr->flags;
4253 return &action->ib_action;
4257 return ERR_PTR(err);
4261 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4262 const struct ib_flow_action_attrs_esp *attr,
4263 struct uverbs_attr_bundle *attrs)
4265 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4266 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4269 if (attr->keymat || attr->replay || attr->encap ||
4270 attr->spi || attr->seq || attr->tfc_pad ||
4271 attr->hard_limit_pkts ||
4272 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4273 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4274 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4277 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4280 if (!(maction->esp_aes_gcm.ib_flags &
4281 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4282 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4283 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4286 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4287 sizeof(accel_attrs));
4289 accel_attrs.esn = attr->esn;
4290 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4291 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4293 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4295 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4300 maction->esp_aes_gcm.ib_flags &=
4301 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4302 maction->esp_aes_gcm.ib_flags |=
4303 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4308 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4310 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4312 switch (action->type) {
4313 case IB_FLOW_ACTION_ESP:
4315 * We only support aes_gcm by now, so we implicitly know this is
4316 * the underline crypto.
4318 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4320 case IB_FLOW_ACTION_UNSPECIFIED:
4321 mlx5_ib_destroy_flow_action_raw(maction);
4332 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4334 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4335 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4340 to_mpd(ibqp->pd)->uid : 0;
4342 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4343 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4347 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4349 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4350 ibqp->qp_num, gid->raw);
4355 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4357 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4362 to_mpd(ibqp->pd)->uid : 0;
4363 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4365 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4366 ibqp->qp_num, gid->raw);
4371 static int init_node_data(struct mlx5_ib_dev *dev)
4375 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4379 dev->mdev->rev_id = dev->mdev->pdev->revision;
4381 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4384 static ssize_t fw_pages_show(struct device *device,
4385 struct device_attribute *attr, char *buf)
4387 struct mlx5_ib_dev *dev =
4388 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4390 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4392 static DEVICE_ATTR_RO(fw_pages);
4394 static ssize_t reg_pages_show(struct device *device,
4395 struct device_attribute *attr, char *buf)
4397 struct mlx5_ib_dev *dev =
4398 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4400 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4402 static DEVICE_ATTR_RO(reg_pages);
4404 static ssize_t hca_type_show(struct device *device,
4405 struct device_attribute *attr, char *buf)
4407 struct mlx5_ib_dev *dev =
4408 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4410 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4412 static DEVICE_ATTR_RO(hca_type);
4414 static ssize_t hw_rev_show(struct device *device,
4415 struct device_attribute *attr, char *buf)
4417 struct mlx5_ib_dev *dev =
4418 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4420 return sprintf(buf, "%x\n", dev->mdev->rev_id);
4422 static DEVICE_ATTR_RO(hw_rev);
4424 static ssize_t board_id_show(struct device *device,
4425 struct device_attribute *attr, char *buf)
4427 struct mlx5_ib_dev *dev =
4428 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4430 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4431 dev->mdev->board_id);
4433 static DEVICE_ATTR_RO(board_id);
4435 static struct attribute *mlx5_class_attributes[] = {
4436 &dev_attr_hw_rev.attr,
4437 &dev_attr_hca_type.attr,
4438 &dev_attr_board_id.attr,
4439 &dev_attr_fw_pages.attr,
4440 &dev_attr_reg_pages.attr,
4444 static const struct attribute_group mlx5_attr_group = {
4445 .attrs = mlx5_class_attributes,
4448 static void pkey_change_handler(struct work_struct *work)
4450 struct mlx5_ib_port_resources *ports =
4451 container_of(work, struct mlx5_ib_port_resources,
4454 mutex_lock(&ports->devr->mutex);
4455 mlx5_ib_gsi_pkey_change(ports->gsi);
4456 mutex_unlock(&ports->devr->mutex);
4459 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4461 struct mlx5_ib_qp *mqp;
4462 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4463 struct mlx5_core_cq *mcq;
4464 struct list_head cq_armed_list;
4465 unsigned long flags_qp;
4466 unsigned long flags_cq;
4467 unsigned long flags;
4469 INIT_LIST_HEAD(&cq_armed_list);
4471 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4472 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4473 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4474 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4475 if (mqp->sq.tail != mqp->sq.head) {
4476 send_mcq = to_mcq(mqp->ibqp.send_cq);
4477 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4478 if (send_mcq->mcq.comp &&
4479 mqp->ibqp.send_cq->comp_handler) {
4480 if (!send_mcq->mcq.reset_notify_added) {
4481 send_mcq->mcq.reset_notify_added = 1;
4482 list_add_tail(&send_mcq->mcq.reset_notify,
4486 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4488 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4489 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4490 /* no handling is needed for SRQ */
4491 if (!mqp->ibqp.srq) {
4492 if (mqp->rq.tail != mqp->rq.head) {
4493 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4494 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4495 if (recv_mcq->mcq.comp &&
4496 mqp->ibqp.recv_cq->comp_handler) {
4497 if (!recv_mcq->mcq.reset_notify_added) {
4498 recv_mcq->mcq.reset_notify_added = 1;
4499 list_add_tail(&recv_mcq->mcq.reset_notify,
4503 spin_unlock_irqrestore(&recv_mcq->lock,
4507 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4509 /*At that point all inflight post send were put to be executed as of we
4510 * lock/unlock above locks Now need to arm all involved CQs.
4512 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4513 mcq->comp(mcq, NULL);
4515 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4518 static void delay_drop_handler(struct work_struct *work)
4521 struct mlx5_ib_delay_drop *delay_drop =
4522 container_of(work, struct mlx5_ib_delay_drop,
4525 atomic_inc(&delay_drop->events_cnt);
4527 mutex_lock(&delay_drop->lock);
4528 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4529 delay_drop->timeout);
4531 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4532 delay_drop->timeout);
4533 delay_drop->activate = false;
4535 mutex_unlock(&delay_drop->lock);
4538 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4539 struct ib_event *ibev)
4541 u8 port = (eqe->data.port.port >> 4) & 0xf;
4543 switch (eqe->sub_type) {
4544 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
4545 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4546 IB_LINK_LAYER_ETHERNET)
4547 schedule_work(&ibdev->delay_drop.delay_drop_work);
4549 default: /* do nothing */
4554 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4555 struct ib_event *ibev)
4557 u8 port = (eqe->data.port.port >> 4) & 0xf;
4559 ibev->element.port_num = port;
4561 switch (eqe->sub_type) {
4562 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4563 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4564 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4565 /* In RoCE, port up/down events are handled in
4566 * mlx5_netdev_event().
4568 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4569 IB_LINK_LAYER_ETHERNET)
4572 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4573 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4576 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4577 ibev->event = IB_EVENT_LID_CHANGE;
4580 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4581 ibev->event = IB_EVENT_PKEY_CHANGE;
4582 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4585 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4586 ibev->event = IB_EVENT_GID_CHANGE;
4589 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4590 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4599 static void mlx5_ib_handle_event(struct work_struct *_work)
4601 struct mlx5_ib_event_work *work =
4602 container_of(_work, struct mlx5_ib_event_work, work);
4603 struct mlx5_ib_dev *ibdev;
4604 struct ib_event ibev;
4607 if (work->is_slave) {
4608 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
4615 switch (work->event) {
4616 case MLX5_DEV_EVENT_SYS_ERROR:
4617 ibev.event = IB_EVENT_DEVICE_FATAL;
4618 mlx5_ib_handle_internal_error(ibdev);
4619 ibev.element.port_num = (u8)(unsigned long)work->param;
4622 case MLX5_EVENT_TYPE_PORT_CHANGE:
4623 if (handle_port_change(ibdev, work->param, &ibev))
4626 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4627 handle_general_event(ibdev, work->param, &ibev);
4633 ibev.device = &ibdev->ib_dev;
4635 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4636 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
4640 if (ibdev->ib_active)
4641 ib_dispatch_event(&ibev);
4644 ibdev->ib_active = false;
4649 static int mlx5_ib_event(struct notifier_block *nb,
4650 unsigned long event, void *param)
4652 struct mlx5_ib_event_work *work;
4654 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4658 INIT_WORK(&work->work, mlx5_ib_handle_event);
4659 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4660 work->is_slave = false;
4661 work->param = param;
4662 work->event = event;
4664 queue_work(mlx5_ib_event_wq, &work->work);
4669 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4670 unsigned long event, void *param)
4672 struct mlx5_ib_event_work *work;
4674 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4678 INIT_WORK(&work->work, mlx5_ib_handle_event);
4679 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4680 work->is_slave = true;
4681 work->param = param;
4682 work->event = event;
4683 queue_work(mlx5_ib_event_wq, &work->work);
4688 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4690 struct mlx5_hca_vport_context vport_ctx;
4694 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
4695 dev->mdev->port_caps[port - 1].has_smi = false;
4696 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4697 MLX5_CAP_PORT_TYPE_IB) {
4698 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4699 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4703 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4707 dev->mdev->port_caps[port - 1].has_smi =
4710 dev->mdev->port_caps[port - 1].has_smi = true;
4717 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4721 for (port = 1; port <= dev->num_ports; port++)
4722 mlx5_query_ext_port_caps(dev, port);
4725 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4727 struct ib_device_attr *dprops = NULL;
4728 struct ib_port_attr *pprops = NULL;
4730 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4732 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
4736 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4740 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4742 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4746 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4748 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4753 dev->mdev->port_caps[port - 1].pkey_table_len =
4755 dev->mdev->port_caps[port - 1].gid_table_len =
4756 pprops->gid_tbl_len;
4757 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4758 port, dprops->max_pkeys, pprops->gid_tbl_len);
4767 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4769 /* For representors use port 1, is this is the only native
4773 return __get_port_caps(dev, 1);
4774 return __get_port_caps(dev, port);
4777 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4781 err = mlx5_mr_cache_cleanup(dev);
4783 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4786 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4788 ib_free_cq(dev->umrc.cq);
4790 ib_dealloc_pd(dev->umrc.pd);
4797 static int create_umr_res(struct mlx5_ib_dev *dev)
4799 struct ib_qp_init_attr *init_attr = NULL;
4800 struct ib_qp_attr *attr = NULL;
4806 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4807 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4808 if (!attr || !init_attr) {
4813 pd = ib_alloc_pd(&dev->ib_dev, 0);
4815 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4820 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4822 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4827 init_attr->send_cq = cq;
4828 init_attr->recv_cq = cq;
4829 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4830 init_attr->cap.max_send_wr = MAX_UMR_WR;
4831 init_attr->cap.max_send_sge = 1;
4832 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4833 init_attr->port_num = 1;
4834 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4836 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4840 qp->device = &dev->ib_dev;
4843 qp->qp_type = MLX5_IB_QPT_REG_UMR;
4844 qp->send_cq = init_attr->send_cq;
4845 qp->recv_cq = init_attr->recv_cq;
4847 attr->qp_state = IB_QPS_INIT;
4849 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4852 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4856 memset(attr, 0, sizeof(*attr));
4857 attr->qp_state = IB_QPS_RTR;
4858 attr->path_mtu = IB_MTU_256;
4860 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4862 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4866 memset(attr, 0, sizeof(*attr));
4867 attr->qp_state = IB_QPS_RTS;
4868 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4870 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4878 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4879 ret = mlx5_mr_cache_init(dev);
4881 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4891 mlx5_ib_destroy_qp(qp, NULL);
4892 dev->umrc.qp = NULL;
4896 dev->umrc.cq = NULL;
4900 dev->umrc.pd = NULL;
4908 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4910 switch (umr_fence_cap) {
4911 case MLX5_CAP_UMR_FENCE_NONE:
4912 return MLX5_FENCE_MODE_NONE;
4913 case MLX5_CAP_UMR_FENCE_SMALL:
4914 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4916 return MLX5_FENCE_MODE_STRONG_ORDERING;
4920 static int create_dev_resources(struct mlx5_ib_resources *devr)
4922 struct ib_srq_init_attr attr;
4923 struct mlx5_ib_dev *dev;
4924 struct ib_device *ibdev;
4925 struct ib_cq_init_attr cq_attr = {.cqe = 1};
4929 dev = container_of(devr, struct mlx5_ib_dev, devr);
4930 ibdev = &dev->ib_dev;
4932 mutex_init(&devr->mutex);
4934 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4938 devr->p0->device = ibdev;
4939 devr->p0->uobject = NULL;
4940 atomic_set(&devr->p0->usecnt, 0);
4942 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
4946 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4952 devr->c0->device = &dev->ib_dev;
4953 atomic_set(&devr->c0->usecnt, 0);
4955 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4959 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4960 if (IS_ERR(devr->x0)) {
4961 ret = PTR_ERR(devr->x0);
4964 devr->x0->device = &dev->ib_dev;
4965 devr->x0->inode = NULL;
4966 atomic_set(&devr->x0->usecnt, 0);
4967 mutex_init(&devr->x0->tgt_qp_mutex);
4968 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4970 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4971 if (IS_ERR(devr->x1)) {
4972 ret = PTR_ERR(devr->x1);
4975 devr->x1->device = &dev->ib_dev;
4976 devr->x1->inode = NULL;
4977 atomic_set(&devr->x1->usecnt, 0);
4978 mutex_init(&devr->x1->tgt_qp_mutex);
4979 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4981 memset(&attr, 0, sizeof(attr));
4982 attr.attr.max_sge = 1;
4983 attr.attr.max_wr = 1;
4984 attr.srq_type = IB_SRQT_XRC;
4985 attr.ext.cq = devr->c0;
4986 attr.ext.xrc.xrcd = devr->x0;
4988 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4994 devr->s0->device = &dev->ib_dev;
4995 devr->s0->pd = devr->p0;
4996 devr->s0->srq_type = IB_SRQT_XRC;
4997 devr->s0->ext.xrc.xrcd = devr->x0;
4998 devr->s0->ext.cq = devr->c0;
4999 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5003 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
5004 atomic_inc(&devr->s0->ext.cq->usecnt);
5005 atomic_inc(&devr->p0->usecnt);
5006 atomic_set(&devr->s0->usecnt, 0);
5008 memset(&attr, 0, sizeof(attr));
5009 attr.attr.max_sge = 1;
5010 attr.attr.max_wr = 1;
5011 attr.srq_type = IB_SRQT_BASIC;
5012 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5018 devr->s1->device = &dev->ib_dev;
5019 devr->s1->pd = devr->p0;
5020 devr->s1->srq_type = IB_SRQT_BASIC;
5021 devr->s1->ext.cq = devr->c0;
5023 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5027 atomic_inc(&devr->p0->usecnt);
5028 atomic_set(&devr->s1->usecnt, 0);
5030 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5031 INIT_WORK(&devr->ports[port].pkey_change_work,
5032 pkey_change_handler);
5033 devr->ports[port].devr = devr;
5041 mlx5_ib_destroy_srq(devr->s0, NULL);
5045 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5047 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5049 mlx5_ib_destroy_cq(devr->c0, NULL);
5053 mlx5_ib_dealloc_pd(devr->p0, NULL);
5059 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5063 mlx5_ib_destroy_srq(devr->s1, NULL);
5065 mlx5_ib_destroy_srq(devr->s0, NULL);
5067 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5068 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5069 mlx5_ib_destroy_cq(devr->c0, NULL);
5071 mlx5_ib_dealloc_pd(devr->p0, NULL);
5074 /* Make sure no change P_Key work items are still executing */
5075 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
5076 cancel_work_sync(&devr->ports[port].pkey_change_work);
5079 static u32 get_core_cap_flags(struct ib_device *ibdev,
5080 struct mlx5_hca_vport_context *rep)
5082 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5083 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5084 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5085 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
5086 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
5089 if (rep->grh_required)
5090 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5092 if (ll == IB_LINK_LAYER_INFINIBAND)
5093 return ret | RDMA_CORE_PORT_IBA_IB;
5096 ret |= RDMA_CORE_PORT_RAW_PACKET;
5098 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
5101 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
5104 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5105 ret |= RDMA_CORE_PORT_IBA_ROCE;
5107 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5108 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5113 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5114 struct ib_port_immutable *immutable)
5116 struct ib_port_attr attr;
5117 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5118 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
5119 struct mlx5_hca_vport_context rep = {0};
5122 err = ib_query_port(ibdev, port_num, &attr);
5126 if (ll == IB_LINK_LAYER_INFINIBAND) {
5127 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5133 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5134 immutable->gid_tbl_len = attr.gid_tbl_len;
5135 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
5136 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5137 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
5142 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5143 struct ib_port_immutable *immutable)
5145 struct ib_port_attr attr;
5148 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5150 err = ib_query_port(ibdev, port_num, &attr);
5154 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5155 immutable->gid_tbl_len = attr.gid_tbl_len;
5156 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5161 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
5163 struct mlx5_ib_dev *dev =
5164 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
5165 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5166 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5167 fw_rev_sub(dev->mdev));
5170 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
5172 struct mlx5_core_dev *mdev = dev->mdev;
5173 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5174 MLX5_FLOW_NAMESPACE_LAG);
5175 struct mlx5_flow_table *ft;
5178 if (!ns || !mlx5_lag_is_roce(mdev))
5181 err = mlx5_cmd_create_vport_lag(mdev);
5185 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5188 goto err_destroy_vport_lag;
5191 dev->flow_db->lag_demux_ft = ft;
5192 dev->lag_active = true;
5195 err_destroy_vport_lag:
5196 mlx5_cmd_destroy_vport_lag(mdev);
5200 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
5202 struct mlx5_core_dev *mdev = dev->mdev;
5204 if (dev->lag_active) {
5205 dev->lag_active = false;
5207 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5208 dev->flow_db->lag_demux_ft = NULL;
5210 mlx5_cmd_destroy_vport_lag(mdev);
5214 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5218 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5219 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
5221 dev->port[port_num].roce.nb.notifier_call = NULL;
5228 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5230 if (dev->port[port_num].roce.nb.notifier_call) {
5231 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5232 dev->port[port_num].roce.nb.notifier_call = NULL;
5236 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
5240 if (MLX5_CAP_GEN(dev->mdev, roce)) {
5241 err = mlx5_nic_vport_enable_roce(dev->mdev);
5246 err = mlx5_eth_lag_init(dev);
5248 goto err_disable_roce;
5253 if (MLX5_CAP_GEN(dev->mdev, roce))
5254 mlx5_nic_vport_disable_roce(dev->mdev);
5259 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
5261 mlx5_eth_lag_cleanup(dev);
5262 if (MLX5_CAP_GEN(dev->mdev, roce))
5263 mlx5_nic_vport_disable_roce(dev->mdev);
5266 struct mlx5_ib_counter {
5271 #define INIT_Q_COUNTER(_name) \
5272 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5274 static const struct mlx5_ib_counter basic_q_cnts[] = {
5275 INIT_Q_COUNTER(rx_write_requests),
5276 INIT_Q_COUNTER(rx_read_requests),
5277 INIT_Q_COUNTER(rx_atomic_requests),
5278 INIT_Q_COUNTER(out_of_buffer),
5281 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
5282 INIT_Q_COUNTER(out_of_sequence),
5285 static const struct mlx5_ib_counter retrans_q_cnts[] = {
5286 INIT_Q_COUNTER(duplicate_request),
5287 INIT_Q_COUNTER(rnr_nak_retry_err),
5288 INIT_Q_COUNTER(packet_seq_err),
5289 INIT_Q_COUNTER(implied_nak_seq_err),
5290 INIT_Q_COUNTER(local_ack_timeout_err),
5293 #define INIT_CONG_COUNTER(_name) \
5294 { .name = #_name, .offset = \
5295 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5297 static const struct mlx5_ib_counter cong_cnts[] = {
5298 INIT_CONG_COUNTER(rp_cnp_ignored),
5299 INIT_CONG_COUNTER(rp_cnp_handled),
5300 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5301 INIT_CONG_COUNTER(np_cnp_sent),
5304 static const struct mlx5_ib_counter extended_err_cnts[] = {
5305 INIT_Q_COUNTER(resp_local_length_error),
5306 INIT_Q_COUNTER(resp_cqe_error),
5307 INIT_Q_COUNTER(req_cqe_error),
5308 INIT_Q_COUNTER(req_remote_invalid_request),
5309 INIT_Q_COUNTER(req_remote_access_errors),
5310 INIT_Q_COUNTER(resp_remote_access_errors),
5311 INIT_Q_COUNTER(resp_cqe_flush_error),
5312 INIT_Q_COUNTER(req_cqe_flush_error),
5315 #define INIT_EXT_PPCNT_COUNTER(_name) \
5316 { .name = #_name, .offset = \
5317 MLX5_BYTE_OFF(ppcnt_reg, \
5318 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5320 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5321 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5324 static bool is_mdev_switchdev_mode(const struct mlx5_core_dev *mdev)
5326 return MLX5_ESWITCH_MANAGER(mdev) &&
5327 mlx5_ib_eswitch_mode(mdev->priv.eswitch) ==
5328 MLX5_ESWITCH_OFFLOADS;
5331 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
5336 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5338 for (i = 0; i < num_cnt_ports; i++) {
5339 if (dev->port[i].cnts.set_id_valid)
5340 mlx5_core_dealloc_q_counter(dev->mdev,
5341 dev->port[i].cnts.set_id);
5342 kfree(dev->port[i].cnts.names);
5343 kfree(dev->port[i].cnts.offsets);
5347 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5348 struct mlx5_ib_counters *cnts)
5352 num_counters = ARRAY_SIZE(basic_q_cnts);
5354 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5355 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5357 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5358 num_counters += ARRAY_SIZE(retrans_q_cnts);
5360 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5361 num_counters += ARRAY_SIZE(extended_err_cnts);
5363 cnts->num_q_counters = num_counters;
5365 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5366 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5367 num_counters += ARRAY_SIZE(cong_cnts);
5369 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5370 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5371 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5373 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5377 cnts->offsets = kcalloc(num_counters,
5378 sizeof(cnts->offsets), GFP_KERNEL);
5390 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5397 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5398 names[j] = basic_q_cnts[i].name;
5399 offsets[j] = basic_q_cnts[i].offset;
5402 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5403 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5404 names[j] = out_of_seq_q_cnts[i].name;
5405 offsets[j] = out_of_seq_q_cnts[i].offset;
5409 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5410 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5411 names[j] = retrans_q_cnts[i].name;
5412 offsets[j] = retrans_q_cnts[i].offset;
5416 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5417 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5418 names[j] = extended_err_cnts[i].name;
5419 offsets[j] = extended_err_cnts[i].offset;
5423 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5424 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5425 names[j] = cong_cnts[i].name;
5426 offsets[j] = cong_cnts[i].offset;
5430 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5431 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5432 names[j] = ext_ppcnt_cnts[i].name;
5433 offsets[j] = ext_ppcnt_cnts[i].offset;
5438 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5445 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
5446 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5448 for (i = 0; i < num_cnt_ports; i++) {
5449 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5453 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5454 dev->port[i].cnts.offsets);
5456 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5457 &dev->port[i].cnts.set_id,
5459 MLX5_SHARED_RESOURCE_UID : 0);
5462 "couldn't allocate queue counter for port %d, err %d\n",
5466 dev->port[i].cnts.set_id_valid = true;
5471 mlx5_ib_dealloc_counters(dev);
5475 static const struct mlx5_ib_counters *get_counters(struct mlx5_ib_dev *dev,
5478 return is_mdev_switchdev_mode(dev->mdev) ? &dev->port[0].cnts :
5479 &dev->port[port_num].cnts;
5483 * mlx5_ib_get_counters_id - Returns counters id to use for device+port
5484 * @dev: Pointer to mlx5 IB device
5485 * @port_num: Zero based port number
5487 * mlx5_ib_get_counters_id() Returns counters set id to use for given
5488 * device port combination in switchdev and non switchdev mode of the
5491 u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num)
5493 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num);
5495 return cnts->set_id;
5498 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5501 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5502 const struct mlx5_ib_counters *cnts;
5503 bool is_switchdev = is_mdev_switchdev_mode(dev->mdev);
5505 if ((is_switchdev && port_num) || (!is_switchdev && !port_num))
5508 cnts = get_counters(dev, port_num - 1);
5510 return rdma_alloc_hw_stats_struct(cnts->names,
5511 cnts->num_q_counters +
5512 cnts->num_cong_counters +
5513 cnts->num_ext_ppcnt_counters,
5514 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5517 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5518 const struct mlx5_ib_counters *cnts,
5519 struct rdma_hw_stats *stats,
5522 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5527 out = kvzalloc(outlen, GFP_KERNEL);
5531 ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
5535 for (i = 0; i < cnts->num_q_counters; i++) {
5536 val = *(__be32 *)(out + cnts->offsets[i]);
5537 stats->value[i] = (u64)be32_to_cpu(val);
5545 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5546 const struct mlx5_ib_counters *cnts,
5547 struct rdma_hw_stats *stats)
5549 int offset = cnts->num_q_counters + cnts->num_cong_counters;
5550 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5554 out = kvzalloc(sz, GFP_KERNEL);
5558 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5562 for (i = 0; i < cnts->num_ext_ppcnt_counters; i++)
5563 stats->value[i + offset] =
5564 be64_to_cpup((__be64 *)(out +
5565 cnts->offsets[i + offset]));
5571 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5572 struct rdma_hw_stats *stats,
5573 u8 port_num, int index)
5575 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5576 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num - 1);
5577 struct mlx5_core_dev *mdev;
5578 int ret, num_counters;
5584 num_counters = cnts->num_q_counters +
5585 cnts->num_cong_counters +
5586 cnts->num_ext_ppcnt_counters;
5588 /* q_counters are per IB device, query the master mdev */
5589 ret = mlx5_ib_query_q_counters(dev->mdev, cnts, stats, cnts->set_id);
5593 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5594 ret = mlx5_ib_query_ext_ppcnt_counters(dev, cnts, stats);
5599 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5600 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5603 /* If port is not affiliated yet, its in down state
5604 * which doesn't have any counters yet, so it would be
5605 * zero. So no need to read from the HCA.
5609 ret = mlx5_lag_query_cong_counters(dev->mdev,
5611 cnts->num_q_counters,
5612 cnts->num_cong_counters,
5614 cnts->num_q_counters);
5616 mlx5_ib_put_native_port_mdev(dev, port_num);
5622 return num_counters;
5625 static struct rdma_hw_stats *
5626 mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5628 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5629 const struct mlx5_ib_counters *cnts =
5630 get_counters(dev, counter->port - 1);
5632 /* Q counters are in the beginning of all counters */
5633 return rdma_alloc_hw_stats_struct(cnts->names,
5634 cnts->num_q_counters,
5635 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5638 static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5640 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5641 const struct mlx5_ib_counters *cnts =
5642 get_counters(dev, counter->port - 1);
5644 return mlx5_ib_query_q_counters(dev->mdev, cnts,
5645 counter->stats, counter->id);
5648 static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5651 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5656 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5658 MLX5_SHARED_RESOURCE_UID);
5661 counter->id = cnt_set_id;
5664 err = mlx5_ib_qp_set_counter(qp, counter);
5666 goto fail_set_counter;
5671 mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5677 static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5679 return mlx5_ib_qp_set_counter(qp, NULL);
5682 static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5684 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5686 return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5689 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5690 enum rdma_netdev_t type,
5691 struct rdma_netdev_alloc_params *params)
5693 if (type != RDMA_NETDEV_IPOIB)
5696 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
5699 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5701 if (!dev->delay_drop.dbg)
5703 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5704 kfree(dev->delay_drop.dbg);
5705 dev->delay_drop.dbg = NULL;
5708 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5710 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5713 cancel_work_sync(&dev->delay_drop.delay_drop_work);
5714 delay_drop_debugfs_cleanup(dev);
5717 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5718 size_t count, loff_t *pos)
5720 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5724 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5725 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5728 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5729 size_t count, loff_t *pos)
5731 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5735 if (kstrtouint_from_user(buf, count, 0, &var))
5738 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5741 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5744 delay_drop->timeout = timeout;
5749 static const struct file_operations fops_delay_drop_timeout = {
5750 .owner = THIS_MODULE,
5751 .open = simple_open,
5752 .write = delay_drop_timeout_write,
5753 .read = delay_drop_timeout_read,
5756 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5758 struct mlx5_ib_dbg_delay_drop *dbg;
5760 if (!mlx5_debugfs_root)
5763 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5767 dev->delay_drop.dbg = dbg;
5770 debugfs_create_dir("delay_drop",
5771 dev->mdev->priv.dbg_root);
5772 if (!dbg->dir_debugfs)
5775 dbg->events_cnt_debugfs =
5776 debugfs_create_atomic_t("num_timeout_events", 0400,
5778 &dev->delay_drop.events_cnt);
5779 if (!dbg->events_cnt_debugfs)
5782 dbg->rqs_cnt_debugfs =
5783 debugfs_create_atomic_t("num_rqs", 0400,
5785 &dev->delay_drop.rqs_cnt);
5786 if (!dbg->rqs_cnt_debugfs)
5789 dbg->timeout_debugfs =
5790 debugfs_create_file("timeout", 0600,
5793 &fops_delay_drop_timeout);
5794 if (!dbg->timeout_debugfs)
5800 delay_drop_debugfs_cleanup(dev);
5804 static void init_delay_drop(struct mlx5_ib_dev *dev)
5806 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5809 mutex_init(&dev->delay_drop.lock);
5810 dev->delay_drop.dev = dev;
5811 dev->delay_drop.activate = false;
5812 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5813 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5814 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5815 atomic_set(&dev->delay_drop.events_cnt, 0);
5817 if (delay_drop_debugfs_init(dev))
5818 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5821 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5822 struct mlx5_ib_multiport_info *mpi)
5824 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5825 struct mlx5_ib_port *port = &ibdev->port[port_num];
5830 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5832 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5834 spin_lock(&port->mp.mpi_lock);
5836 spin_unlock(&port->mp.mpi_lock);
5842 spin_unlock(&port->mp.mpi_lock);
5843 if (mpi->mdev_events.notifier_call)
5844 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5845 mpi->mdev_events.notifier_call = NULL;
5846 mlx5_remove_netdev_notifier(ibdev, port_num);
5847 spin_lock(&port->mp.mpi_lock);
5849 comps = mpi->mdev_refcnt;
5851 mpi->unaffiliate = true;
5852 init_completion(&mpi->unref_comp);
5853 spin_unlock(&port->mp.mpi_lock);
5855 for (i = 0; i < comps; i++)
5856 wait_for_completion(&mpi->unref_comp);
5858 spin_lock(&port->mp.mpi_lock);
5859 mpi->unaffiliate = false;
5862 port->mp.mpi = NULL;
5864 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5866 spin_unlock(&port->mp.mpi_lock);
5868 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5870 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5871 /* Log an error, still needed to cleanup the pointers and add
5872 * it back to the list.
5875 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5878 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
5881 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5882 struct mlx5_ib_multiport_info *mpi)
5884 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5887 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5889 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5890 if (ibdev->port[port_num].mp.mpi) {
5891 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5893 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5897 ibdev->port[port_num].mp.mpi = mpi;
5899 mpi->mdev_events.notifier_call = NULL;
5900 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5902 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5906 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5910 err = mlx5_add_netdev_notifier(ibdev, port_num);
5912 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5917 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5918 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5920 mlx5_ib_init_cong_debugfs(ibdev, port_num);
5925 mlx5_ib_unbind_slave_port(ibdev, mpi);
5929 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5931 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5932 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5934 struct mlx5_ib_multiport_info *mpi;
5938 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5941 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5942 &dev->sys_image_guid);
5946 err = mlx5_nic_vport_enable_roce(dev->mdev);
5950 mutex_lock(&mlx5_ib_multiport_mutex);
5951 for (i = 0; i < dev->num_ports; i++) {
5954 /* build a stub multiport info struct for the native port. */
5955 if (i == port_num) {
5956 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5958 mutex_unlock(&mlx5_ib_multiport_mutex);
5959 mlx5_nic_vport_disable_roce(dev->mdev);
5963 mpi->is_master = true;
5964 mpi->mdev = dev->mdev;
5965 mpi->sys_image_guid = dev->sys_image_guid;
5966 dev->port[i].mp.mpi = mpi;
5972 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5974 if (dev->sys_image_guid == mpi->sys_image_guid &&
5975 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5976 bound = mlx5_ib_bind_slave_port(dev, mpi);
5980 dev_dbg(mpi->mdev->device,
5981 "removing port from unaffiliated list.\n");
5982 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5983 list_del(&mpi->list);
5988 get_port_caps(dev, i + 1);
5989 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5994 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5995 mutex_unlock(&mlx5_ib_multiport_mutex);
5999 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
6001 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6002 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
6006 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
6009 mutex_lock(&mlx5_ib_multiport_mutex);
6010 for (i = 0; i < dev->num_ports; i++) {
6011 if (dev->port[i].mp.mpi) {
6012 /* Destroy the native port stub */
6013 if (i == port_num) {
6014 kfree(dev->port[i].mp.mpi);
6015 dev->port[i].mp.mpi = NULL;
6017 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
6018 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
6023 mlx5_ib_dbg(dev, "removing from devlist\n");
6024 list_del(&dev->ib_dev_list);
6025 mutex_unlock(&mlx5_ib_multiport_mutex);
6027 mlx5_nic_vport_disable_roce(dev->mdev);
6030 ADD_UVERBS_ATTRIBUTES_SIMPLE(
6033 UVERBS_METHOD_DM_ALLOC,
6034 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
6035 UVERBS_ATTR_TYPE(u64),
6037 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6038 UVERBS_ATTR_TYPE(u16),
6040 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6041 enum mlx5_ib_uapi_dm_type,
6044 ADD_UVERBS_ATTRIBUTES_SIMPLE(
6045 mlx5_ib_flow_action,
6046 UVERBS_OBJECT_FLOW_ACTION,
6047 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
6048 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6049 enum mlx5_ib_uapi_flow_action_flags));
6051 static const struct uapi_definition mlx5_ib_defs[] = {
6052 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
6053 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
6054 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
6057 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6058 &mlx5_ib_flow_action),
6059 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
6063 static int mlx5_ib_read_counters(struct ib_counters *counters,
6064 struct ib_counters_read_attr *read_attr,
6065 struct uverbs_attr_bundle *attrs)
6067 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6068 struct mlx5_read_counters_attr mread_attr = {};
6069 struct mlx5_ib_flow_counters_desc *desc;
6072 mutex_lock(&mcounters->mcntrs_mutex);
6073 if (mcounters->cntrs_max_index > read_attr->ncounters) {
6078 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6080 if (!mread_attr.out) {
6085 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6086 mread_attr.flags = read_attr->flags;
6087 ret = mcounters->read_counters(counters->device, &mread_attr);
6091 /* do the pass over the counters data array to assign according to the
6092 * descriptions and indexing pairs
6094 desc = mcounters->counters_data;
6095 for (i = 0; i < mcounters->ncounters; i++)
6096 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6099 kfree(mread_attr.out);
6101 mutex_unlock(&mcounters->mcntrs_mutex);
6105 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6107 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6109 counters_clear_description(counters);
6110 if (mcounters->hw_cntrs_hndl)
6111 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6112 mcounters->hw_cntrs_hndl);
6119 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6120 struct uverbs_attr_bundle *attrs)
6122 struct mlx5_ib_mcounters *mcounters;
6124 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6126 return ERR_PTR(-ENOMEM);
6128 mutex_init(&mcounters->mcntrs_mutex);
6130 return &mcounters->ibcntrs;
6133 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
6135 mlx5_ib_cleanup_multiport_master(dev);
6136 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6137 srcu_barrier(&dev->mr_srcu);
6138 cleanup_srcu_struct(&dev->mr_srcu);
6141 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
6144 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
6146 struct mlx5_core_dev *mdev = dev->mdev;
6150 for (i = 0; i < dev->num_ports; i++) {
6151 spin_lock_init(&dev->port[i].mp.mpi_lock);
6152 rwlock_init(&dev->port[i].roce.netdev_lock);
6153 dev->port[i].roce.dev = dev;
6154 dev->port[i].roce.native_port_num = i + 1;
6155 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
6158 mlx5_ib_internal_fill_odp_caps(dev);
6160 err = mlx5_ib_init_multiport_master(dev);
6164 err = set_has_smi_cap(dev);
6168 if (!mlx5_core_mp_enabled(mdev)) {
6169 for (i = 1; i <= dev->num_ports; i++) {
6170 err = get_port_caps(dev, i);
6175 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6180 if (mlx5_use_mad_ifc(dev))
6181 get_ext_port_caps(dev);
6183 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
6184 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
6185 dev->ib_dev.phys_port_cnt = dev->num_ports;
6186 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
6187 dev->ib_dev.dev.parent = mdev->device;
6189 mutex_init(&dev->cap_mask_mutex);
6190 INIT_LIST_HEAD(&dev->qp_list);
6191 spin_lock_init(&dev->reset_flow_resource_lock);
6193 spin_lock_init(&dev->dm.lock);
6196 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6197 err = init_srcu_struct(&dev->mr_srcu);
6205 mlx5_ib_cleanup_multiport_master(dev);
6210 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6212 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6217 mutex_init(&dev->flow_db->lock);
6222 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6224 kfree(dev->flow_db);
6227 static const struct ib_device_ops mlx5_ib_dev_ops = {
6228 .owner = THIS_MODULE,
6229 .driver_id = RDMA_DRIVER_MLX5,
6230 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
6232 .add_gid = mlx5_ib_add_gid,
6233 .alloc_mr = mlx5_ib_alloc_mr,
6234 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
6235 .alloc_pd = mlx5_ib_alloc_pd,
6236 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6237 .attach_mcast = mlx5_ib_mcg_attach,
6238 .check_mr_status = mlx5_ib_check_mr_status,
6239 .create_ah = mlx5_ib_create_ah,
6240 .create_counters = mlx5_ib_create_counters,
6241 .create_cq = mlx5_ib_create_cq,
6242 .create_flow = mlx5_ib_create_flow,
6243 .create_qp = mlx5_ib_create_qp,
6244 .create_srq = mlx5_ib_create_srq,
6245 .dealloc_pd = mlx5_ib_dealloc_pd,
6246 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6247 .del_gid = mlx5_ib_del_gid,
6248 .dereg_mr = mlx5_ib_dereg_mr,
6249 .destroy_ah = mlx5_ib_destroy_ah,
6250 .destroy_counters = mlx5_ib_destroy_counters,
6251 .destroy_cq = mlx5_ib_destroy_cq,
6252 .destroy_flow = mlx5_ib_destroy_flow,
6253 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6254 .destroy_qp = mlx5_ib_destroy_qp,
6255 .destroy_srq = mlx5_ib_destroy_srq,
6256 .detach_mcast = mlx5_ib_mcg_detach,
6257 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6258 .drain_rq = mlx5_ib_drain_rq,
6259 .drain_sq = mlx5_ib_drain_sq,
6260 .fill_res_entry = mlx5_ib_fill_res_entry,
6261 .fill_stat_entry = mlx5_ib_fill_stat_entry,
6262 .get_dev_fw_str = get_dev_fw_str,
6263 .get_dma_mr = mlx5_ib_get_dma_mr,
6264 .get_link_layer = mlx5_ib_port_link_layer,
6265 .map_mr_sg = mlx5_ib_map_mr_sg,
6266 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
6267 .mmap = mlx5_ib_mmap,
6268 .modify_cq = mlx5_ib_modify_cq,
6269 .modify_device = mlx5_ib_modify_device,
6270 .modify_port = mlx5_ib_modify_port,
6271 .modify_qp = mlx5_ib_modify_qp,
6272 .modify_srq = mlx5_ib_modify_srq,
6273 .poll_cq = mlx5_ib_poll_cq,
6274 .post_recv = mlx5_ib_post_recv,
6275 .post_send = mlx5_ib_post_send,
6276 .post_srq_recv = mlx5_ib_post_srq_recv,
6277 .process_mad = mlx5_ib_process_mad,
6278 .query_ah = mlx5_ib_query_ah,
6279 .query_device = mlx5_ib_query_device,
6280 .query_gid = mlx5_ib_query_gid,
6281 .query_pkey = mlx5_ib_query_pkey,
6282 .query_qp = mlx5_ib_query_qp,
6283 .query_srq = mlx5_ib_query_srq,
6284 .read_counters = mlx5_ib_read_counters,
6285 .reg_user_mr = mlx5_ib_reg_user_mr,
6286 .req_notify_cq = mlx5_ib_arm_cq,
6287 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6288 .resize_cq = mlx5_ib_resize_cq,
6290 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
6291 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
6292 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
6293 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
6294 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
6297 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6298 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6299 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6302 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6303 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6306 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6307 .get_vf_config = mlx5_ib_get_vf_config,
6308 .get_vf_stats = mlx5_ib_get_vf_stats,
6309 .set_vf_guid = mlx5_ib_set_vf_guid,
6310 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6313 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6314 .alloc_mw = mlx5_ib_alloc_mw,
6315 .dealloc_mw = mlx5_ib_dealloc_mw,
6318 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6319 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6320 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6323 static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6324 .alloc_dm = mlx5_ib_alloc_dm,
6325 .dealloc_dm = mlx5_ib_dealloc_dm,
6326 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6329 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
6331 struct mlx5_core_dev *mdev = dev->mdev;
6334 dev->ib_dev.uverbs_cmd_mask =
6335 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6336 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6337 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6338 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6339 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
6340 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6341 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
6342 (1ull << IB_USER_VERBS_CMD_REG_MR) |
6343 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
6344 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6345 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6346 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6347 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6348 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6349 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6350 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6351 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6352 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6353 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6354 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6355 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6356 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6357 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6358 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6359 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6360 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
6361 dev->ib_dev.uverbs_ex_cmd_mask =
6362 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6363 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
6364 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
6365 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
6366 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6367 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6368 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6370 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6371 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
6372 ib_set_device_ops(&dev->ib_dev,
6373 &mlx5_ib_dev_ipoib_enhanced_ops);
6375 if (mlx5_core_is_pf(mdev))
6376 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
6378 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6380 if (MLX5_CAP_GEN(mdev, imaicl)) {
6381 dev->ib_dev.uverbs_cmd_mask |=
6382 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6383 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
6384 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
6387 if (MLX5_CAP_GEN(mdev, xrc)) {
6388 dev->ib_dev.uverbs_cmd_mask |=
6389 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6390 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
6391 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
6394 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6395 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6396 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
6397 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
6399 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
6400 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6401 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
6402 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
6404 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6405 dev->ib_dev.driver_def = mlx5_ib_defs;
6407 err = init_node_data(dev);
6411 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
6412 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6413 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
6414 mutex_init(&dev->lb.mutex);
6416 dev->ib_dev.use_cq_dim = true;
6421 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6422 .get_port_immutable = mlx5_port_immutable,
6423 .query_port = mlx5_ib_query_port,
6426 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6428 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
6432 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6433 .get_port_immutable = mlx5_port_rep_immutable,
6434 .query_port = mlx5_ib_rep_query_port,
6437 static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
6439 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
6443 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6444 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6445 .create_wq = mlx5_ib_create_wq,
6446 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6447 .destroy_wq = mlx5_ib_destroy_wq,
6448 .get_netdev = mlx5_ib_get_netdev,
6449 .modify_wq = mlx5_ib_modify_wq,
6452 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
6456 dev->ib_dev.uverbs_ex_cmd_mask |=
6457 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6458 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6459 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6460 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6461 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
6462 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
6464 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6466 /* Register only for native ports */
6467 return mlx5_add_netdev_notifier(dev, port_num);
6470 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6472 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6474 mlx5_remove_netdev_notifier(dev, port_num);
6477 static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
6479 struct mlx5_core_dev *mdev = dev->mdev;
6480 enum rdma_link_layer ll;
6484 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6485 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6487 if (ll == IB_LINK_LAYER_ETHERNET)
6488 err = mlx5_ib_stage_common_roce_init(dev);
6493 static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
6495 mlx5_ib_stage_common_roce_cleanup(dev);
6498 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6500 struct mlx5_core_dev *mdev = dev->mdev;
6501 enum rdma_link_layer ll;
6505 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6506 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6508 if (ll == IB_LINK_LAYER_ETHERNET) {
6509 err = mlx5_ib_stage_common_roce_init(dev);
6513 err = mlx5_enable_eth(dev);
6520 mlx5_ib_stage_common_roce_cleanup(dev);
6525 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6527 struct mlx5_core_dev *mdev = dev->mdev;
6528 enum rdma_link_layer ll;
6531 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6532 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6534 if (ll == IB_LINK_LAYER_ETHERNET) {
6535 mlx5_disable_eth(dev);
6536 mlx5_ib_stage_common_roce_cleanup(dev);
6540 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6542 return create_dev_resources(&dev->devr);
6545 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6547 destroy_dev_resources(&dev->devr);
6550 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6552 return mlx5_ib_odp_init_one(dev);
6555 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6557 mlx5_ib_odp_cleanup_one(dev);
6560 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6561 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6562 .get_hw_stats = mlx5_ib_get_hw_stats,
6563 .counter_bind_qp = mlx5_ib_counter_bind_qp,
6564 .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6565 .counter_dealloc = mlx5_ib_counter_dealloc,
6566 .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6567 .counter_update_stats = mlx5_ib_counter_update_stats,
6570 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6572 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6573 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
6575 return mlx5_ib_alloc_counters(dev);
6581 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6583 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6584 mlx5_ib_dealloc_counters(dev);
6587 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6589 mlx5_ib_init_cong_debugfs(dev,
6590 mlx5_core_native_port_num(dev->mdev) - 1);
6594 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6596 mlx5_ib_cleanup_cong_debugfs(dev,
6597 mlx5_core_native_port_num(dev->mdev) - 1);
6600 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6602 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6603 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6606 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6608 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6611 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6615 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6619 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6621 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6626 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6628 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6629 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6632 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6636 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
6637 if (!mlx5_lag_is_roce(dev->mdev))
6640 name = "mlx5_bond_%d";
6641 return ib_register_device(&dev->ib_dev, name);
6644 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6646 destroy_umrc_res(dev);
6649 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6651 ib_unregister_device(&dev->ib_dev);
6654 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6656 return create_umr_res(dev);
6659 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6661 init_delay_drop(dev);
6666 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6668 cancel_delay_drop(dev);
6671 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6673 dev->mdev_events.notifier_call = mlx5_ib_event;
6674 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6678 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6680 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6683 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6687 uid = mlx5_ib_devx_create(dev, false);
6689 dev->devx_whitelist_uid = uid;
6690 mlx5_ib_devx_init_event_table(dev);
6695 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6697 if (dev->devx_whitelist_uid) {
6698 mlx5_ib_devx_cleanup_event_table(dev);
6699 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6703 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6704 const struct mlx5_ib_profile *profile,
6707 /* Number of stages to cleanup */
6710 if (profile->stage[stage].cleanup)
6711 profile->stage[stage].cleanup(dev);
6715 ib_dealloc_device(&dev->ib_dev);
6718 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6719 const struct mlx5_ib_profile *profile)
6724 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6725 if (profile->stage[i].init) {
6726 err = profile->stage[i].init(dev);
6732 dev->profile = profile;
6733 dev->ib_active = true;
6738 __mlx5_ib_remove(dev, profile, i);
6743 static const struct mlx5_ib_profile pf_profile = {
6744 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6745 mlx5_ib_stage_init_init,
6746 mlx5_ib_stage_init_cleanup),
6747 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6748 mlx5_ib_stage_flow_db_init,
6749 mlx5_ib_stage_flow_db_cleanup),
6750 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6751 mlx5_ib_stage_caps_init,
6753 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6754 mlx5_ib_stage_non_default_cb,
6756 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6757 mlx5_ib_stage_roce_init,
6758 mlx5_ib_stage_roce_cleanup),
6759 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6760 mlx5_init_srq_table,
6761 mlx5_cleanup_srq_table),
6762 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6763 mlx5_ib_stage_dev_res_init,
6764 mlx5_ib_stage_dev_res_cleanup),
6765 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6766 mlx5_ib_stage_dev_notifier_init,
6767 mlx5_ib_stage_dev_notifier_cleanup),
6768 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6769 mlx5_ib_stage_odp_init,
6770 mlx5_ib_stage_odp_cleanup),
6771 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6772 mlx5_ib_stage_counters_init,
6773 mlx5_ib_stage_counters_cleanup),
6774 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6775 mlx5_ib_stage_cong_debugfs_init,
6776 mlx5_ib_stage_cong_debugfs_cleanup),
6777 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6778 mlx5_ib_stage_uar_init,
6779 mlx5_ib_stage_uar_cleanup),
6780 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6781 mlx5_ib_stage_bfrag_init,
6782 mlx5_ib_stage_bfrag_cleanup),
6783 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6785 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6786 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6787 mlx5_ib_stage_devx_init,
6788 mlx5_ib_stage_devx_cleanup),
6789 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6790 mlx5_ib_stage_ib_reg_init,
6791 mlx5_ib_stage_ib_reg_cleanup),
6792 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6793 mlx5_ib_stage_post_ib_reg_umr_init,
6795 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6796 mlx5_ib_stage_delay_drop_init,
6797 mlx5_ib_stage_delay_drop_cleanup),
6800 const struct mlx5_ib_profile uplink_rep_profile = {
6801 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6802 mlx5_ib_stage_init_init,
6803 mlx5_ib_stage_init_cleanup),
6804 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6805 mlx5_ib_stage_flow_db_init,
6806 mlx5_ib_stage_flow_db_cleanup),
6807 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6808 mlx5_ib_stage_caps_init,
6810 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6811 mlx5_ib_stage_rep_non_default_cb,
6813 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6814 mlx5_ib_stage_rep_roce_init,
6815 mlx5_ib_stage_rep_roce_cleanup),
6816 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6817 mlx5_init_srq_table,
6818 mlx5_cleanup_srq_table),
6819 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6820 mlx5_ib_stage_dev_res_init,
6821 mlx5_ib_stage_dev_res_cleanup),
6822 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6823 mlx5_ib_stage_dev_notifier_init,
6824 mlx5_ib_stage_dev_notifier_cleanup),
6825 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6826 mlx5_ib_stage_counters_init,
6827 mlx5_ib_stage_counters_cleanup),
6828 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6829 mlx5_ib_stage_uar_init,
6830 mlx5_ib_stage_uar_cleanup),
6831 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6832 mlx5_ib_stage_bfrag_init,
6833 mlx5_ib_stage_bfrag_cleanup),
6834 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6836 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6837 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6838 mlx5_ib_stage_devx_init,
6839 mlx5_ib_stage_devx_cleanup),
6840 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6841 mlx5_ib_stage_ib_reg_init,
6842 mlx5_ib_stage_ib_reg_cleanup),
6843 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6844 mlx5_ib_stage_post_ib_reg_umr_init,
6848 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6850 struct mlx5_ib_multiport_info *mpi;
6851 struct mlx5_ib_dev *dev;
6855 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6861 err = mlx5_query_nic_vport_system_image_guid(mdev,
6862 &mpi->sys_image_guid);
6868 mutex_lock(&mlx5_ib_multiport_mutex);
6869 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6870 if (dev->sys_image_guid == mpi->sys_image_guid)
6871 bound = mlx5_ib_bind_slave_port(dev, mpi);
6874 rdma_roce_rescan_device(&dev->ib_dev);
6880 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6881 dev_dbg(mdev->device,
6882 "no suitable IB device found to bind to, added to unaffiliated list.\n");
6884 mutex_unlock(&mlx5_ib_multiport_mutex);
6889 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6891 enum rdma_link_layer ll;
6892 struct mlx5_ib_dev *dev;
6896 printk_once(KERN_INFO "%s", mlx5_version);
6898 if (MLX5_ESWITCH_MANAGER(mdev) &&
6899 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
6900 if (!mlx5_core_mp_enabled(mdev))
6901 mlx5_ib_register_vport_reps(mdev);
6905 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6906 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6908 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6909 return mlx5_ib_add_slave_port(mdev);
6911 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6912 MLX5_CAP_GEN(mdev, num_vhca_ports));
6913 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
6916 dev->port = kcalloc(num_ports, sizeof(*dev->port),
6919 ib_dealloc_device(&dev->ib_dev);
6924 dev->num_ports = num_ports;
6926 return __mlx5_ib_add(dev, &pf_profile);
6929 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6931 struct mlx5_ib_multiport_info *mpi;
6932 struct mlx5_ib_dev *dev;
6934 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6935 mlx5_ib_unregister_vport_reps(mdev);
6939 if (mlx5_core_is_mp_slave(mdev)) {
6941 mutex_lock(&mlx5_ib_multiport_mutex);
6943 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6944 list_del(&mpi->list);
6945 mutex_unlock(&mlx5_ib_multiport_mutex);
6951 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6954 static struct mlx5_interface mlx5_ib_interface = {
6956 .remove = mlx5_ib_remove,
6957 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
6960 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6962 mutex_lock(&xlt_emergency_page_mutex);
6963 return xlt_emergency_page;
6966 void mlx5_ib_put_xlt_emergency_page(void)
6968 mutex_unlock(&xlt_emergency_page_mutex);
6971 static int __init mlx5_ib_init(void)
6975 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6976 if (!xlt_emergency_page)
6979 mutex_init(&xlt_emergency_page_mutex);
6981 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6982 if (!mlx5_ib_event_wq) {
6983 free_page(xlt_emergency_page);
6989 err = mlx5_register_interface(&mlx5_ib_interface);
6994 static void __exit mlx5_ib_cleanup(void)
6996 mlx5_unregister_interface(&mlx5_ib_interface);
6997 destroy_workqueue(mlx5_ib_event_wq);
6998 mutex_destroy(&xlt_emergency_page_mutex);
6999 free_page(xlt_emergency_page);
7002 module_init(mlx5_ib_init);
7003 module_exit(mlx5_ib_cleanup);