e9f0830eca1c79d3657b5ac24f500a5758506124
[sfrench/cifs-2.6.git] / drivers / infiniband / hw / mlx5 / main.c
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
41 #include <asm/pat.h>
42 #endif
43 #include <linux/sched.h>
44 #include <linux/delay.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_addr.h>
47 #include <rdma/ib_cache.h>
48 #include <linux/mlx5/port.h>
49 #include <linux/mlx5/vport.h>
50 #include <linux/list.h>
51 #include <rdma/ib_smi.h>
52 #include <rdma/ib_umem.h>
53 #include <linux/in.h>
54 #include <linux/etherdevice.h>
55 #include <linux/mlx5/fs.h>
56 #include "mlx5_ib.h"
57
58 #define DRIVER_NAME "mlx5_ib"
59 #define DRIVER_VERSION "2.2-1"
60 #define DRIVER_RELDATE  "Feb 2014"
61
62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_VERSION(DRIVER_VERSION);
66
67 static int deprecated_prof_sel = 2;
68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
70
71 static char mlx5_version[] =
72         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
74
75 enum {
76         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77 };
78
79 static enum rdma_link_layer
80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
81 {
82         switch (port_type_cap) {
83         case MLX5_CAP_PORT_TYPE_IB:
84                 return IB_LINK_LAYER_INFINIBAND;
85         case MLX5_CAP_PORT_TYPE_ETH:
86                 return IB_LINK_LAYER_ETHERNET;
87         default:
88                 return IB_LINK_LAYER_UNSPECIFIED;
89         }
90 }
91
92 static enum rdma_link_layer
93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94 {
95         struct mlx5_ib_dev *dev = to_mdev(device);
96         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99 }
100
101 static int mlx5_netdev_event(struct notifier_block *this,
102                              unsigned long event, void *ptr)
103 {
104         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
105         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
106                                                  roce.nb);
107
108         switch (event) {
109         case NETDEV_REGISTER:
110         case NETDEV_UNREGISTER:
111                 write_lock(&ibdev->roce.netdev_lock);
112                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
113                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
114                                              NULL : ndev;
115                 write_unlock(&ibdev->roce.netdev_lock);
116                 break;
117
118         case NETDEV_UP:
119         case NETDEV_DOWN: {
120                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
121                 struct net_device *upper = NULL;
122
123                 if (lag_ndev) {
124                         upper = netdev_master_upper_dev_get(lag_ndev);
125                         dev_put(lag_ndev);
126                 }
127
128                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
129                     && ibdev->ib_active) {
130                         struct ib_event ibev = { };
131
132                         ibev.device = &ibdev->ib_dev;
133                         ibev.event = (event == NETDEV_UP) ?
134                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
135                         ibev.element.port_num = 1;
136                         ib_dispatch_event(&ibev);
137                 }
138                 break;
139         }
140
141         default:
142                 break;
143         }
144
145         return NOTIFY_DONE;
146 }
147
148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
149                                              u8 port_num)
150 {
151         struct mlx5_ib_dev *ibdev = to_mdev(device);
152         struct net_device *ndev;
153
154         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
155         if (ndev)
156                 return ndev;
157
158         /* Ensure ndev does not disappear before we invoke dev_hold()
159          */
160         read_lock(&ibdev->roce.netdev_lock);
161         ndev = ibdev->roce.netdev;
162         if (ndev)
163                 dev_hold(ndev);
164         read_unlock(&ibdev->roce.netdev_lock);
165
166         return ndev;
167 }
168
169 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
170                                 struct ib_port_attr *props)
171 {
172         struct mlx5_ib_dev *dev = to_mdev(device);
173         struct net_device *ndev, *upper;
174         enum ib_mtu ndev_ib_mtu;
175         u16 qkey_viol_cntr;
176
177         memset(props, 0, sizeof(*props));
178
179         props->port_cap_flags  |= IB_PORT_CM_SUP;
180         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
181
182         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
183                                                 roce_address_table_size);
184         props->max_mtu          = IB_MTU_4096;
185         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
186         props->pkey_tbl_len     = 1;
187         props->state            = IB_PORT_DOWN;
188         props->phys_state       = 3;
189
190         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
191         props->qkey_viol_cntr = qkey_viol_cntr;
192
193         ndev = mlx5_ib_get_netdev(device, port_num);
194         if (!ndev)
195                 return 0;
196
197         if (mlx5_lag_is_active(dev->mdev)) {
198                 rcu_read_lock();
199                 upper = netdev_master_upper_dev_get_rcu(ndev);
200                 if (upper) {
201                         dev_put(ndev);
202                         ndev = upper;
203                         dev_hold(ndev);
204                 }
205                 rcu_read_unlock();
206         }
207
208         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
209                 props->state      = IB_PORT_ACTIVE;
210                 props->phys_state = 5;
211         }
212
213         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
214
215         dev_put(ndev);
216
217         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
218
219         props->active_width     = IB_WIDTH_4X;  /* TODO */
220         props->active_speed     = IB_SPEED_QDR; /* TODO */
221
222         return 0;
223 }
224
225 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
226                                      const struct ib_gid_attr *attr,
227                                      void *mlx5_addr)
228 {
229 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
230         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
231                                                source_l3_address);
232         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
233                                                source_mac_47_32);
234
235         if (!gid)
236                 return;
237
238         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
239
240         if (is_vlan_dev(attr->ndev)) {
241                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
242                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
243         }
244
245         switch (attr->gid_type) {
246         case IB_GID_TYPE_IB:
247                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
248                 break;
249         case IB_GID_TYPE_ROCE_UDP_ENCAP:
250                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
251                 break;
252
253         default:
254                 WARN_ON(true);
255         }
256
257         if (attr->gid_type != IB_GID_TYPE_IB) {
258                 if (ipv6_addr_v4mapped((void *)gid))
259                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
260                                     MLX5_ROCE_L3_TYPE_IPV4);
261                 else
262                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
263                                     MLX5_ROCE_L3_TYPE_IPV6);
264         }
265
266         if ((attr->gid_type == IB_GID_TYPE_IB) ||
267             !ipv6_addr_v4mapped((void *)gid))
268                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
269         else
270                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
271 }
272
273 static int set_roce_addr(struct ib_device *device, u8 port_num,
274                          unsigned int index,
275                          const union ib_gid *gid,
276                          const struct ib_gid_attr *attr)
277 {
278         struct mlx5_ib_dev *dev = to_mdev(device);
279         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
280         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
281         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
282         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
283
284         if (ll != IB_LINK_LAYER_ETHERNET)
285                 return -EINVAL;
286
287         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
288
289         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
290         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
291         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
292 }
293
294 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
295                            unsigned int index, const union ib_gid *gid,
296                            const struct ib_gid_attr *attr,
297                            __always_unused void **context)
298 {
299         return set_roce_addr(device, port_num, index, gid, attr);
300 }
301
302 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
303                            unsigned int index, __always_unused void **context)
304 {
305         return set_roce_addr(device, port_num, index, NULL, NULL);
306 }
307
308 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
309                                int index)
310 {
311         struct ib_gid_attr attr;
312         union ib_gid gid;
313
314         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
315                 return 0;
316
317         if (!attr.ndev)
318                 return 0;
319
320         dev_put(attr.ndev);
321
322         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
323                 return 0;
324
325         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
326 }
327
328 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
329 {
330         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
331                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
332         return 0;
333 }
334
335 enum {
336         MLX5_VPORT_ACCESS_METHOD_MAD,
337         MLX5_VPORT_ACCESS_METHOD_HCA,
338         MLX5_VPORT_ACCESS_METHOD_NIC,
339 };
340
341 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
342 {
343         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
344                 return MLX5_VPORT_ACCESS_METHOD_MAD;
345
346         if (mlx5_ib_port_link_layer(ibdev, 1) ==
347             IB_LINK_LAYER_ETHERNET)
348                 return MLX5_VPORT_ACCESS_METHOD_NIC;
349
350         return MLX5_VPORT_ACCESS_METHOD_HCA;
351 }
352
353 static void get_atomic_caps(struct mlx5_ib_dev *dev,
354                             struct ib_device_attr *props)
355 {
356         u8 tmp;
357         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
358         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
359         u8 atomic_req_8B_endianness_mode =
360                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
361
362         /* Check if HW supports 8 bytes standard atomic operations and capable
363          * of host endianness respond
364          */
365         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
366         if (((atomic_operations & tmp) == tmp) &&
367             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
368             (atomic_req_8B_endianness_mode)) {
369                 props->atomic_cap = IB_ATOMIC_HCA;
370         } else {
371                 props->atomic_cap = IB_ATOMIC_NONE;
372         }
373 }
374
375 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
376                                         __be64 *sys_image_guid)
377 {
378         struct mlx5_ib_dev *dev = to_mdev(ibdev);
379         struct mlx5_core_dev *mdev = dev->mdev;
380         u64 tmp;
381         int err;
382
383         switch (mlx5_get_vport_access_method(ibdev)) {
384         case MLX5_VPORT_ACCESS_METHOD_MAD:
385                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
386                                                             sys_image_guid);
387
388         case MLX5_VPORT_ACCESS_METHOD_HCA:
389                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
390                 break;
391
392         case MLX5_VPORT_ACCESS_METHOD_NIC:
393                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
394                 break;
395
396         default:
397                 return -EINVAL;
398         }
399
400         if (!err)
401                 *sys_image_guid = cpu_to_be64(tmp);
402
403         return err;
404
405 }
406
407 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
408                                 u16 *max_pkeys)
409 {
410         struct mlx5_ib_dev *dev = to_mdev(ibdev);
411         struct mlx5_core_dev *mdev = dev->mdev;
412
413         switch (mlx5_get_vport_access_method(ibdev)) {
414         case MLX5_VPORT_ACCESS_METHOD_MAD:
415                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
416
417         case MLX5_VPORT_ACCESS_METHOD_HCA:
418         case MLX5_VPORT_ACCESS_METHOD_NIC:
419                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
420                                                 pkey_table_size));
421                 return 0;
422
423         default:
424                 return -EINVAL;
425         }
426 }
427
428 static int mlx5_query_vendor_id(struct ib_device *ibdev,
429                                 u32 *vendor_id)
430 {
431         struct mlx5_ib_dev *dev = to_mdev(ibdev);
432
433         switch (mlx5_get_vport_access_method(ibdev)) {
434         case MLX5_VPORT_ACCESS_METHOD_MAD:
435                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
436
437         case MLX5_VPORT_ACCESS_METHOD_HCA:
438         case MLX5_VPORT_ACCESS_METHOD_NIC:
439                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
440
441         default:
442                 return -EINVAL;
443         }
444 }
445
446 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
447                                 __be64 *node_guid)
448 {
449         u64 tmp;
450         int err;
451
452         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
453         case MLX5_VPORT_ACCESS_METHOD_MAD:
454                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
455
456         case MLX5_VPORT_ACCESS_METHOD_HCA:
457                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
458                 break;
459
460         case MLX5_VPORT_ACCESS_METHOD_NIC:
461                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
462                 break;
463
464         default:
465                 return -EINVAL;
466         }
467
468         if (!err)
469                 *node_guid = cpu_to_be64(tmp);
470
471         return err;
472 }
473
474 struct mlx5_reg_node_desc {
475         u8      desc[IB_DEVICE_NODE_DESC_MAX];
476 };
477
478 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
479 {
480         struct mlx5_reg_node_desc in;
481
482         if (mlx5_use_mad_ifc(dev))
483                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
484
485         memset(&in, 0, sizeof(in));
486
487         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
488                                     sizeof(struct mlx5_reg_node_desc),
489                                     MLX5_REG_NODE_DESC, 0, 0);
490 }
491
492 static int mlx5_ib_query_device(struct ib_device *ibdev,
493                                 struct ib_device_attr *props,
494                                 struct ib_udata *uhw)
495 {
496         struct mlx5_ib_dev *dev = to_mdev(ibdev);
497         struct mlx5_core_dev *mdev = dev->mdev;
498         int err = -ENOMEM;
499         int max_sq_desc;
500         int max_rq_sg;
501         int max_sq_sg;
502         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
503         struct mlx5_ib_query_device_resp resp = {};
504         size_t resp_len;
505         u64 max_tso;
506
507         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
508         if (uhw->outlen && uhw->outlen < resp_len)
509                 return -EINVAL;
510         else
511                 resp.response_length = resp_len;
512
513         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
514                 return -EINVAL;
515
516         memset(props, 0, sizeof(*props));
517         err = mlx5_query_system_image_guid(ibdev,
518                                            &props->sys_image_guid);
519         if (err)
520                 return err;
521
522         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
523         if (err)
524                 return err;
525
526         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
527         if (err)
528                 return err;
529
530         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
531                 (fw_rev_min(dev->mdev) << 16) |
532                 fw_rev_sub(dev->mdev);
533         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
534                 IB_DEVICE_PORT_ACTIVE_EVENT             |
535                 IB_DEVICE_SYS_IMAGE_GUID                |
536                 IB_DEVICE_RC_RNR_NAK_GEN;
537
538         if (MLX5_CAP_GEN(mdev, pkv))
539                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
540         if (MLX5_CAP_GEN(mdev, qkv))
541                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
542         if (MLX5_CAP_GEN(mdev, apm))
543                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
544         if (MLX5_CAP_GEN(mdev, xrc))
545                 props->device_cap_flags |= IB_DEVICE_XRC;
546         if (MLX5_CAP_GEN(mdev, imaicl)) {
547                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
548                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
549                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
550                 /* We support 'Gappy' memory registration too */
551                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
552         }
553         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
554         if (MLX5_CAP_GEN(mdev, sho)) {
555                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
556                 /* At this stage no support for signature handover */
557                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
558                                       IB_PROT_T10DIF_TYPE_2 |
559                                       IB_PROT_T10DIF_TYPE_3;
560                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
561                                        IB_GUARD_T10DIF_CSUM;
562         }
563         if (MLX5_CAP_GEN(mdev, block_lb_mc))
564                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
565
566         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
567                 if (MLX5_CAP_ETH(mdev, csum_cap))
568                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
569
570                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
571                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
572                         if (max_tso) {
573                                 resp.tso_caps.max_tso = 1 << max_tso;
574                                 resp.tso_caps.supported_qpts |=
575                                         1 << IB_QPT_RAW_PACKET;
576                                 resp.response_length += sizeof(resp.tso_caps);
577                         }
578                 }
579
580                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
581                         resp.rss_caps.rx_hash_function =
582                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
583                         resp.rss_caps.rx_hash_fields_mask =
584                                                 MLX5_RX_HASH_SRC_IPV4 |
585                                                 MLX5_RX_HASH_DST_IPV4 |
586                                                 MLX5_RX_HASH_SRC_IPV6 |
587                                                 MLX5_RX_HASH_DST_IPV6 |
588                                                 MLX5_RX_HASH_SRC_PORT_TCP |
589                                                 MLX5_RX_HASH_DST_PORT_TCP |
590                                                 MLX5_RX_HASH_SRC_PORT_UDP |
591                                                 MLX5_RX_HASH_DST_PORT_UDP;
592                         resp.response_length += sizeof(resp.rss_caps);
593                 }
594         } else {
595                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
596                         resp.response_length += sizeof(resp.tso_caps);
597                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
598                         resp.response_length += sizeof(resp.rss_caps);
599         }
600
601         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
602                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
603                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
604         }
605
606         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
607             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
608                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
609
610         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
611                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
612
613         props->vendor_part_id      = mdev->pdev->device;
614         props->hw_ver              = mdev->pdev->revision;
615
616         props->max_mr_size         = ~0ull;
617         props->page_size_cap       = ~(min_page_size - 1);
618         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
619         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
620         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
621                      sizeof(struct mlx5_wqe_data_seg);
622         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
623         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
624                      sizeof(struct mlx5_wqe_raddr_seg)) /
625                 sizeof(struct mlx5_wqe_data_seg);
626         props->max_sge = min(max_rq_sg, max_sq_sg);
627         props->max_sge_rd          = MLX5_MAX_SGE_RD;
628         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
629         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
630         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
631         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
632         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
633         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
634         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
635         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
636         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
637         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
638         props->max_srq_sge         = max_rq_sg - 1;
639         props->max_fast_reg_page_list_len =
640                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
641         get_atomic_caps(dev, props);
642         props->masked_atomic_cap   = IB_ATOMIC_NONE;
643         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
644         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
645         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
646                                            props->max_mcast_grp;
647         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
648         props->max_ah = INT_MAX;
649         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
650         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
651
652 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
653         if (MLX5_CAP_GEN(mdev, pg))
654                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
655         props->odp_caps = dev->odp_caps;
656 #endif
657
658         if (MLX5_CAP_GEN(mdev, cd))
659                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
660
661         if (!mlx5_core_is_pf(mdev))
662                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
663
664         if (mlx5_ib_port_link_layer(ibdev, 1) ==
665             IB_LINK_LAYER_ETHERNET) {
666                 props->rss_caps.max_rwq_indirection_tables =
667                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
668                 props->rss_caps.max_rwq_indirection_table_size =
669                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
670                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
671                 props->max_wq_type_rq =
672                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
673         }
674
675         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
676                 resp.cqe_comp_caps.max_num =
677                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
678                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
679                 resp.cqe_comp_caps.supported_format =
680                         MLX5_IB_CQE_RES_FORMAT_HASH |
681                         MLX5_IB_CQE_RES_FORMAT_CSUM;
682                 resp.response_length += sizeof(resp.cqe_comp_caps);
683         }
684
685         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
686                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
687                     MLX5_CAP_GEN(mdev, qos)) {
688                         resp.packet_pacing_caps.qp_rate_limit_max =
689                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
690                         resp.packet_pacing_caps.qp_rate_limit_min =
691                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
692                         resp.packet_pacing_caps.supported_qpts |=
693                                 1 << IB_QPT_RAW_PACKET;
694                 }
695                 resp.response_length += sizeof(resp.packet_pacing_caps);
696         }
697
698         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
699                         uhw->outlen)) {
700                 resp.mlx5_ib_support_multi_pkt_send_wqes =
701                         MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
702                 resp.response_length +=
703                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
704         }
705
706         if (field_avail(typeof(resp), reserved, uhw->outlen))
707                 resp.response_length += sizeof(resp.reserved);
708
709         if (uhw->outlen) {
710                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
711
712                 if (err)
713                         return err;
714         }
715
716         return 0;
717 }
718
719 enum mlx5_ib_width {
720         MLX5_IB_WIDTH_1X        = 1 << 0,
721         MLX5_IB_WIDTH_2X        = 1 << 1,
722         MLX5_IB_WIDTH_4X        = 1 << 2,
723         MLX5_IB_WIDTH_8X        = 1 << 3,
724         MLX5_IB_WIDTH_12X       = 1 << 4
725 };
726
727 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
728                                   u8 *ib_width)
729 {
730         struct mlx5_ib_dev *dev = to_mdev(ibdev);
731         int err = 0;
732
733         if (active_width & MLX5_IB_WIDTH_1X) {
734                 *ib_width = IB_WIDTH_1X;
735         } else if (active_width & MLX5_IB_WIDTH_2X) {
736                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
737                             (int)active_width);
738                 err = -EINVAL;
739         } else if (active_width & MLX5_IB_WIDTH_4X) {
740                 *ib_width = IB_WIDTH_4X;
741         } else if (active_width & MLX5_IB_WIDTH_8X) {
742                 *ib_width = IB_WIDTH_8X;
743         } else if (active_width & MLX5_IB_WIDTH_12X) {
744                 *ib_width = IB_WIDTH_12X;
745         } else {
746                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
747                             (int)active_width);
748                 err = -EINVAL;
749         }
750
751         return err;
752 }
753
754 static int mlx5_mtu_to_ib_mtu(int mtu)
755 {
756         switch (mtu) {
757         case 256: return 1;
758         case 512: return 2;
759         case 1024: return 3;
760         case 2048: return 4;
761         case 4096: return 5;
762         default:
763                 pr_warn("invalid mtu\n");
764                 return -1;
765         }
766 }
767
768 enum ib_max_vl_num {
769         __IB_MAX_VL_0           = 1,
770         __IB_MAX_VL_0_1         = 2,
771         __IB_MAX_VL_0_3         = 3,
772         __IB_MAX_VL_0_7         = 4,
773         __IB_MAX_VL_0_14        = 5,
774 };
775
776 enum mlx5_vl_hw_cap {
777         MLX5_VL_HW_0    = 1,
778         MLX5_VL_HW_0_1  = 2,
779         MLX5_VL_HW_0_2  = 3,
780         MLX5_VL_HW_0_3  = 4,
781         MLX5_VL_HW_0_4  = 5,
782         MLX5_VL_HW_0_5  = 6,
783         MLX5_VL_HW_0_6  = 7,
784         MLX5_VL_HW_0_7  = 8,
785         MLX5_VL_HW_0_14 = 15
786 };
787
788 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
789                                 u8 *max_vl_num)
790 {
791         switch (vl_hw_cap) {
792         case MLX5_VL_HW_0:
793                 *max_vl_num = __IB_MAX_VL_0;
794                 break;
795         case MLX5_VL_HW_0_1:
796                 *max_vl_num = __IB_MAX_VL_0_1;
797                 break;
798         case MLX5_VL_HW_0_3:
799                 *max_vl_num = __IB_MAX_VL_0_3;
800                 break;
801         case MLX5_VL_HW_0_7:
802                 *max_vl_num = __IB_MAX_VL_0_7;
803                 break;
804         case MLX5_VL_HW_0_14:
805                 *max_vl_num = __IB_MAX_VL_0_14;
806                 break;
807
808         default:
809                 return -EINVAL;
810         }
811
812         return 0;
813 }
814
815 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
816                                struct ib_port_attr *props)
817 {
818         struct mlx5_ib_dev *dev = to_mdev(ibdev);
819         struct mlx5_core_dev *mdev = dev->mdev;
820         struct mlx5_hca_vport_context *rep;
821         u16 max_mtu;
822         u16 oper_mtu;
823         int err;
824         u8 ib_link_width_oper;
825         u8 vl_hw_cap;
826
827         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
828         if (!rep) {
829                 err = -ENOMEM;
830                 goto out;
831         }
832
833         memset(props, 0, sizeof(*props));
834
835         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
836         if (err)
837                 goto out;
838
839         props->lid              = rep->lid;
840         props->lmc              = rep->lmc;
841         props->sm_lid           = rep->sm_lid;
842         props->sm_sl            = rep->sm_sl;
843         props->state            = rep->vport_state;
844         props->phys_state       = rep->port_physical_state;
845         props->port_cap_flags   = rep->cap_mask1;
846         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
847         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
848         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
849         props->bad_pkey_cntr    = rep->pkey_violation_counter;
850         props->qkey_viol_cntr   = rep->qkey_violation_counter;
851         props->subnet_timeout   = rep->subnet_timeout;
852         props->init_type_reply  = rep->init_type_reply;
853         props->grh_required     = rep->grh_required;
854
855         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
856         if (err)
857                 goto out;
858
859         err = translate_active_width(ibdev, ib_link_width_oper,
860                                      &props->active_width);
861         if (err)
862                 goto out;
863         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
864         if (err)
865                 goto out;
866
867         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
868
869         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
870
871         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
872
873         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
874
875         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
876         if (err)
877                 goto out;
878
879         err = translate_max_vl_num(ibdev, vl_hw_cap,
880                                    &props->max_vl_num);
881 out:
882         kfree(rep);
883         return err;
884 }
885
886 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
887                        struct ib_port_attr *props)
888 {
889         switch (mlx5_get_vport_access_method(ibdev)) {
890         case MLX5_VPORT_ACCESS_METHOD_MAD:
891                 return mlx5_query_mad_ifc_port(ibdev, port, props);
892
893         case MLX5_VPORT_ACCESS_METHOD_HCA:
894                 return mlx5_query_hca_port(ibdev, port, props);
895
896         case MLX5_VPORT_ACCESS_METHOD_NIC:
897                 return mlx5_query_port_roce(ibdev, port, props);
898
899         default:
900                 return -EINVAL;
901         }
902 }
903
904 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
905                              union ib_gid *gid)
906 {
907         struct mlx5_ib_dev *dev = to_mdev(ibdev);
908         struct mlx5_core_dev *mdev = dev->mdev;
909
910         switch (mlx5_get_vport_access_method(ibdev)) {
911         case MLX5_VPORT_ACCESS_METHOD_MAD:
912                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
913
914         case MLX5_VPORT_ACCESS_METHOD_HCA:
915                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
916
917         default:
918                 return -EINVAL;
919         }
920
921 }
922
923 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
924                               u16 *pkey)
925 {
926         struct mlx5_ib_dev *dev = to_mdev(ibdev);
927         struct mlx5_core_dev *mdev = dev->mdev;
928
929         switch (mlx5_get_vport_access_method(ibdev)) {
930         case MLX5_VPORT_ACCESS_METHOD_MAD:
931                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
932
933         case MLX5_VPORT_ACCESS_METHOD_HCA:
934         case MLX5_VPORT_ACCESS_METHOD_NIC:
935                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
936                                                  pkey);
937         default:
938                 return -EINVAL;
939         }
940 }
941
942 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
943                                  struct ib_device_modify *props)
944 {
945         struct mlx5_ib_dev *dev = to_mdev(ibdev);
946         struct mlx5_reg_node_desc in;
947         struct mlx5_reg_node_desc out;
948         int err;
949
950         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
951                 return -EOPNOTSUPP;
952
953         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
954                 return 0;
955
956         /*
957          * If possible, pass node desc to FW, so it can generate
958          * a 144 trap.  If cmd fails, just ignore.
959          */
960         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
961         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
962                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
963         if (err)
964                 return err;
965
966         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
967
968         return err;
969 }
970
971 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
972                                struct ib_port_modify *props)
973 {
974         struct mlx5_ib_dev *dev = to_mdev(ibdev);
975         struct ib_port_attr attr;
976         u32 tmp;
977         int err;
978
979         mutex_lock(&dev->cap_mask_mutex);
980
981         err = mlx5_ib_query_port(ibdev, port, &attr);
982         if (err)
983                 goto out;
984
985         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
986                 ~props->clr_port_cap_mask;
987
988         err = mlx5_set_port_caps(dev->mdev, port, tmp);
989
990 out:
991         mutex_unlock(&dev->cap_mask_mutex);
992         return err;
993 }
994
995 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
996                                                   struct ib_udata *udata)
997 {
998         struct mlx5_ib_dev *dev = to_mdev(ibdev);
999         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1000         struct mlx5_ib_alloc_ucontext_resp resp = {};
1001         struct mlx5_ib_ucontext *context;
1002         struct mlx5_bfreg_info *bfregi;
1003         struct mlx5_uar *uars;
1004         int gross_bfregs;
1005         int num_uars;
1006         int ver;
1007         int bfregn;
1008         int err;
1009         int i;
1010         size_t reqlen;
1011         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1012                                      max_cqe_version);
1013
1014         if (!dev->ib_active)
1015                 return ERR_PTR(-EAGAIN);
1016
1017         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1018                 return ERR_PTR(-EINVAL);
1019
1020         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1021         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1022                 ver = 0;
1023         else if (reqlen >= min_req_v2)
1024                 ver = 2;
1025         else
1026                 return ERR_PTR(-EINVAL);
1027
1028         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1029         if (err)
1030                 return ERR_PTR(err);
1031
1032         if (req.flags)
1033                 return ERR_PTR(-EINVAL);
1034
1035         if (req.total_num_bfregs > MLX5_MAX_BFREGS)
1036                 return ERR_PTR(-ENOMEM);
1037
1038         if (req.total_num_bfregs == 0)
1039                 return ERR_PTR(-EINVAL);
1040
1041         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1042                 return ERR_PTR(-EOPNOTSUPP);
1043
1044         if (reqlen > sizeof(req) &&
1045             !ib_is_udata_cleared(udata, sizeof(req),
1046                                  reqlen - sizeof(req)))
1047                 return ERR_PTR(-EOPNOTSUPP);
1048
1049         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1050                                     MLX5_NON_FP_BFREGS_PER_UAR);
1051         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1052                 return ERR_PTR(-EINVAL);
1053
1054         num_uars = req.total_num_bfregs / MLX5_NON_FP_BFREGS_PER_UAR;
1055         gross_bfregs = num_uars * MLX5_BFREGS_PER_UAR;
1056         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1057         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1058                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1059         resp.cache_line_size = cache_line_size();
1060         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1061         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1062         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1063         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1064         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1065         resp.cqe_version = min_t(__u8,
1066                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1067                                  req.max_cqe_version);
1068         resp.response_length = min(offsetof(typeof(resp), response_length) +
1069                                    sizeof(resp.response_length), udata->outlen);
1070
1071         context = kzalloc(sizeof(*context), GFP_KERNEL);
1072         if (!context)
1073                 return ERR_PTR(-ENOMEM);
1074
1075         bfregi = &context->bfregi;
1076         mutex_init(&bfregi->lock);
1077         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1078         if (!uars) {
1079                 err = -ENOMEM;
1080                 goto out_ctx;
1081         }
1082
1083         bfregi->bitmap = kcalloc(BITS_TO_LONGS(gross_bfregs),
1084                                 sizeof(*bfregi->bitmap),
1085                                 GFP_KERNEL);
1086         if (!bfregi->bitmap) {
1087                 err = -ENOMEM;
1088                 goto out_uar_ctx;
1089         }
1090         /*
1091          * clear all fast path bfregs
1092          */
1093         for (i = 0; i < gross_bfregs; i++) {
1094                 bfregn = i & 3;
1095                 if (bfregn == 2 || bfregn == 3)
1096                         set_bit(i, bfregi->bitmap);
1097         }
1098
1099         bfregi->count = kcalloc(gross_bfregs,
1100                                 sizeof(*bfregi->count), GFP_KERNEL);
1101         if (!bfregi->count) {
1102                 err = -ENOMEM;
1103                 goto out_bitmap;
1104         }
1105
1106         for (i = 0; i < num_uars; i++) {
1107                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1108                 if (err)
1109                         goto out_count;
1110         }
1111
1112 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1113         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1114 #endif
1115
1116         context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1117         if (!context->upd_xlt_page) {
1118                 err = -ENOMEM;
1119                 goto out_uars;
1120         }
1121         mutex_init(&context->upd_xlt_page_mutex);
1122
1123         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1124                 err = mlx5_core_alloc_transport_domain(dev->mdev,
1125                                                        &context->tdn);
1126                 if (err)
1127                         goto out_page;
1128         }
1129
1130         INIT_LIST_HEAD(&context->vma_private_list);
1131         INIT_LIST_HEAD(&context->db_page_list);
1132         mutex_init(&context->db_page_mutex);
1133
1134         resp.tot_bfregs = req.total_num_bfregs;
1135         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1136
1137         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1138                 resp.response_length += sizeof(resp.cqe_version);
1139
1140         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1141                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1142                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1143                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1144         }
1145
1146         /*
1147          * We don't want to expose information from the PCI bar that is located
1148          * after 4096 bytes, so if the arch only supports larger pages, let's
1149          * pretend we don't support reading the HCA's core clock. This is also
1150          * forced by mmap function.
1151          */
1152         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1153                 if (PAGE_SIZE <= 4096) {
1154                         resp.comp_mask |=
1155                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1156                         resp.hca_core_clock_offset =
1157                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1158                 }
1159                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1160                                         sizeof(resp.reserved2);
1161         }
1162
1163         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1164         if (err)
1165                 goto out_td;
1166
1167         bfregi->ver = ver;
1168         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1169         bfregi->uars = uars;
1170         bfregi->num_uars = num_uars;
1171         context->cqe_version = resp.cqe_version;
1172
1173         return &context->ibucontext;
1174
1175 out_td:
1176         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1177                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1178
1179 out_page:
1180         free_page(context->upd_xlt_page);
1181
1182 out_uars:
1183         for (i--; i >= 0; i--)
1184                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1185 out_count:
1186         kfree(bfregi->count);
1187
1188 out_bitmap:
1189         kfree(bfregi->bitmap);
1190
1191 out_uar_ctx:
1192         kfree(uars);
1193
1194 out_ctx:
1195         kfree(context);
1196         return ERR_PTR(err);
1197 }
1198
1199 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1200 {
1201         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1202         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1203         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1204         int i;
1205
1206         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1207                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1208
1209         free_page(context->upd_xlt_page);
1210
1211         for (i = 0; i < bfregi->num_uars; i++) {
1212                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->uars[i].index))
1213                         mlx5_ib_warn(dev, "Failed to free UAR 0x%x\n",
1214                                      bfregi->uars[i].index);
1215         }
1216
1217         kfree(bfregi->count);
1218         kfree(bfregi->bitmap);
1219         kfree(bfregi->uars);
1220         kfree(context);
1221
1222         return 0;
1223 }
1224
1225 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1226 {
1227         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1228 }
1229
1230 static int get_command(unsigned long offset)
1231 {
1232         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1233 }
1234
1235 static int get_arg(unsigned long offset)
1236 {
1237         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1238 }
1239
1240 static int get_index(unsigned long offset)
1241 {
1242         return get_arg(offset);
1243 }
1244
1245 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1246 {
1247         /* vma_open is called when a new VMA is created on top of our VMA.  This
1248          * is done through either mremap flow or split_vma (usually due to
1249          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1250          * as this VMA is strongly hardware related.  Therefore we set the
1251          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1252          * calling us again and trying to do incorrect actions.  We assume that
1253          * the original VMA size is exactly a single page, and therefore all
1254          * "splitting" operation will not happen to it.
1255          */
1256         area->vm_ops = NULL;
1257 }
1258
1259 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1260 {
1261         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1262
1263         /* It's guaranteed that all VMAs opened on a FD are closed before the
1264          * file itself is closed, therefore no sync is needed with the regular
1265          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1266          * However need a sync with accessing the vma as part of
1267          * mlx5_ib_disassociate_ucontext.
1268          * The close operation is usually called under mm->mmap_sem except when
1269          * process is exiting.
1270          * The exiting case is handled explicitly as part of
1271          * mlx5_ib_disassociate_ucontext.
1272          */
1273         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1274
1275         /* setting the vma context pointer to null in the mlx5_ib driver's
1276          * private data, to protect a race condition in
1277          * mlx5_ib_disassociate_ucontext().
1278          */
1279         mlx5_ib_vma_priv_data->vma = NULL;
1280         list_del(&mlx5_ib_vma_priv_data->list);
1281         kfree(mlx5_ib_vma_priv_data);
1282 }
1283
1284 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1285         .open = mlx5_ib_vma_open,
1286         .close = mlx5_ib_vma_close
1287 };
1288
1289 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1290                                 struct mlx5_ib_ucontext *ctx)
1291 {
1292         struct mlx5_ib_vma_private_data *vma_prv;
1293         struct list_head *vma_head = &ctx->vma_private_list;
1294
1295         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1296         if (!vma_prv)
1297                 return -ENOMEM;
1298
1299         vma_prv->vma = vma;
1300         vma->vm_private_data = vma_prv;
1301         vma->vm_ops =  &mlx5_ib_vm_ops;
1302
1303         list_add(&vma_prv->list, vma_head);
1304
1305         return 0;
1306 }
1307
1308 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1309 {
1310         int ret;
1311         struct vm_area_struct *vma;
1312         struct mlx5_ib_vma_private_data *vma_private, *n;
1313         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1314         struct task_struct *owning_process  = NULL;
1315         struct mm_struct   *owning_mm       = NULL;
1316
1317         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1318         if (!owning_process)
1319                 return;
1320
1321         owning_mm = get_task_mm(owning_process);
1322         if (!owning_mm) {
1323                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1324                 while (1) {
1325                         put_task_struct(owning_process);
1326                         usleep_range(1000, 2000);
1327                         owning_process = get_pid_task(ibcontext->tgid,
1328                                                       PIDTYPE_PID);
1329                         if (!owning_process ||
1330                             owning_process->state == TASK_DEAD) {
1331                                 pr_info("disassociate ucontext done, task was terminated\n");
1332                                 /* in case task was dead need to release the
1333                                  * task struct.
1334                                  */
1335                                 if (owning_process)
1336                                         put_task_struct(owning_process);
1337                                 return;
1338                         }
1339                 }
1340         }
1341
1342         /* need to protect from a race on closing the vma as part of
1343          * mlx5_ib_vma_close.
1344          */
1345         down_read(&owning_mm->mmap_sem);
1346         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1347                                  list) {
1348                 vma = vma_private->vma;
1349                 ret = zap_vma_ptes(vma, vma->vm_start,
1350                                    PAGE_SIZE);
1351                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1352                 /* context going to be destroyed, should
1353                  * not access ops any more.
1354                  */
1355                 vma->vm_ops = NULL;
1356                 list_del(&vma_private->list);
1357                 kfree(vma_private);
1358         }
1359         up_read(&owning_mm->mmap_sem);
1360         mmput(owning_mm);
1361         put_task_struct(owning_process);
1362 }
1363
1364 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1365 {
1366         switch (cmd) {
1367         case MLX5_IB_MMAP_WC_PAGE:
1368                 return "WC";
1369         case MLX5_IB_MMAP_REGULAR_PAGE:
1370                 return "best effort WC";
1371         case MLX5_IB_MMAP_NC_PAGE:
1372                 return "NC";
1373         default:
1374                 return NULL;
1375         }
1376 }
1377
1378 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1379                     struct vm_area_struct *vma,
1380                     struct mlx5_ib_ucontext *context)
1381 {
1382         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1383         int err;
1384         unsigned long idx;
1385         phys_addr_t pfn, pa;
1386         pgprot_t prot;
1387
1388         switch (cmd) {
1389         case MLX5_IB_MMAP_WC_PAGE:
1390 /* Some architectures don't support WC memory */
1391 #if defined(CONFIG_X86)
1392                 if (!pat_enabled())
1393                         return -EPERM;
1394 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1395                         return -EPERM;
1396 #endif
1397         /* fall through */
1398         case MLX5_IB_MMAP_REGULAR_PAGE:
1399                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1400                 prot = pgprot_writecombine(vma->vm_page_prot);
1401                 break;
1402         case MLX5_IB_MMAP_NC_PAGE:
1403                 prot = pgprot_noncached(vma->vm_page_prot);
1404                 break;
1405         default:
1406                 return -EINVAL;
1407         }
1408
1409         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1410                 return -EINVAL;
1411
1412         idx = get_index(vma->vm_pgoff);
1413         if (idx >= bfregi->num_uars)
1414                 return -EINVAL;
1415
1416         pfn = uar_index2pfn(dev, bfregi->uars[idx].index);
1417         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1418
1419         vma->vm_page_prot = prot;
1420         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1421                                  PAGE_SIZE, vma->vm_page_prot);
1422         if (err) {
1423                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1424                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1425                 return -EAGAIN;
1426         }
1427
1428         pa = pfn << PAGE_SHIFT;
1429         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1430                     vma->vm_start, &pa);
1431
1432         return mlx5_ib_set_vma_data(vma, context);
1433 }
1434
1435 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1436 {
1437         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1438         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1439         unsigned long command;
1440         phys_addr_t pfn;
1441
1442         command = get_command(vma->vm_pgoff);
1443         switch (command) {
1444         case MLX5_IB_MMAP_WC_PAGE:
1445         case MLX5_IB_MMAP_NC_PAGE:
1446         case MLX5_IB_MMAP_REGULAR_PAGE:
1447                 return uar_mmap(dev, command, vma, context);
1448
1449         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1450                 return -ENOSYS;
1451
1452         case MLX5_IB_MMAP_CORE_CLOCK:
1453                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1454                         return -EINVAL;
1455
1456                 if (vma->vm_flags & VM_WRITE)
1457                         return -EPERM;
1458
1459                 /* Don't expose to user-space information it shouldn't have */
1460                 if (PAGE_SIZE > 4096)
1461                         return -EOPNOTSUPP;
1462
1463                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1464                 pfn = (dev->mdev->iseg_base +
1465                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1466                         PAGE_SHIFT;
1467                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1468                                        PAGE_SIZE, vma->vm_page_prot))
1469                         return -EAGAIN;
1470
1471                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1472                             vma->vm_start,
1473                             (unsigned long long)pfn << PAGE_SHIFT);
1474                 break;
1475
1476         default:
1477                 return -EINVAL;
1478         }
1479
1480         return 0;
1481 }
1482
1483 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1484                                       struct ib_ucontext *context,
1485                                       struct ib_udata *udata)
1486 {
1487         struct mlx5_ib_alloc_pd_resp resp;
1488         struct mlx5_ib_pd *pd;
1489         int err;
1490
1491         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1492         if (!pd)
1493                 return ERR_PTR(-ENOMEM);
1494
1495         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1496         if (err) {
1497                 kfree(pd);
1498                 return ERR_PTR(err);
1499         }
1500
1501         if (context) {
1502                 resp.pdn = pd->pdn;
1503                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1504                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1505                         kfree(pd);
1506                         return ERR_PTR(-EFAULT);
1507                 }
1508         }
1509
1510         return &pd->ibpd;
1511 }
1512
1513 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1514 {
1515         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1516         struct mlx5_ib_pd *mpd = to_mpd(pd);
1517
1518         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1519         kfree(mpd);
1520
1521         return 0;
1522 }
1523
1524 enum {
1525         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1526         MATCH_CRITERIA_ENABLE_MISC_BIT,
1527         MATCH_CRITERIA_ENABLE_INNER_BIT
1528 };
1529
1530 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1531         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1532                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1533
1534 static u8 get_match_criteria_enable(u32 *match_criteria)
1535 {
1536         u8 match_criteria_enable;
1537
1538         match_criteria_enable =
1539                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1540                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1541         match_criteria_enable |=
1542                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1543                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1544         match_criteria_enable |=
1545                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1546                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1547
1548         return match_criteria_enable;
1549 }
1550
1551 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1552 {
1553         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1554         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1555 }
1556
1557 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1558                            bool inner)
1559 {
1560         if (inner) {
1561                 MLX5_SET(fte_match_set_misc,
1562                          misc_c, inner_ipv6_flow_label, mask);
1563                 MLX5_SET(fte_match_set_misc,
1564                          misc_v, inner_ipv6_flow_label, val);
1565         } else {
1566                 MLX5_SET(fte_match_set_misc,
1567                          misc_c, outer_ipv6_flow_label, mask);
1568                 MLX5_SET(fte_match_set_misc,
1569                          misc_v, outer_ipv6_flow_label, val);
1570         }
1571 }
1572
1573 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1574 {
1575         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1576         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1577         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1578         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1579 }
1580
1581 #define LAST_ETH_FIELD vlan_tag
1582 #define LAST_IB_FIELD sl
1583 #define LAST_IPV4_FIELD tos
1584 #define LAST_IPV6_FIELD traffic_class
1585 #define LAST_TCP_UDP_FIELD src_port
1586 #define LAST_TUNNEL_FIELD tunnel_id
1587
1588 /* Field is the last supported field */
1589 #define FIELDS_NOT_SUPPORTED(filter, field)\
1590         memchr_inv((void *)&filter.field  +\
1591                    sizeof(filter.field), 0,\
1592                    sizeof(filter) -\
1593                    offsetof(typeof(filter), field) -\
1594                    sizeof(filter.field))
1595
1596 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1597                            const union ib_flow_spec *ib_spec)
1598 {
1599         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1600                                            misc_parameters);
1601         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1602                                            misc_parameters);
1603         void *headers_c;
1604         void *headers_v;
1605
1606         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1607                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1608                                          inner_headers);
1609                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1610                                          inner_headers);
1611         } else {
1612                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1613                                          outer_headers);
1614                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1615                                          outer_headers);
1616         }
1617
1618         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1619         case IB_FLOW_SPEC_ETH:
1620                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1621                         return -ENOTSUPP;
1622
1623                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1624                                              dmac_47_16),
1625                                 ib_spec->eth.mask.dst_mac);
1626                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1627                                              dmac_47_16),
1628                                 ib_spec->eth.val.dst_mac);
1629
1630                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1631                                              smac_47_16),
1632                                 ib_spec->eth.mask.src_mac);
1633                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1634                                              smac_47_16),
1635                                 ib_spec->eth.val.src_mac);
1636
1637                 if (ib_spec->eth.mask.vlan_tag) {
1638                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1639                                  vlan_tag, 1);
1640                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1641                                  vlan_tag, 1);
1642
1643                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1644                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1645                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1646                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1647
1648                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1649                                  first_cfi,
1650                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1651                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1652                                  first_cfi,
1653                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1654
1655                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1656                                  first_prio,
1657                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1658                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1659                                  first_prio,
1660                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1661                 }
1662                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1663                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1664                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1665                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1666                 break;
1667         case IB_FLOW_SPEC_IPV4:
1668                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1669                         return -ENOTSUPP;
1670
1671                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1672                          ethertype, 0xffff);
1673                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1674                          ethertype, ETH_P_IP);
1675
1676                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1677                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1678                        &ib_spec->ipv4.mask.src_ip,
1679                        sizeof(ib_spec->ipv4.mask.src_ip));
1680                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1681                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1682                        &ib_spec->ipv4.val.src_ip,
1683                        sizeof(ib_spec->ipv4.val.src_ip));
1684                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1685                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1686                        &ib_spec->ipv4.mask.dst_ip,
1687                        sizeof(ib_spec->ipv4.mask.dst_ip));
1688                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1689                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1690                        &ib_spec->ipv4.val.dst_ip,
1691                        sizeof(ib_spec->ipv4.val.dst_ip));
1692
1693                 set_tos(headers_c, headers_v,
1694                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1695
1696                 set_proto(headers_c, headers_v,
1697                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1698                 break;
1699         case IB_FLOW_SPEC_IPV6:
1700                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1701                         return -ENOTSUPP;
1702
1703                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1704                          ethertype, 0xffff);
1705                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1706                          ethertype, ETH_P_IPV6);
1707
1708                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1709                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1710                        &ib_spec->ipv6.mask.src_ip,
1711                        sizeof(ib_spec->ipv6.mask.src_ip));
1712                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1713                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1714                        &ib_spec->ipv6.val.src_ip,
1715                        sizeof(ib_spec->ipv6.val.src_ip));
1716                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1717                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1718                        &ib_spec->ipv6.mask.dst_ip,
1719                        sizeof(ib_spec->ipv6.mask.dst_ip));
1720                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1721                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1722                        &ib_spec->ipv6.val.dst_ip,
1723                        sizeof(ib_spec->ipv6.val.dst_ip));
1724
1725                 set_tos(headers_c, headers_v,
1726                         ib_spec->ipv6.mask.traffic_class,
1727                         ib_spec->ipv6.val.traffic_class);
1728
1729                 set_proto(headers_c, headers_v,
1730                           ib_spec->ipv6.mask.next_hdr,
1731                           ib_spec->ipv6.val.next_hdr);
1732
1733                 set_flow_label(misc_params_c, misc_params_v,
1734                                ntohl(ib_spec->ipv6.mask.flow_label),
1735                                ntohl(ib_spec->ipv6.val.flow_label),
1736                                ib_spec->type & IB_FLOW_SPEC_INNER);
1737
1738                 break;
1739         case IB_FLOW_SPEC_TCP:
1740                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1741                                          LAST_TCP_UDP_FIELD))
1742                         return -ENOTSUPP;
1743
1744                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1745                          0xff);
1746                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1747                          IPPROTO_TCP);
1748
1749                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
1750                          ntohs(ib_spec->tcp_udp.mask.src_port));
1751                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1752                          ntohs(ib_spec->tcp_udp.val.src_port));
1753
1754                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
1755                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1756                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1757                          ntohs(ib_spec->tcp_udp.val.dst_port));
1758                 break;
1759         case IB_FLOW_SPEC_UDP:
1760                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1761                                          LAST_TCP_UDP_FIELD))
1762                         return -ENOTSUPP;
1763
1764                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1765                          0xff);
1766                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1767                          IPPROTO_UDP);
1768
1769                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
1770                          ntohs(ib_spec->tcp_udp.mask.src_port));
1771                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1772                          ntohs(ib_spec->tcp_udp.val.src_port));
1773
1774                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
1775                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1776                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1777                          ntohs(ib_spec->tcp_udp.val.dst_port));
1778                 break;
1779         case IB_FLOW_SPEC_VXLAN_TUNNEL:
1780                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1781                                          LAST_TUNNEL_FIELD))
1782                         return -ENOTSUPP;
1783
1784                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
1785                          ntohl(ib_spec->tunnel.mask.tunnel_id));
1786                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
1787                          ntohl(ib_spec->tunnel.val.tunnel_id));
1788                 break;
1789         default:
1790                 return -EINVAL;
1791         }
1792
1793         return 0;
1794 }
1795
1796 /* If a flow could catch both multicast and unicast packets,
1797  * it won't fall into the multicast flow steering table and this rule
1798  * could steal other multicast packets.
1799  */
1800 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1801 {
1802         struct ib_flow_spec_eth *eth_spec;
1803
1804         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1805             ib_attr->size < sizeof(struct ib_flow_attr) +
1806             sizeof(struct ib_flow_spec_eth) ||
1807             ib_attr->num_of_specs < 1)
1808                 return false;
1809
1810         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1811         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1812             eth_spec->size != sizeof(*eth_spec))
1813                 return false;
1814
1815         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1816                is_multicast_ether_addr(eth_spec->val.dst_mac);
1817 }
1818
1819 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1820 {
1821         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1822         bool has_ipv4_spec = false;
1823         bool eth_type_ipv4 = true;
1824         unsigned int spec_index;
1825
1826         /* Validate that ethertype is correct */
1827         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1828                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1829                     ib_spec->eth.mask.ether_type) {
1830                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1831                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1832                                 eth_type_ipv4 = false;
1833                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1834                         has_ipv4_spec = true;
1835                 }
1836                 ib_spec = (void *)ib_spec + ib_spec->size;
1837         }
1838         return !has_ipv4_spec || eth_type_ipv4;
1839 }
1840
1841 static void put_flow_table(struct mlx5_ib_dev *dev,
1842                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1843 {
1844         prio->refcount -= !!ft_added;
1845         if (!prio->refcount) {
1846                 mlx5_destroy_flow_table(prio->flow_table);
1847                 prio->flow_table = NULL;
1848         }
1849 }
1850
1851 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1852 {
1853         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1854         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1855                                                           struct mlx5_ib_flow_handler,
1856                                                           ibflow);
1857         struct mlx5_ib_flow_handler *iter, *tmp;
1858
1859         mutex_lock(&dev->flow_db.lock);
1860
1861         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1862                 mlx5_del_flow_rules(iter->rule);
1863                 put_flow_table(dev, iter->prio, true);
1864                 list_del(&iter->list);
1865                 kfree(iter);
1866         }
1867
1868         mlx5_del_flow_rules(handler->rule);
1869         put_flow_table(dev, handler->prio, true);
1870         mutex_unlock(&dev->flow_db.lock);
1871
1872         kfree(handler);
1873
1874         return 0;
1875 }
1876
1877 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1878 {
1879         priority *= 2;
1880         if (!dont_trap)
1881                 priority++;
1882         return priority;
1883 }
1884
1885 enum flow_table_type {
1886         MLX5_IB_FT_RX,
1887         MLX5_IB_FT_TX
1888 };
1889
1890 #define MLX5_FS_MAX_TYPES        10
1891 #define MLX5_FS_MAX_ENTRIES      32000UL
1892 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1893                                                 struct ib_flow_attr *flow_attr,
1894                                                 enum flow_table_type ft_type)
1895 {
1896         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1897         struct mlx5_flow_namespace *ns = NULL;
1898         struct mlx5_ib_flow_prio *prio;
1899         struct mlx5_flow_table *ft;
1900         int num_entries;
1901         int num_groups;
1902         int priority;
1903         int err = 0;
1904
1905         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1906                 if (flow_is_multicast_only(flow_attr) &&
1907                     !dont_trap)
1908                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1909                 else
1910                         priority = ib_prio_to_core_prio(flow_attr->priority,
1911                                                         dont_trap);
1912                 ns = mlx5_get_flow_namespace(dev->mdev,
1913                                              MLX5_FLOW_NAMESPACE_BYPASS);
1914                 num_entries = MLX5_FS_MAX_ENTRIES;
1915                 num_groups = MLX5_FS_MAX_TYPES;
1916                 prio = &dev->flow_db.prios[priority];
1917         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1918                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1919                 ns = mlx5_get_flow_namespace(dev->mdev,
1920                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1921                 build_leftovers_ft_param(&priority,
1922                                          &num_entries,
1923                                          &num_groups);
1924                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1925         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1926                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1927                                         allow_sniffer_and_nic_rx_shared_tir))
1928                         return ERR_PTR(-ENOTSUPP);
1929
1930                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1931                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1932                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1933
1934                 prio = &dev->flow_db.sniffer[ft_type];
1935                 priority = 0;
1936                 num_entries = 1;
1937                 num_groups = 1;
1938         }
1939
1940         if (!ns)
1941                 return ERR_PTR(-ENOTSUPP);
1942
1943         ft = prio->flow_table;
1944         if (!ft) {
1945                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1946                                                          num_entries,
1947                                                          num_groups,
1948                                                          0, 0);
1949
1950                 if (!IS_ERR(ft)) {
1951                         prio->refcount = 0;
1952                         prio->flow_table = ft;
1953                 } else {
1954                         err = PTR_ERR(ft);
1955                 }
1956         }
1957
1958         return err ? ERR_PTR(err) : prio;
1959 }
1960
1961 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1962                                                      struct mlx5_ib_flow_prio *ft_prio,
1963                                                      const struct ib_flow_attr *flow_attr,
1964                                                      struct mlx5_flow_destination *dst)
1965 {
1966         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1967         struct mlx5_ib_flow_handler *handler;
1968         struct mlx5_flow_act flow_act = {0};
1969         struct mlx5_flow_spec *spec;
1970         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1971         unsigned int spec_index;
1972         int err = 0;
1973
1974         if (!is_valid_attr(flow_attr))
1975                 return ERR_PTR(-EINVAL);
1976
1977         spec = mlx5_vzalloc(sizeof(*spec));
1978         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1979         if (!handler || !spec) {
1980                 err = -ENOMEM;
1981                 goto free;
1982         }
1983
1984         INIT_LIST_HEAD(&handler->list);
1985
1986         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1987                 err = parse_flow_attr(spec->match_criteria,
1988                                       spec->match_value, ib_flow);
1989                 if (err < 0)
1990                         goto free;
1991
1992                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1993         }
1994
1995         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1996         flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1997                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1998         flow_act.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1999         handler->rule = mlx5_add_flow_rules(ft, spec,
2000                                             &flow_act,
2001                                             dst, 1);
2002
2003         if (IS_ERR(handler->rule)) {
2004                 err = PTR_ERR(handler->rule);
2005                 goto free;
2006         }
2007
2008         ft_prio->refcount++;
2009         handler->prio = ft_prio;
2010
2011         ft_prio->flow_table = ft;
2012 free:
2013         if (err)
2014                 kfree(handler);
2015         kvfree(spec);
2016         return err ? ERR_PTR(err) : handler;
2017 }
2018
2019 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2020                                                           struct mlx5_ib_flow_prio *ft_prio,
2021                                                           struct ib_flow_attr *flow_attr,
2022                                                           struct mlx5_flow_destination *dst)
2023 {
2024         struct mlx5_ib_flow_handler *handler_dst = NULL;
2025         struct mlx5_ib_flow_handler *handler = NULL;
2026
2027         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2028         if (!IS_ERR(handler)) {
2029                 handler_dst = create_flow_rule(dev, ft_prio,
2030                                                flow_attr, dst);
2031                 if (IS_ERR(handler_dst)) {
2032                         mlx5_del_flow_rules(handler->rule);
2033                         ft_prio->refcount--;
2034                         kfree(handler);
2035                         handler = handler_dst;
2036                 } else {
2037                         list_add(&handler_dst->list, &handler->list);
2038                 }
2039         }
2040
2041         return handler;
2042 }
2043 enum {
2044         LEFTOVERS_MC,
2045         LEFTOVERS_UC,
2046 };
2047
2048 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2049                                                           struct mlx5_ib_flow_prio *ft_prio,
2050                                                           struct ib_flow_attr *flow_attr,
2051                                                           struct mlx5_flow_destination *dst)
2052 {
2053         struct mlx5_ib_flow_handler *handler_ucast = NULL;
2054         struct mlx5_ib_flow_handler *handler = NULL;
2055
2056         static struct {
2057                 struct ib_flow_attr     flow_attr;
2058                 struct ib_flow_spec_eth eth_flow;
2059         } leftovers_specs[] = {
2060                 [LEFTOVERS_MC] = {
2061                         .flow_attr = {
2062                                 .num_of_specs = 1,
2063                                 .size = sizeof(leftovers_specs[0])
2064                         },
2065                         .eth_flow = {
2066                                 .type = IB_FLOW_SPEC_ETH,
2067                                 .size = sizeof(struct ib_flow_spec_eth),
2068                                 .mask = {.dst_mac = {0x1} },
2069                                 .val =  {.dst_mac = {0x1} }
2070                         }
2071                 },
2072                 [LEFTOVERS_UC] = {
2073                         .flow_attr = {
2074                                 .num_of_specs = 1,
2075                                 .size = sizeof(leftovers_specs[0])
2076                         },
2077                         .eth_flow = {
2078                                 .type = IB_FLOW_SPEC_ETH,
2079                                 .size = sizeof(struct ib_flow_spec_eth),
2080                                 .mask = {.dst_mac = {0x1} },
2081                                 .val = {.dst_mac = {} }
2082                         }
2083                 }
2084         };
2085
2086         handler = create_flow_rule(dev, ft_prio,
2087                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2088                                    dst);
2089         if (!IS_ERR(handler) &&
2090             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2091                 handler_ucast = create_flow_rule(dev, ft_prio,
2092                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2093                                                  dst);
2094                 if (IS_ERR(handler_ucast)) {
2095                         mlx5_del_flow_rules(handler->rule);
2096                         ft_prio->refcount--;
2097                         kfree(handler);
2098                         handler = handler_ucast;
2099                 } else {
2100                         list_add(&handler_ucast->list, &handler->list);
2101                 }
2102         }
2103
2104         return handler;
2105 }
2106
2107 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2108                                                         struct mlx5_ib_flow_prio *ft_rx,
2109                                                         struct mlx5_ib_flow_prio *ft_tx,
2110                                                         struct mlx5_flow_destination *dst)
2111 {
2112         struct mlx5_ib_flow_handler *handler_rx;
2113         struct mlx5_ib_flow_handler *handler_tx;
2114         int err;
2115         static const struct ib_flow_attr flow_attr  = {
2116                 .num_of_specs = 0,
2117                 .size = sizeof(flow_attr)
2118         };
2119
2120         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2121         if (IS_ERR(handler_rx)) {
2122                 err = PTR_ERR(handler_rx);
2123                 goto err;
2124         }
2125
2126         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2127         if (IS_ERR(handler_tx)) {
2128                 err = PTR_ERR(handler_tx);
2129                 goto err_tx;
2130         }
2131
2132         list_add(&handler_tx->list, &handler_rx->list);
2133
2134         return handler_rx;
2135
2136 err_tx:
2137         mlx5_del_flow_rules(handler_rx->rule);
2138         ft_rx->refcount--;
2139         kfree(handler_rx);
2140 err:
2141         return ERR_PTR(err);
2142 }
2143
2144 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2145                                            struct ib_flow_attr *flow_attr,
2146                                            int domain)
2147 {
2148         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2149         struct mlx5_ib_qp *mqp = to_mqp(qp);
2150         struct mlx5_ib_flow_handler *handler = NULL;
2151         struct mlx5_flow_destination *dst = NULL;
2152         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2153         struct mlx5_ib_flow_prio *ft_prio;
2154         int err;
2155
2156         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2157                 return ERR_PTR(-ENOSPC);
2158
2159         if (domain != IB_FLOW_DOMAIN_USER ||
2160             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2161             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2162                 return ERR_PTR(-EINVAL);
2163
2164         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2165         if (!dst)
2166                 return ERR_PTR(-ENOMEM);
2167
2168         mutex_lock(&dev->flow_db.lock);
2169
2170         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2171         if (IS_ERR(ft_prio)) {
2172                 err = PTR_ERR(ft_prio);
2173                 goto unlock;
2174         }
2175         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2176                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2177                 if (IS_ERR(ft_prio_tx)) {
2178                         err = PTR_ERR(ft_prio_tx);
2179                         ft_prio_tx = NULL;
2180                         goto destroy_ft;
2181                 }
2182         }
2183
2184         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2185         if (mqp->flags & MLX5_IB_QP_RSS)
2186                 dst->tir_num = mqp->rss_qp.tirn;
2187         else
2188                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2189
2190         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2191                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2192                         handler = create_dont_trap_rule(dev, ft_prio,
2193                                                         flow_attr, dst);
2194                 } else {
2195                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2196                                                    dst);
2197                 }
2198         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2199                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2200                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2201                                                 dst);
2202         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2203                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2204         } else {
2205                 err = -EINVAL;
2206                 goto destroy_ft;
2207         }
2208
2209         if (IS_ERR(handler)) {
2210                 err = PTR_ERR(handler);
2211                 handler = NULL;
2212                 goto destroy_ft;
2213         }
2214
2215         mutex_unlock(&dev->flow_db.lock);
2216         kfree(dst);
2217
2218         return &handler->ibflow;
2219
2220 destroy_ft:
2221         put_flow_table(dev, ft_prio, false);
2222         if (ft_prio_tx)
2223                 put_flow_table(dev, ft_prio_tx, false);
2224 unlock:
2225         mutex_unlock(&dev->flow_db.lock);
2226         kfree(dst);
2227         kfree(handler);
2228         return ERR_PTR(err);
2229 }
2230
2231 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2232 {
2233         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2234         int err;
2235
2236         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2237         if (err)
2238                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2239                              ibqp->qp_num, gid->raw);
2240
2241         return err;
2242 }
2243
2244 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2245 {
2246         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2247         int err;
2248
2249         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2250         if (err)
2251                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2252                              ibqp->qp_num, gid->raw);
2253
2254         return err;
2255 }
2256
2257 static int init_node_data(struct mlx5_ib_dev *dev)
2258 {
2259         int err;
2260
2261         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2262         if (err)
2263                 return err;
2264
2265         dev->mdev->rev_id = dev->mdev->pdev->revision;
2266
2267         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2268 }
2269
2270 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2271                              char *buf)
2272 {
2273         struct mlx5_ib_dev *dev =
2274                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2275
2276         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2277 }
2278
2279 static ssize_t show_reg_pages(struct device *device,
2280                               struct device_attribute *attr, char *buf)
2281 {
2282         struct mlx5_ib_dev *dev =
2283                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2284
2285         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2286 }
2287
2288 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2289                         char *buf)
2290 {
2291         struct mlx5_ib_dev *dev =
2292                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2293         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2294 }
2295
2296 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2297                         char *buf)
2298 {
2299         struct mlx5_ib_dev *dev =
2300                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2301         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2302 }
2303
2304 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2305                           char *buf)
2306 {
2307         struct mlx5_ib_dev *dev =
2308                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2309         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2310                        dev->mdev->board_id);
2311 }
2312
2313 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2314 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2315 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2316 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2317 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2318
2319 static struct device_attribute *mlx5_class_attributes[] = {
2320         &dev_attr_hw_rev,
2321         &dev_attr_hca_type,
2322         &dev_attr_board_id,
2323         &dev_attr_fw_pages,
2324         &dev_attr_reg_pages,
2325 };
2326
2327 static void pkey_change_handler(struct work_struct *work)
2328 {
2329         struct mlx5_ib_port_resources *ports =
2330                 container_of(work, struct mlx5_ib_port_resources,
2331                              pkey_change_work);
2332
2333         mutex_lock(&ports->devr->mutex);
2334         mlx5_ib_gsi_pkey_change(ports->gsi);
2335         mutex_unlock(&ports->devr->mutex);
2336 }
2337
2338 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2339 {
2340         struct mlx5_ib_qp *mqp;
2341         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2342         struct mlx5_core_cq *mcq;
2343         struct list_head cq_armed_list;
2344         unsigned long flags_qp;
2345         unsigned long flags_cq;
2346         unsigned long flags;
2347
2348         INIT_LIST_HEAD(&cq_armed_list);
2349
2350         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2351         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2352         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2353                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2354                 if (mqp->sq.tail != mqp->sq.head) {
2355                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2356                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2357                         if (send_mcq->mcq.comp &&
2358                             mqp->ibqp.send_cq->comp_handler) {
2359                                 if (!send_mcq->mcq.reset_notify_added) {
2360                                         send_mcq->mcq.reset_notify_added = 1;
2361                                         list_add_tail(&send_mcq->mcq.reset_notify,
2362                                                       &cq_armed_list);
2363                                 }
2364                         }
2365                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2366                 }
2367                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2368                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2369                 /* no handling is needed for SRQ */
2370                 if (!mqp->ibqp.srq) {
2371                         if (mqp->rq.tail != mqp->rq.head) {
2372                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2373                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2374                                 if (recv_mcq->mcq.comp &&
2375                                     mqp->ibqp.recv_cq->comp_handler) {
2376                                         if (!recv_mcq->mcq.reset_notify_added) {
2377                                                 recv_mcq->mcq.reset_notify_added = 1;
2378                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2379                                                               &cq_armed_list);
2380                                         }
2381                                 }
2382                                 spin_unlock_irqrestore(&recv_mcq->lock,
2383                                                        flags_cq);
2384                         }
2385                 }
2386                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2387         }
2388         /*At that point all inflight post send were put to be executed as of we
2389          * lock/unlock above locks Now need to arm all involved CQs.
2390          */
2391         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2392                 mcq->comp(mcq);
2393         }
2394         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2395 }
2396
2397 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2398                           enum mlx5_dev_event event, unsigned long param)
2399 {
2400         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2401         struct ib_event ibev;
2402         bool fatal = false;
2403         u8 port = 0;
2404
2405         switch (event) {
2406         case MLX5_DEV_EVENT_SYS_ERROR:
2407                 ibev.event = IB_EVENT_DEVICE_FATAL;
2408                 mlx5_ib_handle_internal_error(ibdev);
2409                 fatal = true;
2410                 break;
2411
2412         case MLX5_DEV_EVENT_PORT_UP:
2413         case MLX5_DEV_EVENT_PORT_DOWN:
2414         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2415                 port = (u8)param;
2416
2417                 /* In RoCE, port up/down events are handled in
2418                  * mlx5_netdev_event().
2419                  */
2420                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2421                         IB_LINK_LAYER_ETHERNET)
2422                         return;
2423
2424                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2425                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2426                 break;
2427
2428         case MLX5_DEV_EVENT_LID_CHANGE:
2429                 ibev.event = IB_EVENT_LID_CHANGE;
2430                 port = (u8)param;
2431                 break;
2432
2433         case MLX5_DEV_EVENT_PKEY_CHANGE:
2434                 ibev.event = IB_EVENT_PKEY_CHANGE;
2435                 port = (u8)param;
2436
2437                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2438                 break;
2439
2440         case MLX5_DEV_EVENT_GUID_CHANGE:
2441                 ibev.event = IB_EVENT_GID_CHANGE;
2442                 port = (u8)param;
2443                 break;
2444
2445         case MLX5_DEV_EVENT_CLIENT_REREG:
2446                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2447                 port = (u8)param;
2448                 break;
2449         default:
2450                 return;
2451         }
2452
2453         ibev.device           = &ibdev->ib_dev;
2454         ibev.element.port_num = port;
2455
2456         if (port < 1 || port > ibdev->num_ports) {
2457                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2458                 return;
2459         }
2460
2461         if (ibdev->ib_active)
2462                 ib_dispatch_event(&ibev);
2463
2464         if (fatal)
2465                 ibdev->ib_active = false;
2466 }
2467
2468 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2469 {
2470         int port;
2471
2472         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2473                 mlx5_query_ext_port_caps(dev, port);
2474 }
2475
2476 static int get_port_caps(struct mlx5_ib_dev *dev)
2477 {
2478         struct ib_device_attr *dprops = NULL;
2479         struct ib_port_attr *pprops = NULL;
2480         int err = -ENOMEM;
2481         int port;
2482         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2483
2484         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2485         if (!pprops)
2486                 goto out;
2487
2488         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2489         if (!dprops)
2490                 goto out;
2491
2492         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2493         if (err) {
2494                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2495                 goto out;
2496         }
2497
2498         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2499                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2500                 if (err) {
2501                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2502                                      port, err);
2503                         break;
2504                 }
2505                 dev->mdev->port_caps[port - 1].pkey_table_len =
2506                                                 dprops->max_pkeys;
2507                 dev->mdev->port_caps[port - 1].gid_table_len =
2508                                                 pprops->gid_tbl_len;
2509                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2510                             dprops->max_pkeys, pprops->gid_tbl_len);
2511         }
2512
2513 out:
2514         kfree(pprops);
2515         kfree(dprops);
2516
2517         return err;
2518 }
2519
2520 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2521 {
2522         int err;
2523
2524         err = mlx5_mr_cache_cleanup(dev);
2525         if (err)
2526                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2527
2528         mlx5_ib_destroy_qp(dev->umrc.qp);
2529         ib_free_cq(dev->umrc.cq);
2530         ib_dealloc_pd(dev->umrc.pd);
2531 }
2532
2533 enum {
2534         MAX_UMR_WR = 128,
2535 };
2536
2537 static int create_umr_res(struct mlx5_ib_dev *dev)
2538 {
2539         struct ib_qp_init_attr *init_attr = NULL;
2540         struct ib_qp_attr *attr = NULL;
2541         struct ib_pd *pd;
2542         struct ib_cq *cq;
2543         struct ib_qp *qp;
2544         int ret;
2545
2546         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2547         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2548         if (!attr || !init_attr) {
2549                 ret = -ENOMEM;
2550                 goto error_0;
2551         }
2552
2553         pd = ib_alloc_pd(&dev->ib_dev, 0);
2554         if (IS_ERR(pd)) {
2555                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2556                 ret = PTR_ERR(pd);
2557                 goto error_0;
2558         }
2559
2560         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2561         if (IS_ERR(cq)) {
2562                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2563                 ret = PTR_ERR(cq);
2564                 goto error_2;
2565         }
2566
2567         init_attr->send_cq = cq;
2568         init_attr->recv_cq = cq;
2569         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2570         init_attr->cap.max_send_wr = MAX_UMR_WR;
2571         init_attr->cap.max_send_sge = 1;
2572         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2573         init_attr->port_num = 1;
2574         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2575         if (IS_ERR(qp)) {
2576                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2577                 ret = PTR_ERR(qp);
2578                 goto error_3;
2579         }
2580         qp->device     = &dev->ib_dev;
2581         qp->real_qp    = qp;
2582         qp->uobject    = NULL;
2583         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2584
2585         attr->qp_state = IB_QPS_INIT;
2586         attr->port_num = 1;
2587         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2588                                 IB_QP_PORT, NULL);
2589         if (ret) {
2590                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2591                 goto error_4;
2592         }
2593
2594         memset(attr, 0, sizeof(*attr));
2595         attr->qp_state = IB_QPS_RTR;
2596         attr->path_mtu = IB_MTU_256;
2597
2598         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2599         if (ret) {
2600                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2601                 goto error_4;
2602         }
2603
2604         memset(attr, 0, sizeof(*attr));
2605         attr->qp_state = IB_QPS_RTS;
2606         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2607         if (ret) {
2608                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2609                 goto error_4;
2610         }
2611
2612         dev->umrc.qp = qp;
2613         dev->umrc.cq = cq;
2614         dev->umrc.pd = pd;
2615
2616         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2617         ret = mlx5_mr_cache_init(dev);
2618         if (ret) {
2619                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2620                 goto error_4;
2621         }
2622
2623         kfree(attr);
2624         kfree(init_attr);
2625
2626         return 0;
2627
2628 error_4:
2629         mlx5_ib_destroy_qp(qp);
2630
2631 error_3:
2632         ib_free_cq(cq);
2633
2634 error_2:
2635         ib_dealloc_pd(pd);
2636
2637 error_0:
2638         kfree(attr);
2639         kfree(init_attr);
2640         return ret;
2641 }
2642
2643 static int create_dev_resources(struct mlx5_ib_resources *devr)
2644 {
2645         struct ib_srq_init_attr attr;
2646         struct mlx5_ib_dev *dev;
2647         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2648         int port;
2649         int ret = 0;
2650
2651         dev = container_of(devr, struct mlx5_ib_dev, devr);
2652
2653         mutex_init(&devr->mutex);
2654
2655         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2656         if (IS_ERR(devr->p0)) {
2657                 ret = PTR_ERR(devr->p0);
2658                 goto error0;
2659         }
2660         devr->p0->device  = &dev->ib_dev;
2661         devr->p0->uobject = NULL;
2662         atomic_set(&devr->p0->usecnt, 0);
2663
2664         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2665         if (IS_ERR(devr->c0)) {
2666                 ret = PTR_ERR(devr->c0);
2667                 goto error1;
2668         }
2669         devr->c0->device        = &dev->ib_dev;
2670         devr->c0->uobject       = NULL;
2671         devr->c0->comp_handler  = NULL;
2672         devr->c0->event_handler = NULL;
2673         devr->c0->cq_context    = NULL;
2674         atomic_set(&devr->c0->usecnt, 0);
2675
2676         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2677         if (IS_ERR(devr->x0)) {
2678                 ret = PTR_ERR(devr->x0);
2679                 goto error2;
2680         }
2681         devr->x0->device = &dev->ib_dev;
2682         devr->x0->inode = NULL;
2683         atomic_set(&devr->x0->usecnt, 0);
2684         mutex_init(&devr->x0->tgt_qp_mutex);
2685         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2686
2687         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2688         if (IS_ERR(devr->x1)) {
2689                 ret = PTR_ERR(devr->x1);
2690                 goto error3;
2691         }
2692         devr->x1->device = &dev->ib_dev;
2693         devr->x1->inode = NULL;
2694         atomic_set(&devr->x1->usecnt, 0);
2695         mutex_init(&devr->x1->tgt_qp_mutex);
2696         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2697
2698         memset(&attr, 0, sizeof(attr));
2699         attr.attr.max_sge = 1;
2700         attr.attr.max_wr = 1;
2701         attr.srq_type = IB_SRQT_XRC;
2702         attr.ext.xrc.cq = devr->c0;
2703         attr.ext.xrc.xrcd = devr->x0;
2704
2705         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2706         if (IS_ERR(devr->s0)) {
2707                 ret = PTR_ERR(devr->s0);
2708                 goto error4;
2709         }
2710         devr->s0->device        = &dev->ib_dev;
2711         devr->s0->pd            = devr->p0;
2712         devr->s0->uobject       = NULL;
2713         devr->s0->event_handler = NULL;
2714         devr->s0->srq_context   = NULL;
2715         devr->s0->srq_type      = IB_SRQT_XRC;
2716         devr->s0->ext.xrc.xrcd  = devr->x0;
2717         devr->s0->ext.xrc.cq    = devr->c0;
2718         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2719         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2720         atomic_inc(&devr->p0->usecnt);
2721         atomic_set(&devr->s0->usecnt, 0);
2722
2723         memset(&attr, 0, sizeof(attr));
2724         attr.attr.max_sge = 1;
2725         attr.attr.max_wr = 1;
2726         attr.srq_type = IB_SRQT_BASIC;
2727         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2728         if (IS_ERR(devr->s1)) {
2729                 ret = PTR_ERR(devr->s1);
2730                 goto error5;
2731         }
2732         devr->s1->device        = &dev->ib_dev;
2733         devr->s1->pd            = devr->p0;
2734         devr->s1->uobject       = NULL;
2735         devr->s1->event_handler = NULL;
2736         devr->s1->srq_context   = NULL;
2737         devr->s1->srq_type      = IB_SRQT_BASIC;
2738         devr->s1->ext.xrc.cq    = devr->c0;
2739         atomic_inc(&devr->p0->usecnt);
2740         atomic_set(&devr->s0->usecnt, 0);
2741
2742         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2743                 INIT_WORK(&devr->ports[port].pkey_change_work,
2744                           pkey_change_handler);
2745                 devr->ports[port].devr = devr;
2746         }
2747
2748         return 0;
2749
2750 error5:
2751         mlx5_ib_destroy_srq(devr->s0);
2752 error4:
2753         mlx5_ib_dealloc_xrcd(devr->x1);
2754 error3:
2755         mlx5_ib_dealloc_xrcd(devr->x0);
2756 error2:
2757         mlx5_ib_destroy_cq(devr->c0);
2758 error1:
2759         mlx5_ib_dealloc_pd(devr->p0);
2760 error0:
2761         return ret;
2762 }
2763
2764 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2765 {
2766         struct mlx5_ib_dev *dev =
2767                 container_of(devr, struct mlx5_ib_dev, devr);
2768         int port;
2769
2770         mlx5_ib_destroy_srq(devr->s1);
2771         mlx5_ib_destroy_srq(devr->s0);
2772         mlx5_ib_dealloc_xrcd(devr->x0);
2773         mlx5_ib_dealloc_xrcd(devr->x1);
2774         mlx5_ib_destroy_cq(devr->c0);
2775         mlx5_ib_dealloc_pd(devr->p0);
2776
2777         /* Make sure no change P_Key work items are still executing */
2778         for (port = 0; port < dev->num_ports; ++port)
2779                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2780 }
2781
2782 static u32 get_core_cap_flags(struct ib_device *ibdev)
2783 {
2784         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2785         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2786         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2787         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2788         u32 ret = 0;
2789
2790         if (ll == IB_LINK_LAYER_INFINIBAND)
2791                 return RDMA_CORE_PORT_IBA_IB;
2792
2793         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2794                 return 0;
2795
2796         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2797                 return 0;
2798
2799         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2800                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2801
2802         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2803                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2804
2805         return ret;
2806 }
2807
2808 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2809                                struct ib_port_immutable *immutable)
2810 {
2811         struct ib_port_attr attr;
2812         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2813         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2814         int err;
2815
2816         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2817         if (err)
2818                 return err;
2819
2820         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2821         immutable->gid_tbl_len = attr.gid_tbl_len;
2822         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2823         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
2824                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2825
2826         return 0;
2827 }
2828
2829 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2830                            size_t str_len)
2831 {
2832         struct mlx5_ib_dev *dev =
2833                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2834         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2835                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2836 }
2837
2838 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
2839 {
2840         struct mlx5_core_dev *mdev = dev->mdev;
2841         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2842                                                                  MLX5_FLOW_NAMESPACE_LAG);
2843         struct mlx5_flow_table *ft;
2844         int err;
2845
2846         if (!ns || !mlx5_lag_is_active(mdev))
2847                 return 0;
2848
2849         err = mlx5_cmd_create_vport_lag(mdev);
2850         if (err)
2851                 return err;
2852
2853         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2854         if (IS_ERR(ft)) {
2855                 err = PTR_ERR(ft);
2856                 goto err_destroy_vport_lag;
2857         }
2858
2859         dev->flow_db.lag_demux_ft = ft;
2860         return 0;
2861
2862 err_destroy_vport_lag:
2863         mlx5_cmd_destroy_vport_lag(mdev);
2864         return err;
2865 }
2866
2867 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
2868 {
2869         struct mlx5_core_dev *mdev = dev->mdev;
2870
2871         if (dev->flow_db.lag_demux_ft) {
2872                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2873                 dev->flow_db.lag_demux_ft = NULL;
2874
2875                 mlx5_cmd_destroy_vport_lag(mdev);
2876         }
2877 }
2878
2879 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
2880 {
2881         int err;
2882
2883         dev->roce.nb.notifier_call = mlx5_netdev_event;
2884         err = register_netdevice_notifier(&dev->roce.nb);
2885         if (err) {
2886                 dev->roce.nb.notifier_call = NULL;
2887                 return err;
2888         }
2889
2890         return 0;
2891 }
2892
2893 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
2894 {
2895         if (dev->roce.nb.notifier_call) {
2896                 unregister_netdevice_notifier(&dev->roce.nb);
2897                 dev->roce.nb.notifier_call = NULL;
2898         }
2899 }
2900
2901 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
2902 {
2903         int err;
2904
2905         err = mlx5_add_netdev_notifier(dev);
2906         if (err)
2907                 return err;
2908
2909         if (MLX5_CAP_GEN(dev->mdev, roce)) {
2910                 err = mlx5_nic_vport_enable_roce(dev->mdev);
2911                 if (err)
2912                         goto err_unregister_netdevice_notifier;
2913         }
2914
2915         err = mlx5_eth_lag_init(dev);
2916         if (err)
2917                 goto err_disable_roce;
2918
2919         return 0;
2920
2921 err_disable_roce:
2922         if (MLX5_CAP_GEN(dev->mdev, roce))
2923                 mlx5_nic_vport_disable_roce(dev->mdev);
2924
2925 err_unregister_netdevice_notifier:
2926         mlx5_remove_netdev_notifier(dev);
2927         return err;
2928 }
2929
2930 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
2931 {
2932         mlx5_eth_lag_cleanup(dev);
2933         if (MLX5_CAP_GEN(dev->mdev, roce))
2934                 mlx5_nic_vport_disable_roce(dev->mdev);
2935 }
2936
2937 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2938 {
2939         unsigned int i;
2940
2941         for (i = 0; i < dev->num_ports; i++)
2942                 mlx5_core_dealloc_q_counter(dev->mdev,
2943                                             dev->port[i].q_cnt_id);
2944 }
2945
2946 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2947 {
2948         int i;
2949         int ret;
2950
2951         for (i = 0; i < dev->num_ports; i++) {
2952                 ret = mlx5_core_alloc_q_counter(dev->mdev,
2953                                                 &dev->port[i].q_cnt_id);
2954                 if (ret) {
2955                         mlx5_ib_warn(dev,
2956                                      "couldn't allocate queue counter for port %d, err %d\n",
2957                                      i + 1, ret);
2958                         goto dealloc_counters;
2959                 }
2960         }
2961
2962         return 0;
2963
2964 dealloc_counters:
2965         while (--i >= 0)
2966                 mlx5_core_dealloc_q_counter(dev->mdev,
2967                                             dev->port[i].q_cnt_id);
2968
2969         return ret;
2970 }
2971
2972 static const char * const names[] = {
2973         "rx_write_requests",
2974         "rx_read_requests",
2975         "rx_atomic_requests",
2976         "out_of_buffer",
2977         "out_of_sequence",
2978         "duplicate_request",
2979         "rnr_nak_retry_err",
2980         "packet_seq_err",
2981         "implied_nak_seq_err",
2982         "local_ack_timeout_err",
2983 };
2984
2985 static const size_t stats_offsets[] = {
2986         MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2987         MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2988         MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2989         MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2990         MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2991         MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2992         MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2993         MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2994         MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2995         MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2996 };
2997
2998 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2999                                                     u8 port_num)
3000 {
3001         BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
3002
3003         /* We support only per port stats */
3004         if (port_num == 0)
3005                 return NULL;
3006
3007         return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
3008                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
3009 }
3010
3011 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3012                                 struct rdma_hw_stats *stats,
3013                                 u8 port, int index)
3014 {
3015         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3016         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3017         void *out;
3018         __be32 val;
3019         int ret;
3020         int i;
3021
3022         if (!port || !stats)
3023                 return -ENOSYS;
3024
3025         out = mlx5_vzalloc(outlen);
3026         if (!out)
3027                 return -ENOMEM;
3028
3029         ret = mlx5_core_query_q_counter(dev->mdev,
3030                                         dev->port[port - 1].q_cnt_id, 0,
3031                                         out, outlen);
3032         if (ret)
3033                 goto free;
3034
3035         for (i = 0; i < ARRAY_SIZE(names); i++) {
3036                 val = *(__be32 *)(out + stats_offsets[i]);
3037                 stats->value[i] = (u64)be32_to_cpu(val);
3038         }
3039 free:
3040         kvfree(out);
3041         return ARRAY_SIZE(names);
3042 }
3043
3044 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3045 {
3046         struct mlx5_ib_dev *dev;
3047         enum rdma_link_layer ll;
3048         int port_type_cap;
3049         const char *name;
3050         int err;
3051         int i;
3052
3053         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3054         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3055
3056         printk_once(KERN_INFO "%s", mlx5_version);
3057
3058         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3059         if (!dev)
3060                 return NULL;
3061
3062         dev->mdev = mdev;
3063
3064         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3065                             GFP_KERNEL);
3066         if (!dev->port)
3067                 goto err_dealloc;
3068
3069         rwlock_init(&dev->roce.netdev_lock);
3070         err = get_port_caps(dev);
3071         if (err)
3072                 goto err_free_port;
3073
3074         if (mlx5_use_mad_ifc(dev))
3075                 get_ext_port_caps(dev);
3076
3077         if (!mlx5_lag_is_active(mdev))
3078                 name = "mlx5_%d";
3079         else
3080                 name = "mlx5_bond_%d";
3081
3082         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3083         dev->ib_dev.owner               = THIS_MODULE;
3084         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
3085         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
3086         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
3087         dev->ib_dev.phys_port_cnt     = dev->num_ports;
3088         dev->ib_dev.num_comp_vectors    =
3089                 dev->mdev->priv.eq_table.num_comp_vectors;
3090         dev->ib_dev.dma_device  = &mdev->pdev->dev;
3091
3092         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
3093         dev->ib_dev.uverbs_cmd_mask     =
3094                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
3095                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
3096                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
3097                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
3098                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
3099                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
3100                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
3101                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
3102                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
3103                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
3104                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3105                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
3106                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
3107                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
3108                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
3109                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
3110                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
3111                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
3112                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
3113                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
3114                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
3115                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
3116                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
3117                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
3118                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
3119                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3120         dev->ib_dev.uverbs_ex_cmd_mask =
3121                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
3122                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
3123                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
3124                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3125
3126         dev->ib_dev.query_device        = mlx5_ib_query_device;
3127         dev->ib_dev.query_port          = mlx5_ib_query_port;
3128         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3129         if (ll == IB_LINK_LAYER_ETHERNET)
3130                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3131         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3132         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3133         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3134         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3135         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3136         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3137         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3138         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3139         dev->ib_dev.mmap                = mlx5_ib_mmap;
3140         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3141         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3142         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3143         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3144         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3145         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3146         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3147         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3148         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3149         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3150         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3151         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3152         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3153         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3154         dev->ib_dev.post_send           = mlx5_ib_post_send;
3155         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3156         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3157         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3158         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3159         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3160         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3161         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3162         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3163         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3164         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3165         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3166         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3167         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3168         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3169         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3170         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3171         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3172         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3173         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3174         if (mlx5_core_is_pf(mdev)) {
3175                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3176                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3177                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3178                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3179         }
3180
3181         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3182
3183         mlx5_ib_internal_fill_odp_caps(dev);
3184
3185         if (MLX5_CAP_GEN(mdev, imaicl)) {
3186                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3187                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3188                 dev->ib_dev.uverbs_cmd_mask |=
3189                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3190                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3191         }
3192
3193         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3194             MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3195                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3196                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3197         }
3198
3199         if (MLX5_CAP_GEN(mdev, xrc)) {
3200                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3201                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3202                 dev->ib_dev.uverbs_cmd_mask |=
3203                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3204                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3205         }
3206
3207         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3208             IB_LINK_LAYER_ETHERNET) {
3209                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3210                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3211                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3212                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3213                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3214                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3215                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3216                 dev->ib_dev.uverbs_ex_cmd_mask |=
3217                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3218                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3219                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3220                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3221                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3222                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3223                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3224         }
3225         err = init_node_data(dev);
3226         if (err)
3227                 goto err_free_port;
3228
3229         mutex_init(&dev->flow_db.lock);
3230         mutex_init(&dev->cap_mask_mutex);
3231         INIT_LIST_HEAD(&dev->qp_list);
3232         spin_lock_init(&dev->reset_flow_resource_lock);
3233
3234         if (ll == IB_LINK_LAYER_ETHERNET) {
3235                 err = mlx5_enable_eth(dev);
3236                 if (err)
3237                         goto err_free_port;
3238         }
3239
3240         err = create_dev_resources(&dev->devr);
3241         if (err)
3242                 goto err_disable_eth;
3243
3244         err = mlx5_ib_odp_init_one(dev);
3245         if (err)
3246                 goto err_rsrc;
3247
3248         err = mlx5_ib_alloc_q_counters(dev);
3249         if (err)
3250                 goto err_odp;
3251
3252         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3253         if (!dev->mdev->priv.uar)
3254                 goto err_q_cnt;
3255
3256         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3257         if (err)
3258                 goto err_uar_page;
3259
3260         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3261         if (err)
3262                 goto err_bfreg;
3263
3264         err = ib_register_device(&dev->ib_dev, NULL);
3265         if (err)
3266                 goto err_fp_bfreg;
3267
3268         err = create_umr_res(dev);
3269         if (err)
3270                 goto err_dev;
3271
3272         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3273                 err = device_create_file(&dev->ib_dev.dev,
3274                                          mlx5_class_attributes[i]);
3275                 if (err)
3276                         goto err_umrc;
3277         }
3278
3279         dev->ib_active = true;
3280
3281         return dev;
3282
3283 err_umrc:
3284         destroy_umrc_res(dev);
3285
3286 err_dev:
3287         ib_unregister_device(&dev->ib_dev);
3288
3289 err_fp_bfreg:
3290         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3291
3292 err_bfreg:
3293         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3294
3295 err_uar_page:
3296         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3297
3298 err_q_cnt:
3299         mlx5_ib_dealloc_q_counters(dev);
3300
3301 err_odp:
3302         mlx5_ib_odp_remove_one(dev);
3303
3304 err_rsrc:
3305         destroy_dev_resources(&dev->devr);
3306
3307 err_disable_eth:
3308         if (ll == IB_LINK_LAYER_ETHERNET) {
3309                 mlx5_disable_eth(dev);
3310                 mlx5_remove_netdev_notifier(dev);
3311         }
3312
3313 err_free_port:
3314         kfree(dev->port);
3315
3316 err_dealloc:
3317         ib_dealloc_device((struct ib_device *)dev);
3318
3319         return NULL;
3320 }
3321
3322 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3323 {
3324         struct mlx5_ib_dev *dev = context;
3325         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3326
3327         mlx5_remove_netdev_notifier(dev);
3328         ib_unregister_device(&dev->ib_dev);
3329         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3330         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3331         mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
3332         mlx5_ib_dealloc_q_counters(dev);
3333         destroy_umrc_res(dev);
3334         mlx5_ib_odp_remove_one(dev);
3335         destroy_dev_resources(&dev->devr);
3336         if (ll == IB_LINK_LAYER_ETHERNET)
3337                 mlx5_disable_eth(dev);
3338         kfree(dev->port);
3339         ib_dealloc_device(&dev->ib_dev);
3340 }
3341
3342 static struct mlx5_interface mlx5_ib_interface = {
3343         .add            = mlx5_ib_add,
3344         .remove         = mlx5_ib_remove,
3345         .event          = mlx5_ib_event,
3346 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3347         .pfault         = mlx5_ib_pfault,
3348 #endif
3349         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3350 };
3351
3352 static int __init mlx5_ib_init(void)
3353 {
3354         int err;
3355
3356         if (deprecated_prof_sel != 2)
3357                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3358
3359         err = mlx5_register_interface(&mlx5_ib_interface);
3360
3361         return err;
3362 }
3363
3364 static void __exit mlx5_ib_cleanup(void)
3365 {
3366         mlx5_unregister_interface(&mlx5_ib_interface);
3367 }
3368
3369 module_init(mlx5_ib_init);
3370 module_exit(mlx5_ib_cleanup);