drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/bitmap.h>
  42 #if defined(CONFIG_X86)
  43 #include <asm/pat.h>
  44 #endif
  45 #include <linux/sched.h>
  46 #include <linux/sched/mm.h>
  47 #include <linux/sched/task.h>
  48 #include <linux/delay.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <rdma/ib_addr.h>
  51 #include <rdma/ib_cache.h>
  52 #include <linux/mlx5/port.h>
  53 #include <linux/mlx5/vport.h>
  54 #include <linux/mlx5/fs.h>
  55 #include <linux/mlx5/eswitch.h>
  56 #include <linux/list.h>
  57 #include <rdma/ib_smi.h>
  58 #include <rdma/ib_umem.h>
  59 #include <linux/in.h>
  60 #include <linux/etherdevice.h>
  61 #include "mlx5_ib.h"
  62 #include "ib_rep.h"
  63 #include "cmd.h"
  64 #include "srq.h"
  65 #include <linux/mlx5/fs_helpers.h>
  66 #include <linux/mlx5/accel.h>
  67 #include <rdma/uverbs_std_types.h>
  68 #include <rdma/mlx5_user_ioctl_verbs.h>
  69 #include <rdma/mlx5_user_ioctl_cmds.h>
  70
  71 #define UVERBS_MODULE_NAME mlx5_ib
  72 #include <rdma/uverbs_named_ioctl.h>
  73
  74 #define DRIVER_NAME "mlx5_ib"
  75 #define DRIVER_VERSION "5.0-0"
  76
  77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  78 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  79 MODULE_LICENSE("Dual BSD/GPL");
  80
  81 static char mlx5_version[] =
  82         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  83         DRIVER_VERSION "\n";
  84
  85 struct mlx5_ib_event_work {
  86         struct work_struct      work;
  87         union {
  88                 struct mlx5_ib_dev            *dev;
  89                 struct mlx5_ib_multiport_info *mpi;
  90         };
  91         bool                    is_slave;
  92         unsigned int            event;
  93         void                    *param;
  94 };
  95
  96 enum {
  97         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  98 };
  99
 100 static struct workqueue_struct *mlx5_ib_event_wq;
 101 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
 102 static LIST_HEAD(mlx5_ib_dev_list);
 103 /*
 104  * This mutex should be held when accessing either of the above lists
 105  */
 106 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
 107
 108 /* We can't use an array for xlt_emergency_page because dma_map_single
 109  * doesn't work on kernel modules memory
 110  */
 111 static unsigned long xlt_emergency_page;
 112 static struct mutex xlt_emergency_page_mutex;
 113
 114 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
 115 {
 116         struct mlx5_ib_dev *dev;
 117
 118         mutex_lock(&mlx5_ib_multiport_mutex);
 119         dev = mpi->ibdev;
 120         mutex_unlock(&mlx5_ib_multiport_mutex);
 121         return dev;
 122 }
 123
 124 static enum rdma_link_layer
 125 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 126 {
 127         switch (port_type_cap) {
 128         case MLX5_CAP_PORT_TYPE_IB:
 129                 return IB_LINK_LAYER_INFINIBAND;
 130         case MLX5_CAP_PORT_TYPE_ETH:
 131                 return IB_LINK_LAYER_ETHERNET;
 132         default:
 133                 return IB_LINK_LAYER_UNSPECIFIED;
 134         }
 135 }
 136
 137 static enum rdma_link_layer
 138 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 139 {
 140         struct mlx5_ib_dev *dev = to_mdev(device);
 141         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 142
 143         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 144 }
 145
 146 static int get_port_state(struct ib_device *ibdev,
 147                           u8 port_num,
 148                           enum ib_port_state *state)
 149 {
 150         struct ib_port_attr attr;
 151         int ret;
 152
 153         memset(&attr, 0, sizeof(attr));
 154         ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 155         if (!ret)
 156                 *state = attr.state;
 157         return ret;
 158 }
 159
 160 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
 161                                            struct net_device *ndev,
 162                                            u8 *port_num)
 163 {
 164         struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
 165         struct net_device *rep_ndev;
 166         struct mlx5_ib_port *port;
 167         int i;
 168
 169         for (i = 0; i < dev->num_ports; i++) {
 170                 port  = &dev->port[i];
 171                 if (!port->rep)
 172                         continue;
 173
 174                 read_lock(&port->roce.netdev_lock);
 175                 rep_ndev = mlx5_ib_get_rep_netdev(esw,
 176                                                   port->rep->vport);
 177                 if (rep_ndev == ndev) {
 178                         read_unlock(&port->roce.netdev_lock);
 179                         *port_num = i + 1;
 180                         return &port->roce;
 181                 }
 182                 read_unlock(&port->roce.netdev_lock);
 183         }
 184
 185         return NULL;
 186 }
 187
 188 static int mlx5_netdev_event(struct notifier_block *this,
 189                              unsigned long event, void *ptr)
 190 {
 191         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 192         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 193         u8 port_num = roce->native_port_num;
 194         struct mlx5_core_dev *mdev;
 195         struct mlx5_ib_dev *ibdev;
 196
 197         ibdev = roce->dev;
 198         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 199         if (!mdev)
 200                 return NOTIFY_DONE;
 201
 202         switch (event) {
 203         case NETDEV_REGISTER:
 204                 /* Should already be registered during the load */
 205                 if (ibdev->is_rep)
 206                         break;
 207                 write_lock(&roce->netdev_lock);
 208                 if (ndev->dev.parent == mdev->device)
 209                         roce->netdev = ndev;
 210                 write_unlock(&roce->netdev_lock);
 211                 break;
 212
 213         case NETDEV_UNREGISTER:
 214                 /* In case of reps, ib device goes away before the netdevs */
 215                 write_lock(&roce->netdev_lock);
 216                 if (roce->netdev == ndev)
 217                         roce->netdev = NULL;
 218                 write_unlock(&roce->netdev_lock);
 219                 break;
 220
 221         case NETDEV_CHANGE:
 222         case NETDEV_UP:
 223         case NETDEV_DOWN: {
 224                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 225                 struct net_device *upper = NULL;
 226
 227                 if (lag_ndev) {
 228                         upper = netdev_master_upper_dev_get(lag_ndev);
 229                         dev_put(lag_ndev);
 230                 }
 231
 232                 if (ibdev->is_rep)
 233                         roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
 234                 if (!roce)
 235                         return NOTIFY_DONE;
 236                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 237                     && ibdev->ib_active) {
 238                         struct ib_event ibev = { };
 239                         enum ib_port_state port_state;
 240
 241                         if (get_port_state(&ibdev->ib_dev, port_num,
 242                                            &port_state))
 243                                 goto done;
 244
 245                         if (roce->last_port_state == port_state)
 246                                 goto done;
 247
 248                         roce->last_port_state = port_state;
 249                         ibev.device = &ibdev->ib_dev;
 250                         if (port_state == IB_PORT_DOWN)
 251                                 ibev.event = IB_EVENT_PORT_ERR;
 252                         else if (port_state == IB_PORT_ACTIVE)
 253                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 254                         else
 255                                 goto done;
 256
 257                         ibev.element.port_num = port_num;
 258                         ib_dispatch_event(&ibev);
 259                 }
 260                 break;
 261         }
 262
 263         default:
 264                 break;
 265         }
 266 done:
 267         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 268         return NOTIFY_DONE;
 269 }
 270
 271 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 272                                              u8 port_num)
 273 {
 274         struct mlx5_ib_dev *ibdev = to_mdev(device);
 275         struct net_device *ndev;
 276         struct mlx5_core_dev *mdev;
 277
 278         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 279         if (!mdev)
 280                 return NULL;
 281
 282         ndev = mlx5_lag_get_roce_netdev(mdev);
 283         if (ndev)
 284                 goto out;
 285
 286         /* Ensure ndev does not disappear before we invoke dev_hold()
 287          */
 288         read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
 289         ndev = ibdev->port[port_num - 1].roce.netdev;
 290         if (ndev)
 291                 dev_hold(ndev);
 292         read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
 293
 294 out:
 295         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 296         return ndev;
 297 }
 298
 299 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 300                                                    u8 ib_port_num,
 301                                                    u8 *native_port_num)
 302 {
 303         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 304                                                           ib_port_num);
 305         struct mlx5_core_dev *mdev = NULL;
 306         struct mlx5_ib_multiport_info *mpi;
 307         struct mlx5_ib_port *port;
 308
 309         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 310             ll != IB_LINK_LAYER_ETHERNET) {
 311                 if (native_port_num)
 312                         *native_port_num = ib_port_num;
 313                 return ibdev->mdev;
 314         }
 315
 316         if (native_port_num)
 317                 *native_port_num = 1;
 318
 319         port = &ibdev->port[ib_port_num - 1];
 320         if (!port)
 321                 return NULL;
 322
 323         spin_lock(&port->mp.mpi_lock);
 324         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 325         if (mpi && !mpi->unaffiliate) {
 326                 mdev = mpi->mdev;
 327                 /* If it's the master no need to refcount, it'll exist
 328                  * as long as the ib_dev exists.
 329                  */
 330                 if (!mpi->is_master)
 331                         mpi->mdev_refcnt++;
 332         }
 333         spin_unlock(&port->mp.mpi_lock);
 334
 335         return mdev;
 336 }
 337
 338 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 339 {
 340         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 341                                                           port_num);
 342         struct mlx5_ib_multiport_info *mpi;
 343         struct mlx5_ib_port *port;
 344
 345         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 346                 return;
 347
 348         port = &ibdev->port[port_num - 1];
 349
 350         spin_lock(&port->mp.mpi_lock);
 351         mpi = ibdev->port[port_num - 1].mp.mpi;
 352         if (mpi->is_master)
 353                 goto out;
 354
 355         mpi->mdev_refcnt--;
 356         if (mpi->unaffiliate)
 357                 complete(&mpi->unref_comp);
 358 out:
 359         spin_unlock(&port->mp.mpi_lock);
 360 }
 361
 362 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 363                                            u8 *active_width)
 364 {
 365         switch (eth_proto_oper) {
 366         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 367         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 368         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 369         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 370                 *active_width = IB_WIDTH_1X;
 371                 *active_speed = IB_SPEED_SDR;
 372                 break;
 373         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 374         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 375         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 376         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 377         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 378         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 379         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 380                 *active_width = IB_WIDTH_1X;
 381                 *active_speed = IB_SPEED_QDR;
 382                 break;
 383         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 384         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 385         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 386                 *active_width = IB_WIDTH_1X;
 387                 *active_speed = IB_SPEED_EDR;
 388                 break;
 389         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 390         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 391         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 392         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 393                 *active_width = IB_WIDTH_4X;
 394                 *active_speed = IB_SPEED_QDR;
 395                 break;
 396         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 397         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 398         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 399                 *active_width = IB_WIDTH_1X;
 400                 *active_speed = IB_SPEED_HDR;
 401                 break;
 402         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 403                 *active_width = IB_WIDTH_4X;
 404                 *active_speed = IB_SPEED_FDR;
 405                 break;
 406         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 407         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 408         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 409         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 410                 *active_width = IB_WIDTH_4X;
 411                 *active_speed = IB_SPEED_EDR;
 412                 break;
 413         default:
 414                 return -EINVAL;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 421                                         u8 *active_width)
 422 {
 423         switch (eth_proto_oper) {
 424         case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 425         case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 426                 *active_width = IB_WIDTH_1X;
 427                 *active_speed = IB_SPEED_SDR;
 428                 break;
 429         case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 430                 *active_width = IB_WIDTH_1X;
 431                 *active_speed = IB_SPEED_DDR;
 432                 break;
 433         case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 434                 *active_width = IB_WIDTH_1X;
 435                 *active_speed = IB_SPEED_QDR;
 436                 break;
 437         case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 438                 *active_width = IB_WIDTH_4X;
 439                 *active_speed = IB_SPEED_QDR;
 440                 break;
 441         case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 442                 *active_width = IB_WIDTH_1X;
 443                 *active_speed = IB_SPEED_EDR;
 444                 break;
 445         case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 446                 *active_width = IB_WIDTH_2X;
 447                 *active_speed = IB_SPEED_EDR;
 448                 break;
 449         case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 450                 *active_width = IB_WIDTH_1X;
 451                 *active_speed = IB_SPEED_HDR;
 452                 break;
 453         case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
 454                 *active_width = IB_WIDTH_4X;
 455                 *active_speed = IB_SPEED_EDR;
 456                 break;
 457         case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 458                 *active_width = IB_WIDTH_2X;
 459                 *active_speed = IB_SPEED_HDR;
 460                 break;
 461         case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 462                 *active_width = IB_WIDTH_4X;
 463                 *active_speed = IB_SPEED_HDR;
 464                 break;
 465         default:
 466                 return -EINVAL;
 467         }
 468
 469         return 0;
 470 }
 471
 472 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 473                                     u8 *active_width, bool ext)
 474 {
 475         return ext ?
 476                 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 477                                              active_width) :
 478                 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 479                                                 active_width);
 480 }
 481
 482 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 483                                 struct ib_port_attr *props)
 484 {
 485         struct mlx5_ib_dev *dev = to_mdev(device);
 486         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 487         struct mlx5_core_dev *mdev;
 488         struct net_device *ndev, *upper;
 489         enum ib_mtu ndev_ib_mtu;
 490         bool put_mdev = true;
 491         u16 qkey_viol_cntr;
 492         u32 eth_prot_oper;
 493         u8 mdev_port_num;
 494         bool ext;
 495         int err;
 496
 497         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 498         if (!mdev) {
 499                 /* This means the port isn't affiliated yet. Get the
 500                  * info for the master port instead.
 501                  */
 502                 put_mdev = false;
 503                 mdev = dev->mdev;
 504                 mdev_port_num = 1;
 505                 port_num = 1;
 506         }
 507
 508         /* Possible bad flows are checked before filling out props so in case
 509          * of an error it will still be zeroed out.
 510          * Use native port in case of reps
 511          */
 512         if (dev->is_rep)
 513                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 514                                            1);
 515         else
 516                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 517                                            mdev_port_num);
 518         if (err)
 519                 goto out;
 520         ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
 521         eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 522
 523         props->active_width     = IB_WIDTH_4X;
 524         props->active_speed     = IB_SPEED_QDR;
 525
 526         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 527                                  &props->active_width, ext);
 528
 529         props->port_cap_flags |= IB_PORT_CM_SUP;
 530         props->ip_gids = true;
 531
 532         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 533                                                 roce_address_table_size);
 534         props->max_mtu          = IB_MTU_4096;
 535         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 536         props->pkey_tbl_len     = 1;
 537         props->state            = IB_PORT_DOWN;
 538         props->phys_state       = 3;
 539
 540         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 541         props->qkey_viol_cntr = qkey_viol_cntr;
 542
 543         /* If this is a stub query for an unaffiliated port stop here */
 544         if (!put_mdev)
 545                 goto out;
 546
 547         ndev = mlx5_ib_get_netdev(device, port_num);
 548         if (!ndev)
 549                 goto out;
 550
 551         if (dev->lag_active) {
 552                 rcu_read_lock();
 553                 upper = netdev_master_upper_dev_get_rcu(ndev);
 554                 if (upper) {
 555                         dev_put(ndev);
 556                         ndev = upper;
 557                         dev_hold(ndev);
 558                 }
 559                 rcu_read_unlock();
 560         }
 561
 562         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 563                 props->state      = IB_PORT_ACTIVE;
 564                 props->phys_state = 5;
 565         }
 566
 567         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 568
 569         dev_put(ndev);
 570
 571         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 572 out:
 573         if (put_mdev)
 574                 mlx5_ib_put_native_port_mdev(dev, port_num);
 575         return err;
 576 }
 577
 578 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 579                          unsigned int index, const union ib_gid *gid,
 580                          const struct ib_gid_attr *attr)
 581 {
 582         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 583         u16 vlan_id = 0xffff;
 584         u8 roce_version = 0;
 585         u8 roce_l3_type = 0;
 586         u8 mac[ETH_ALEN];
 587         int ret;
 588
 589         if (gid) {
 590                 gid_type = attr->gid_type;
 591                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
 592                 if (ret)
 593                         return ret;
 594         }
 595
 596         switch (gid_type) {
 597         case IB_GID_TYPE_IB:
 598                 roce_version = MLX5_ROCE_VERSION_1;
 599                 break;
 600         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 601                 roce_version = MLX5_ROCE_VERSION_2;
 602                 if (ipv6_addr_v4mapped((void *)gid))
 603                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 604                 else
 605                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 606                 break;
 607
 608         default:
 609                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 610         }
 611
 612         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 613                                       roce_l3_type, gid->raw, mac,
 614                                       vlan_id < VLAN_CFI_MASK, vlan_id,
 615                                       port_num);
 616 }
 617
 618 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 619                            __always_unused void **context)
 620 {
 621         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 622                              attr->index, &attr->gid, attr);
 623 }
 624
 625 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 626                            __always_unused void **context)
 627 {
 628         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 629                              attr->index, NULL, NULL);
 630 }
 631
 632 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
 633                                const struct ib_gid_attr *attr)
 634 {
 635         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 636                 return 0;
 637
 638         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 639 }
 640
 641 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 642 {
 643         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 644                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 645         return 0;
 646 }
 647
 648 enum {
 649         MLX5_VPORT_ACCESS_METHOD_MAD,
 650         MLX5_VPORT_ACCESS_METHOD_HCA,
 651         MLX5_VPORT_ACCESS_METHOD_NIC,
 652 };
 653
 654 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 655 {
 656         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 657                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 658
 659         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 660             IB_LINK_LAYER_ETHERNET)
 661                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 662
 663         return MLX5_VPORT_ACCESS_METHOD_HCA;
 664 }
 665
 666 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 667                             u8 atomic_size_qp,
 668                             struct ib_device_attr *props)
 669 {
 670         u8 tmp;
 671         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 672         u8 atomic_req_8B_endianness_mode =
 673                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 674
 675         /* Check if HW supports 8 bytes standard atomic operations and capable
 676          * of host endianness respond
 677          */
 678         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 679         if (((atomic_operations & tmp) == tmp) &&
 680             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 681             (atomic_req_8B_endianness_mode)) {
 682                 props->atomic_cap = IB_ATOMIC_HCA;
 683         } else {
 684                 props->atomic_cap = IB_ATOMIC_NONE;
 685         }
 686 }
 687
 688 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 689                                struct ib_device_attr *props)
 690 {
 691         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 692
 693         get_atomic_caps(dev, atomic_size_qp, props);
 694 }
 695
 696 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 697                                struct ib_device_attr *props)
 698 {
 699         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 700
 701         get_atomic_caps(dev, atomic_size_qp, props);
 702 }
 703
 704 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 705 {
 706         struct ib_device_attr props = {};
 707
 708         get_atomic_caps_dc(dev, &props);
 709         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 710 }
 711 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 712                                         __be64 *sys_image_guid)
 713 {
 714         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 715         struct mlx5_core_dev *mdev = dev->mdev;
 716         u64 tmp;
 717         int err;
 718
 719         switch (mlx5_get_vport_access_method(ibdev)) {
 720         case MLX5_VPORT_ACCESS_METHOD_MAD:
 721                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 722                                                             sys_image_guid);
 723
 724         case MLX5_VPORT_ACCESS_METHOD_HCA:
 725                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 726                 break;
 727
 728         case MLX5_VPORT_ACCESS_METHOD_NIC:
 729                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 730                 break;
 731
 732         default:
 733                 return -EINVAL;
 734         }
 735
 736         if (!err)
 737                 *sys_image_guid = cpu_to_be64(tmp);
 738
 739         return err;
 740
 741 }
 742
 743 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 744                                 u16 *max_pkeys)
 745 {
 746         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 747         struct mlx5_core_dev *mdev = dev->mdev;
 748
 749         switch (mlx5_get_vport_access_method(ibdev)) {
 750         case MLX5_VPORT_ACCESS_METHOD_MAD:
 751                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 752
 753         case MLX5_VPORT_ACCESS_METHOD_HCA:
 754         case MLX5_VPORT_ACCESS_METHOD_NIC:
 755                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 756                                                 pkey_table_size));
 757                 return 0;
 758
 759         default:
 760                 return -EINVAL;
 761         }
 762 }
 763
 764 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 765                                 u32 *vendor_id)
 766 {
 767         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 768
 769         switch (mlx5_get_vport_access_method(ibdev)) {
 770         case MLX5_VPORT_ACCESS_METHOD_MAD:
 771                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 772
 773         case MLX5_VPORT_ACCESS_METHOD_HCA:
 774         case MLX5_VPORT_ACCESS_METHOD_NIC:
 775                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 776
 777         default:
 778                 return -EINVAL;
 779         }
 780 }
 781
 782 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 783                                 __be64 *node_guid)
 784 {
 785         u64 tmp;
 786         int err;
 787
 788         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 789         case MLX5_VPORT_ACCESS_METHOD_MAD:
 790                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 791
 792         case MLX5_VPORT_ACCESS_METHOD_HCA:
 793                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 794                 break;
 795
 796         case MLX5_VPORT_ACCESS_METHOD_NIC:
 797                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 798                 break;
 799
 800         default:
 801                 return -EINVAL;
 802         }
 803
 804         if (!err)
 805                 *node_guid = cpu_to_be64(tmp);
 806
 807         return err;
 808 }
 809
 810 struct mlx5_reg_node_desc {
 811         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 812 };
 813
 814 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 815 {
 816         struct mlx5_reg_node_desc in;
 817
 818         if (mlx5_use_mad_ifc(dev))
 819                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 820
 821         memset(&in, 0, sizeof(in));
 822
 823         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 824                                     sizeof(struct mlx5_reg_node_desc),
 825                                     MLX5_REG_NODE_DESC, 0, 0);
 826 }
 827
 828 static int mlx5_ib_query_device(struct ib_device *ibdev,
 829                                 struct ib_device_attr *props,
 830                                 struct ib_udata *uhw)
 831 {
 832         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 833         struct mlx5_core_dev *mdev = dev->mdev;
 834         int err = -ENOMEM;
 835         int max_sq_desc;
 836         int max_rq_sg;
 837         int max_sq_sg;
 838         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 839         bool raw_support = !mlx5_core_mp_enabled(mdev);
 840         struct mlx5_ib_query_device_resp resp = {};
 841         size_t resp_len;
 842         u64 max_tso;
 843
 844         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 845         if (uhw->outlen && uhw->outlen < resp_len)
 846                 return -EINVAL;
 847         else
 848                 resp.response_length = resp_len;
 849
 850         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 851                 return -EINVAL;
 852
 853         memset(props, 0, sizeof(*props));
 854         err = mlx5_query_system_image_guid(ibdev,
 855                                            &props->sys_image_guid);
 856         if (err)
 857                 return err;
 858
 859         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 860         if (err)
 861                 return err;
 862
 863         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 864         if (err)
 865                 return err;
 866
 867         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 868                 (fw_rev_min(dev->mdev) << 16) |
 869                 fw_rev_sub(dev->mdev);
 870         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 871                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 872                 IB_DEVICE_SYS_IMAGE_GUID                |
 873                 IB_DEVICE_RC_RNR_NAK_GEN;
 874
 875         if (MLX5_CAP_GEN(mdev, pkv))
 876                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 877         if (MLX5_CAP_GEN(mdev, qkv))
 878                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 879         if (MLX5_CAP_GEN(mdev, apm))
 880                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 881         if (MLX5_CAP_GEN(mdev, xrc))
 882                 props->device_cap_flags |= IB_DEVICE_XRC;
 883         if (MLX5_CAP_GEN(mdev, imaicl)) {
 884                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 885                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 886                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 887                 /* We support 'Gappy' memory registration too */
 888                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 889         }
 890         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 891         if (MLX5_CAP_GEN(mdev, sho)) {
 892                 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
 893                 /* At this stage no support for signature handover */
 894                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 895                                       IB_PROT_T10DIF_TYPE_2 |
 896                                       IB_PROT_T10DIF_TYPE_3;
 897                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 898                                        IB_GUARD_T10DIF_CSUM;
 899         }
 900         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 901                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 902
 903         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 904                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 905                         /* Legacy bit to support old userspace libraries */
 906                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 907                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 908                 }
 909
 910                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 911                         props->raw_packet_caps |=
 912                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 913
 914                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 915                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 916                         if (max_tso) {
 917                                 resp.tso_caps.max_tso = 1 << max_tso;
 918                                 resp.tso_caps.supported_qpts |=
 919                                         1 << IB_QPT_RAW_PACKET;
 920                                 resp.response_length += sizeof(resp.tso_caps);
 921                         }
 922                 }
 923
 924                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 925                         resp.rss_caps.rx_hash_function =
 926                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 927                         resp.rss_caps.rx_hash_fields_mask =
 928                                                 MLX5_RX_HASH_SRC_IPV4 |
 929                                                 MLX5_RX_HASH_DST_IPV4 |
 930                                                 MLX5_RX_HASH_SRC_IPV6 |
 931                                                 MLX5_RX_HASH_DST_IPV6 |
 932                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 933                                                 MLX5_RX_HASH_DST_PORT_TCP |
 934                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 935                                                 MLX5_RX_HASH_DST_PORT_UDP |
 936                                                 MLX5_RX_HASH_INNER;
 937                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 938                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 939                                 resp.rss_caps.rx_hash_fields_mask |=
 940                                         MLX5_RX_HASH_IPSEC_SPI;
 941                         resp.response_length += sizeof(resp.rss_caps);
 942                 }
 943         } else {
 944                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 945                         resp.response_length += sizeof(resp.tso_caps);
 946                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 947                         resp.response_length += sizeof(resp.rss_caps);
 948         }
 949
 950         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 951                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 952                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 953         }
 954
 955         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 956             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 957             raw_support)
 958                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 959
 960         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 961             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 962                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 963
 964         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 965             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 966             raw_support) {
 967                 /* Legacy bit to support old userspace libraries */
 968                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 969                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 970         }
 971
 972         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 973                 props->max_dm_size =
 974                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 975         }
 976
 977         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 978                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 979
 980         if (MLX5_CAP_GEN(mdev, end_pad))
 981                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 982
 983         props->vendor_part_id      = mdev->pdev->device;
 984         props->hw_ver              = mdev->pdev->revision;
 985
 986         props->max_mr_size         = ~0ull;
 987         props->page_size_cap       = ~(min_page_size - 1);
 988         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 989         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 990         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 991                      sizeof(struct mlx5_wqe_data_seg);
 992         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 993         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 994                      sizeof(struct mlx5_wqe_raddr_seg)) /
 995                 sizeof(struct mlx5_wqe_data_seg);
 996         props->max_send_sge = max_sq_sg;
 997         props->max_recv_sge = max_rq_sg;
 998         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 999         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
1000         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
1001         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1002         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1003         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1004         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1005         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1006         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1007         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
1008         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
1009         props->max_srq_sge         = max_rq_sg - 1;
1010         props->max_fast_reg_page_list_len =
1011                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
1012         props->max_pi_fast_reg_page_list_len =
1013                 props->max_fast_reg_page_list_len / 2;
1014         get_atomic_caps_qp(dev, props);
1015         props->masked_atomic_cap   = IB_ATOMIC_NONE;
1016         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1017         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1018         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1019                                            props->max_mcast_grp;
1020         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
1021         props->max_ah = INT_MAX;
1022         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1023         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1024
1025         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1026                 if (MLX5_CAP_GEN(mdev, pg))
1027                         props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1028                 props->odp_caps = dev->odp_caps;
1029         }
1030
1031         if (MLX5_CAP_GEN(mdev, cd))
1032                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1033
1034         if (!mlx5_core_is_pf(mdev))
1035                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1036
1037         if (mlx5_ib_port_link_layer(ibdev, 1) ==
1038             IB_LINK_LAYER_ETHERNET && raw_support) {
1039                 props->rss_caps.max_rwq_indirection_tables =
1040                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1041                 props->rss_caps.max_rwq_indirection_table_size =
1042                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1043                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1044                 props->max_wq_type_rq =
1045                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1046         }
1047
1048         if (MLX5_CAP_GEN(mdev, tag_matching)) {
1049                 props->tm_caps.max_num_tags =
1050                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1051                 props->tm_caps.max_ops =
1052                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1053                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1054         }
1055
1056         if (MLX5_CAP_GEN(mdev, tag_matching) &&
1057             MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1058                 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1059                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1060         }
1061
1062         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1063                 props->cq_caps.max_cq_moderation_count =
1064                                                 MLX5_MAX_CQ_COUNT;
1065                 props->cq_caps.max_cq_moderation_period =
1066                                                 MLX5_MAX_CQ_PERIOD;
1067         }
1068
1069         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
1070                 resp.response_length += sizeof(resp.cqe_comp_caps);
1071
1072                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1073                         resp.cqe_comp_caps.max_num =
1074                                 MLX5_CAP_GEN(dev->mdev,
1075                                              cqe_compression_max_num);
1076
1077                         resp.cqe_comp_caps.supported_format =
1078                                 MLX5_IB_CQE_RES_FORMAT_HASH |
1079                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
1080
1081                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1082                                 resp.cqe_comp_caps.supported_format |=
1083                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1084                 }
1085         }
1086
1087         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1088             raw_support) {
1089                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1090                     MLX5_CAP_GEN(mdev, qos)) {
1091                         resp.packet_pacing_caps.qp_rate_limit_max =
1092                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1093                         resp.packet_pacing_caps.qp_rate_limit_min =
1094                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1095                         resp.packet_pacing_caps.supported_qpts |=
1096                                 1 << IB_QPT_RAW_PACKET;
1097                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1098                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1099                                 resp.packet_pacing_caps.cap_flags |=
1100                                         MLX5_IB_PP_SUPPORT_BURST;
1101                 }
1102                 resp.response_length += sizeof(resp.packet_pacing_caps);
1103         }
1104
1105         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1106                         uhw->outlen)) {
1107                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1108                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1109                                 MLX5_IB_ALLOW_MPW;
1110
1111                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1112                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1113                                 MLX5_IB_SUPPORT_EMPW;
1114
1115                 resp.response_length +=
1116                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1117         }
1118
1119         if (field_avail(typeof(resp), flags, uhw->outlen)) {
1120                 resp.response_length += sizeof(resp.flags);
1121
1122                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1123                         resp.flags |=
1124                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1125
1126                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1127                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1128                 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1129                         resp.flags |=
1130                                 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1131
1132                 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1133         }
1134
1135         if (field_avail(typeof(resp), sw_parsing_caps,
1136                         uhw->outlen)) {
1137                 resp.response_length += sizeof(resp.sw_parsing_caps);
1138                 if (MLX5_CAP_ETH(mdev, swp)) {
1139                         resp.sw_parsing_caps.sw_parsing_offloads |=
1140                                 MLX5_IB_SW_PARSING;
1141
1142                         if (MLX5_CAP_ETH(mdev, swp_csum))
1143                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1144                                         MLX5_IB_SW_PARSING_CSUM;
1145
1146                         if (MLX5_CAP_ETH(mdev, swp_lso))
1147                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1148                                         MLX5_IB_SW_PARSING_LSO;
1149
1150                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1151                                 resp.sw_parsing_caps.supported_qpts =
1152                                         BIT(IB_QPT_RAW_PACKET);
1153                 }
1154         }
1155
1156         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1157             raw_support) {
1158                 resp.response_length += sizeof(resp.striding_rq_caps);
1159                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1160                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1161                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1162                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1163                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1164                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1165                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1166                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1167                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1168                         resp.striding_rq_caps.supported_qpts =
1169                                 BIT(IB_QPT_RAW_PACKET);
1170                 }
1171         }
1172
1173         if (field_avail(typeof(resp), tunnel_offloads_caps,
1174                         uhw->outlen)) {
1175                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1176                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1177                         resp.tunnel_offloads_caps |=
1178                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1179                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1180                         resp.tunnel_offloads_caps |=
1181                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1182                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1183                         resp.tunnel_offloads_caps |=
1184                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1185                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1186                     MLX5_FLEX_PROTO_CW_MPLS_GRE)
1187                         resp.tunnel_offloads_caps |=
1188                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1189                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1190                     MLX5_FLEX_PROTO_CW_MPLS_UDP)
1191                         resp.tunnel_offloads_caps |=
1192                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1193         }
1194
1195         if (uhw->outlen) {
1196                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1197
1198                 if (err)
1199                         return err;
1200         }
1201
1202         return 0;
1203 }
1204
1205 enum mlx5_ib_width {
1206         MLX5_IB_WIDTH_1X        = 1 << 0,
1207         MLX5_IB_WIDTH_2X        = 1 << 1,
1208         MLX5_IB_WIDTH_4X        = 1 << 2,
1209         MLX5_IB_WIDTH_8X        = 1 << 3,
1210         MLX5_IB_WIDTH_12X       = 1 << 4
1211 };
1212
1213 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1214                                   u8 *ib_width)
1215 {
1216         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1217
1218         if (active_width & MLX5_IB_WIDTH_1X)
1219                 *ib_width = IB_WIDTH_1X;
1220         else if (active_width & MLX5_IB_WIDTH_2X)
1221                 *ib_width = IB_WIDTH_2X;
1222         else if (active_width & MLX5_IB_WIDTH_4X)
1223                 *ib_width = IB_WIDTH_4X;
1224         else if (active_width & MLX5_IB_WIDTH_8X)
1225                 *ib_width = IB_WIDTH_8X;
1226         else if (active_width & MLX5_IB_WIDTH_12X)
1227                 *ib_width = IB_WIDTH_12X;
1228         else {
1229                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1230                             (int)active_width);
1231                 *ib_width = IB_WIDTH_4X;
1232         }
1233
1234         return;
1235 }
1236
1237 static int mlx5_mtu_to_ib_mtu(int mtu)
1238 {
1239         switch (mtu) {
1240         case 256: return 1;
1241         case 512: return 2;
1242         case 1024: return 3;
1243         case 2048: return 4;
1244         case 4096: return 5;
1245         default:
1246                 pr_warn("invalid mtu\n");
1247                 return -1;
1248         }
1249 }
1250
1251 enum ib_max_vl_num {
1252         __IB_MAX_VL_0           = 1,
1253         __IB_MAX_VL_0_1         = 2,
1254         __IB_MAX_VL_0_3         = 3,
1255         __IB_MAX_VL_0_7         = 4,
1256         __IB_MAX_VL_0_14        = 5,
1257 };
1258
1259 enum mlx5_vl_hw_cap {
1260         MLX5_VL_HW_0    = 1,
1261         MLX5_VL_HW_0_1  = 2,
1262         MLX5_VL_HW_0_2  = 3,
1263         MLX5_VL_HW_0_3  = 4,
1264         MLX5_VL_HW_0_4  = 5,
1265         MLX5_VL_HW_0_5  = 6,
1266         MLX5_VL_HW_0_6  = 7,
1267         MLX5_VL_HW_0_7  = 8,
1268         MLX5_VL_HW_0_14 = 15
1269 };
1270
1271 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1272                                 u8 *max_vl_num)
1273 {
1274         switch (vl_hw_cap) {
1275         case MLX5_VL_HW_0:
1276                 *max_vl_num = __IB_MAX_VL_0;
1277                 break;
1278         case MLX5_VL_HW_0_1:
1279                 *max_vl_num = __IB_MAX_VL_0_1;
1280                 break;
1281         case MLX5_VL_HW_0_3:
1282                 *max_vl_num = __IB_MAX_VL_0_3;
1283                 break;
1284         case MLX5_VL_HW_0_7:
1285                 *max_vl_num = __IB_MAX_VL_0_7;
1286                 break;
1287         case MLX5_VL_HW_0_14:
1288                 *max_vl_num = __IB_MAX_VL_0_14;
1289                 break;
1290
1291         default:
1292                 return -EINVAL;
1293         }
1294
1295         return 0;
1296 }
1297
1298 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1299                                struct ib_port_attr *props)
1300 {
1301         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1302         struct mlx5_core_dev *mdev = dev->mdev;
1303         struct mlx5_hca_vport_context *rep;
1304         u16 max_mtu;
1305         u16 oper_mtu;
1306         int err;
1307         u8 ib_link_width_oper;
1308         u8 vl_hw_cap;
1309
1310         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1311         if (!rep) {
1312                 err = -ENOMEM;
1313                 goto out;
1314         }
1315
1316         /* props being zeroed by the caller, avoid zeroing it here */
1317
1318         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1319         if (err)
1320                 goto out;
1321
1322         props->lid              = rep->lid;
1323         props->lmc              = rep->lmc;
1324         props->sm_lid           = rep->sm_lid;
1325         props->sm_sl            = rep->sm_sl;
1326         props->state            = rep->vport_state;
1327         props->phys_state       = rep->port_physical_state;
1328         props->port_cap_flags   = rep->cap_mask1;
1329         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1330         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1331         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1332         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1333         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1334         props->subnet_timeout   = rep->subnet_timeout;
1335         props->init_type_reply  = rep->init_type_reply;
1336
1337         if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1338                 props->port_cap_flags2 = rep->cap_mask2;
1339
1340         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1341         if (err)
1342                 goto out;
1343
1344         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1345
1346         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1347         if (err)
1348                 goto out;
1349
1350         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1351
1352         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1353
1354         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1355
1356         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1357
1358         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1359         if (err)
1360                 goto out;
1361
1362         err = translate_max_vl_num(ibdev, vl_hw_cap,
1363                                    &props->max_vl_num);
1364 out:
1365         kfree(rep);
1366         return err;
1367 }
1368
1369 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1370                        struct ib_port_attr *props)
1371 {
1372         unsigned int count;
1373         int ret;
1374
1375         switch (mlx5_get_vport_access_method(ibdev)) {
1376         case MLX5_VPORT_ACCESS_METHOD_MAD:
1377                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1378                 break;
1379
1380         case MLX5_VPORT_ACCESS_METHOD_HCA:
1381                 ret = mlx5_query_hca_port(ibdev, port, props);
1382                 break;
1383
1384         case MLX5_VPORT_ACCESS_METHOD_NIC:
1385                 ret = mlx5_query_port_roce(ibdev, port, props);
1386                 break;
1387
1388         default:
1389                 ret = -EINVAL;
1390         }
1391
1392         if (!ret && props) {
1393                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1394                 struct mlx5_core_dev *mdev;
1395                 bool put_mdev = true;
1396
1397                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1398                 if (!mdev) {
1399                         /* If the port isn't affiliated yet query the master.
1400                          * The master and slave will have the same values.
1401                          */
1402                         mdev = dev->mdev;
1403                         port = 1;
1404                         put_mdev = false;
1405                 }
1406                 count = mlx5_core_reserved_gids_count(mdev);
1407                 if (put_mdev)
1408                         mlx5_ib_put_native_port_mdev(dev, port);
1409                 props->gid_tbl_len -= count;
1410         }
1411         return ret;
1412 }
1413
1414 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1415                                   struct ib_port_attr *props)
1416 {
1417         int ret;
1418
1419         /* Only link layer == ethernet is valid for representors
1420          * and we always use port 1
1421          */
1422         ret = mlx5_query_port_roce(ibdev, port, props);
1423         if (ret || !props)
1424                 return ret;
1425
1426         /* We don't support GIDS */
1427         props->gid_tbl_len = 0;
1428
1429         return ret;
1430 }
1431
1432 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1433                              union ib_gid *gid)
1434 {
1435         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1436         struct mlx5_core_dev *mdev = dev->mdev;
1437
1438         switch (mlx5_get_vport_access_method(ibdev)) {
1439         case MLX5_VPORT_ACCESS_METHOD_MAD:
1440                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1441
1442         case MLX5_VPORT_ACCESS_METHOD_HCA:
1443                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1444
1445         default:
1446                 return -EINVAL;
1447         }
1448
1449 }
1450
1451 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1452                                    u16 index, u16 *pkey)
1453 {
1454         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1455         struct mlx5_core_dev *mdev;
1456         bool put_mdev = true;
1457         u8 mdev_port_num;
1458         int err;
1459
1460         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1461         if (!mdev) {
1462                 /* The port isn't affiliated yet, get the PKey from the master
1463                  * port. For RoCE the PKey tables will be the same.
1464                  */
1465                 put_mdev = false;
1466                 mdev = dev->mdev;
1467                 mdev_port_num = 1;
1468         }
1469
1470         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1471                                         index, pkey);
1472         if (put_mdev)
1473                 mlx5_ib_put_native_port_mdev(dev, port);
1474
1475         return err;
1476 }
1477
1478 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1479                               u16 *pkey)
1480 {
1481         switch (mlx5_get_vport_access_method(ibdev)) {
1482         case MLX5_VPORT_ACCESS_METHOD_MAD:
1483                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1484
1485         case MLX5_VPORT_ACCESS_METHOD_HCA:
1486         case MLX5_VPORT_ACCESS_METHOD_NIC:
1487                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1488         default:
1489                 return -EINVAL;
1490         }
1491 }
1492
1493 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1494                                  struct ib_device_modify *props)
1495 {
1496         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1497         struct mlx5_reg_node_desc in;
1498         struct mlx5_reg_node_desc out;
1499         int err;
1500
1501         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1502                 return -EOPNOTSUPP;
1503
1504         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1505                 return 0;
1506
1507         /*
1508          * If possible, pass node desc to FW, so it can generate
1509          * a 144 trap.  If cmd fails, just ignore.
1510          */
1511         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1512         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1513                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1514         if (err)
1515                 return err;
1516
1517         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1518
1519         return err;
1520 }
1521
1522 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1523                                 u32 value)
1524 {
1525         struct mlx5_hca_vport_context ctx = {};
1526         struct mlx5_core_dev *mdev;
1527         u8 mdev_port_num;
1528         int err;
1529
1530         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1531         if (!mdev)
1532                 return -ENODEV;
1533
1534         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1535         if (err)
1536                 goto out;
1537
1538         if (~ctx.cap_mask1_perm & mask) {
1539                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1540                              mask, ctx.cap_mask1_perm);
1541                 err = -EINVAL;
1542                 goto out;
1543         }
1544
1545         ctx.cap_mask1 = value;
1546         ctx.cap_mask1_perm = mask;
1547         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1548                                                  0, &ctx);
1549
1550 out:
1551         mlx5_ib_put_native_port_mdev(dev, port_num);
1552
1553         return err;
1554 }
1555
1556 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1557                                struct ib_port_modify *props)
1558 {
1559         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1560         struct ib_port_attr attr;
1561         u32 tmp;
1562         int err;
1563         u32 change_mask;
1564         u32 value;
1565         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1566                       IB_LINK_LAYER_INFINIBAND);
1567
1568         /* CM layer calls ib_modify_port() regardless of the link layer. For
1569          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1570          */
1571         if (!is_ib)
1572                 return 0;
1573
1574         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1575                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1576                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1577                 return set_port_caps_atomic(dev, port, change_mask, value);
1578         }
1579
1580         mutex_lock(&dev->cap_mask_mutex);
1581
1582         err = ib_query_port(ibdev, port, &attr);
1583         if (err)
1584                 goto out;
1585
1586         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1587                 ~props->clr_port_cap_mask;
1588
1589         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1590
1591 out:
1592         mutex_unlock(&dev->cap_mask_mutex);
1593         return err;
1594 }
1595
1596 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1597 {
1598         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1599                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1600 }
1601
1602 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1603 {
1604         /* Large page with non 4k uar support might limit the dynamic size */
1605         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1606                 return MLX5_MIN_DYN_BFREGS;
1607
1608         return MLX5_MAX_DYN_BFREGS;
1609 }
1610
1611 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1612                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1613                              struct mlx5_bfreg_info *bfregi)
1614 {
1615         int uars_per_sys_page;
1616         int bfregs_per_sys_page;
1617         int ref_bfregs = req->total_num_bfregs;
1618
1619         if (req->total_num_bfregs == 0)
1620                 return -EINVAL;
1621
1622         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1623         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1624
1625         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1626                 return -ENOMEM;
1627
1628         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1629         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1630         /* This holds the required static allocation asked by the user */
1631         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1632         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1633                 return -EINVAL;
1634
1635         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1636         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1637         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1638         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1639
1640         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1641                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1642                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1643                     req->total_num_bfregs, bfregi->total_num_bfregs,
1644                     bfregi->num_sys_pages);
1645
1646         return 0;
1647 }
1648
1649 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1650 {
1651         struct mlx5_bfreg_info *bfregi;
1652         int err;
1653         int i;
1654
1655         bfregi = &context->bfregi;
1656         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1657                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1658                 if (err)
1659                         goto error;
1660
1661                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1662         }
1663
1664         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1665                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1666
1667         return 0;
1668
1669 error:
1670         for (--i; i >= 0; i--)
1671                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1672                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1673
1674         return err;
1675 }
1676
1677 static void deallocate_uars(struct mlx5_ib_dev *dev,
1678                             struct mlx5_ib_ucontext *context)
1679 {
1680         struct mlx5_bfreg_info *bfregi;
1681         int i;
1682
1683         bfregi = &context->bfregi;
1684         for (i = 0; i < bfregi->num_sys_pages; i++)
1685                 if (i < bfregi->num_static_sys_pages ||
1686                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1687                         mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1688 }
1689
1690 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1691 {
1692         int err = 0;
1693
1694         mutex_lock(&dev->lb.mutex);
1695         if (td)
1696                 dev->lb.user_td++;
1697         if (qp)
1698                 dev->lb.qps++;
1699
1700         if (dev->lb.user_td == 2 ||
1701             dev->lb.qps == 1) {
1702                 if (!dev->lb.enabled) {
1703                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1704                         dev->lb.enabled = true;
1705                 }
1706         }
1707
1708         mutex_unlock(&dev->lb.mutex);
1709
1710         return err;
1711 }
1712
1713 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1714 {
1715         mutex_lock(&dev->lb.mutex);
1716         if (td)
1717                 dev->lb.user_td--;
1718         if (qp)
1719                 dev->lb.qps--;
1720
1721         if (dev->lb.user_td == 1 &&
1722             dev->lb.qps == 0) {
1723                 if (dev->lb.enabled) {
1724                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1725                         dev->lb.enabled = false;
1726                 }
1727         }
1728
1729         mutex_unlock(&dev->lb.mutex);
1730 }
1731
1732 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1733                                           u16 uid)
1734 {
1735         int err;
1736
1737         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1738                 return 0;
1739
1740         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1741         if (err)
1742                 return err;
1743
1744         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1745             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1746              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1747                 return err;
1748
1749         return mlx5_ib_enable_lb(dev, true, false);
1750 }
1751
1752 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1753                                              u16 uid)
1754 {
1755         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1756                 return;
1757
1758         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1759
1760         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1761             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1762              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1763                 return;
1764
1765         mlx5_ib_disable_lb(dev, true, false);
1766 }
1767
1768 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1769                                   struct ib_udata *udata)
1770 {
1771         struct ib_device *ibdev = uctx->device;
1772         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1773         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1774         struct mlx5_ib_alloc_ucontext_resp resp = {};
1775         struct mlx5_core_dev *mdev = dev->mdev;
1776         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1777         struct mlx5_bfreg_info *bfregi;
1778         int ver;
1779         int err;
1780         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1781                                      max_cqe_version);
1782         u32 dump_fill_mkey;
1783         bool lib_uar_4k;
1784
1785         if (!dev->ib_active)
1786                 return -EAGAIN;
1787
1788         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1789                 ver = 0;
1790         else if (udata->inlen >= min_req_v2)
1791                 ver = 2;
1792         else
1793                 return -EINVAL;
1794
1795         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1796         if (err)
1797                 return err;
1798
1799         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1800                 return -EOPNOTSUPP;
1801
1802         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1803                 return -EOPNOTSUPP;
1804
1805         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1806                                     MLX5_NON_FP_BFREGS_PER_UAR);
1807         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1808                 return -EINVAL;
1809
1810         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1811         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1812                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1813         resp.cache_line_size = cache_line_size();
1814         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1815         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1816         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1817         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1818         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1819         resp.cqe_version = min_t(__u8,
1820                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1821                                  req.max_cqe_version);
1822         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1823                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1824         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1825                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1826         resp.response_length = min(offsetof(typeof(resp), response_length) +
1827                                    sizeof(resp.response_length), udata->outlen);
1828
1829         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1830                 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1831                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1832                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1833                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1834                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1835                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1836                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1837                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1838                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1839         }
1840
1841         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1842         bfregi = &context->bfregi;
1843
1844         /* updates req->total_num_bfregs */
1845         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1846         if (err)
1847                 goto out_ctx;
1848
1849         mutex_init(&bfregi->lock);
1850         bfregi->lib_uar_4k = lib_uar_4k;
1851         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1852                                 GFP_KERNEL);
1853         if (!bfregi->count) {
1854                 err = -ENOMEM;
1855                 goto out_ctx;
1856         }
1857
1858         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1859                                     sizeof(*bfregi->sys_pages),
1860                                     GFP_KERNEL);
1861         if (!bfregi->sys_pages) {
1862                 err = -ENOMEM;
1863                 goto out_count;
1864         }
1865
1866         err = allocate_uars(dev, context);
1867         if (err)
1868                 goto out_sys_pages;
1869
1870         if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING)
1871                 context->ibucontext.invalidate_range =
1872                         &mlx5_ib_invalidate_range;
1873
1874         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1875                 err = mlx5_ib_devx_create(dev, true);
1876                 if (err < 0)
1877                         goto out_uars;
1878                 context->devx_uid = err;
1879         }
1880
1881         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1882                                              context->devx_uid);
1883         if (err)
1884                 goto out_devx;
1885
1886         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1887                 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1888                 if (err)
1889                         goto out_mdev;
1890         }
1891
1892         INIT_LIST_HEAD(&context->db_page_list);
1893         mutex_init(&context->db_page_mutex);
1894
1895         resp.tot_bfregs = req.total_num_bfregs;
1896         resp.num_ports = dev->num_ports;
1897
1898         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1899                 resp.response_length += sizeof(resp.cqe_version);
1900
1901         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1902                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1903                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1904                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1905         }
1906
1907         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1908                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1909                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1910                         resp.eth_min_inline++;
1911                 }
1912                 resp.response_length += sizeof(resp.eth_min_inline);
1913         }
1914
1915         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1916                 if (mdev->clock_info)
1917                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1918                 resp.response_length += sizeof(resp.clock_info_versions);
1919         }
1920
1921         /*
1922          * We don't want to expose information from the PCI bar that is located
1923          * after 4096 bytes, so if the arch only supports larger pages, let's
1924          * pretend we don't support reading the HCA's core clock. This is also
1925          * forced by mmap function.
1926          */
1927         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1928                 if (PAGE_SIZE <= 4096) {
1929                         resp.comp_mask |=
1930                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1931                         resp.hca_core_clock_offset =
1932                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1933                 }
1934                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1935         }
1936
1937         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1938                 resp.response_length += sizeof(resp.log_uar_size);
1939
1940         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1941                 resp.response_length += sizeof(resp.num_uars_per_page);
1942
1943         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1944                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1945                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1946         }
1947
1948         if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1949                 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1950                         resp.dump_fill_mkey = dump_fill_mkey;
1951                         resp.comp_mask |=
1952                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1953                 }
1954                 resp.response_length += sizeof(resp.dump_fill_mkey);
1955         }
1956
1957         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1958         if (err)
1959                 goto out_mdev;
1960
1961         bfregi->ver = ver;
1962         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1963         context->cqe_version = resp.cqe_version;
1964         context->lib_caps = req.lib_caps;
1965         print_lib_caps(dev, context->lib_caps);
1966
1967         if (dev->lag_active) {
1968                 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
1969
1970                 atomic_set(&context->tx_port_affinity,
1971                            atomic_add_return(
1972                                    1, &dev->port[port].roce.tx_port_affinity));
1973         }
1974
1975         return 0;
1976
1977 out_mdev:
1978         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1979 out_devx:
1980         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1981                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1982
1983 out_uars:
1984         deallocate_uars(dev, context);
1985
1986 out_sys_pages:
1987         kfree(bfregi->sys_pages);
1988
1989 out_count:
1990         kfree(bfregi->count);
1991
1992 out_ctx:
1993         return err;
1994 }
1995
1996 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1997 {
1998         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1999         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2000         struct mlx5_bfreg_info *bfregi;
2001
2002         /* All umem's must be destroyed before destroying the ucontext. */
2003         mutex_lock(&ibcontext->per_mm_list_lock);
2004         WARN_ON(!list_empty(&ibcontext->per_mm_list));
2005         mutex_unlock(&ibcontext->per_mm_list_lock);
2006
2007         bfregi = &context->bfregi;
2008         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2009
2010         if (context->devx_uid)
2011                 mlx5_ib_devx_destroy(dev, context->devx_uid);
2012
2013         deallocate_uars(dev, context);
2014         kfree(bfregi->sys_pages);
2015         kfree(bfregi->count);
2016 }
2017
2018 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2019                                  int uar_idx)
2020 {
2021         int fw_uars_per_page;
2022
2023         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2024
2025         return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2026 }
2027
2028 static int get_command(unsigned long offset)
2029 {
2030         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2031 }
2032
2033 static int get_arg(unsigned long offset)
2034 {
2035         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2036 }
2037
2038 static int get_index(unsigned long offset)
2039 {
2040         return get_arg(offset);
2041 }
2042
2043 /* Index resides in an extra byte to enable larger values than 255 */
2044 static int get_extended_index(unsigned long offset)
2045 {
2046         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2047 }
2048
2049
2050 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2051 {
2052 }
2053
2054 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2055 {
2056         switch (cmd) {
2057         case MLX5_IB_MMAP_WC_PAGE:
2058                 return "WC";
2059         case MLX5_IB_MMAP_REGULAR_PAGE:
2060                 return "best effort WC";
2061         case MLX5_IB_MMAP_NC_PAGE:
2062                 return "NC";
2063         case MLX5_IB_MMAP_DEVICE_MEM:
2064                 return "Device Memory";
2065         default:
2066                 return NULL;
2067         }
2068 }
2069
2070 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2071                                         struct vm_area_struct *vma,
2072                                         struct mlx5_ib_ucontext *context)
2073 {
2074         if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2075             !(vma->vm_flags & VM_SHARED))
2076                 return -EINVAL;
2077
2078         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2079                 return -EOPNOTSUPP;
2080
2081         if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2082                 return -EPERM;
2083         vma->vm_flags &= ~VM_MAYWRITE;
2084
2085         if (!dev->mdev->clock_info)
2086                 return -EOPNOTSUPP;
2087
2088         return vm_insert_page(vma, vma->vm_start,
2089                               virt_to_page(dev->mdev->clock_info));
2090 }
2091
2092 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2093                     struct vm_area_struct *vma,
2094                     struct mlx5_ib_ucontext *context)
2095 {
2096         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2097         int err;
2098         unsigned long idx;
2099         phys_addr_t pfn;
2100         pgprot_t prot;
2101         u32 bfreg_dyn_idx = 0;
2102         u32 uar_index;
2103         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2104         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2105                                 bfregi->num_static_sys_pages;
2106
2107         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2108                 return -EINVAL;
2109
2110         if (dyn_uar)
2111                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2112         else
2113                 idx = get_index(vma->vm_pgoff);
2114
2115         if (idx >= max_valid_idx) {
2116                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2117                              idx, max_valid_idx);
2118                 return -EINVAL;
2119         }
2120
2121         switch (cmd) {
2122         case MLX5_IB_MMAP_WC_PAGE:
2123         case MLX5_IB_MMAP_ALLOC_WC:
2124 /* Some architectures don't support WC memory */
2125 #if defined(CONFIG_X86)
2126                 if (!pat_enabled())
2127                         return -EPERM;
2128 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2129                         return -EPERM;
2130 #endif
2131         /* fall through */
2132         case MLX5_IB_MMAP_REGULAR_PAGE:
2133                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2134                 prot = pgprot_writecombine(vma->vm_page_prot);
2135                 break;
2136         case MLX5_IB_MMAP_NC_PAGE:
2137                 prot = pgprot_noncached(vma->vm_page_prot);
2138                 break;
2139         default:
2140                 return -EINVAL;
2141         }
2142
2143         if (dyn_uar) {
2144                 int uars_per_page;
2145
2146                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2147                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2148                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2149                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2150                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2151                         return -EINVAL;
2152                 }
2153
2154                 mutex_lock(&bfregi->lock);
2155                 /* Fail if uar already allocated, first bfreg index of each
2156                  * page holds its count.
2157                  */
2158                 if (bfregi->count[bfreg_dyn_idx]) {
2159                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2160                         mutex_unlock(&bfregi->lock);
2161                         return -EINVAL;
2162                 }
2163
2164                 bfregi->count[bfreg_dyn_idx]++;
2165                 mutex_unlock(&bfregi->lock);
2166
2167                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2168                 if (err) {
2169                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2170                         goto free_bfreg;
2171                 }
2172         } else {
2173                 uar_index = bfregi->sys_pages[idx];
2174         }
2175
2176         pfn = uar_index2pfn(dev, uar_index);
2177         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2178
2179         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2180                                 prot);
2181         if (err) {
2182                 mlx5_ib_err(dev,
2183                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2184                             err, mmap_cmd2str(cmd));
2185                 goto err;
2186         }
2187
2188         if (dyn_uar)
2189                 bfregi->sys_pages[idx] = uar_index;
2190         return 0;
2191
2192 err:
2193         if (!dyn_uar)
2194                 return err;
2195
2196         mlx5_cmd_free_uar(dev->mdev, idx);
2197
2198 free_bfreg:
2199         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2200
2201         return err;
2202 }
2203
2204 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2205 {
2206         struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2207         struct mlx5_ib_dev *dev = to_mdev(context->device);
2208         u16 page_idx = get_extended_index(vma->vm_pgoff);
2209         size_t map_size = vma->vm_end - vma->vm_start;
2210         u32 npages = map_size >> PAGE_SHIFT;
2211         phys_addr_t pfn;
2212
2213         if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2214             page_idx + npages)
2215                 return -EINVAL;
2216
2217         pfn = ((dev->mdev->bar_addr +
2218               MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2219               PAGE_SHIFT) +
2220               page_idx;
2221         return rdma_user_mmap_io(context, vma, pfn, map_size,
2222                                  pgprot_writecombine(vma->vm_page_prot));
2223 }
2224
2225 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2226 {
2227         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2228         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2229         unsigned long command;
2230         phys_addr_t pfn;
2231
2232         command = get_command(vma->vm_pgoff);
2233         switch (command) {
2234         case MLX5_IB_MMAP_WC_PAGE:
2235         case MLX5_IB_MMAP_NC_PAGE:
2236         case MLX5_IB_MMAP_REGULAR_PAGE:
2237         case MLX5_IB_MMAP_ALLOC_WC:
2238                 return uar_mmap(dev, command, vma, context);
2239
2240         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2241                 return -ENOSYS;
2242
2243         case MLX5_IB_MMAP_CORE_CLOCK:
2244                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2245                         return -EINVAL;
2246
2247                 if (vma->vm_flags & VM_WRITE)
2248                         return -EPERM;
2249                 vma->vm_flags &= ~VM_MAYWRITE;
2250
2251                 /* Don't expose to user-space information it shouldn't have */
2252                 if (PAGE_SIZE > 4096)
2253                         return -EOPNOTSUPP;
2254
2255                 pfn = (dev->mdev->iseg_base +
2256                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2257                         PAGE_SHIFT;
2258                 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2259                                          PAGE_SIZE,
2260                                          pgprot_noncached(vma->vm_page_prot));
2261         case MLX5_IB_MMAP_CLOCK_INFO:
2262                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2263
2264         case MLX5_IB_MMAP_DEVICE_MEM:
2265                 return dm_mmap(ibcontext, vma);
2266
2267         default:
2268                 return -EINVAL;
2269         }
2270
2271         return 0;
2272 }
2273
2274 static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2275                                         u32 type)
2276 {
2277         switch (type) {
2278         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2279                 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2280                         return -EOPNOTSUPP;
2281                 break;
2282         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2283                 if (!capable(CAP_SYS_RAWIO) ||
2284                     !capable(CAP_NET_RAW))
2285                         return -EPERM;
2286
2287                 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2288                       MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2289                         return -EOPNOTSUPP;
2290                 break;
2291         }
2292
2293         return 0;
2294 }
2295
2296 static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2297                                  struct mlx5_ib_dm *dm,
2298                                  struct ib_dm_alloc_attr *attr,
2299                                  struct uverbs_attr_bundle *attrs)
2300 {
2301         struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2302         u64 start_offset;
2303         u32 page_idx;
2304         int err;
2305
2306         dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2307
2308         err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2309                                    dm->size, attr->alignment);
2310         if (err)
2311                 return err;
2312
2313         page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2314                     MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
2315                     PAGE_SHIFT;
2316
2317         err = uverbs_copy_to(attrs,
2318                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2319                              &page_idx, sizeof(page_idx));
2320         if (err)
2321                 goto err_dealloc;
2322
2323         start_offset = dm->dev_addr & ~PAGE_MASK;
2324         err = uverbs_copy_to(attrs,
2325                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2326                              &start_offset, sizeof(start_offset));
2327         if (err)
2328                 goto err_dealloc;
2329
2330         bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2331                    DIV_ROUND_UP(dm->size, PAGE_SIZE));
2332
2333         return 0;
2334
2335 err_dealloc:
2336         mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2337
2338         return err;
2339 }
2340
2341 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2342                                   struct mlx5_ib_dm *dm,
2343                                   struct ib_dm_alloc_attr *attr,
2344                                   struct uverbs_attr_bundle *attrs,
2345                                   int type)
2346 {
2347         struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2348         u64 act_size;
2349         int err;
2350
2351         /* Allocation size must a multiple of the basic block size
2352          * and a power of 2.
2353          */
2354         act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dm_db->dev));
2355         act_size = roundup_pow_of_two(act_size);
2356
2357         dm->size = act_size;
2358         err = mlx5_cmd_alloc_sw_icm(dm_db, type, act_size,
2359                                     to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2360                                     &dm->icm_dm.obj_id);
2361         if (err)
2362                 return err;
2363
2364         err = uverbs_copy_to(attrs,
2365                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2366                              &dm->dev_addr, sizeof(dm->dev_addr));
2367         if (err)
2368                 mlx5_cmd_dealloc_sw_icm(dm_db, type, dm->size,
2369                                         to_mucontext(ctx)->devx_uid,
2370                                         dm->dev_addr, dm->icm_dm.obj_id);
2371
2372         return err;
2373 }
2374
2375 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2376                                struct ib_ucontext *context,
2377                                struct ib_dm_alloc_attr *attr,
2378                                struct uverbs_attr_bundle *attrs)
2379 {
2380         struct mlx5_ib_dm *dm;
2381         enum mlx5_ib_uapi_dm_type type;
2382         int err;
2383
2384         err = uverbs_get_const_default(&type, attrs,
2385                                        MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2386                                        MLX5_IB_UAPI_DM_TYPE_MEMIC);
2387         if (err)
2388                 return ERR_PTR(err);
2389
2390         mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2391                     type, attr->length, attr->alignment);
2392
2393         err = check_dm_type_support(to_mdev(ibdev), type);
2394         if (err)
2395                 return ERR_PTR(err);
2396
2397         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2398         if (!dm)
2399                 return ERR_PTR(-ENOMEM);
2400
2401         dm->type = type;
2402
2403         switch (type) {
2404         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2405                 err = handle_alloc_dm_memic(context, dm,
2406                                             attr,
2407                                             attrs);
2408                 break;
2409         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2410         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2411                 err = handle_alloc_dm_sw_icm(context, dm, attr, attrs, type);
2412                 break;
2413         default:
2414                 err = -EOPNOTSUPP;
2415         }
2416
2417         if (err)
2418                 goto err_free;
2419
2420         return &dm->ibdm;
2421
2422 err_free:
2423         kfree(dm);
2424         return ERR_PTR(err);
2425 }
2426
2427 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
2428 {
2429         struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2430                 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2431         struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
2432         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2433         u32 page_idx;
2434         int ret;
2435
2436         switch (dm->type) {
2437         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2438                 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2439                 if (ret)
2440                         return ret;
2441
2442                 page_idx = (dm->dev_addr -
2443                             pci_resource_start(dm_db->dev->pdev, 0) -
2444                             MLX5_CAP64_DEV_MEM(dm_db->dev,
2445                                                memic_bar_start_addr)) >>
2446                            PAGE_SHIFT;
2447                 bitmap_clear(ctx->dm_pages, page_idx,
2448                              DIV_ROUND_UP(dm->size, PAGE_SIZE));
2449                 break;
2450         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2451         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2452                 ret = mlx5_cmd_dealloc_sw_icm(dm_db, dm->type, dm->size,
2453                                               ctx->devx_uid, dm->dev_addr,
2454                                               dm->icm_dm.obj_id);
2455                 if (ret)
2456                         return ret;
2457                 break;
2458         default:
2459                 return -EOPNOTSUPP;
2460         }
2461
2462         kfree(dm);
2463
2464         return 0;
2465 }
2466
2467 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2468 {
2469         struct mlx5_ib_pd *pd = to_mpd(ibpd);
2470         struct ib_device *ibdev = ibpd->device;
2471         struct mlx5_ib_alloc_pd_resp resp;
2472         int err;
2473         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2474         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)]   = {};
2475         u16 uid = 0;
2476         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2477                 udata, struct mlx5_ib_ucontext, ibucontext);
2478
2479         uid = context ? context->devx_uid : 0;
2480         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2481         MLX5_SET(alloc_pd_in, in, uid, uid);
2482         err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2483                             out, sizeof(out));
2484         if (err)
2485                 return err;
2486
2487         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2488         pd->uid = uid;
2489         if (udata) {
2490                 resp.pdn = pd->pdn;
2491                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2492                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2493                         return -EFAULT;
2494                 }
2495         }
2496
2497         return 0;
2498 }
2499
2500 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2501 {
2502         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2503         struct mlx5_ib_pd *mpd = to_mpd(pd);
2504
2505         mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2506 }
2507
2508 enum {
2509         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2510         MATCH_CRITERIA_ENABLE_MISC_BIT,
2511         MATCH_CRITERIA_ENABLE_INNER_BIT,
2512         MATCH_CRITERIA_ENABLE_MISC2_BIT
2513 };
2514
2515 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2516         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2517                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2518
2519 static u8 get_match_criteria_enable(u32 *match_criteria)
2520 {
2521         u8 match_criteria_enable;
2522
2523         match_criteria_enable =
2524                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2525                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2526         match_criteria_enable |=
2527                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2528                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2529         match_criteria_enable |=
2530                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2531                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2532         match_criteria_enable |=
2533                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2534                 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2535
2536         return match_criteria_enable;
2537 }
2538
2539 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2540 {
2541         u8 entry_mask;
2542         u8 entry_val;
2543         int err = 0;
2544
2545         if (!mask)
2546                 goto out;
2547
2548         entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2549                               ip_protocol);
2550         entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2551                              ip_protocol);
2552         if (!entry_mask) {
2553                 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2554                 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2555                 goto out;
2556         }
2557         /* Don't override existing ip protocol */
2558         if (mask != entry_mask || val != entry_val)
2559                 err = -EINVAL;
2560 out:
2561         return err;
2562 }
2563
2564 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2565                            bool inner)
2566 {
2567         if (inner) {
2568                 MLX5_SET(fte_match_set_misc,
2569                          misc_c, inner_ipv6_flow_label, mask);
2570                 MLX5_SET(fte_match_set_misc,
2571                          misc_v, inner_ipv6_flow_label, val);
2572         } else {
2573                 MLX5_SET(fte_match_set_misc,
2574                          misc_c, outer_ipv6_flow_label, mask);
2575                 MLX5_SET(fte_match_set_misc,
2576                          misc_v, outer_ipv6_flow_label, val);
2577         }
2578 }
2579
2580 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2581 {
2582         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2583         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2584         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2585         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2586 }
2587
2588 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2589 {
2590         if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2591             !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2592                 return -EOPNOTSUPP;
2593
2594         if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2595             !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2596                 return -EOPNOTSUPP;
2597
2598         if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2599             !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2600                 return -EOPNOTSUPP;
2601
2602         if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2603             !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2604                 return -EOPNOTSUPP;
2605
2606         return 0;
2607 }
2608
2609 #define LAST_ETH_FIELD vlan_tag
2610 #define LAST_IB_FIELD sl
2611 #define LAST_IPV4_FIELD tos
2612 #define LAST_IPV6_FIELD traffic_class
2613 #define LAST_TCP_UDP_FIELD src_port
2614 #define LAST_TUNNEL_FIELD tunnel_id
2615 #define LAST_FLOW_TAG_FIELD tag_id
2616 #define LAST_DROP_FIELD size
2617 #define LAST_COUNTERS_FIELD counters
2618
2619 /* Field is the last supported field */
2620 #define FIELDS_NOT_SUPPORTED(filter, field)\
2621         memchr_inv((void *)&filter.field  +\
2622                    sizeof(filter.field), 0,\
2623                    sizeof(filter) -\
2624                    offsetof(typeof(filter), field) -\
2625                    sizeof(filter.field))
2626
2627 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2628                            bool is_egress,
2629                            struct mlx5_flow_act *action)
2630 {
2631
2632         switch (maction->ib_action.type) {
2633         case IB_FLOW_ACTION_ESP:
2634                 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2635                                       MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2636                         return -EINVAL;
2637                 /* Currently only AES_GCM keymat is supported by the driver */
2638                 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2639                 action->action |= is_egress ?
2640                         MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2641                         MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2642                 return 0;
2643         case IB_FLOW_ACTION_UNSPECIFIED:
2644                 if (maction->flow_action_raw.sub_type ==
2645                     MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2646                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2647                                 return -EINVAL;
2648                         action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2649                         action->modify_id = maction->flow_action_raw.action_id;
2650                         return 0;
2651                 }
2652                 if (maction->flow_action_raw.sub_type ==
2653                     MLX5_IB_FLOW_ACTION_DECAP) {
2654                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2655                                 return -EINVAL;
2656                         action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2657                         return 0;
2658                 }
2659                 if (maction->flow_action_raw.sub_type ==
2660                     MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
2661                         if (action->action &
2662                             MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2663                                 return -EINVAL;
2664                         action->action |=
2665                                 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2666                         action->reformat_id =
2667                                 maction->flow_action_raw.action_id;
2668                         return 0;
2669                 }
2670                 /* fall through */
2671         default:
2672                 return -EOPNOTSUPP;
2673         }
2674 }
2675
2676 static int parse_flow_attr(struct mlx5_core_dev *mdev,
2677                            struct mlx5_flow_spec *spec,
2678                            const union ib_flow_spec *ib_spec,
2679                            const struct ib_flow_attr *flow_attr,
2680                            struct mlx5_flow_act *action, u32 prev_type)
2681 {
2682         struct mlx5_flow_context *flow_context = &spec->flow_context;
2683         u32 *match_c = spec->match_criteria;
2684         u32 *match_v = spec->match_value;
2685         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2686                                            misc_parameters);
2687         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2688                                            misc_parameters);
2689         void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2690                                             misc_parameters_2);
2691         void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2692                                             misc_parameters_2);
2693         void *headers_c;
2694         void *headers_v;
2695         int match_ipv;
2696         int ret;
2697
2698         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2699                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2700                                          inner_headers);
2701                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2702                                          inner_headers);
2703                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2704                                         ft_field_support.inner_ip_version);
2705         } else {
2706                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2707                                          outer_headers);
2708                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2709                                          outer_headers);
2710                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2711                                         ft_field_support.outer_ip_version);
2712         }
2713
2714         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2715         case IB_FLOW_SPEC_ETH:
2716                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2717                         return -EOPNOTSUPP;
2718
2719                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2720                                              dmac_47_16),
2721                                 ib_spec->eth.mask.dst_mac);
2722                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2723                                              dmac_47_16),
2724                                 ib_spec->eth.val.dst_mac);
2725
2726                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2727                                              smac_47_16),
2728                                 ib_spec->eth.mask.src_mac);
2729                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2730                                              smac_47_16),
2731                                 ib_spec->eth.val.src_mac);
2732
2733                 if (ib_spec->eth.mask.vlan_tag) {
2734                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2735                                  cvlan_tag, 1);
2736                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2737                                  cvlan_tag, 1);
2738
2739                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2740                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2741                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2742                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2743
2744                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2745                                  first_cfi,
2746                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2747                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2748                                  first_cfi,
2749                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2750
2751                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2752                                  first_prio,
2753                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2754                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2755                                  first_prio,
2756                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2757                 }
2758                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2759                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2760                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2761                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2762                 break;
2763         case IB_FLOW_SPEC_IPV4:
2764                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2765                         return -EOPNOTSUPP;
2766
2767                 if (match_ipv) {
2768                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2769                                  ip_version, 0xf);
2770                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2771                                  ip_version, MLX5_FS_IPV4_VERSION);
2772                 } else {
2773                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2774                                  ethertype, 0xffff);
2775                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2776                                  ethertype, ETH_P_IP);
2777                 }
2778
2779                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2780                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2781                        &ib_spec->ipv4.mask.src_ip,
2782                        sizeof(ib_spec->ipv4.mask.src_ip));
2783                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2784                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2785                        &ib_spec->ipv4.val.src_ip,
2786                        sizeof(ib_spec->ipv4.val.src_ip));
2787                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2788                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2789                        &ib_spec->ipv4.mask.dst_ip,
2790                        sizeof(ib_spec->ipv4.mask.dst_ip));
2791                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2792                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2793                        &ib_spec->ipv4.val.dst_ip,
2794                        sizeof(ib_spec->ipv4.val.dst_ip));
2795
2796                 set_tos(headers_c, headers_v,
2797                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2798
2799                 if (set_proto(headers_c, headers_v,
2800                               ib_spec->ipv4.mask.proto,
2801                               ib_spec->ipv4.val.proto))
2802                         return -EINVAL;
2803                 break;
2804         case IB_FLOW_SPEC_IPV6:
2805                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2806                         return -EOPNOTSUPP;
2807
2808                 if (match_ipv) {
2809                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2810                                  ip_version, 0xf);
2811                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2812                                  ip_version, MLX5_FS_IPV6_VERSION);
2813                 } else {
2814                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2815                                  ethertype, 0xffff);
2816                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2817                                  ethertype, ETH_P_IPV6);
2818                 }
2819
2820                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2821                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2822                        &ib_spec->ipv6.mask.src_ip,
2823                        sizeof(ib_spec->ipv6.mask.src_ip));
2824                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2825                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2826                        &ib_spec->ipv6.val.src_ip,
2827                        sizeof(ib_spec->ipv6.val.src_ip));
2828                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2829                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2830                        &ib_spec->ipv6.mask.dst_ip,
2831                        sizeof(ib_spec->ipv6.mask.dst_ip));
2832                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2833                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2834                        &ib_spec->ipv6.val.dst_ip,
2835                        sizeof(ib_spec->ipv6.val.dst_ip));
2836
2837                 set_tos(headers_c, headers_v,
2838                         ib_spec->ipv6.mask.traffic_class,
2839                         ib_spec->ipv6.val.traffic_class);
2840
2841                 if (set_proto(headers_c, headers_v,
2842                               ib_spec->ipv6.mask.next_hdr,
2843                               ib_spec->ipv6.val.next_hdr))
2844                         return -EINVAL;
2845
2846                 set_flow_label(misc_params_c, misc_params_v,
2847                                ntohl(ib_spec->ipv6.mask.flow_label),
2848                                ntohl(ib_spec->ipv6.val.flow_label),
2849                                ib_spec->type & IB_FLOW_SPEC_INNER);
2850                 break;
2851         case IB_FLOW_SPEC_ESP:
2852                 if (ib_spec->esp.mask.seq)
2853                         return -EOPNOTSUPP;
2854
2855                 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2856                          ntohl(ib_spec->esp.mask.spi));
2857                 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2858                          ntohl(ib_spec->esp.val.spi));
2859                 break;
2860         case IB_FLOW_SPEC_TCP:
2861                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2862                                          LAST_TCP_UDP_FIELD))
2863                         return -EOPNOTSUPP;
2864
2865                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2866                         return -EINVAL;
2867
2868                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2869                          ntohs(ib_spec->tcp_udp.mask.src_port));
2870                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2871                          ntohs(ib_spec->tcp_udp.val.src_port));
2872
2873                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2874                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2875                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2876                          ntohs(ib_spec->tcp_udp.val.dst_port));
2877                 break;
2878         case IB_FLOW_SPEC_UDP:
2879                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2880                                          LAST_TCP_UDP_FIELD))
2881                         return -EOPNOTSUPP;
2882
2883                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2884                         return -EINVAL;
2885
2886                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2887                          ntohs(ib_spec->tcp_udp.mask.src_port));
2888                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2889                          ntohs(ib_spec->tcp_udp.val.src_port));
2890
2891                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2892                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2893                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2894                          ntohs(ib_spec->tcp_udp.val.dst_port));
2895                 break;
2896         case IB_FLOW_SPEC_GRE:
2897                 if (ib_spec->gre.mask.c_ks_res0_ver)
2898                         return -EOPNOTSUPP;
2899
2900                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2901                         return -EINVAL;
2902
2903                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2904                          0xff);
2905                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2906                          IPPROTO_GRE);
2907
2908                 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2909                          ntohs(ib_spec->gre.mask.protocol));
2910                 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2911                          ntohs(ib_spec->gre.val.protocol));
2912
2913                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2914                                     gre_key.nvgre.hi),
2915                        &ib_spec->gre.mask.key,
2916                        sizeof(ib_spec->gre.mask.key));
2917                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2918                                     gre_key.nvgre.hi),
2919                        &ib_spec->gre.val.key,
2920                        sizeof(ib_spec->gre.val.key));
2921                 break;
2922         case IB_FLOW_SPEC_MPLS:
2923                 switch (prev_type) {
2924                 case IB_FLOW_SPEC_UDP:
2925                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2926                                                    ft_field_support.outer_first_mpls_over_udp),
2927                                                    &ib_spec->mpls.mask.tag))
2928                                 return -EOPNOTSUPP;
2929
2930                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2931                                             outer_first_mpls_over_udp),
2932                                &ib_spec->mpls.val.tag,
2933                                sizeof(ib_spec->mpls.val.tag));
2934                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2935                                             outer_first_mpls_over_udp),
2936                                &ib_spec->mpls.mask.tag,
2937                                sizeof(ib_spec->mpls.mask.tag));
2938                         break;
2939                 case IB_FLOW_SPEC_GRE:
2940                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2941                                                    ft_field_support.outer_first_mpls_over_gre),
2942                                                    &ib_spec->mpls.mask.tag))
2943                                 return -EOPNOTSUPP;
2944
2945                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2946                                             outer_first_mpls_over_gre),
2947                                &ib_spec->mpls.val.tag,
2948                                sizeof(ib_spec->mpls.val.tag));
2949                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2950                                             outer_first_mpls_over_gre),
2951                                &ib_spec->mpls.mask.tag,
2952                                sizeof(ib_spec->mpls.mask.tag));
2953                         break;
2954                 default:
2955                         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2956                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2957                                                            ft_field_support.inner_first_mpls),
2958                                                            &ib_spec->mpls.mask.tag))
2959                                         return -EOPNOTSUPP;
2960
2961                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2962                                                     inner_first_mpls),
2963                                        &ib_spec->mpls.val.tag,
2964                                        sizeof(ib_spec->mpls.val.tag));
2965                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2966                                                     inner_first_mpls),
2967                                        &ib_spec->mpls.mask.tag,
2968                                        sizeof(ib_spec->mpls.mask.tag));
2969                         } else {
2970                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2971                                                            ft_field_support.outer_first_mpls),
2972                                                            &ib_spec->mpls.mask.tag))
2973                                         return -EOPNOTSUPP;
2974
2975                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2976                                                     outer_first_mpls),
2977                                        &ib_spec->mpls.val.tag,
2978                                        sizeof(ib_spec->mpls.val.tag));
2979                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2980                                                     outer_first_mpls),
2981                                        &ib_spec->mpls.mask.tag,
2982                                        sizeof(ib_spec->mpls.mask.tag));
2983                         }
2984                 }
2985                 break;
2986         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2987                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2988                                          LAST_TUNNEL_FIELD))
2989                         return -EOPNOTSUPP;
2990
2991                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2992                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2993                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2994                          ntohl(ib_spec->tunnel.val.tunnel_id));
2995                 break;
2996         case IB_FLOW_SPEC_ACTION_TAG:
2997                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2998                                          LAST_FLOW_TAG_FIELD))
2999                         return -EOPNOTSUPP;
3000                 if (ib_spec->flow_tag.tag_id >= BIT(24))
3001                         return -EINVAL;
3002
3003                 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3004                 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
3005                 break;
3006         case IB_FLOW_SPEC_ACTION_DROP:
3007                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3008                                          LAST_DROP_FIELD))
3009                         return -EOPNOTSUPP;
3010                 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3011                 break;
3012         case IB_FLOW_SPEC_ACTION_HANDLE:
3013                 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3014                         flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
3015                 if (ret)
3016                         return ret;
3017                 break;
3018         case IB_FLOW_SPEC_ACTION_COUNT:
3019                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3020                                          LAST_COUNTERS_FIELD))
3021                         return -EOPNOTSUPP;
3022
3023                 /* for now support only one counters spec per flow */
3024                 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3025                         return -EINVAL;
3026
3027                 action->counters = ib_spec->flow_count.counters;
3028                 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3029                 break;
3030         default:
3031                 return -EINVAL;
3032         }
3033
3034         return 0;
3035 }
3036
3037 /* If a flow could catch both multicast and unicast packets,
3038  * it won't fall into the multicast flow steering table and this rule
3039  * could steal other multicast packets.
3040  */
3041 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
3042 {
3043         union ib_flow_spec *flow_spec;
3044
3045         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
3046             ib_attr->num_of_specs < 1)
3047                 return false;
3048
3049         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3050         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3051                 struct ib_flow_spec_ipv4 *ipv4_spec;
3052
3053                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3054                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3055                         return true;
3056
3057                 return false;
3058         }
3059
3060         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3061                 struct ib_flow_spec_eth *eth_spec;
3062
3063                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3064                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3065                        is_multicast_ether_addr(eth_spec->val.dst_mac);
3066         }
3067
3068         return false;
3069 }
3070
3071 enum valid_spec {
3072         VALID_SPEC_INVALID,
3073         VALID_SPEC_VALID,
3074         VALID_SPEC_NA,
3075 };
3076
3077 static enum valid_spec
3078 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3079                      const struct mlx5_flow_spec *spec,
3080                      const struct mlx5_flow_act *flow_act,
3081                      bool egress)
3082 {
3083         const u32 *match_c = spec->match_criteria;
3084         bool is_crypto =
3085                 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3086                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3087         bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3088         bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3089
3090         /*
3091          * Currently only crypto is supported in egress, when regular egress
3092          * rules would be supported, always return VALID_SPEC_NA.
3093          */
3094         if (!is_crypto)
3095                 return VALID_SPEC_NA;
3096
3097         return is_crypto && is_ipsec &&
3098                 (!egress || (!is_drop &&
3099                              !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
3100                 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3101 }
3102
3103 static bool is_valid_spec(struct mlx5_core_dev *mdev,
3104                           const struct mlx5_flow_spec *spec,
3105                           const struct mlx5_flow_act *flow_act,
3106                           bool egress)
3107 {
3108         /* We curretly only support ipsec egress flow */
3109         return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3110 }
3111
3112 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3113                                const struct ib_flow_attr *flow_attr,
3114                                bool check_inner)
3115 {
3116         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
3117         int match_ipv = check_inner ?
3118                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3119                                         ft_field_support.inner_ip_version) :
3120                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3121                                         ft_field_support.outer_ip_version);
3122         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3123         bool ipv4_spec_valid, ipv6_spec_valid;
3124         unsigned int ip_spec_type = 0;
3125         bool has_ethertype = false;
3126         unsigned int spec_index;
3127         bool mask_valid = true;
3128         u16 eth_type = 0;
3129         bool type_valid;
3130
3131         /* Validate that ethertype is correct */
3132         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3133                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
3134                     ib_spec->eth.mask.ether_type) {
3135                         mask_valid = (ib_spec->eth.mask.ether_type ==
3136                                       htons(0xffff));
3137                         has_ethertype = true;
3138                         eth_type = ntohs(ib_spec->eth.val.ether_type);
3139                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3140                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3141                         ip_spec_type = ib_spec->type;
3142                 }
3143                 ib_spec = (void *)ib_spec + ib_spec->size;
3144         }
3145
3146         type_valid = (!has_ethertype) || (!ip_spec_type);
3147         if (!type_valid && mask_valid) {
3148                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3149                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3150                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3151                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
3152
3153                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3154                              (((eth_type == ETH_P_MPLS_UC) ||
3155                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
3156         }
3157
3158         return type_valid;
3159 }
3160
3161 static bool is_valid_attr(struct mlx5_core_dev *mdev,
3162                           const struct ib_flow_attr *flow_attr)
3163 {
3164         return is_valid_ethertype(mdev, flow_attr, false) &&
3165                is_valid_ethertype(mdev, flow_attr, true);
3166 }
3167
3168 static void put_flow_table(struct mlx5_ib_dev *dev,
3169                            struct mlx5_ib_flow_prio *prio, bool ft_added)
3170 {
3171         prio->refcount -= !!ft_added;
3172         if (!prio->refcount) {
3173                 mlx5_destroy_flow_table(prio->flow_table);
3174                 prio->flow_table = NULL;
3175         }
3176 }
3177
3178 static void counters_clear_description(struct ib_counters *counters)
3179 {
3180         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3181
3182         mutex_lock(&mcounters->mcntrs_mutex);
3183         kfree(mcounters->counters_data);
3184         mcounters->counters_data = NULL;
3185         mcounters->cntrs_max_index = 0;
3186         mutex_unlock(&mcounters->mcntrs_mutex);
3187 }
3188
3189 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3190 {
3191         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3192                                                           struct mlx5_ib_flow_handler,
3193                                                           ibflow);
3194         struct mlx5_ib_flow_handler *iter, *tmp;
3195         struct mlx5_ib_dev *dev = handler->dev;
3196
3197         mutex_lock(&dev->flow_db->lock);
3198
3199         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3200                 mlx5_del_flow_rules(iter->rule);
3201                 put_flow_table(dev, iter->prio, true);
3202                 list_del(&iter->list);
3203                 kfree(iter);
3204         }
3205
3206         mlx5_del_flow_rules(handler->rule);
3207         put_flow_table(dev, handler->prio, true);
3208         if (handler->ibcounters &&
3209             atomic_read(&handler->ibcounters->usecnt) == 1)
3210                 counters_clear_description(handler->ibcounters);
3211
3212         mutex_unlock(&dev->flow_db->lock);
3213         if (handler->flow_matcher)
3214                 atomic_dec(&handler->flow_matcher->usecnt);
3215         kfree(handler);
3216
3217         return 0;
3218 }
3219
3220 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3221 {
3222         priority *= 2;
3223         if (!dont_trap)
3224                 priority++;
3225         return priority;
3226 }
3227
3228 enum flow_table_type {
3229         MLX5_IB_FT_RX,
3230         MLX5_IB_FT_TX
3231 };
3232
3233 #define MLX5_FS_MAX_TYPES        6
3234 #define MLX5_FS_MAX_ENTRIES      BIT(16)
3235
3236 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3237                                            struct mlx5_ib_flow_prio *prio,
3238                                            int priority,
3239                                            int num_entries, int num_groups,
3240                                            u32 flags)
3241 {
3242         struct mlx5_flow_table *ft;
3243
3244         ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3245                                                  num_entries,
3246                                                  num_groups,
3247                                                  0, flags);
3248         if (IS_ERR(ft))
3249                 return ERR_CAST(ft);
3250
3251         prio->flow_table = ft;
3252         prio->refcount = 0;
3253         return prio;
3254 }
3255
3256 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3257                                                 struct ib_flow_attr *flow_attr,
3258                                                 enum flow_table_type ft_type)
3259 {
3260         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3261         struct mlx5_flow_namespace *ns = NULL;
3262         struct mlx5_ib_flow_prio *prio;
3263         struct mlx5_flow_table *ft;
3264         int max_table_size;
3265         int num_entries;
3266         int num_groups;
3267         bool esw_encap;
3268         u32 flags = 0;
3269         int priority;
3270
3271         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3272                                                        log_max_ft_size));
3273         esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3274                 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3275         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3276                 enum mlx5_flow_namespace_type fn_type;
3277
3278                 if (flow_is_multicast_only(flow_attr) &&
3279                     !dont_trap)
3280                         priority = MLX5_IB_FLOW_MCAST_PRIO;
3281                 else
3282                         priority = ib_prio_to_core_prio(flow_attr->priority,
3283                                                         dont_trap);
3284                 if (ft_type == MLX5_IB_FT_RX) {
3285                         fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3286                         prio = &dev->flow_db->prios[priority];
3287                         if (!dev->is_rep && !esw_encap &&
3288                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3289                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3290                         if (!dev->is_rep && !esw_encap &&
3291                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3292                                         reformat_l3_tunnel_to_l2))
3293                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3294                 } else {
3295                         max_table_size =
3296                                 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3297                                                               log_max_ft_size));
3298                         fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3299                         prio = &dev->flow_db->egress_prios[priority];
3300                         if (!dev->is_rep && !esw_encap &&
3301                             MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3302                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3303                 }
3304                 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3305                 num_entries = MLX5_FS_MAX_ENTRIES;
3306                 num_groups = MLX5_FS_MAX_TYPES;
3307         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3308                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3309                 ns = mlx5_get_flow_namespace(dev->mdev,
3310                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
3311                 build_leftovers_ft_param(&priority,
3312                                          &num_entries,
3313                                          &num_groups);
3314                 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3315         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3316                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3317                                         allow_sniffer_and_nic_rx_shared_tir))
3318                         return ERR_PTR(-ENOTSUPP);
3319
3320                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3321                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3322                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3323
3324                 prio = &dev->flow_db->sniffer[ft_type];
3325                 priority = 0;
3326                 num_entries = 1;
3327                 num_groups = 1;
3328         }
3329
3330         if (!ns)
3331                 return ERR_PTR(-ENOTSUPP);
3332
3333         max_table_size = min_t(int, num_entries, max_table_size);
3334
3335         ft = prio->flow_table;
3336         if (!ft)
3337                 return _get_prio(ns, prio, priority, max_table_size, num_groups,
3338                                  flags);
3339
3340         return prio;
3341 }
3342
3343 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3344                             struct mlx5_flow_spec *spec,
3345                             u32 underlay_qpn)
3346 {
3347         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3348                                            spec->match_criteria,
3349                                            misc_parameters);
3350         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3351                                            misc_parameters);
3352
3353         if (underlay_qpn &&
3354             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3355                                       ft_field_support.bth_dst_qp)) {
3356                 MLX5_SET(fte_match_set_misc,
3357                          misc_params_v, bth_dst_qp, underlay_qpn);
3358                 MLX5_SET(fte_match_set_misc,
3359                          misc_params_c, bth_dst_qp, 0xffffff);
3360         }
3361 }
3362
3363 static int read_flow_counters(struct ib_device *ibdev,
3364                               struct mlx5_read_counters_attr *read_attr)
3365 {
3366         struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3367         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3368
3369         return mlx5_fc_query(dev->mdev, fc,
3370                              &read_attr->out[IB_COUNTER_PACKETS],
3371                              &read_attr->out[IB_COUNTER_BYTES]);
3372 }
3373
3374 /* flow counters currently expose two counters packets and bytes */
3375 #define FLOW_COUNTERS_NUM 2
3376 static int counters_set_description(struct ib_counters *counters,
3377                                     enum mlx5_ib_counters_type counters_type,
3378                                     struct mlx5_ib_flow_counters_desc *desc_data,
3379                                     u32 ncounters)
3380 {
3381         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3382         u32 cntrs_max_index = 0;
3383         int i;
3384
3385         if (counters_type != MLX5_IB_COUNTERS_FLOW)
3386                 return -EINVAL;
3387
3388         /* init the fields for the object */
3389         mcounters->type = counters_type;
3390         mcounters->read_counters = read_flow_counters;
3391         mcounters->counters_num = FLOW_COUNTERS_NUM;
3392         mcounters->ncounters = ncounters;
3393         /* each counter entry have both description and index pair */
3394         for (i = 0; i < ncounters; i++) {
3395                 if (desc_data[i].description > IB_COUNTER_BYTES)
3396                         return -EINVAL;
3397
3398                 if (cntrs_max_index <= desc_data[i].index)
3399                         cntrs_max_index = desc_data[i].index + 1;
3400         }
3401
3402         mutex_lock(&mcounters->mcntrs_mutex);
3403         mcounters->counters_data = desc_data;
3404         mcounters->cntrs_max_index = cntrs_max_index;
3405         mutex_unlock(&mcounters->mcntrs_mutex);
3406
3407         return 0;
3408 }
3409
3410 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3411 static int flow_counters_set_data(struct ib_counters *ibcounters,
3412                                   struct mlx5_ib_create_flow *ucmd)
3413 {
3414         struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3415         struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3416         struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3417         bool hw_hndl = false;
3418         int ret = 0;
3419
3420         if (ucmd && ucmd->ncounters_data != 0) {
3421                 cntrs_data = ucmd->data;
3422                 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3423                         return -EINVAL;
3424
3425                 desc_data = kcalloc(cntrs_data->ncounters,
3426                                     sizeof(*desc_data),
3427                                     GFP_KERNEL);
3428                 if (!desc_data)
3429                         return  -ENOMEM;
3430
3431                 if (copy_from_user(desc_data,
3432                                    u64_to_user_ptr(cntrs_data->counters_data),
3433                                    sizeof(*desc_data) * cntrs_data->ncounters)) {
3434                         ret = -EFAULT;
3435                         goto free;
3436                 }
3437         }
3438
3439         if (!mcounters->hw_cntrs_hndl) {
3440                 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3441                         to_mdev(ibcounters->device)->mdev, false);
3442                 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3443                         ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3444                         goto free;
3445                 }
3446                 hw_hndl = true;
3447         }
3448
3449         if (desc_data) {
3450                 /* counters already bound to at least one flow */
3451                 if (mcounters->cntrs_max_index) {
3452                         ret = -EINVAL;
3453                         goto free_hndl;
3454                 }
3455
3456                 ret = counters_set_description(ibcounters,
3457                                                MLX5_IB_COUNTERS_FLOW,
3458                                                desc_data,
3459                                                cntrs_data->ncounters);
3460                 if (ret)
3461                         goto free_hndl;
3462
3463         } else if (!mcounters->cntrs_max_index) {
3464                 /* counters not bound yet, must have udata passed */
3465                 ret = -EINVAL;
3466                 goto free_hndl;
3467         }
3468
3469         return 0;
3470
3471 free_hndl:
3472         if (hw_hndl) {
3473                 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3474                                 mcounters->hw_cntrs_hndl);
3475                 mcounters->hw_cntrs_hndl = NULL;
3476         }
3477 free:
3478         kfree(desc_data);
3479         return ret;
3480 }
3481
3482 static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3483                                          struct mlx5_flow_spec *spec,
3484                                          struct mlx5_eswitch_rep *rep)
3485 {
3486         struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3487         void *misc;
3488
3489         if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3490                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3491                                     misc_parameters_2);
3492
3493                 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3494                          mlx5_eswitch_get_vport_metadata_for_match(esw,
3495                                                                    rep->vport));
3496                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3497                                     misc_parameters_2);
3498
3499                 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
3500         } else {
3501                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3502                                     misc_parameters);
3503
3504                 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3505
3506                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3507                                     misc_parameters);
3508
3509                 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3510         }
3511 }
3512
3513 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3514                                                       struct mlx5_ib_flow_prio *ft_prio,
3515                                                       const struct ib_flow_attr *flow_attr,
3516                                                       struct mlx5_flow_destination *dst,
3517                                                       u32 underlay_qpn,
3518                                                       struct mlx5_ib_create_flow *ucmd)
3519 {
3520         struct mlx5_flow_table  *ft = ft_prio->flow_table;
3521         struct mlx5_ib_flow_handler *handler;
3522         struct mlx5_flow_act flow_act = {};
3523         struct mlx5_flow_spec *spec;
3524         struct mlx5_flow_destination dest_arr[2] = {};
3525         struct mlx5_flow_destination *rule_dst = dest_arr;
3526         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3527         unsigned int spec_index;
3528         u32 prev_type = 0;
3529         int err = 0;
3530         int dest_num = 0;
3531         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3532
3533         if (!is_valid_attr(dev->mdev, flow_attr))
3534                 return ERR_PTR(-EINVAL);
3535
3536         if (dev->is_rep && is_egress)
3537                 return ERR_PTR(-EINVAL);
3538
3539         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3540         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3541         if (!handler || !spec) {
3542                 err = -ENOMEM;
3543                 goto free;
3544         }
3545
3546         INIT_LIST_HEAD(&handler->list);
3547         if (dst) {
3548                 memcpy(&dest_arr[0], dst, sizeof(*dst));
3549                 dest_num++;
3550         }
3551
3552         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3553                 err = parse_flow_attr(dev->mdev, spec,
3554                                       ib_flow, flow_attr, &flow_act,
3555                                       prev_type);
3556                 if (err < 0)
3557                         goto free;
3558
3559                 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3560                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3561         }
3562
3563         if (!flow_is_multicast_only(flow_attr))
3564                 set_underlay_qp(dev, spec, underlay_qpn);
3565
3566         if (dev->is_rep) {
3567                 struct mlx5_eswitch_rep *rep;
3568
3569                 rep = dev->port[flow_attr->port - 1].rep;
3570                 if (!rep) {
3571                         err = -EINVAL;
3572                         goto free;
3573                 }
3574
3575                 mlx5_ib_set_rule_source_port(dev, spec, rep);
3576         }
3577
3578         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3579
3580         if (is_egress &&
3581             !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3582                 err = -EINVAL;
3583                 goto free;
3584         }
3585
3586         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3587                 struct mlx5_ib_mcounters *mcounters;
3588
3589                 err = flow_counters_set_data(flow_act.counters, ucmd);
3590                 if (err)
3591                         goto free;
3592
3593                 mcounters = to_mcounters(flow_act.counters);
3594                 handler->ibcounters = flow_act.counters;
3595                 dest_arr[dest_num].type =
3596                         MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3597                 dest_arr[dest_num].counter_id =
3598                         mlx5_fc_id(mcounters->hw_cntrs_hndl);
3599                 dest_num++;
3600         }
3601
3602         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3603                 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3604                         rule_dst = NULL;
3605                         dest_num = 0;
3606                 }
3607         } else {
3608                 if (is_egress)
3609                         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3610                 else
3611                         flow_act.action |=
3612                                 dest_num ?  MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3613                                         MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3614         }
3615
3616         if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG)  &&
3617             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3618              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3619                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3620                              spec->flow_context.flow_tag, flow_attr->type);
3621                 err = -EINVAL;
3622                 goto free;
3623         }
3624         handler->rule = mlx5_add_flow_rules(ft, spec,
3625                                             &flow_act,
3626                                             rule_dst, dest_num);
3627
3628         if (IS_ERR(handler->rule)) {
3629                 err = PTR_ERR(handler->rule);
3630                 goto free;
3631         }
3632
3633         ft_prio->refcount++;
3634         handler->prio = ft_prio;
3635         handler->dev = dev;
3636
3637         ft_prio->flow_table = ft;
3638 free:
3639         if (err && handler) {
3640                 if (handler->ibcounters &&
3641                     atomic_read(&handler->ibcounters->usecnt) == 1)
3642                         counters_clear_description(handler->ibcounters);
3643                 kfree(handler);
3644         }
3645         kvfree(spec);
3646         return err ? ERR_PTR(err) : handler;
3647 }
3648
3649 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3650                                                      struct mlx5_ib_flow_prio *ft_prio,
3651                                                      const struct ib_flow_attr *flow_attr,
3652                                                      struct mlx5_flow_destination *dst)
3653 {
3654         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3655 }
3656
3657 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3658                                                           struct mlx5_ib_flow_prio *ft_prio,
3659                                                           struct ib_flow_attr *flow_attr,
3660                                                           struct mlx5_flow_destination *dst)
3661 {
3662         struct mlx5_ib_flow_handler *handler_dst = NULL;
3663         struct mlx5_ib_flow_handler *handler = NULL;
3664
3665         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3666         if (!IS_ERR(handler)) {
3667                 handler_dst = create_flow_rule(dev, ft_prio,
3668                                                flow_attr, dst);
3669                 if (IS_ERR(handler_dst)) {
3670                         mlx5_del_flow_rules(handler->rule);
3671                         ft_prio->refcount--;
3672                         kfree(handler);
3673                         handler = handler_dst;
3674                 } else {
3675                         list_add(&handler_dst->list, &handler->list);
3676                 }
3677         }
3678
3679         return handler;
3680 }
3681 enum {
3682         LEFTOVERS_MC,
3683         LEFTOVERS_UC,
3684 };
3685
3686 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3687                                                           struct mlx5_ib_flow_prio *ft_prio,
3688                                                           struct ib_flow_attr *flow_attr,
3689                                                           struct mlx5_flow_destination *dst)
3690 {
3691         struct mlx5_ib_flow_handler *handler_ucast = NULL;
3692         struct mlx5_ib_flow_handler *handler = NULL;
3693
3694         static struct {
3695                 struct ib_flow_attr     flow_attr;
3696                 struct ib_flow_spec_eth eth_flow;
3697         } leftovers_specs[] = {
3698                 [LEFTOVERS_MC] = {
3699                         .flow_attr = {
3700                                 .num_of_specs = 1,
3701                                 .size = sizeof(leftovers_specs[0])
3702                         },
3703                         .eth_flow = {
3704                                 .type = IB_FLOW_SPEC_ETH,
3705                                 .size = sizeof(struct ib_flow_spec_eth),
3706                                 .mask = {.dst_mac = {0x1} },
3707                                 .val =  {.dst_mac = {0x1} }
3708                         }
3709                 },
3710                 [LEFTOVERS_UC] = {
3711                         .flow_attr = {
3712                                 .num_of_specs = 1,
3713                                 .size = sizeof(leftovers_specs[0])
3714                         },
3715                         .eth_flow = {
3716                                 .type = IB_FLOW_SPEC_ETH,
3717                                 .size = sizeof(struct ib_flow_spec_eth),
3718                                 .mask = {.dst_mac = {0x1} },
3719                                 .val = {.dst_mac = {} }
3720                         }
3721                 }
3722         };
3723
3724         handler = create_flow_rule(dev, ft_prio,
3725                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
3726                                    dst);
3727         if (!IS_ERR(handler) &&
3728             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3729                 handler_ucast = create_flow_rule(dev, ft_prio,
3730                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
3731                                                  dst);
3732                 if (IS_ERR(handler_ucast)) {
3733                         mlx5_del_flow_rules(handler->rule);
3734                         ft_prio->refcount--;
3735                         kfree(handler);
3736                         handler = handler_ucast;
3737                 } else {
3738                         list_add(&handler_ucast->list, &handler->list);
3739                 }
3740         }
3741
3742         return handler;
3743 }
3744
3745 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3746                                                         struct mlx5_ib_flow_prio *ft_rx,
3747                                                         struct mlx5_ib_flow_prio *ft_tx,
3748                                                         struct mlx5_flow_destination *dst)
3749 {
3750         struct mlx5_ib_flow_handler *handler_rx;
3751         struct mlx5_ib_flow_handler *handler_tx;
3752         int err;
3753         static const struct ib_flow_attr flow_attr  = {
3754                 .num_of_specs = 0,
3755                 .size = sizeof(flow_attr)
3756         };
3757
3758         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3759         if (IS_ERR(handler_rx)) {
3760                 err = PTR_ERR(handler_rx);
3761                 goto err;
3762         }
3763
3764         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3765         if (IS_ERR(handler_tx)) {
3766                 err = PTR_ERR(handler_tx);
3767                 goto err_tx;
3768         }
3769
3770         list_add(&handler_tx->list, &handler_rx->list);
3771
3772         return handler_rx;
3773
3774 err_tx:
3775         mlx5_del_flow_rules(handler_rx->rule);
3776         ft_rx->refcount--;
3777         kfree(handler_rx);
3778 err:
3779         return ERR_PTR(err);
3780 }
3781
3782 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3783                                            struct ib_flow_attr *flow_attr,
3784                                            int domain,
3785                                            struct ib_udata *udata)
3786 {
3787         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3788         struct mlx5_ib_qp *mqp = to_mqp(qp);
3789         struct mlx5_ib_flow_handler *handler = NULL;
3790         struct mlx5_flow_destination *dst = NULL;
3791         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3792         struct mlx5_ib_flow_prio *ft_prio;
3793         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3794         struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3795         size_t min_ucmd_sz, required_ucmd_sz;
3796         int err;
3797         int underlay_qpn;
3798
3799         if (udata && udata->inlen) {
3800                 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3801                                 sizeof(ucmd_hdr.reserved);
3802                 if (udata->inlen < min_ucmd_sz)
3803                         return ERR_PTR(-EOPNOTSUPP);
3804
3805                 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3806                 if (err)
3807                         return ERR_PTR(err);
3808
3809                 /* currently supports only one counters data */
3810                 if (ucmd_hdr.ncounters_data > 1)
3811                         return ERR_PTR(-EINVAL);
3812
3813                 required_ucmd_sz = min_ucmd_sz +
3814                         sizeof(struct mlx5_ib_flow_counters_data) *
3815                         ucmd_hdr.ncounters_data;
3816                 if (udata->inlen > required_ucmd_sz &&
3817                     !ib_is_udata_cleared(udata, required_ucmd_sz,
3818                                          udata->inlen - required_ucmd_sz))
3819                         return ERR_PTR(-EOPNOTSUPP);
3820
3821                 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3822                 if (!ucmd)
3823                         return ERR_PTR(-ENOMEM);
3824
3825                 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3826                 if (err)
3827                         goto free_ucmd;
3828         }
3829
3830         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3831                 err = -ENOMEM;
3832                 goto free_ucmd;
3833         }
3834
3835         if (domain != IB_FLOW_DOMAIN_USER ||
3836             flow_attr->port > dev->num_ports ||
3837             (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3838                                   IB_FLOW_ATTR_FLAGS_EGRESS))) {
3839                 err = -EINVAL;
3840                 goto free_ucmd;
3841         }
3842
3843         if (is_egress &&
3844             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3845              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3846                 err = -EINVAL;
3847                 goto free_ucmd;
3848         }
3849
3850         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3851         if (!dst) {
3852                 err = -ENOMEM;
3853                 goto free_ucmd;
3854         }
3855
3856         mutex_lock(&dev->flow_db->lock);
3857
3858         ft_prio = get_flow_table(dev, flow_attr,
3859                                  is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3860         if (IS_ERR(ft_prio)) {
3861                 err = PTR_ERR(ft_prio);
3862                 goto unlock;
3863         }
3864         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3865                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3866                 if (IS_ERR(ft_prio_tx)) {
3867                         err = PTR_ERR(ft_prio_tx);
3868                         ft_prio_tx = NULL;
3869                         goto destroy_ft;
3870                 }
3871         }
3872
3873         if (is_egress) {
3874                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3875         } else {
3876                 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3877                 if (mqp->flags & MLX5_IB_QP_RSS)
3878                         dst->tir_num = mqp->rss_qp.tirn;
3879                 else
3880                         dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3881         }
3882
3883         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3884                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3885                         handler = create_dont_trap_rule(dev, ft_prio,
3886                                                         flow_attr, dst);
3887                 } else {
3888                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3889                                         mqp->underlay_qpn : 0;
3890                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3891                                                     dst, underlay_qpn, ucmd);
3892                 }
3893         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3894                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3895                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3896                                                 dst);
3897         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3898                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3899         } else {
3900                 err = -EINVAL;
3901                 goto destroy_ft;
3902         }
3903
3904         if (IS_ERR(handler)) {
3905                 err = PTR_ERR(handler);
3906                 handler = NULL;
3907                 goto destroy_ft;
3908         }
3909
3910         mutex_unlock(&dev->flow_db->lock);
3911         kfree(dst);
3912         kfree(ucmd);
3913
3914         return &handler->ibflow;
3915
3916 destroy_ft:
3917         put_flow_table(dev, ft_prio, false);
3918         if (ft_prio_tx)
3919                 put_flow_table(dev, ft_prio_tx, false);
3920 unlock:
3921         mutex_unlock(&dev->flow_db->lock);
3922         kfree(dst);
3923 free_ucmd:
3924         kfree(ucmd);
3925         return ERR_PTR(err);
3926 }
3927
3928 static struct mlx5_ib_flow_prio *
3929 _get_flow_table(struct mlx5_ib_dev *dev,
3930                 struct mlx5_ib_flow_matcher *fs_matcher,
3931                 bool mcast)
3932 {
3933         struct mlx5_flow_namespace *ns = NULL;
3934         struct mlx5_ib_flow_prio *prio = NULL;
3935         int max_table_size = 0;
3936         bool esw_encap;
3937         u32 flags = 0;
3938         int priority;
3939
3940         if (mcast)
3941                 priority = MLX5_IB_FLOW_MCAST_PRIO;
3942         else
3943                 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3944
3945         esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3946                 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3947         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3948                 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3949                                         log_max_ft_size));
3950                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
3951                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3952                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3953                                               reformat_l3_tunnel_to_l2) &&
3954                     !esw_encap)
3955                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3956         } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3957                 max_table_size = BIT(
3958                         MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
3959                 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
3960                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3961         } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3962                 max_table_size = BIT(
3963                         MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
3964                 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3965                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3966                 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3967                     esw_encap)
3968                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3969                 priority = FDB_BYPASS_PATH;
3970         }
3971
3972         max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
3973
3974         ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
3975         if (!ns)
3976                 return ERR_PTR(-ENOTSUPP);
3977
3978         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3979                 prio = &dev->flow_db->prios[priority];
3980         else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
3981                 prio = &dev->flow_db->egress_prios[priority];
3982         else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3983                 prio = &dev->flow_db->fdb;
3984
3985         if (!prio)
3986                 return ERR_PTR(-EINVAL);
3987
3988         if (prio->flow_table)
3989                 return prio;
3990
3991         return _get_prio(ns, prio, priority, max_table_size,
3992                          MLX5_FS_MAX_TYPES, flags);
3993 }
3994
3995 static struct mlx5_ib_flow_handler *
3996 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
3997                       struct mlx5_ib_flow_prio *ft_prio,
3998                       struct mlx5_flow_destination *dst,
3999                       struct mlx5_ib_flow_matcher  *fs_matcher,
4000                       struct mlx5_flow_context *flow_context,
4001                       struct mlx5_flow_act *flow_act,
4002                       void *cmd_in, int inlen,
4003                       int dst_num)
4004 {
4005         struct mlx5_ib_flow_handler *handler;
4006         struct mlx5_flow_spec *spec;
4007         struct mlx5_flow_table *ft = ft_prio->flow_table;
4008         int err = 0;
4009
4010         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4011         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4012         if (!handler || !spec) {
4013                 err = -ENOMEM;
4014                 goto free;
4015         }
4016
4017         INIT_LIST_HEAD(&handler->list);
4018
4019         memcpy(spec->match_value, cmd_in, inlen);
4020         memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4021                fs_matcher->mask_len);
4022         spec->match_criteria_enable = fs_matcher->match_criteria_enable;
4023         spec->flow_context = *flow_context;
4024
4025         handler->rule = mlx5_add_flow_rules(ft, spec,
4026                                             flow_act, dst, dst_num);
4027
4028         if (IS_ERR(handler->rule)) {
4029                 err = PTR_ERR(handler->rule);
4030                 goto free;
4031         }
4032
4033         ft_prio->refcount++;
4034         handler->prio = ft_prio;
4035         handler->dev = dev;
4036         ft_prio->flow_table = ft;
4037
4038 free:
4039         if (err)
4040                 kfree(handler);
4041         kvfree(spec);
4042         return err ? ERR_PTR(err) : handler;
4043 }
4044
4045 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4046                                 void *match_v)
4047 {
4048         void *match_c;
4049         void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4050         void *dmac, *dmac_mask;
4051         void *ipv4, *ipv4_mask;
4052
4053         if (!(fs_matcher->match_criteria_enable &
4054               (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4055                 return false;
4056
4057         match_c = fs_matcher->matcher_mask.match_params;
4058         match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4059                                            outer_headers);
4060         match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4061                                            outer_headers);
4062
4063         dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4064                             dmac_47_16);
4065         dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4066                                  dmac_47_16);
4067
4068         if (is_multicast_ether_addr(dmac) &&
4069             is_multicast_ether_addr(dmac_mask))
4070                 return true;
4071
4072         ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4073                             dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4074
4075         ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4076                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4077
4078         if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4079             ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4080                 return true;
4081
4082         return false;
4083 }
4084
4085 struct mlx5_ib_flow_handler *
4086 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4087                         struct mlx5_ib_flow_matcher *fs_matcher,
4088                         struct mlx5_flow_context *flow_context,
4089                         struct mlx5_flow_act *flow_act,
4090                         u32 counter_id,
4091                         void *cmd_in, int inlen, int dest_id,
4092                         int dest_type)
4093 {
4094         struct mlx5_flow_destination *dst;
4095         struct mlx5_ib_flow_prio *ft_prio;
4096         struct mlx5_ib_flow_handler *handler;
4097         int dst_num = 0;
4098         bool mcast;
4099         int err;
4100
4101         if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4102                 return ERR_PTR(-EOPNOTSUPP);
4103
4104         if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4105                 return ERR_PTR(-ENOMEM);
4106
4107         dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
4108         if (!dst)
4109                 return ERR_PTR(-ENOMEM);
4110
4111         mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4112         mutex_lock(&dev->flow_db->lock);
4113
4114         ft_prio = _get_flow_table(dev, fs_matcher, mcast);
4115         if (IS_ERR(ft_prio)) {
4116                 err = PTR_ERR(ft_prio);
4117                 goto unlock;
4118         }
4119
4120         if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
4121                 dst[dst_num].type = dest_type;
4122                 dst[dst_num].tir_num = dest_id;
4123                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4124         } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
4125                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4126                 dst[dst_num].ft_num = dest_id;
4127                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4128         } else {
4129                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
4130                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
4131         }
4132
4133         dst_num++;
4134
4135         if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4136                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4137                 dst[dst_num].counter_id = counter_id;
4138                 dst_num++;
4139         }
4140
4141         handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4142                                         flow_context, flow_act,
4143                                         cmd_in, inlen, dst_num);
4144
4145         if (IS_ERR(handler)) {
4146                 err = PTR_ERR(handler);
4147                 goto destroy_ft;
4148         }
4149
4150         mutex_unlock(&dev->flow_db->lock);
4151         atomic_inc(&fs_matcher->usecnt);
4152         handler->flow_matcher = fs_matcher;
4153
4154         kfree(dst);
4155
4156         return handler;
4157
4158 destroy_ft:
4159         put_flow_table(dev, ft_prio, false);
4160 unlock:
4161         mutex_unlock(&dev->flow_db->lock);
4162         kfree(dst);
4163
4164         return ERR_PTR(err);
4165 }
4166
4167 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4168 {
4169         u32 flags = 0;
4170
4171         if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4172                 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4173
4174         return flags;
4175 }
4176
4177 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED      MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4178 static struct ib_flow_action *
4179 mlx5_ib_create_flow_action_esp(struct ib_device *device,
4180                                const struct ib_flow_action_attrs_esp *attr,
4181                                struct uverbs_attr_bundle *attrs)
4182 {
4183         struct mlx5_ib_dev *mdev = to_mdev(device);
4184         struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4185         struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4186         struct mlx5_ib_flow_action *action;
4187         u64 action_flags;
4188         u64 flags;
4189         int err = 0;
4190
4191         err = uverbs_get_flags64(
4192                 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4193                 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4194         if (err)
4195                 return ERR_PTR(err);
4196
4197         flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4198
4199         /* We current only support a subset of the standard features. Only a
4200          * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4201          * (with overlap). Full offload mode isn't supported.
4202          */
4203         if (!attr->keymat || attr->replay || attr->encap ||
4204             attr->spi || attr->seq || attr->tfc_pad ||
4205             attr->hard_limit_pkts ||
4206             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4207                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4208                 return ERR_PTR(-EOPNOTSUPP);
4209
4210         if (attr->keymat->protocol !=
4211             IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4212                 return ERR_PTR(-EOPNOTSUPP);
4213
4214         aes_gcm = &attr->keymat->keymat.aes_gcm;
4215
4216         if (aes_gcm->icv_len != 16 ||
4217             aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4218                 return ERR_PTR(-EOPNOTSUPP);
4219
4220         action = kmalloc(sizeof(*action), GFP_KERNEL);
4221         if (!action)
4222                 return ERR_PTR(-ENOMEM);
4223
4224         action->esp_aes_gcm.ib_flags = attr->flags;
4225         memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4226                sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4227         accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4228         memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4229                sizeof(accel_attrs.keymat.aes_gcm.salt));
4230         memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4231                sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4232         accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4233         accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4234         accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4235
4236         accel_attrs.esn = attr->esn;
4237         if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4238                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4239         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4240                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4241
4242         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4243                 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4244
4245         action->esp_aes_gcm.ctx =
4246                 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4247         if (IS_ERR(action->esp_aes_gcm.ctx)) {
4248                 err = PTR_ERR(action->esp_aes_gcm.ctx);
4249                 goto err_parse;
4250         }
4251
4252         action->esp_aes_gcm.ib_flags = attr->flags;
4253
4254         return &action->ib_action;
4255
4256 err_parse:
4257         kfree(action);
4258         return ERR_PTR(err);
4259 }
4260
4261 static int
4262 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4263                                const struct ib_flow_action_attrs_esp *attr,
4264                                struct uverbs_attr_bundle *attrs)
4265 {
4266         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4267         struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4268         int err = 0;
4269
4270         if (attr->keymat || attr->replay || attr->encap ||
4271             attr->spi || attr->seq || attr->tfc_pad ||
4272             attr->hard_limit_pkts ||
4273             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4274                              IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4275                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4276                 return -EOPNOTSUPP;
4277
4278         /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4279          * be modified.
4280          */
4281         if (!(maction->esp_aes_gcm.ib_flags &
4282               IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4283             attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4284                            IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4285                 return -EINVAL;
4286
4287         memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4288                sizeof(accel_attrs));
4289
4290         accel_attrs.esn = attr->esn;
4291         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4292                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4293         else
4294                 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4295
4296         err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4297                                          &accel_attrs);
4298         if (err)
4299                 return err;
4300
4301         maction->esp_aes_gcm.ib_flags &=
4302                 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4303         maction->esp_aes_gcm.ib_flags |=
4304                 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4305
4306         return 0;
4307 }
4308
4309 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4310 {
4311         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4312
4313         switch (action->type) {
4314         case IB_FLOW_ACTION_ESP:
4315                 /*
4316                  * We only support aes_gcm by now, so we implicitly know this is
4317                  * the underline crypto.
4318                  */
4319                 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4320                 break;
4321         case IB_FLOW_ACTION_UNSPECIFIED:
4322                 mlx5_ib_destroy_flow_action_raw(maction);
4323                 break;
4324         default:
4325                 WARN_ON(true);
4326                 break;
4327         }
4328
4329         kfree(maction);
4330         return 0;
4331 }
4332
4333 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4334 {
4335         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4336         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4337         int err;
4338         u16 uid;
4339
4340         uid = ibqp->pd ?
4341                 to_mpd(ibqp->pd)->uid : 0;
4342
4343         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4344                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4345                 return -EOPNOTSUPP;
4346         }
4347
4348         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4349         if (err)
4350                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4351                              ibqp->qp_num, gid->raw);
4352
4353         return err;
4354 }
4355
4356 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4357 {
4358         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4359         int err;
4360         u16 uid;
4361
4362         uid = ibqp->pd ?
4363                 to_mpd(ibqp->pd)->uid : 0;
4364         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4365         if (err)
4366                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4367                              ibqp->qp_num, gid->raw);
4368
4369         return err;
4370 }
4371
4372 static int init_node_data(struct mlx5_ib_dev *dev)
4373 {
4374         int err;
4375
4376         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4377         if (err)
4378                 return err;
4379
4380         dev->mdev->rev_id = dev->mdev->pdev->revision;
4381
4382         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4383 }
4384
4385 static ssize_t fw_pages_show(struct device *device,
4386                              struct device_attribute *attr, char *buf)
4387 {
4388         struct mlx5_ib_dev *dev =
4389                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4390
4391         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4392 }
4393 static DEVICE_ATTR_RO(fw_pages);
4394
4395 static ssize_t reg_pages_show(struct device *device,
4396                               struct device_attribute *attr, char *buf)
4397 {
4398         struct mlx5_ib_dev *dev =
4399                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4400
4401         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4402 }
4403 static DEVICE_ATTR_RO(reg_pages);
4404
4405 static ssize_t hca_type_show(struct device *device,
4406                              struct device_attribute *attr, char *buf)
4407 {
4408         struct mlx5_ib_dev *dev =
4409                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4410
4411         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4412 }
4413 static DEVICE_ATTR_RO(hca_type);
4414
4415 static ssize_t hw_rev_show(struct device *device,
4416                            struct device_attribute *attr, char *buf)
4417 {
4418         struct mlx5_ib_dev *dev =
4419                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4420
4421         return sprintf(buf, "%x\n", dev->mdev->rev_id);
4422 }
4423 static DEVICE_ATTR_RO(hw_rev);
4424
4425 static ssize_t board_id_show(struct device *device,
4426                              struct device_attribute *attr, char *buf)
4427 {
4428         struct mlx5_ib_dev *dev =
4429                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4430
4431         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4432                        dev->mdev->board_id);
4433 }
4434 static DEVICE_ATTR_RO(board_id);
4435
4436 static struct attribute *mlx5_class_attributes[] = {
4437         &dev_attr_hw_rev.attr,
4438         &dev_attr_hca_type.attr,
4439         &dev_attr_board_id.attr,
4440         &dev_attr_fw_pages.attr,
4441         &dev_attr_reg_pages.attr,
4442         NULL,
4443 };
4444
4445 static const struct attribute_group mlx5_attr_group = {
4446         .attrs = mlx5_class_attributes,
4447 };
4448
4449 static void pkey_change_handler(struct work_struct *work)
4450 {
4451         struct mlx5_ib_port_resources *ports =
4452                 container_of(work, struct mlx5_ib_port_resources,
4453                              pkey_change_work);
4454
4455         mutex_lock(&ports->devr->mutex);
4456         mlx5_ib_gsi_pkey_change(ports->gsi);
4457         mutex_unlock(&ports->devr->mutex);
4458 }
4459
4460 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4461 {
4462         struct mlx5_ib_qp *mqp;
4463         struct mlx5_ib_cq *send_mcq, *recv_mcq;
4464         struct mlx5_core_cq *mcq;
4465         struct list_head cq_armed_list;
4466         unsigned long flags_qp;
4467         unsigned long flags_cq;
4468         unsigned long flags;
4469
4470         INIT_LIST_HEAD(&cq_armed_list);
4471
4472         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4473         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4474         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4475                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4476                 if (mqp->sq.tail != mqp->sq.head) {
4477                         send_mcq = to_mcq(mqp->ibqp.send_cq);
4478                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
4479                         if (send_mcq->mcq.comp &&
4480                             mqp->ibqp.send_cq->comp_handler) {
4481                                 if (!send_mcq->mcq.reset_notify_added) {
4482                                         send_mcq->mcq.reset_notify_added = 1;
4483                                         list_add_tail(&send_mcq->mcq.reset_notify,
4484                                                       &cq_armed_list);
4485                                 }
4486                         }
4487                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4488                 }
4489                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4490                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4491                 /* no handling is needed for SRQ */
4492                 if (!mqp->ibqp.srq) {
4493                         if (mqp->rq.tail != mqp->rq.head) {
4494                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4495                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4496                                 if (recv_mcq->mcq.comp &&
4497                                     mqp->ibqp.recv_cq->comp_handler) {
4498                                         if (!recv_mcq->mcq.reset_notify_added) {
4499                                                 recv_mcq->mcq.reset_notify_added = 1;
4500                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
4501                                                               &cq_armed_list);
4502                                         }
4503                                 }
4504                                 spin_unlock_irqrestore(&recv_mcq->lock,
4505                                                        flags_cq);
4506                         }
4507                 }
4508                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4509         }
4510         /*At that point all inflight post send were put to be executed as of we
4511          * lock/unlock above locks Now need to arm all involved CQs.
4512          */
4513         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4514                 mcq->comp(mcq, NULL);
4515         }
4516         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4517 }
4518
4519 static void delay_drop_handler(struct work_struct *work)
4520 {
4521         int err;
4522         struct mlx5_ib_delay_drop *delay_drop =
4523                 container_of(work, struct mlx5_ib_delay_drop,
4524                              delay_drop_work);
4525
4526         atomic_inc(&delay_drop->events_cnt);
4527
4528         mutex_lock(&delay_drop->lock);
4529         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4530                                        delay_drop->timeout);
4531         if (err) {
4532                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4533                              delay_drop->timeout);
4534                 delay_drop->activate = false;
4535         }
4536         mutex_unlock(&delay_drop->lock);
4537 }
4538
4539 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4540                                  struct ib_event *ibev)
4541 {
4542         u8 port = (eqe->data.port.port >> 4) & 0xf;
4543
4544         switch (eqe->sub_type) {
4545         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
4546                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4547                                             IB_LINK_LAYER_ETHERNET)
4548                         schedule_work(&ibdev->delay_drop.delay_drop_work);
4549                 break;
4550         default: /* do nothing */
4551                 return;
4552         }
4553 }
4554
4555 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4556                               struct ib_event *ibev)
4557 {
4558         u8 port = (eqe->data.port.port >> 4) & 0xf;
4559
4560         ibev->element.port_num = port;
4561
4562         switch (eqe->sub_type) {
4563         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4564         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4565         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4566                 /* In RoCE, port up/down events are handled in
4567                  * mlx5_netdev_event().
4568                  */
4569                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4570                                             IB_LINK_LAYER_ETHERNET)
4571                         return -EINVAL;
4572
4573                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4574                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4575                 break;
4576
4577         case MLX5_PORT_CHANGE_SUBTYPE_LID:
4578                 ibev->event = IB_EVENT_LID_CHANGE;
4579                 break;
4580
4581         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4582                 ibev->event = IB_EVENT_PKEY_CHANGE;
4583                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4584                 break;
4585
4586         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4587                 ibev->event = IB_EVENT_GID_CHANGE;
4588                 break;
4589
4590         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4591                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4592                 break;
4593         default:
4594                 return -EINVAL;
4595         }
4596
4597         return 0;
4598 }
4599
4600 static void mlx5_ib_handle_event(struct work_struct *_work)
4601 {
4602         struct mlx5_ib_event_work *work =
4603                 container_of(_work, struct mlx5_ib_event_work, work);
4604         struct mlx5_ib_dev *ibdev;
4605         struct ib_event ibev;
4606         bool fatal = false;
4607
4608         if (work->is_slave) {
4609                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
4610                 if (!ibdev)
4611                         goto out;
4612         } else {
4613                 ibdev = work->dev;
4614         }
4615
4616         switch (work->event) {
4617         case MLX5_DEV_EVENT_SYS_ERROR:
4618                 ibev.event = IB_EVENT_DEVICE_FATAL;
4619                 mlx5_ib_handle_internal_error(ibdev);
4620                 ibev.element.port_num  = (u8)(unsigned long)work->param;
4621                 fatal = true;
4622                 break;
4623         case MLX5_EVENT_TYPE_PORT_CHANGE:
4624                 if (handle_port_change(ibdev, work->param, &ibev))
4625                         goto out;
4626                 break;
4627         case MLX5_EVENT_TYPE_GENERAL_EVENT:
4628                 handle_general_event(ibdev, work->param, &ibev);
4629                 /* fall through */
4630         default:
4631                 goto out;
4632         }
4633
4634         ibev.device = &ibdev->ib_dev;
4635
4636         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4637                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
4638                 goto out;
4639         }
4640
4641         if (ibdev->ib_active)
4642                 ib_dispatch_event(&ibev);
4643
4644         if (fatal)
4645                 ibdev->ib_active = false;
4646 out:
4647         kfree(work);
4648 }
4649
4650 static int mlx5_ib_event(struct notifier_block *nb,
4651                          unsigned long event, void *param)
4652 {
4653         struct mlx5_ib_event_work *work;
4654
4655         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4656         if (!work)
4657                 return NOTIFY_DONE;
4658
4659         INIT_WORK(&work->work, mlx5_ib_handle_event);
4660         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4661         work->is_slave = false;
4662         work->param = param;
4663         work->event = event;
4664
4665         queue_work(mlx5_ib_event_wq, &work->work);
4666
4667         return NOTIFY_OK;
4668 }
4669
4670 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4671                                     unsigned long event, void *param)
4672 {
4673         struct mlx5_ib_event_work *work;
4674
4675         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4676         if (!work)
4677                 return NOTIFY_DONE;
4678
4679         INIT_WORK(&work->work, mlx5_ib_handle_event);
4680         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4681         work->is_slave = true;
4682         work->param = param;
4683         work->event = event;
4684         queue_work(mlx5_ib_event_wq, &work->work);
4685
4686         return NOTIFY_OK;
4687 }
4688
4689 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4690 {
4691         struct mlx5_hca_vport_context vport_ctx;
4692         int err;
4693         int port;
4694
4695         for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
4696                 dev->mdev->port_caps[port - 1].has_smi = false;
4697                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4698                     MLX5_CAP_PORT_TYPE_IB) {
4699                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4700                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4701                                                                    port, 0,
4702                                                                    &vport_ctx);
4703                                 if (err) {
4704                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4705                                                     port, err);
4706                                         return err;
4707                                 }
4708                                 dev->mdev->port_caps[port - 1].has_smi =
4709                                         vport_ctx.has_smi;
4710                         } else {
4711                                 dev->mdev->port_caps[port - 1].has_smi = true;
4712                         }
4713                 }
4714         }
4715         return 0;
4716 }
4717
4718 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4719 {
4720         int port;
4721
4722         for (port = 1; port <= dev->num_ports; port++)
4723                 mlx5_query_ext_port_caps(dev, port);
4724 }
4725
4726 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4727 {
4728         struct ib_device_attr *dprops = NULL;
4729         struct ib_port_attr *pprops = NULL;
4730         int err = -ENOMEM;
4731         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4732
4733         pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
4734         if (!pprops)
4735                 goto out;
4736
4737         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4738         if (!dprops)
4739                 goto out;
4740
4741         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4742         if (err) {
4743                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4744                 goto out;
4745         }
4746
4747         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4748         if (err) {
4749                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4750                              port, err);
4751                 goto out;
4752         }
4753
4754         dev->mdev->port_caps[port - 1].pkey_table_len =
4755                                         dprops->max_pkeys;
4756         dev->mdev->port_caps[port - 1].gid_table_len =
4757                                         pprops->gid_tbl_len;
4758         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4759                     port, dprops->max_pkeys, pprops->gid_tbl_len);
4760
4761 out:
4762         kfree(pprops);
4763         kfree(dprops);
4764
4765         return err;
4766 }
4767
4768 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4769 {
4770         /* For representors use port 1, is this is the only native
4771          * port
4772          */
4773         if (dev->is_rep)
4774                 return __get_port_caps(dev, 1);
4775         return __get_port_caps(dev, port);
4776 }
4777
4778 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4779 {
4780         int err;
4781
4782         err = mlx5_mr_cache_cleanup(dev);
4783         if (err)
4784                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4785
4786         if (dev->umrc.qp)
4787                 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4788         if (dev->umrc.cq)
4789                 ib_free_cq(dev->umrc.cq);
4790         if (dev->umrc.pd)
4791                 ib_dealloc_pd(dev->umrc.pd);
4792 }
4793
4794 enum {
4795         MAX_UMR_WR = 128,
4796 };
4797
4798 static int create_umr_res(struct mlx5_ib_dev *dev)
4799 {
4800         struct ib_qp_init_attr *init_attr = NULL;
4801         struct ib_qp_attr *attr = NULL;
4802         struct ib_pd *pd;
4803         struct ib_cq *cq;
4804         struct ib_qp *qp;
4805         int ret;
4806
4807         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4808         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4809         if (!attr || !init_attr) {
4810                 ret = -ENOMEM;
4811                 goto error_0;
4812         }
4813
4814         pd = ib_alloc_pd(&dev->ib_dev, 0);
4815         if (IS_ERR(pd)) {
4816                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4817                 ret = PTR_ERR(pd);
4818                 goto error_0;
4819         }
4820
4821         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4822         if (IS_ERR(cq)) {
4823                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4824                 ret = PTR_ERR(cq);
4825                 goto error_2;
4826         }
4827
4828         init_attr->send_cq = cq;
4829         init_attr->recv_cq = cq;
4830         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4831         init_attr->cap.max_send_wr = MAX_UMR_WR;
4832         init_attr->cap.max_send_sge = 1;
4833         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4834         init_attr->port_num = 1;
4835         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4836         if (IS_ERR(qp)) {
4837                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4838                 ret = PTR_ERR(qp);
4839                 goto error_3;
4840         }
4841         qp->device     = &dev->ib_dev;
4842         qp->real_qp    = qp;
4843         qp->uobject    = NULL;
4844         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4845         qp->send_cq    = init_attr->send_cq;
4846         qp->recv_cq    = init_attr->recv_cq;
4847
4848         attr->qp_state = IB_QPS_INIT;
4849         attr->port_num = 1;
4850         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4851                                 IB_QP_PORT, NULL);
4852         if (ret) {
4853                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4854                 goto error_4;
4855         }
4856
4857         memset(attr, 0, sizeof(*attr));
4858         attr->qp_state = IB_QPS_RTR;
4859         attr->path_mtu = IB_MTU_256;
4860
4861         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4862         if (ret) {
4863                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4864                 goto error_4;
4865         }
4866
4867         memset(attr, 0, sizeof(*attr));
4868         attr->qp_state = IB_QPS_RTS;
4869         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4870         if (ret) {
4871                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4872                 goto error_4;
4873         }
4874
4875         dev->umrc.qp = qp;
4876         dev->umrc.cq = cq;
4877         dev->umrc.pd = pd;
4878
4879         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4880         ret = mlx5_mr_cache_init(dev);
4881         if (ret) {
4882                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4883                 goto error_4;
4884         }
4885
4886         kfree(attr);
4887         kfree(init_attr);
4888
4889         return 0;
4890
4891 error_4:
4892         mlx5_ib_destroy_qp(qp, NULL);
4893         dev->umrc.qp = NULL;
4894
4895 error_3:
4896         ib_free_cq(cq);
4897         dev->umrc.cq = NULL;
4898
4899 error_2:
4900         ib_dealloc_pd(pd);
4901         dev->umrc.pd = NULL;
4902
4903 error_0:
4904         kfree(attr);
4905         kfree(init_attr);
4906         return ret;
4907 }
4908
4909 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4910 {
4911         switch (umr_fence_cap) {
4912         case MLX5_CAP_UMR_FENCE_NONE:
4913                 return MLX5_FENCE_MODE_NONE;
4914         case MLX5_CAP_UMR_FENCE_SMALL:
4915                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4916         default:
4917                 return MLX5_FENCE_MODE_STRONG_ORDERING;
4918         }
4919 }
4920
4921 static int create_dev_resources(struct mlx5_ib_resources *devr)
4922 {
4923         struct ib_srq_init_attr attr;
4924         struct mlx5_ib_dev *dev;
4925         struct ib_device *ibdev;
4926         struct ib_cq_init_attr cq_attr = {.cqe = 1};
4927         int port;
4928         int ret = 0;
4929
4930         dev = container_of(devr, struct mlx5_ib_dev, devr);
4931         ibdev = &dev->ib_dev;
4932
4933         mutex_init(&devr->mutex);
4934
4935         devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4936         if (!devr->p0)
4937                 return -ENOMEM;
4938
4939         devr->p0->device  = ibdev;
4940         devr->p0->uobject = NULL;
4941         atomic_set(&devr->p0->usecnt, 0);
4942
4943         ret = mlx5_ib_alloc_pd(devr->p0, NULL);
4944         if (ret)
4945                 goto error0;
4946
4947         devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4948         if (!devr->c0) {
4949                 ret = -ENOMEM;
4950                 goto error1;
4951         }
4952
4953         devr->c0->device = &dev->ib_dev;
4954         atomic_set(&devr->c0->usecnt, 0);
4955
4956         ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4957         if (ret)
4958                 goto err_create_cq;
4959
4960         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4961         if (IS_ERR(devr->x0)) {
4962                 ret = PTR_ERR(devr->x0);
4963                 goto error2;
4964         }
4965         devr->x0->device = &dev->ib_dev;
4966         devr->x0->inode = NULL;
4967         atomic_set(&devr->x0->usecnt, 0);
4968         mutex_init(&devr->x0->tgt_qp_mutex);
4969         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4970
4971         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4972         if (IS_ERR(devr->x1)) {
4973                 ret = PTR_ERR(devr->x1);
4974                 goto error3;
4975         }
4976         devr->x1->device = &dev->ib_dev;
4977         devr->x1->inode = NULL;
4978         atomic_set(&devr->x1->usecnt, 0);
4979         mutex_init(&devr->x1->tgt_qp_mutex);
4980         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4981
4982         memset(&attr, 0, sizeof(attr));
4983         attr.attr.max_sge = 1;
4984         attr.attr.max_wr = 1;
4985         attr.srq_type = IB_SRQT_XRC;
4986         attr.ext.cq = devr->c0;
4987         attr.ext.xrc.xrcd = devr->x0;
4988
4989         devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4990         if (!devr->s0) {
4991                 ret = -ENOMEM;
4992                 goto error4;
4993         }
4994
4995         devr->s0->device        = &dev->ib_dev;
4996         devr->s0->pd            = devr->p0;
4997         devr->s0->srq_type      = IB_SRQT_XRC;
4998         devr->s0->ext.xrc.xrcd  = devr->x0;
4999         devr->s0->ext.cq        = devr->c0;
5000         ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5001         if (ret)
5002                 goto err_create;
5003
5004         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
5005         atomic_inc(&devr->s0->ext.cq->usecnt);
5006         atomic_inc(&devr->p0->usecnt);
5007         atomic_set(&devr->s0->usecnt, 0);
5008
5009         memset(&attr, 0, sizeof(attr));
5010         attr.attr.max_sge = 1;
5011         attr.attr.max_wr = 1;
5012         attr.srq_type = IB_SRQT_BASIC;
5013         devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5014         if (!devr->s1) {
5015                 ret = -ENOMEM;
5016                 goto error5;
5017         }
5018
5019         devr->s1->device        = &dev->ib_dev;
5020         devr->s1->pd            = devr->p0;
5021         devr->s1->srq_type      = IB_SRQT_BASIC;
5022         devr->s1->ext.cq        = devr->c0;
5023
5024         ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5025         if (ret)
5026                 goto error6;
5027
5028         atomic_inc(&devr->p0->usecnt);
5029         atomic_set(&devr->s1->usecnt, 0);
5030
5031         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5032                 INIT_WORK(&devr->ports[port].pkey_change_work,
5033                           pkey_change_handler);
5034                 devr->ports[port].devr = devr;
5035         }
5036
5037         return 0;
5038
5039 error6:
5040         kfree(devr->s1);
5041 error5:
5042         mlx5_ib_destroy_srq(devr->s0, NULL);
5043 err_create:
5044         kfree(devr->s0);
5045 error4:
5046         mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5047 error3:
5048         mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5049 error2:
5050         mlx5_ib_destroy_cq(devr->c0, NULL);
5051 err_create_cq:
5052         kfree(devr->c0);
5053 error1:
5054         mlx5_ib_dealloc_pd(devr->p0, NULL);
5055 error0:
5056         kfree(devr->p0);
5057         return ret;
5058 }
5059
5060 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5061 {
5062         int port;
5063
5064         mlx5_ib_destroy_srq(devr->s1, NULL);
5065         kfree(devr->s1);
5066         mlx5_ib_destroy_srq(devr->s0, NULL);
5067         kfree(devr->s0);
5068         mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5069         mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5070         mlx5_ib_destroy_cq(devr->c0, NULL);
5071         kfree(devr->c0);
5072         mlx5_ib_dealloc_pd(devr->p0, NULL);
5073         kfree(devr->p0);
5074
5075         /* Make sure no change P_Key work items are still executing */
5076         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
5077                 cancel_work_sync(&devr->ports[port].pkey_change_work);
5078 }
5079
5080 static u32 get_core_cap_flags(struct ib_device *ibdev,
5081                               struct mlx5_hca_vport_context *rep)
5082 {
5083         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5084         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5085         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5086         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
5087         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
5088         u32 ret = 0;
5089
5090         if (rep->grh_required)
5091                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5092
5093         if (ll == IB_LINK_LAYER_INFINIBAND)
5094                 return ret | RDMA_CORE_PORT_IBA_IB;
5095
5096         if (raw_support)
5097                 ret |= RDMA_CORE_PORT_RAW_PACKET;
5098
5099         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
5100                 return ret;
5101
5102         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
5103                 return ret;
5104
5105         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5106                 ret |= RDMA_CORE_PORT_IBA_ROCE;
5107
5108         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5109                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5110
5111         return ret;
5112 }
5113
5114 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5115                                struct ib_port_immutable *immutable)
5116 {
5117         struct ib_port_attr attr;
5118         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5119         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
5120         struct mlx5_hca_vport_context rep = {0};
5121         int err;
5122
5123         err = ib_query_port(ibdev, port_num, &attr);
5124         if (err)
5125                 return err;
5126
5127         if (ll == IB_LINK_LAYER_INFINIBAND) {
5128                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5129                                                    &rep);
5130                 if (err)
5131                         return err;
5132         }
5133
5134         immutable->pkey_tbl_len = attr.pkey_tbl_len;
5135         immutable->gid_tbl_len = attr.gid_tbl_len;
5136         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
5137         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5138                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
5139
5140         return 0;
5141 }
5142
5143 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5144                                    struct ib_port_immutable *immutable)
5145 {
5146         struct ib_port_attr attr;
5147         int err;
5148
5149         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5150
5151         err = ib_query_port(ibdev, port_num, &attr);
5152         if (err)
5153                 return err;
5154
5155         immutable->pkey_tbl_len = attr.pkey_tbl_len;
5156         immutable->gid_tbl_len = attr.gid_tbl_len;
5157         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5158
5159         return 0;
5160 }
5161
5162 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
5163 {
5164         struct mlx5_ib_dev *dev =
5165                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
5166         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5167                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5168                  fw_rev_sub(dev->mdev));
5169 }
5170
5171 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
5172 {
5173         struct mlx5_core_dev *mdev = dev->mdev;
5174         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5175                                                                  MLX5_FLOW_NAMESPACE_LAG);
5176         struct mlx5_flow_table *ft;
5177         int err;
5178
5179         if (!ns || !mlx5_lag_is_roce(mdev))
5180                 return 0;
5181
5182         err = mlx5_cmd_create_vport_lag(mdev);
5183         if (err)
5184                 return err;
5185
5186         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5187         if (IS_ERR(ft)) {
5188                 err = PTR_ERR(ft);
5189                 goto err_destroy_vport_lag;
5190         }
5191
5192         dev->flow_db->lag_demux_ft = ft;
5193         dev->lag_active = true;
5194         return 0;
5195
5196 err_destroy_vport_lag:
5197         mlx5_cmd_destroy_vport_lag(mdev);
5198         return err;
5199 }
5200
5201 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
5202 {
5203         struct mlx5_core_dev *mdev = dev->mdev;
5204
5205         if (dev->lag_active) {
5206                 dev->lag_active = false;
5207
5208                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5209                 dev->flow_db->lag_demux_ft = NULL;
5210
5211                 mlx5_cmd_destroy_vport_lag(mdev);
5212         }
5213 }
5214
5215 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5216 {
5217         int err;
5218
5219         dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5220         err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
5221         if (err) {
5222                 dev->port[port_num].roce.nb.notifier_call = NULL;
5223                 return err;
5224         }
5225
5226         return 0;
5227 }
5228
5229 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5230 {
5231         if (dev->port[port_num].roce.nb.notifier_call) {
5232                 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5233                 dev->port[port_num].roce.nb.notifier_call = NULL;
5234         }
5235 }
5236
5237 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
5238 {
5239         int err;
5240
5241         if (MLX5_CAP_GEN(dev->mdev, roce)) {
5242                 err = mlx5_nic_vport_enable_roce(dev->mdev);
5243                 if (err)
5244                         return err;
5245         }
5246
5247         err = mlx5_eth_lag_init(dev);
5248         if (err)
5249                 goto err_disable_roce;
5250
5251         return 0;
5252
5253 err_disable_roce:
5254         if (MLX5_CAP_GEN(dev->mdev, roce))
5255                 mlx5_nic_vport_disable_roce(dev->mdev);
5256
5257         return err;
5258 }
5259
5260 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
5261 {
5262         mlx5_eth_lag_cleanup(dev);
5263         if (MLX5_CAP_GEN(dev->mdev, roce))
5264                 mlx5_nic_vport_disable_roce(dev->mdev);
5265 }
5266
5267 struct mlx5_ib_counter {
5268         const char *name;
5269         size_t offset;
5270 };
5271
5272 #define INIT_Q_COUNTER(_name)           \
5273         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5274
5275 static const struct mlx5_ib_counter basic_q_cnts[] = {
5276         INIT_Q_COUNTER(rx_write_requests),
5277         INIT_Q_COUNTER(rx_read_requests),
5278         INIT_Q_COUNTER(rx_atomic_requests),
5279         INIT_Q_COUNTER(out_of_buffer),
5280 };
5281
5282 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
5283         INIT_Q_COUNTER(out_of_sequence),
5284 };
5285
5286 static const struct mlx5_ib_counter retrans_q_cnts[] = {
5287         INIT_Q_COUNTER(duplicate_request),
5288         INIT_Q_COUNTER(rnr_nak_retry_err),
5289         INIT_Q_COUNTER(packet_seq_err),
5290         INIT_Q_COUNTER(implied_nak_seq_err),
5291         INIT_Q_COUNTER(local_ack_timeout_err),
5292 };
5293
5294 #define INIT_CONG_COUNTER(_name)                \
5295         { .name = #_name, .offset =     \
5296                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5297
5298 static const struct mlx5_ib_counter cong_cnts[] = {
5299         INIT_CONG_COUNTER(rp_cnp_ignored),
5300         INIT_CONG_COUNTER(rp_cnp_handled),
5301         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5302         INIT_CONG_COUNTER(np_cnp_sent),
5303 };
5304
5305 static const struct mlx5_ib_counter extended_err_cnts[] = {
5306         INIT_Q_COUNTER(resp_local_length_error),
5307         INIT_Q_COUNTER(resp_cqe_error),
5308         INIT_Q_COUNTER(req_cqe_error),
5309         INIT_Q_COUNTER(req_remote_invalid_request),
5310         INIT_Q_COUNTER(req_remote_access_errors),
5311         INIT_Q_COUNTER(resp_remote_access_errors),
5312         INIT_Q_COUNTER(resp_cqe_flush_error),
5313         INIT_Q_COUNTER(req_cqe_flush_error),
5314 };
5315
5316 #define INIT_EXT_PPCNT_COUNTER(_name)           \
5317         { .name = #_name, .offset =     \
5318         MLX5_BYTE_OFF(ppcnt_reg, \
5319                       counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5320
5321 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5322         INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5323 };
5324
5325 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
5326 {
5327         int i;
5328
5329         for (i = 0; i < dev->num_ports; i++) {
5330                 if (dev->port[i].cnts.set_id_valid)
5331                         mlx5_core_dealloc_q_counter(dev->mdev,
5332                                                     dev->port[i].cnts.set_id);
5333                 kfree(dev->port[i].cnts.names);
5334                 kfree(dev->port[i].cnts.offsets);
5335         }
5336 }
5337
5338 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5339                                     struct mlx5_ib_counters *cnts)
5340 {
5341         u32 num_counters;
5342
5343         num_counters = ARRAY_SIZE(basic_q_cnts);
5344
5345         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5346                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5347
5348         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5349                 num_counters += ARRAY_SIZE(retrans_q_cnts);
5350
5351         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5352                 num_counters += ARRAY_SIZE(extended_err_cnts);
5353
5354         cnts->num_q_counters = num_counters;
5355
5356         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5357                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5358                 num_counters += ARRAY_SIZE(cong_cnts);
5359         }
5360         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5361                 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5362                 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5363         }
5364         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5365         if (!cnts->names)
5366                 return -ENOMEM;
5367
5368         cnts->offsets = kcalloc(num_counters,
5369                                 sizeof(cnts->offsets), GFP_KERNEL);
5370         if (!cnts->offsets)
5371                 goto err_names;
5372
5373         return 0;
5374
5375 err_names:
5376         kfree(cnts->names);
5377         cnts->names = NULL;
5378         return -ENOMEM;
5379 }
5380
5381 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5382                                   const char **names,
5383                                   size_t *offsets)
5384 {
5385         int i;
5386         int j = 0;
5387
5388         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5389                 names[j] = basic_q_cnts[i].name;
5390                 offsets[j] = basic_q_cnts[i].offset;
5391         }
5392
5393         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5394                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5395                         names[j] = out_of_seq_q_cnts[i].name;
5396                         offsets[j] = out_of_seq_q_cnts[i].offset;
5397                 }
5398         }
5399
5400         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5401                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5402                         names[j] = retrans_q_cnts[i].name;
5403                         offsets[j] = retrans_q_cnts[i].offset;
5404                 }
5405         }
5406
5407         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5408                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5409                         names[j] = extended_err_cnts[i].name;
5410                         offsets[j] = extended_err_cnts[i].offset;
5411                 }
5412         }
5413
5414         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5415                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5416                         names[j] = cong_cnts[i].name;
5417                         offsets[j] = cong_cnts[i].offset;
5418                 }
5419         }
5420
5421         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5422                 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5423                         names[j] = ext_ppcnt_cnts[i].name;
5424                         offsets[j] = ext_ppcnt_cnts[i].offset;
5425                 }
5426         }
5427 }
5428
5429 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5430 {
5431         int err = 0;
5432         int i;
5433         bool is_shared;
5434
5435         is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
5436
5437         for (i = 0; i < dev->num_ports; i++) {
5438                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5439                 if (err)
5440                         goto err_alloc;
5441
5442                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5443                                       dev->port[i].cnts.offsets);
5444
5445                 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5446                                                &dev->port[i].cnts.set_id,
5447                                                is_shared ?
5448                                                MLX5_SHARED_RESOURCE_UID : 0);
5449                 if (err) {
5450                         mlx5_ib_warn(dev,
5451                                      "couldn't allocate queue counter for port %d, err %d\n",
5452                                      i + 1, err);
5453                         goto err_alloc;
5454                 }
5455                 dev->port[i].cnts.set_id_valid = true;
5456         }
5457
5458         return 0;
5459
5460 err_alloc:
5461         mlx5_ib_dealloc_counters(dev);
5462         return err;
5463 }
5464
5465 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5466                                                     u8 port_num)
5467 {
5468         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5469         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5470
5471         /* We support only per port stats */
5472         if (port_num == 0)
5473                 return NULL;
5474
5475         return rdma_alloc_hw_stats_struct(port->cnts.names,
5476                                           port->cnts.num_q_counters +
5477                                           port->cnts.num_cong_counters +
5478                                           port->cnts.num_ext_ppcnt_counters,
5479                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
5480 }
5481
5482 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5483                                     struct mlx5_ib_port *port,
5484                                     struct rdma_hw_stats *stats,
5485                                     u16 set_id)
5486 {
5487         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5488         void *out;
5489         __be32 val;
5490         int ret, i;
5491
5492         out = kvzalloc(outlen, GFP_KERNEL);
5493         if (!out)
5494                 return -ENOMEM;
5495
5496         ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
5497         if (ret)
5498                 goto free;
5499
5500         for (i = 0; i < port->cnts.num_q_counters; i++) {
5501                 val = *(__be32 *)(out + port->cnts.offsets[i]);
5502                 stats->value[i] = (u64)be32_to_cpu(val);
5503         }
5504
5505 free:
5506         kvfree(out);
5507         return ret;
5508 }
5509
5510 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5511                                           struct mlx5_ib_port *port,
5512                                           struct rdma_hw_stats *stats)
5513 {
5514         int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5515         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5516         int ret, i;
5517         void *out;
5518
5519         out = kvzalloc(sz, GFP_KERNEL);
5520         if (!out)
5521                 return -ENOMEM;
5522
5523         ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5524         if (ret)
5525                 goto free;
5526
5527         for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5528                 stats->value[i + offset] =
5529                         be64_to_cpup((__be64 *)(out +
5530                                     port->cnts.offsets[i + offset]));
5531         }
5532
5533 free:
5534         kvfree(out);
5535         return ret;
5536 }
5537
5538 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5539                                 struct rdma_hw_stats *stats,
5540                                 u8 port_num, int index)
5541 {
5542         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5543         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5544         struct mlx5_core_dev *mdev;
5545         int ret, num_counters;
5546         u8 mdev_port_num;
5547
5548         if (!stats)
5549                 return -EINVAL;
5550
5551         num_counters = port->cnts.num_q_counters +
5552                        port->cnts.num_cong_counters +
5553                        port->cnts.num_ext_ppcnt_counters;
5554
5555         /* q_counters are per IB device, query the master mdev */
5556         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats,
5557                                        port->cnts.set_id);
5558         if (ret)
5559                 return ret;
5560
5561         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5562                 ret =  mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5563                 if (ret)
5564                         return ret;
5565         }
5566
5567         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5568                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5569                                                     &mdev_port_num);
5570                 if (!mdev) {
5571                         /* If port is not affiliated yet, its in down state
5572                          * which doesn't have any counters yet, so it would be
5573                          * zero. So no need to read from the HCA.
5574                          */
5575                         goto done;
5576                 }
5577                 ret = mlx5_lag_query_cong_counters(dev->mdev,
5578                                                    stats->value +
5579                                                    port->cnts.num_q_counters,
5580                                                    port->cnts.num_cong_counters,
5581                                                    port->cnts.offsets +
5582                                                    port->cnts.num_q_counters);
5583
5584                 mlx5_ib_put_native_port_mdev(dev, port_num);
5585                 if (ret)
5586                         return ret;
5587         }
5588
5589 done:
5590         return num_counters;
5591 }
5592
5593 static struct rdma_hw_stats *
5594 mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5595 {
5596         struct mlx5_ib_dev *dev = to_mdev(counter->device);
5597         struct mlx5_ib_port *port = &dev->port[counter->port - 1];
5598
5599         /* Q counters are in the beginning of all counters */
5600         return rdma_alloc_hw_stats_struct(port->cnts.names,
5601                                           port->cnts.num_q_counters,
5602                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
5603 }
5604
5605 static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5606 {
5607         struct mlx5_ib_dev *dev = to_mdev(counter->device);
5608         struct mlx5_ib_port *port = &dev->port[counter->port - 1];
5609
5610         return mlx5_ib_query_q_counters(dev->mdev, port,
5611                                         counter->stats, counter->id);
5612 }
5613
5614 static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5615                                    struct ib_qp *qp)
5616 {
5617         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5618         u16 cnt_set_id = 0;
5619         int err;
5620
5621         if (!counter->id) {
5622                 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5623                                                &cnt_set_id,
5624                                                MLX5_SHARED_RESOURCE_UID);
5625                 if (err)
5626                         return err;
5627                 counter->id = cnt_set_id;
5628         }
5629
5630         err = mlx5_ib_qp_set_counter(qp, counter);
5631         if (err)
5632                 goto fail_set_counter;
5633
5634         return 0;
5635
5636 fail_set_counter:
5637         mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5638         counter->id = 0;
5639
5640         return err;
5641 }
5642
5643 static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5644 {
5645         return mlx5_ib_qp_set_counter(qp, NULL);
5646 }
5647
5648 static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5649 {
5650         struct mlx5_ib_dev *dev = to_mdev(counter->device);
5651
5652         return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5653 }
5654
5655 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5656                                  enum rdma_netdev_t type,
5657                                  struct rdma_netdev_alloc_params *params)
5658 {
5659         if (type != RDMA_NETDEV_IPOIB)
5660                 return -EOPNOTSUPP;
5661
5662         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
5663 }
5664
5665 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5666 {
5667         if (!dev->delay_drop.dbg)
5668                 return;
5669         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5670         kfree(dev->delay_drop.dbg);
5671         dev->delay_drop.dbg = NULL;
5672 }
5673
5674 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5675 {
5676         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5677                 return;
5678
5679         cancel_work_sync(&dev->delay_drop.delay_drop_work);
5680         delay_drop_debugfs_cleanup(dev);
5681 }
5682
5683 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5684                                        size_t count, loff_t *pos)
5685 {
5686         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5687         char lbuf[20];
5688         int len;
5689
5690         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5691         return simple_read_from_buffer(buf, count, pos, lbuf, len);
5692 }
5693
5694 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5695                                         size_t count, loff_t *pos)
5696 {
5697         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5698         u32 timeout;
5699         u32 var;
5700
5701         if (kstrtouint_from_user(buf, count, 0, &var))
5702                 return -EFAULT;
5703
5704         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5705                         1000);
5706         if (timeout != var)
5707                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5708                             timeout);
5709
5710         delay_drop->timeout = timeout;
5711
5712         return count;
5713 }
5714
5715 static const struct file_operations fops_delay_drop_timeout = {
5716         .owner  = THIS_MODULE,
5717         .open   = simple_open,
5718         .write  = delay_drop_timeout_write,
5719         .read   = delay_drop_timeout_read,
5720 };
5721
5722 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5723 {
5724         struct mlx5_ib_dbg_delay_drop *dbg;
5725
5726         if (!mlx5_debugfs_root)
5727                 return 0;
5728
5729         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5730         if (!dbg)
5731                 return -ENOMEM;
5732
5733         dev->delay_drop.dbg = dbg;
5734
5735         dbg->dir_debugfs =
5736                 debugfs_create_dir("delay_drop",
5737                                    dev->mdev->priv.dbg_root);
5738         if (!dbg->dir_debugfs)
5739                 goto out_debugfs;
5740
5741         dbg->events_cnt_debugfs =
5742                 debugfs_create_atomic_t("num_timeout_events", 0400,
5743                                         dbg->dir_debugfs,
5744                                         &dev->delay_drop.events_cnt);
5745         if (!dbg->events_cnt_debugfs)
5746                 goto out_debugfs;
5747
5748         dbg->rqs_cnt_debugfs =
5749                 debugfs_create_atomic_t("num_rqs", 0400,
5750                                         dbg->dir_debugfs,
5751                                         &dev->delay_drop.rqs_cnt);
5752         if (!dbg->rqs_cnt_debugfs)
5753                 goto out_debugfs;
5754
5755         dbg->timeout_debugfs =
5756                 debugfs_create_file("timeout", 0600,
5757                                     dbg->dir_debugfs,
5758                                     &dev->delay_drop,
5759                                     &fops_delay_drop_timeout);
5760         if (!dbg->timeout_debugfs)
5761                 goto out_debugfs;
5762
5763         return 0;
5764
5765 out_debugfs:
5766         delay_drop_debugfs_cleanup(dev);
5767         return -ENOMEM;
5768 }
5769
5770 static void init_delay_drop(struct mlx5_ib_dev *dev)
5771 {
5772         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5773                 return;
5774
5775         mutex_init(&dev->delay_drop.lock);
5776         dev->delay_drop.dev = dev;
5777         dev->delay_drop.activate = false;
5778         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5779         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5780         atomic_set(&dev->delay_drop.rqs_cnt, 0);
5781         atomic_set(&dev->delay_drop.events_cnt, 0);
5782
5783         if (delay_drop_debugfs_init(dev))
5784                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5785 }
5786
5787 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5788 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5789                                       struct mlx5_ib_multiport_info *mpi)
5790 {
5791         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5792         struct mlx5_ib_port *port = &ibdev->port[port_num];
5793         int comps;
5794         int err;
5795         int i;
5796
5797         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5798
5799         spin_lock(&port->mp.mpi_lock);
5800         if (!mpi->ibdev) {
5801                 spin_unlock(&port->mp.mpi_lock);
5802                 return;
5803         }
5804
5805         mpi->ibdev = NULL;
5806
5807         spin_unlock(&port->mp.mpi_lock);
5808         if (mpi->mdev_events.notifier_call)
5809                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5810         mpi->mdev_events.notifier_call = NULL;
5811         mlx5_remove_netdev_notifier(ibdev, port_num);
5812         spin_lock(&port->mp.mpi_lock);
5813
5814         comps = mpi->mdev_refcnt;
5815         if (comps) {
5816                 mpi->unaffiliate = true;
5817                 init_completion(&mpi->unref_comp);
5818                 spin_unlock(&port->mp.mpi_lock);
5819
5820                 for (i = 0; i < comps; i++)
5821                         wait_for_completion(&mpi->unref_comp);
5822
5823                 spin_lock(&port->mp.mpi_lock);
5824                 mpi->unaffiliate = false;
5825         }
5826
5827         port->mp.mpi = NULL;
5828
5829         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5830
5831         spin_unlock(&port->mp.mpi_lock);
5832
5833         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5834
5835         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5836         /* Log an error, still needed to cleanup the pointers and add
5837          * it back to the list.
5838          */
5839         if (err)
5840                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5841                             port_num + 1);
5842
5843         ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
5844 }
5845
5846 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5847 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5848                                     struct mlx5_ib_multiport_info *mpi)
5849 {
5850         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5851         int err;
5852
5853         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5854         if (ibdev->port[port_num].mp.mpi) {
5855                 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5856                             port_num + 1);
5857                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5858                 return false;
5859         }
5860
5861         ibdev->port[port_num].mp.mpi = mpi;
5862         mpi->ibdev = ibdev;
5863         mpi->mdev_events.notifier_call = NULL;
5864         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5865
5866         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5867         if (err)
5868                 goto unbind;
5869
5870         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5871         if (err)
5872                 goto unbind;
5873
5874         err = mlx5_add_netdev_notifier(ibdev, port_num);
5875         if (err) {
5876                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5877                             port_num + 1);
5878                 goto unbind;
5879         }
5880
5881         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5882         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5883
5884         mlx5_ib_init_cong_debugfs(ibdev, port_num);
5885
5886         return true;
5887
5888 unbind:
5889         mlx5_ib_unbind_slave_port(ibdev, mpi);
5890         return false;
5891 }
5892
5893 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5894 {
5895         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5896         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5897                                                           port_num + 1);
5898         struct mlx5_ib_multiport_info *mpi;
5899         int err;
5900         int i;
5901
5902         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5903                 return 0;
5904
5905         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5906                                                      &dev->sys_image_guid);
5907         if (err)
5908                 return err;
5909
5910         err = mlx5_nic_vport_enable_roce(dev->mdev);
5911         if (err)
5912                 return err;
5913
5914         mutex_lock(&mlx5_ib_multiport_mutex);
5915         for (i = 0; i < dev->num_ports; i++) {
5916                 bool bound = false;
5917
5918                 /* build a stub multiport info struct for the native port. */
5919                 if (i == port_num) {
5920                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5921                         if (!mpi) {
5922                                 mutex_unlock(&mlx5_ib_multiport_mutex);
5923                                 mlx5_nic_vport_disable_roce(dev->mdev);
5924                                 return -ENOMEM;
5925                         }
5926
5927                         mpi->is_master = true;
5928                         mpi->mdev = dev->mdev;
5929                         mpi->sys_image_guid = dev->sys_image_guid;
5930                         dev->port[i].mp.mpi = mpi;
5931                         mpi->ibdev = dev;
5932                         mpi = NULL;
5933                         continue;
5934                 }
5935
5936                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5937                                     list) {
5938                         if (dev->sys_image_guid == mpi->sys_image_guid &&
5939                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5940                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
5941                         }
5942
5943                         if (bound) {
5944                                 dev_dbg(mpi->mdev->device,
5945                                         "removing port from unaffiliated list.\n");
5946                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5947                                 list_del(&mpi->list);
5948                                 break;
5949                         }
5950                 }
5951                 if (!bound) {
5952                         get_port_caps(dev, i + 1);
5953                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
5954                                     i + 1);
5955                 }
5956         }
5957
5958         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5959         mutex_unlock(&mlx5_ib_multiport_mutex);
5960         return err;
5961 }
5962
5963 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5964 {
5965         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5966         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5967                                                           port_num + 1);
5968         int i;
5969
5970         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5971                 return;
5972
5973         mutex_lock(&mlx5_ib_multiport_mutex);
5974         for (i = 0; i < dev->num_ports; i++) {
5975                 if (dev->port[i].mp.mpi) {
5976                         /* Destroy the native port stub */
5977                         if (i == port_num) {
5978                                 kfree(dev->port[i].mp.mpi);
5979                                 dev->port[i].mp.mpi = NULL;
5980                         } else {
5981                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5982                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5983                         }
5984                 }
5985         }
5986
5987         mlx5_ib_dbg(dev, "removing from devlist\n");
5988         list_del(&dev->ib_dev_list);
5989         mutex_unlock(&mlx5_ib_multiport_mutex);
5990
5991         mlx5_nic_vport_disable_roce(dev->mdev);
5992 }
5993
5994 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5995         mlx5_ib_dm,
5996         UVERBS_OBJECT_DM,
5997         UVERBS_METHOD_DM_ALLOC,
5998         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5999                             UVERBS_ATTR_TYPE(u64),
6000                             UA_MANDATORY),
6001         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6002                             UVERBS_ATTR_TYPE(u16),
6003                             UA_OPTIONAL),
6004         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6005                              enum mlx5_ib_uapi_dm_type,
6006                              UA_OPTIONAL));
6007
6008 ADD_UVERBS_ATTRIBUTES_SIMPLE(
6009         mlx5_ib_flow_action,
6010         UVERBS_OBJECT_FLOW_ACTION,
6011         UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
6012         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6013                              enum mlx5_ib_uapi_flow_action_flags));
6014
6015 static const struct uapi_definition mlx5_ib_defs[] = {
6016 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
6017         UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
6018         UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
6019 #endif
6020
6021         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6022                                 &mlx5_ib_flow_action),
6023         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
6024         {}
6025 };
6026
6027 static int mlx5_ib_read_counters(struct ib_counters *counters,
6028                                  struct ib_counters_read_attr *read_attr,
6029                                  struct uverbs_attr_bundle *attrs)
6030 {
6031         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6032         struct mlx5_read_counters_attr mread_attr = {};
6033         struct mlx5_ib_flow_counters_desc *desc;
6034         int ret, i;
6035
6036         mutex_lock(&mcounters->mcntrs_mutex);
6037         if (mcounters->cntrs_max_index > read_attr->ncounters) {
6038                 ret = -EINVAL;
6039                 goto err_bound;
6040         }
6041
6042         mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6043                                  GFP_KERNEL);
6044         if (!mread_attr.out) {
6045                 ret = -ENOMEM;
6046                 goto err_bound;
6047         }
6048
6049         mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6050         mread_attr.flags = read_attr->flags;
6051         ret = mcounters->read_counters(counters->device, &mread_attr);
6052         if (ret)
6053                 goto err_read;
6054
6055         /* do the pass over the counters data array to assign according to the
6056          * descriptions and indexing pairs
6057          */
6058         desc = mcounters->counters_data;
6059         for (i = 0; i < mcounters->ncounters; i++)
6060                 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6061
6062 err_read:
6063         kfree(mread_attr.out);
6064 err_bound:
6065         mutex_unlock(&mcounters->mcntrs_mutex);
6066         return ret;
6067 }
6068
6069 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6070 {
6071         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6072
6073         counters_clear_description(counters);
6074         if (mcounters->hw_cntrs_hndl)
6075                 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6076                                 mcounters->hw_cntrs_hndl);
6077
6078         kfree(mcounters);
6079
6080         return 0;
6081 }
6082
6083 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6084                                                    struct uverbs_attr_bundle *attrs)
6085 {
6086         struct mlx5_ib_mcounters *mcounters;
6087
6088         mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6089         if (!mcounters)
6090                 return ERR_PTR(-ENOMEM);
6091
6092         mutex_init(&mcounters->mcntrs_mutex);
6093
6094         return &mcounters->ibcntrs;
6095 }
6096
6097 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
6098 {
6099         struct mlx5_core_dev *mdev = dev->mdev;
6100
6101         mlx5_ib_cleanup_multiport_master(dev);
6102         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6103                 srcu_barrier(&dev->mr_srcu);
6104                 cleanup_srcu_struct(&dev->mr_srcu);
6105         }
6106
6107         WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
6108
6109         WARN_ON(dev->dm.steering_sw_icm_alloc_blocks &&
6110                 !bitmap_empty(
6111                         dev->dm.steering_sw_icm_alloc_blocks,
6112                         BIT(MLX5_CAP_DEV_MEM(mdev, log_steering_sw_icm_size) -
6113                             MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6114
6115         kfree(dev->dm.steering_sw_icm_alloc_blocks);
6116
6117         WARN_ON(dev->dm.header_modify_sw_icm_alloc_blocks &&
6118                 !bitmap_empty(dev->dm.header_modify_sw_icm_alloc_blocks,
6119                               BIT(MLX5_CAP_DEV_MEM(
6120                                           mdev, log_header_modify_sw_icm_size) -
6121                                   MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6122
6123         kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
6124 }
6125
6126 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
6127 {
6128         struct mlx5_core_dev *mdev = dev->mdev;
6129         u64 header_modify_icm_blocks = 0;
6130         u64 steering_icm_blocks = 0;
6131         int err;
6132         int i;
6133
6134         for (i = 0; i < dev->num_ports; i++) {
6135                 spin_lock_init(&dev->port[i].mp.mpi_lock);
6136                 rwlock_init(&dev->port[i].roce.netdev_lock);
6137                 dev->port[i].roce.dev = dev;
6138                 dev->port[i].roce.native_port_num = i + 1;
6139                 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
6140         }
6141
6142         err = mlx5_ib_init_multiport_master(dev);
6143         if (err)
6144                 return err;
6145
6146         err = set_has_smi_cap(dev);
6147         if (err)
6148                 return err;
6149
6150         if (!mlx5_core_mp_enabled(mdev)) {
6151                 for (i = 1; i <= dev->num_ports; i++) {
6152                         err = get_port_caps(dev, i);
6153                         if (err)
6154                                 break;
6155                 }
6156         } else {
6157                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6158         }
6159         if (err)
6160                 goto err_mp;
6161
6162         if (mlx5_use_mad_ifc(dev))
6163                 get_ext_port_caps(dev);
6164
6165         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
6166         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
6167         dev->ib_dev.phys_port_cnt       = dev->num_ports;
6168         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_count(mdev);
6169         dev->ib_dev.dev.parent          = mdev->device;
6170
6171         mutex_init(&dev->cap_mask_mutex);
6172         INIT_LIST_HEAD(&dev->qp_list);
6173         spin_lock_init(&dev->reset_flow_resource_lock);
6174
6175         if (MLX5_CAP_GEN_64(mdev, general_obj_types) &
6176             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) {
6177                 if (MLX5_CAP64_DEV_MEM(mdev, steering_sw_icm_start_address)) {
6178                         steering_icm_blocks =
6179                                 BIT(MLX5_CAP_DEV_MEM(mdev,
6180                                                      log_steering_sw_icm_size) -
6181                                     MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6182
6183                         dev->dm.steering_sw_icm_alloc_blocks =
6184                                 kcalloc(BITS_TO_LONGS(steering_icm_blocks),
6185                                         sizeof(unsigned long), GFP_KERNEL);
6186                         if (!dev->dm.steering_sw_icm_alloc_blocks)
6187                                 goto err_mp;
6188                 }
6189
6190                 if (MLX5_CAP64_DEV_MEM(mdev,
6191                                        header_modify_sw_icm_start_address)) {
6192                         header_modify_icm_blocks = BIT(
6193                                 MLX5_CAP_DEV_MEM(
6194                                         mdev, log_header_modify_sw_icm_size) -
6195                                 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6196
6197                         dev->dm.header_modify_sw_icm_alloc_blocks =
6198                                 kcalloc(BITS_TO_LONGS(header_modify_icm_blocks),
6199                                         sizeof(unsigned long), GFP_KERNEL);
6200                         if (!dev->dm.header_modify_sw_icm_alloc_blocks)
6201                                 goto err_dm;
6202                 }
6203         }
6204
6205         spin_lock_init(&dev->dm.lock);
6206         dev->dm.dev = mdev;
6207
6208         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6209                 err = init_srcu_struct(&dev->mr_srcu);
6210                 if (err)
6211                         goto err_dm;
6212         }
6213
6214         return 0;
6215
6216 err_dm:
6217         kfree(dev->dm.steering_sw_icm_alloc_blocks);
6218         kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
6219
6220 err_mp:
6221         mlx5_ib_cleanup_multiport_master(dev);
6222
6223         return -ENOMEM;
6224 }
6225
6226 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6227 {
6228         dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6229
6230         if (!dev->flow_db)
6231                 return -ENOMEM;
6232
6233         mutex_init(&dev->flow_db->lock);
6234
6235         return 0;
6236 }
6237
6238 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6239 {
6240         kfree(dev->flow_db);
6241 }
6242
6243 static const struct ib_device_ops mlx5_ib_dev_ops = {
6244         .owner = THIS_MODULE,
6245         .driver_id = RDMA_DRIVER_MLX5,
6246         .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
6247
6248         .add_gid = mlx5_ib_add_gid,
6249         .alloc_mr = mlx5_ib_alloc_mr,
6250         .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
6251         .alloc_pd = mlx5_ib_alloc_pd,
6252         .alloc_ucontext = mlx5_ib_alloc_ucontext,
6253         .attach_mcast = mlx5_ib_mcg_attach,
6254         .check_mr_status = mlx5_ib_check_mr_status,
6255         .create_ah = mlx5_ib_create_ah,
6256         .create_counters = mlx5_ib_create_counters,
6257         .create_cq = mlx5_ib_create_cq,
6258         .create_flow = mlx5_ib_create_flow,
6259         .create_qp = mlx5_ib_create_qp,
6260         .create_srq = mlx5_ib_create_srq,
6261         .dealloc_pd = mlx5_ib_dealloc_pd,
6262         .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6263         .del_gid = mlx5_ib_del_gid,
6264         .dereg_mr = mlx5_ib_dereg_mr,
6265         .destroy_ah = mlx5_ib_destroy_ah,
6266         .destroy_counters = mlx5_ib_destroy_counters,
6267         .destroy_cq = mlx5_ib_destroy_cq,
6268         .destroy_flow = mlx5_ib_destroy_flow,
6269         .destroy_flow_action = mlx5_ib_destroy_flow_action,
6270         .destroy_qp = mlx5_ib_destroy_qp,
6271         .destroy_srq = mlx5_ib_destroy_srq,
6272         .detach_mcast = mlx5_ib_mcg_detach,
6273         .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6274         .drain_rq = mlx5_ib_drain_rq,
6275         .drain_sq = mlx5_ib_drain_sq,
6276         .get_dev_fw_str = get_dev_fw_str,
6277         .get_dma_mr = mlx5_ib_get_dma_mr,
6278         .get_link_layer = mlx5_ib_port_link_layer,
6279         .map_mr_sg = mlx5_ib_map_mr_sg,
6280         .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
6281         .mmap = mlx5_ib_mmap,
6282         .modify_cq = mlx5_ib_modify_cq,
6283         .modify_device = mlx5_ib_modify_device,
6284         .modify_port = mlx5_ib_modify_port,
6285         .modify_qp = mlx5_ib_modify_qp,
6286         .modify_srq = mlx5_ib_modify_srq,
6287         .poll_cq = mlx5_ib_poll_cq,
6288         .post_recv = mlx5_ib_post_recv,
6289         .post_send = mlx5_ib_post_send,
6290         .post_srq_recv = mlx5_ib_post_srq_recv,
6291         .process_mad = mlx5_ib_process_mad,
6292         .query_ah = mlx5_ib_query_ah,
6293         .query_device = mlx5_ib_query_device,
6294         .query_gid = mlx5_ib_query_gid,
6295         .query_pkey = mlx5_ib_query_pkey,
6296         .query_qp = mlx5_ib_query_qp,
6297         .query_srq = mlx5_ib_query_srq,
6298         .read_counters = mlx5_ib_read_counters,
6299         .reg_user_mr = mlx5_ib_reg_user_mr,
6300         .req_notify_cq = mlx5_ib_arm_cq,
6301         .rereg_user_mr = mlx5_ib_rereg_user_mr,
6302         .resize_cq = mlx5_ib_resize_cq,
6303
6304         INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
6305         INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
6306         INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
6307         INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
6308         INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
6309 };
6310
6311 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6312         .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6313         .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6314 };
6315
6316 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6317         .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6318 };
6319
6320 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6321         .get_vf_config = mlx5_ib_get_vf_config,
6322         .get_vf_stats = mlx5_ib_get_vf_stats,
6323         .set_vf_guid = mlx5_ib_set_vf_guid,
6324         .set_vf_link_state = mlx5_ib_set_vf_link_state,
6325 };
6326
6327 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6328         .alloc_mw = mlx5_ib_alloc_mw,
6329         .dealloc_mw = mlx5_ib_dealloc_mw,
6330 };
6331
6332 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6333         .alloc_xrcd = mlx5_ib_alloc_xrcd,
6334         .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6335 };
6336
6337 static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6338         .alloc_dm = mlx5_ib_alloc_dm,
6339         .dealloc_dm = mlx5_ib_dealloc_dm,
6340         .reg_dm_mr = mlx5_ib_reg_dm_mr,
6341 };
6342
6343 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
6344 {
6345         struct mlx5_core_dev *mdev = dev->mdev;
6346         int err;
6347
6348         dev->ib_dev.uverbs_cmd_mask     =
6349                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
6350                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
6351                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
6352                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
6353                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
6354                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
6355                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
6356                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
6357                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
6358                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
6359                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6360                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
6361                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
6362                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
6363                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
6364                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
6365                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
6366                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
6367                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
6368                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
6369                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
6370                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
6371                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
6372                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
6373                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
6374                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
6375         dev->ib_dev.uverbs_ex_cmd_mask =
6376                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
6377                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
6378                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
6379                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
6380                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ)        |
6381                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW)      |
6382                 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6383
6384         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6385             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
6386                 ib_set_device_ops(&dev->ib_dev,
6387                                   &mlx5_ib_dev_ipoib_enhanced_ops);
6388
6389         if (mlx5_core_is_pf(mdev))
6390                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
6391
6392         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6393
6394         if (MLX5_CAP_GEN(mdev, imaicl)) {
6395                 dev->ib_dev.uverbs_cmd_mask |=
6396                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
6397                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
6398                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
6399         }
6400
6401         if (MLX5_CAP_GEN(mdev, xrc)) {
6402                 dev->ib_dev.uverbs_cmd_mask |=
6403                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6404                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
6405                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
6406         }
6407
6408         if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6409             MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6410             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
6411                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
6412
6413         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
6414             MLX5_ACCEL_IPSEC_CAP_DEVICE)
6415                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
6416         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
6417
6418         if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6419                 dev->ib_dev.driver_def = mlx5_ib_defs;
6420
6421         err = init_node_data(dev);
6422         if (err)
6423                 return err;
6424
6425         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
6426             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6427              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
6428                 mutex_init(&dev->lb.mutex);
6429
6430         dev->ib_dev.use_cq_dim = true;
6431
6432         return 0;
6433 }
6434
6435 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6436         .get_port_immutable = mlx5_port_immutable,
6437         .query_port = mlx5_ib_query_port,
6438 };
6439
6440 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6441 {
6442         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
6443         return 0;
6444 }
6445
6446 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6447         .get_port_immutable = mlx5_port_rep_immutable,
6448         .query_port = mlx5_ib_rep_query_port,
6449 };
6450
6451 static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
6452 {
6453         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
6454         return 0;
6455 }
6456
6457 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6458         .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6459         .create_wq = mlx5_ib_create_wq,
6460         .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6461         .destroy_wq = mlx5_ib_destroy_wq,
6462         .get_netdev = mlx5_ib_get_netdev,
6463         .modify_wq = mlx5_ib_modify_wq,
6464 };
6465
6466 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
6467 {
6468         u8 port_num;
6469
6470         dev->ib_dev.uverbs_ex_cmd_mask |=
6471                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6472                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6473                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6474                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6475                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
6476         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
6477
6478         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6479
6480         /* Register only for native ports */
6481         return mlx5_add_netdev_notifier(dev, port_num);
6482 }
6483
6484 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6485 {
6486         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6487
6488         mlx5_remove_netdev_notifier(dev, port_num);
6489 }
6490
6491 static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
6492 {
6493         struct mlx5_core_dev *mdev = dev->mdev;
6494         enum rdma_link_layer ll;
6495         int port_type_cap;
6496         int err = 0;
6497
6498         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6499         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6500
6501         if (ll == IB_LINK_LAYER_ETHERNET)
6502                 err = mlx5_ib_stage_common_roce_init(dev);
6503
6504         return err;
6505 }
6506
6507 static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
6508 {
6509         mlx5_ib_stage_common_roce_cleanup(dev);
6510 }
6511
6512 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6513 {
6514         struct mlx5_core_dev *mdev = dev->mdev;
6515         enum rdma_link_layer ll;
6516         int port_type_cap;
6517         int err;
6518
6519         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6520         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6521
6522         if (ll == IB_LINK_LAYER_ETHERNET) {
6523                 err = mlx5_ib_stage_common_roce_init(dev);
6524                 if (err)
6525                         return err;
6526
6527                 err = mlx5_enable_eth(dev);
6528                 if (err)
6529                         goto cleanup;
6530         }
6531
6532         return 0;
6533 cleanup:
6534         mlx5_ib_stage_common_roce_cleanup(dev);
6535
6536         return err;
6537 }
6538
6539 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6540 {
6541         struct mlx5_core_dev *mdev = dev->mdev;
6542         enum rdma_link_layer ll;
6543         int port_type_cap;
6544
6545         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6546         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6547
6548         if (ll == IB_LINK_LAYER_ETHERNET) {
6549                 mlx5_disable_eth(dev);
6550                 mlx5_ib_stage_common_roce_cleanup(dev);
6551         }
6552 }
6553
6554 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6555 {
6556         return create_dev_resources(&dev->devr);
6557 }
6558
6559 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6560 {
6561         destroy_dev_resources(&dev->devr);
6562 }
6563
6564 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6565 {
6566         mlx5_ib_internal_fill_odp_caps(dev);
6567
6568         return mlx5_ib_odp_init_one(dev);
6569 }
6570
6571 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6572 {
6573         mlx5_ib_odp_cleanup_one(dev);
6574 }
6575
6576 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6577         .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6578         .get_hw_stats = mlx5_ib_get_hw_stats,
6579         .counter_bind_qp = mlx5_ib_counter_bind_qp,
6580         .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6581         .counter_dealloc = mlx5_ib_counter_dealloc,
6582         .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6583         .counter_update_stats = mlx5_ib_counter_update_stats,
6584 };
6585
6586 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6587 {
6588         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6589                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
6590
6591                 return mlx5_ib_alloc_counters(dev);
6592         }
6593
6594         return 0;
6595 }
6596
6597 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6598 {
6599         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6600                 mlx5_ib_dealloc_counters(dev);
6601 }
6602
6603 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6604 {
6605         mlx5_ib_init_cong_debugfs(dev,
6606                                   mlx5_core_native_port_num(dev->mdev) - 1);
6607         return 0;
6608 }
6609
6610 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6611 {
6612         mlx5_ib_cleanup_cong_debugfs(dev,
6613                                      mlx5_core_native_port_num(dev->mdev) - 1);
6614 }
6615
6616 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6617 {
6618         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6619         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6620 }
6621
6622 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6623 {
6624         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6625 }
6626
6627 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6628 {
6629         int err;
6630
6631         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6632         if (err)
6633                 return err;
6634
6635         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6636         if (err)
6637                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6638
6639         return err;
6640 }
6641
6642 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6643 {
6644         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6645         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6646 }
6647
6648 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6649 {
6650         const char *name;
6651
6652         rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
6653         if (!mlx5_lag_is_roce(dev->mdev))
6654                 name = "mlx5_%d";
6655         else
6656                 name = "mlx5_bond_%d";
6657         return ib_register_device(&dev->ib_dev, name);
6658 }
6659
6660 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6661 {
6662         destroy_umrc_res(dev);
6663 }
6664
6665 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6666 {
6667         ib_unregister_device(&dev->ib_dev);
6668 }
6669
6670 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6671 {
6672         return create_umr_res(dev);
6673 }
6674
6675 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6676 {
6677         init_delay_drop(dev);
6678
6679         return 0;
6680 }
6681
6682 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6683 {
6684         cancel_delay_drop(dev);
6685 }
6686
6687 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6688 {
6689         dev->mdev_events.notifier_call = mlx5_ib_event;
6690         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6691         return 0;
6692 }
6693
6694 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6695 {
6696         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6697 }
6698
6699 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6700 {
6701         int uid;
6702
6703         uid = mlx5_ib_devx_create(dev, false);
6704         if (uid > 0) {
6705                 dev->devx_whitelist_uid = uid;
6706                 mlx5_ib_devx_init_event_table(dev);
6707         }
6708
6709         return 0;
6710 }
6711 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6712 {
6713         if (dev->devx_whitelist_uid) {
6714                 mlx5_ib_devx_cleanup_event_table(dev);
6715                 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6716         }
6717 }
6718
6719 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6720                       const struct mlx5_ib_profile *profile,
6721                       int stage)
6722 {
6723         /* Number of stages to cleanup */
6724         while (stage) {
6725                 stage--;
6726                 if (profile->stage[stage].cleanup)
6727                         profile->stage[stage].cleanup(dev);
6728         }
6729
6730         kfree(dev->port);
6731         ib_dealloc_device(&dev->ib_dev);
6732 }
6733
6734 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6735                     const struct mlx5_ib_profile *profile)
6736 {
6737         int err;
6738         int i;
6739
6740         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6741                 if (profile->stage[i].init) {
6742                         err = profile->stage[i].init(dev);
6743                         if (err)
6744                                 goto err_out;
6745                 }
6746         }
6747
6748         dev->profile = profile;
6749         dev->ib_active = true;
6750
6751         return dev;
6752
6753 err_out:
6754         __mlx5_ib_remove(dev, profile, i);
6755
6756         return NULL;
6757 }
6758
6759 static const struct mlx5_ib_profile pf_profile = {
6760         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6761                      mlx5_ib_stage_init_init,
6762                      mlx5_ib_stage_init_cleanup),
6763         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6764                      mlx5_ib_stage_flow_db_init,
6765                      mlx5_ib_stage_flow_db_cleanup),
6766         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6767                      mlx5_ib_stage_caps_init,
6768                      NULL),
6769         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6770                      mlx5_ib_stage_non_default_cb,
6771                      NULL),
6772         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6773                      mlx5_ib_stage_roce_init,
6774                      mlx5_ib_stage_roce_cleanup),
6775         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6776                      mlx5_init_srq_table,
6777                      mlx5_cleanup_srq_table),
6778         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6779                      mlx5_ib_stage_dev_res_init,
6780                      mlx5_ib_stage_dev_res_cleanup),
6781         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6782                      mlx5_ib_stage_dev_notifier_init,
6783                      mlx5_ib_stage_dev_notifier_cleanup),
6784         STAGE_CREATE(MLX5_IB_STAGE_ODP,
6785                      mlx5_ib_stage_odp_init,
6786                      mlx5_ib_stage_odp_cleanup),
6787         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6788                      mlx5_ib_stage_counters_init,
6789                      mlx5_ib_stage_counters_cleanup),
6790         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6791                      mlx5_ib_stage_cong_debugfs_init,
6792                      mlx5_ib_stage_cong_debugfs_cleanup),
6793         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6794                      mlx5_ib_stage_uar_init,
6795                      mlx5_ib_stage_uar_cleanup),
6796         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6797                      mlx5_ib_stage_bfrag_init,
6798                      mlx5_ib_stage_bfrag_cleanup),
6799         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6800                      NULL,
6801                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6802         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6803                      mlx5_ib_stage_devx_init,
6804                      mlx5_ib_stage_devx_cleanup),
6805         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6806                      mlx5_ib_stage_ib_reg_init,
6807                      mlx5_ib_stage_ib_reg_cleanup),
6808         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6809                      mlx5_ib_stage_post_ib_reg_umr_init,
6810                      NULL),
6811         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6812                      mlx5_ib_stage_delay_drop_init,
6813                      mlx5_ib_stage_delay_drop_cleanup),
6814 };
6815
6816 const struct mlx5_ib_profile uplink_rep_profile = {
6817         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6818                      mlx5_ib_stage_init_init,
6819                      mlx5_ib_stage_init_cleanup),
6820         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6821                      mlx5_ib_stage_flow_db_init,
6822                      mlx5_ib_stage_flow_db_cleanup),
6823         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6824                      mlx5_ib_stage_caps_init,
6825                      NULL),
6826         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6827                      mlx5_ib_stage_rep_non_default_cb,
6828                      NULL),
6829         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6830                      mlx5_ib_stage_rep_roce_init,
6831                      mlx5_ib_stage_rep_roce_cleanup),
6832         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6833                      mlx5_init_srq_table,
6834                      mlx5_cleanup_srq_table),
6835         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6836                      mlx5_ib_stage_dev_res_init,
6837                      mlx5_ib_stage_dev_res_cleanup),
6838         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6839                      mlx5_ib_stage_dev_notifier_init,
6840                      mlx5_ib_stage_dev_notifier_cleanup),
6841         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6842                      mlx5_ib_stage_counters_init,
6843                      mlx5_ib_stage_counters_cleanup),
6844         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6845                      mlx5_ib_stage_uar_init,
6846                      mlx5_ib_stage_uar_cleanup),
6847         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6848                      mlx5_ib_stage_bfrag_init,
6849                      mlx5_ib_stage_bfrag_cleanup),
6850         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6851                      NULL,
6852                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6853         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6854                      mlx5_ib_stage_devx_init,
6855                      mlx5_ib_stage_devx_cleanup),
6856         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6857                      mlx5_ib_stage_ib_reg_init,
6858                      mlx5_ib_stage_ib_reg_cleanup),
6859         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6860                      mlx5_ib_stage_post_ib_reg_umr_init,
6861                      NULL),
6862 };
6863
6864 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6865 {
6866         struct mlx5_ib_multiport_info *mpi;
6867         struct mlx5_ib_dev *dev;
6868         bool bound = false;
6869         int err;
6870
6871         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6872         if (!mpi)
6873                 return NULL;
6874
6875         mpi->mdev = mdev;
6876
6877         err = mlx5_query_nic_vport_system_image_guid(mdev,
6878                                                      &mpi->sys_image_guid);
6879         if (err) {
6880                 kfree(mpi);
6881                 return NULL;
6882         }
6883
6884         mutex_lock(&mlx5_ib_multiport_mutex);
6885         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6886                 if (dev->sys_image_guid == mpi->sys_image_guid)
6887                         bound = mlx5_ib_bind_slave_port(dev, mpi);
6888
6889                 if (bound) {
6890                         rdma_roce_rescan_device(&dev->ib_dev);
6891                         break;
6892                 }
6893         }
6894
6895         if (!bound) {
6896                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6897                 dev_dbg(mdev->device,
6898                         "no suitable IB device found to bind to, added to unaffiliated list.\n");
6899         }
6900         mutex_unlock(&mlx5_ib_multiport_mutex);
6901
6902         return mpi;
6903 }
6904
6905 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6906 {
6907         enum rdma_link_layer ll;
6908         struct mlx5_ib_dev *dev;
6909         int port_type_cap;
6910         int num_ports;
6911
6912         printk_once(KERN_INFO "%s", mlx5_version);
6913
6914         if (MLX5_ESWITCH_MANAGER(mdev) &&
6915             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
6916                 if (!mlx5_core_mp_enabled(mdev))
6917                         mlx5_ib_register_vport_reps(mdev);
6918                 return mdev;
6919         }
6920
6921         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6922         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6923
6924         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6925                 return mlx5_ib_add_slave_port(mdev);
6926
6927         num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6928                         MLX5_CAP_GEN(mdev, num_vhca_ports));
6929         dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
6930         if (!dev)
6931                 return NULL;
6932         dev->port = kcalloc(num_ports, sizeof(*dev->port),
6933                              GFP_KERNEL);
6934         if (!dev->port) {
6935                 ib_dealloc_device((struct ib_device *)dev);
6936                 return NULL;
6937         }
6938
6939         dev->mdev = mdev;
6940         dev->num_ports = num_ports;
6941
6942         return __mlx5_ib_add(dev, &pf_profile);
6943 }
6944
6945 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6946 {
6947         struct mlx5_ib_multiport_info *mpi;
6948         struct mlx5_ib_dev *dev;
6949
6950         if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6951                 mlx5_ib_unregister_vport_reps(mdev);
6952                 return;
6953         }
6954
6955         if (mlx5_core_is_mp_slave(mdev)) {
6956                 mpi = context;
6957                 mutex_lock(&mlx5_ib_multiport_mutex);
6958                 if (mpi->ibdev)
6959                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6960                 list_del(&mpi->list);
6961                 mutex_unlock(&mlx5_ib_multiport_mutex);
6962                 return;
6963         }
6964
6965         dev = context;
6966         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6967 }
6968
6969 static struct mlx5_interface mlx5_ib_interface = {
6970         .add            = mlx5_ib_add,
6971         .remove         = mlx5_ib_remove,
6972         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
6973 };
6974
6975 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6976 {
6977         mutex_lock(&xlt_emergency_page_mutex);
6978         return xlt_emergency_page;
6979 }
6980
6981 void mlx5_ib_put_xlt_emergency_page(void)
6982 {
6983         mutex_unlock(&xlt_emergency_page_mutex);
6984 }
6985
6986 static int __init mlx5_ib_init(void)
6987 {
6988         int err;
6989
6990         xlt_emergency_page = __get_free_page(GFP_KERNEL);
6991         if (!xlt_emergency_page)
6992                 return -ENOMEM;
6993
6994         mutex_init(&xlt_emergency_page_mutex);
6995
6996         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6997         if (!mlx5_ib_event_wq) {
6998                 free_page(xlt_emergency_page);
6999                 return -ENOMEM;
7000         }
7001
7002         mlx5_ib_odp_init();
7003
7004         err = mlx5_register_interface(&mlx5_ib_interface);
7005
7006         return err;
7007 }
7008
7009 static void __exit mlx5_ib_cleanup(void)
7010 {
7011         mlx5_unregister_interface(&mlx5_ib_interface);
7012         destroy_workqueue(mlx5_ib_event_wq);
7013         mutex_destroy(&xlt_emergency_page_mutex);
7014         free_page(xlt_emergency_page);
7015 }
7016
7017 module_init(mlx5_ib_init);
7018 module_exit(mlx5_ib_cleanup);