IB/mlx5: Allow future extension of libmlx5 input data
[sfrench/cifs-2.6.git] / drivers / infiniband / hw / mlx5 / main.c
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
41 #include <asm/pat.h>
42 #endif
43 #include <linux/sched.h>
44 #include <linux/delay.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_addr.h>
47 #include <rdma/ib_cache.h>
48 #include <linux/mlx5/port.h>
49 #include <linux/mlx5/vport.h>
50 #include <linux/list.h>
51 #include <rdma/ib_smi.h>
52 #include <rdma/ib_umem.h>
53 #include <linux/in.h>
54 #include <linux/etherdevice.h>
55 #include <linux/mlx5/fs.h>
56 #include "mlx5_ib.h"
57
58 #define DRIVER_NAME "mlx5_ib"
59 #define DRIVER_VERSION "2.2-1"
60 #define DRIVER_RELDATE  "Feb 2014"
61
62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_VERSION(DRIVER_VERSION);
66
67 static int deprecated_prof_sel = 2;
68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
70
71 static char mlx5_version[] =
72         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
74
75 enum {
76         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77 };
78
79 static enum rdma_link_layer
80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
81 {
82         switch (port_type_cap) {
83         case MLX5_CAP_PORT_TYPE_IB:
84                 return IB_LINK_LAYER_INFINIBAND;
85         case MLX5_CAP_PORT_TYPE_ETH:
86                 return IB_LINK_LAYER_ETHERNET;
87         default:
88                 return IB_LINK_LAYER_UNSPECIFIED;
89         }
90 }
91
92 static enum rdma_link_layer
93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94 {
95         struct mlx5_ib_dev *dev = to_mdev(device);
96         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99 }
100
101 static int mlx5_netdev_event(struct notifier_block *this,
102                              unsigned long event, void *ptr)
103 {
104         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
105         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
106                                                  roce.nb);
107
108         switch (event) {
109         case NETDEV_REGISTER:
110         case NETDEV_UNREGISTER:
111                 write_lock(&ibdev->roce.netdev_lock);
112                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
113                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
114                                              NULL : ndev;
115                 write_unlock(&ibdev->roce.netdev_lock);
116                 break;
117
118         case NETDEV_UP:
119         case NETDEV_DOWN: {
120                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
121                 struct net_device *upper = NULL;
122
123                 if (lag_ndev) {
124                         upper = netdev_master_upper_dev_get(lag_ndev);
125                         dev_put(lag_ndev);
126                 }
127
128                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
129                     && ibdev->ib_active) {
130                         struct ib_event ibev = { };
131
132                         ibev.device = &ibdev->ib_dev;
133                         ibev.event = (event == NETDEV_UP) ?
134                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
135                         ibev.element.port_num = 1;
136                         ib_dispatch_event(&ibev);
137                 }
138                 break;
139         }
140
141         default:
142                 break;
143         }
144
145         return NOTIFY_DONE;
146 }
147
148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
149                                              u8 port_num)
150 {
151         struct mlx5_ib_dev *ibdev = to_mdev(device);
152         struct net_device *ndev;
153
154         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
155         if (ndev)
156                 return ndev;
157
158         /* Ensure ndev does not disappear before we invoke dev_hold()
159          */
160         read_lock(&ibdev->roce.netdev_lock);
161         ndev = ibdev->roce.netdev;
162         if (ndev)
163                 dev_hold(ndev);
164         read_unlock(&ibdev->roce.netdev_lock);
165
166         return ndev;
167 }
168
169 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
170                                 struct ib_port_attr *props)
171 {
172         struct mlx5_ib_dev *dev = to_mdev(device);
173         struct net_device *ndev, *upper;
174         enum ib_mtu ndev_ib_mtu;
175         u16 qkey_viol_cntr;
176
177         memset(props, 0, sizeof(*props));
178
179         props->port_cap_flags  |= IB_PORT_CM_SUP;
180         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
181
182         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
183                                                 roce_address_table_size);
184         props->max_mtu          = IB_MTU_4096;
185         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
186         props->pkey_tbl_len     = 1;
187         props->state            = IB_PORT_DOWN;
188         props->phys_state       = 3;
189
190         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
191         props->qkey_viol_cntr = qkey_viol_cntr;
192
193         ndev = mlx5_ib_get_netdev(device, port_num);
194         if (!ndev)
195                 return 0;
196
197         if (mlx5_lag_is_active(dev->mdev)) {
198                 rcu_read_lock();
199                 upper = netdev_master_upper_dev_get_rcu(ndev);
200                 if (upper) {
201                         dev_put(ndev);
202                         ndev = upper;
203                         dev_hold(ndev);
204                 }
205                 rcu_read_unlock();
206         }
207
208         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
209                 props->state      = IB_PORT_ACTIVE;
210                 props->phys_state = 5;
211         }
212
213         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
214
215         dev_put(ndev);
216
217         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
218
219         props->active_width     = IB_WIDTH_4X;  /* TODO */
220         props->active_speed     = IB_SPEED_QDR; /* TODO */
221
222         return 0;
223 }
224
225 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
226                                      const struct ib_gid_attr *attr,
227                                      void *mlx5_addr)
228 {
229 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
230         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
231                                                source_l3_address);
232         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
233                                                source_mac_47_32);
234
235         if (!gid)
236                 return;
237
238         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
239
240         if (is_vlan_dev(attr->ndev)) {
241                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
242                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
243         }
244
245         switch (attr->gid_type) {
246         case IB_GID_TYPE_IB:
247                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
248                 break;
249         case IB_GID_TYPE_ROCE_UDP_ENCAP:
250                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
251                 break;
252
253         default:
254                 WARN_ON(true);
255         }
256
257         if (attr->gid_type != IB_GID_TYPE_IB) {
258                 if (ipv6_addr_v4mapped((void *)gid))
259                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
260                                     MLX5_ROCE_L3_TYPE_IPV4);
261                 else
262                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
263                                     MLX5_ROCE_L3_TYPE_IPV6);
264         }
265
266         if ((attr->gid_type == IB_GID_TYPE_IB) ||
267             !ipv6_addr_v4mapped((void *)gid))
268                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
269         else
270                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
271 }
272
273 static int set_roce_addr(struct ib_device *device, u8 port_num,
274                          unsigned int index,
275                          const union ib_gid *gid,
276                          const struct ib_gid_attr *attr)
277 {
278         struct mlx5_ib_dev *dev = to_mdev(device);
279         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
280         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
281         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
282         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
283
284         if (ll != IB_LINK_LAYER_ETHERNET)
285                 return -EINVAL;
286
287         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
288
289         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
290         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
291         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
292 }
293
294 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
295                            unsigned int index, const union ib_gid *gid,
296                            const struct ib_gid_attr *attr,
297                            __always_unused void **context)
298 {
299         return set_roce_addr(device, port_num, index, gid, attr);
300 }
301
302 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
303                            unsigned int index, __always_unused void **context)
304 {
305         return set_roce_addr(device, port_num, index, NULL, NULL);
306 }
307
308 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
309                                int index)
310 {
311         struct ib_gid_attr attr;
312         union ib_gid gid;
313
314         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
315                 return 0;
316
317         if (!attr.ndev)
318                 return 0;
319
320         dev_put(attr.ndev);
321
322         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
323                 return 0;
324
325         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
326 }
327
328 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
329 {
330         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
331                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
332         return 0;
333 }
334
335 enum {
336         MLX5_VPORT_ACCESS_METHOD_MAD,
337         MLX5_VPORT_ACCESS_METHOD_HCA,
338         MLX5_VPORT_ACCESS_METHOD_NIC,
339 };
340
341 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
342 {
343         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
344                 return MLX5_VPORT_ACCESS_METHOD_MAD;
345
346         if (mlx5_ib_port_link_layer(ibdev, 1) ==
347             IB_LINK_LAYER_ETHERNET)
348                 return MLX5_VPORT_ACCESS_METHOD_NIC;
349
350         return MLX5_VPORT_ACCESS_METHOD_HCA;
351 }
352
353 static void get_atomic_caps(struct mlx5_ib_dev *dev,
354                             struct ib_device_attr *props)
355 {
356         u8 tmp;
357         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
358         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
359         u8 atomic_req_8B_endianness_mode =
360                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
361
362         /* Check if HW supports 8 bytes standard atomic operations and capable
363          * of host endianness respond
364          */
365         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
366         if (((atomic_operations & tmp) == tmp) &&
367             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
368             (atomic_req_8B_endianness_mode)) {
369                 props->atomic_cap = IB_ATOMIC_HCA;
370         } else {
371                 props->atomic_cap = IB_ATOMIC_NONE;
372         }
373 }
374
375 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
376                                         __be64 *sys_image_guid)
377 {
378         struct mlx5_ib_dev *dev = to_mdev(ibdev);
379         struct mlx5_core_dev *mdev = dev->mdev;
380         u64 tmp;
381         int err;
382
383         switch (mlx5_get_vport_access_method(ibdev)) {
384         case MLX5_VPORT_ACCESS_METHOD_MAD:
385                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
386                                                             sys_image_guid);
387
388         case MLX5_VPORT_ACCESS_METHOD_HCA:
389                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
390                 break;
391
392         case MLX5_VPORT_ACCESS_METHOD_NIC:
393                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
394                 break;
395
396         default:
397                 return -EINVAL;
398         }
399
400         if (!err)
401                 *sys_image_guid = cpu_to_be64(tmp);
402
403         return err;
404
405 }
406
407 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
408                                 u16 *max_pkeys)
409 {
410         struct mlx5_ib_dev *dev = to_mdev(ibdev);
411         struct mlx5_core_dev *mdev = dev->mdev;
412
413         switch (mlx5_get_vport_access_method(ibdev)) {
414         case MLX5_VPORT_ACCESS_METHOD_MAD:
415                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
416
417         case MLX5_VPORT_ACCESS_METHOD_HCA:
418         case MLX5_VPORT_ACCESS_METHOD_NIC:
419                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
420                                                 pkey_table_size));
421                 return 0;
422
423         default:
424                 return -EINVAL;
425         }
426 }
427
428 static int mlx5_query_vendor_id(struct ib_device *ibdev,
429                                 u32 *vendor_id)
430 {
431         struct mlx5_ib_dev *dev = to_mdev(ibdev);
432
433         switch (mlx5_get_vport_access_method(ibdev)) {
434         case MLX5_VPORT_ACCESS_METHOD_MAD:
435                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
436
437         case MLX5_VPORT_ACCESS_METHOD_HCA:
438         case MLX5_VPORT_ACCESS_METHOD_NIC:
439                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
440
441         default:
442                 return -EINVAL;
443         }
444 }
445
446 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
447                                 __be64 *node_guid)
448 {
449         u64 tmp;
450         int err;
451
452         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
453         case MLX5_VPORT_ACCESS_METHOD_MAD:
454                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
455
456         case MLX5_VPORT_ACCESS_METHOD_HCA:
457                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
458                 break;
459
460         case MLX5_VPORT_ACCESS_METHOD_NIC:
461                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
462                 break;
463
464         default:
465                 return -EINVAL;
466         }
467
468         if (!err)
469                 *node_guid = cpu_to_be64(tmp);
470
471         return err;
472 }
473
474 struct mlx5_reg_node_desc {
475         u8      desc[IB_DEVICE_NODE_DESC_MAX];
476 };
477
478 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
479 {
480         struct mlx5_reg_node_desc in;
481
482         if (mlx5_use_mad_ifc(dev))
483                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
484
485         memset(&in, 0, sizeof(in));
486
487         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
488                                     sizeof(struct mlx5_reg_node_desc),
489                                     MLX5_REG_NODE_DESC, 0, 0);
490 }
491
492 static int mlx5_ib_query_device(struct ib_device *ibdev,
493                                 struct ib_device_attr *props,
494                                 struct ib_udata *uhw)
495 {
496         struct mlx5_ib_dev *dev = to_mdev(ibdev);
497         struct mlx5_core_dev *mdev = dev->mdev;
498         int err = -ENOMEM;
499         int max_sq_desc;
500         int max_rq_sg;
501         int max_sq_sg;
502         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
503         struct mlx5_ib_query_device_resp resp = {};
504         size_t resp_len;
505         u64 max_tso;
506
507         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
508         if (uhw->outlen && uhw->outlen < resp_len)
509                 return -EINVAL;
510         else
511                 resp.response_length = resp_len;
512
513         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
514                 return -EINVAL;
515
516         memset(props, 0, sizeof(*props));
517         err = mlx5_query_system_image_guid(ibdev,
518                                            &props->sys_image_guid);
519         if (err)
520                 return err;
521
522         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
523         if (err)
524                 return err;
525
526         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
527         if (err)
528                 return err;
529
530         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
531                 (fw_rev_min(dev->mdev) << 16) |
532                 fw_rev_sub(dev->mdev);
533         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
534                 IB_DEVICE_PORT_ACTIVE_EVENT             |
535                 IB_DEVICE_SYS_IMAGE_GUID                |
536                 IB_DEVICE_RC_RNR_NAK_GEN;
537
538         if (MLX5_CAP_GEN(mdev, pkv))
539                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
540         if (MLX5_CAP_GEN(mdev, qkv))
541                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
542         if (MLX5_CAP_GEN(mdev, apm))
543                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
544         if (MLX5_CAP_GEN(mdev, xrc))
545                 props->device_cap_flags |= IB_DEVICE_XRC;
546         if (MLX5_CAP_GEN(mdev, imaicl)) {
547                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
548                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
549                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
550                 /* We support 'Gappy' memory registration too */
551                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
552         }
553         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
554         if (MLX5_CAP_GEN(mdev, sho)) {
555                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
556                 /* At this stage no support for signature handover */
557                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
558                                       IB_PROT_T10DIF_TYPE_2 |
559                                       IB_PROT_T10DIF_TYPE_3;
560                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
561                                        IB_GUARD_T10DIF_CSUM;
562         }
563         if (MLX5_CAP_GEN(mdev, block_lb_mc))
564                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
565
566         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
567                 if (MLX5_CAP_ETH(mdev, csum_cap))
568                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
569
570                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
571                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
572                         if (max_tso) {
573                                 resp.tso_caps.max_tso = 1 << max_tso;
574                                 resp.tso_caps.supported_qpts |=
575                                         1 << IB_QPT_RAW_PACKET;
576                                 resp.response_length += sizeof(resp.tso_caps);
577                         }
578                 }
579
580                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
581                         resp.rss_caps.rx_hash_function =
582                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
583                         resp.rss_caps.rx_hash_fields_mask =
584                                                 MLX5_RX_HASH_SRC_IPV4 |
585                                                 MLX5_RX_HASH_DST_IPV4 |
586                                                 MLX5_RX_HASH_SRC_IPV6 |
587                                                 MLX5_RX_HASH_DST_IPV6 |
588                                                 MLX5_RX_HASH_SRC_PORT_TCP |
589                                                 MLX5_RX_HASH_DST_PORT_TCP |
590                                                 MLX5_RX_HASH_SRC_PORT_UDP |
591                                                 MLX5_RX_HASH_DST_PORT_UDP;
592                         resp.response_length += sizeof(resp.rss_caps);
593                 }
594         } else {
595                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
596                         resp.response_length += sizeof(resp.tso_caps);
597                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
598                         resp.response_length += sizeof(resp.rss_caps);
599         }
600
601         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
602                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
603                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
604         }
605
606         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
607             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
608                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
609
610         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
611                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
612
613         props->vendor_part_id      = mdev->pdev->device;
614         props->hw_ver              = mdev->pdev->revision;
615
616         props->max_mr_size         = ~0ull;
617         props->page_size_cap       = ~(min_page_size - 1);
618         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
619         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
620         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
621                      sizeof(struct mlx5_wqe_data_seg);
622         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
623         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
624                      sizeof(struct mlx5_wqe_raddr_seg)) /
625                 sizeof(struct mlx5_wqe_data_seg);
626         props->max_sge = min(max_rq_sg, max_sq_sg);
627         props->max_sge_rd          = MLX5_MAX_SGE_RD;
628         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
629         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
630         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
631         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
632         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
633         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
634         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
635         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
636         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
637         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
638         props->max_srq_sge         = max_rq_sg - 1;
639         props->max_fast_reg_page_list_len =
640                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
641         get_atomic_caps(dev, props);
642         props->masked_atomic_cap   = IB_ATOMIC_NONE;
643         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
644         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
645         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
646                                            props->max_mcast_grp;
647         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
648         props->max_ah = INT_MAX;
649         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
650         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
651
652 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
653         if (MLX5_CAP_GEN(mdev, pg))
654                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
655         props->odp_caps = dev->odp_caps;
656 #endif
657
658         if (MLX5_CAP_GEN(mdev, cd))
659                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
660
661         if (!mlx5_core_is_pf(mdev))
662                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
663
664         if (mlx5_ib_port_link_layer(ibdev, 1) ==
665             IB_LINK_LAYER_ETHERNET) {
666                 props->rss_caps.max_rwq_indirection_tables =
667                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
668                 props->rss_caps.max_rwq_indirection_table_size =
669                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
670                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
671                 props->max_wq_type_rq =
672                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
673         }
674
675         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
676                 resp.cqe_comp_caps.max_num =
677                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
678                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
679                 resp.cqe_comp_caps.supported_format =
680                         MLX5_IB_CQE_RES_FORMAT_HASH |
681                         MLX5_IB_CQE_RES_FORMAT_CSUM;
682                 resp.response_length += sizeof(resp.cqe_comp_caps);
683         }
684
685         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
686                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
687                     MLX5_CAP_GEN(mdev, qos)) {
688                         resp.packet_pacing_caps.qp_rate_limit_max =
689                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
690                         resp.packet_pacing_caps.qp_rate_limit_min =
691                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
692                         resp.packet_pacing_caps.supported_qpts |=
693                                 1 << IB_QPT_RAW_PACKET;
694                 }
695                 resp.response_length += sizeof(resp.packet_pacing_caps);
696         }
697
698         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
699                         uhw->outlen)) {
700                 resp.mlx5_ib_support_multi_pkt_send_wqes =
701                         MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
702                 resp.response_length +=
703                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
704         }
705
706         if (field_avail(typeof(resp), reserved, uhw->outlen))
707                 resp.response_length += sizeof(resp.reserved);
708
709         if (uhw->outlen) {
710                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
711
712                 if (err)
713                         return err;
714         }
715
716         return 0;
717 }
718
719 enum mlx5_ib_width {
720         MLX5_IB_WIDTH_1X        = 1 << 0,
721         MLX5_IB_WIDTH_2X        = 1 << 1,
722         MLX5_IB_WIDTH_4X        = 1 << 2,
723         MLX5_IB_WIDTH_8X        = 1 << 3,
724         MLX5_IB_WIDTH_12X       = 1 << 4
725 };
726
727 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
728                                   u8 *ib_width)
729 {
730         struct mlx5_ib_dev *dev = to_mdev(ibdev);
731         int err = 0;
732
733         if (active_width & MLX5_IB_WIDTH_1X) {
734                 *ib_width = IB_WIDTH_1X;
735         } else if (active_width & MLX5_IB_WIDTH_2X) {
736                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
737                             (int)active_width);
738                 err = -EINVAL;
739         } else if (active_width & MLX5_IB_WIDTH_4X) {
740                 *ib_width = IB_WIDTH_4X;
741         } else if (active_width & MLX5_IB_WIDTH_8X) {
742                 *ib_width = IB_WIDTH_8X;
743         } else if (active_width & MLX5_IB_WIDTH_12X) {
744                 *ib_width = IB_WIDTH_12X;
745         } else {
746                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
747                             (int)active_width);
748                 err = -EINVAL;
749         }
750
751         return err;
752 }
753
754 static int mlx5_mtu_to_ib_mtu(int mtu)
755 {
756         switch (mtu) {
757         case 256: return 1;
758         case 512: return 2;
759         case 1024: return 3;
760         case 2048: return 4;
761         case 4096: return 5;
762         default:
763                 pr_warn("invalid mtu\n");
764                 return -1;
765         }
766 }
767
768 enum ib_max_vl_num {
769         __IB_MAX_VL_0           = 1,
770         __IB_MAX_VL_0_1         = 2,
771         __IB_MAX_VL_0_3         = 3,
772         __IB_MAX_VL_0_7         = 4,
773         __IB_MAX_VL_0_14        = 5,
774 };
775
776 enum mlx5_vl_hw_cap {
777         MLX5_VL_HW_0    = 1,
778         MLX5_VL_HW_0_1  = 2,
779         MLX5_VL_HW_0_2  = 3,
780         MLX5_VL_HW_0_3  = 4,
781         MLX5_VL_HW_0_4  = 5,
782         MLX5_VL_HW_0_5  = 6,
783         MLX5_VL_HW_0_6  = 7,
784         MLX5_VL_HW_0_7  = 8,
785         MLX5_VL_HW_0_14 = 15
786 };
787
788 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
789                                 u8 *max_vl_num)
790 {
791         switch (vl_hw_cap) {
792         case MLX5_VL_HW_0:
793                 *max_vl_num = __IB_MAX_VL_0;
794                 break;
795         case MLX5_VL_HW_0_1:
796                 *max_vl_num = __IB_MAX_VL_0_1;
797                 break;
798         case MLX5_VL_HW_0_3:
799                 *max_vl_num = __IB_MAX_VL_0_3;
800                 break;
801         case MLX5_VL_HW_0_7:
802                 *max_vl_num = __IB_MAX_VL_0_7;
803                 break;
804         case MLX5_VL_HW_0_14:
805                 *max_vl_num = __IB_MAX_VL_0_14;
806                 break;
807
808         default:
809                 return -EINVAL;
810         }
811
812         return 0;
813 }
814
815 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
816                                struct ib_port_attr *props)
817 {
818         struct mlx5_ib_dev *dev = to_mdev(ibdev);
819         struct mlx5_core_dev *mdev = dev->mdev;
820         struct mlx5_hca_vport_context *rep;
821         u16 max_mtu;
822         u16 oper_mtu;
823         int err;
824         u8 ib_link_width_oper;
825         u8 vl_hw_cap;
826
827         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
828         if (!rep) {
829                 err = -ENOMEM;
830                 goto out;
831         }
832
833         memset(props, 0, sizeof(*props));
834
835         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
836         if (err)
837                 goto out;
838
839         props->lid              = rep->lid;
840         props->lmc              = rep->lmc;
841         props->sm_lid           = rep->sm_lid;
842         props->sm_sl            = rep->sm_sl;
843         props->state            = rep->vport_state;
844         props->phys_state       = rep->port_physical_state;
845         props->port_cap_flags   = rep->cap_mask1;
846         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
847         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
848         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
849         props->bad_pkey_cntr    = rep->pkey_violation_counter;
850         props->qkey_viol_cntr   = rep->qkey_violation_counter;
851         props->subnet_timeout   = rep->subnet_timeout;
852         props->init_type_reply  = rep->init_type_reply;
853         props->grh_required     = rep->grh_required;
854
855         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
856         if (err)
857                 goto out;
858
859         err = translate_active_width(ibdev, ib_link_width_oper,
860                                      &props->active_width);
861         if (err)
862                 goto out;
863         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
864         if (err)
865                 goto out;
866
867         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
868
869         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
870
871         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
872
873         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
874
875         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
876         if (err)
877                 goto out;
878
879         err = translate_max_vl_num(ibdev, vl_hw_cap,
880                                    &props->max_vl_num);
881 out:
882         kfree(rep);
883         return err;
884 }
885
886 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
887                        struct ib_port_attr *props)
888 {
889         switch (mlx5_get_vport_access_method(ibdev)) {
890         case MLX5_VPORT_ACCESS_METHOD_MAD:
891                 return mlx5_query_mad_ifc_port(ibdev, port, props);
892
893         case MLX5_VPORT_ACCESS_METHOD_HCA:
894                 return mlx5_query_hca_port(ibdev, port, props);
895
896         case MLX5_VPORT_ACCESS_METHOD_NIC:
897                 return mlx5_query_port_roce(ibdev, port, props);
898
899         default:
900                 return -EINVAL;
901         }
902 }
903
904 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
905                              union ib_gid *gid)
906 {
907         struct mlx5_ib_dev *dev = to_mdev(ibdev);
908         struct mlx5_core_dev *mdev = dev->mdev;
909
910         switch (mlx5_get_vport_access_method(ibdev)) {
911         case MLX5_VPORT_ACCESS_METHOD_MAD:
912                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
913
914         case MLX5_VPORT_ACCESS_METHOD_HCA:
915                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
916
917         default:
918                 return -EINVAL;
919         }
920
921 }
922
923 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
924                               u16 *pkey)
925 {
926         struct mlx5_ib_dev *dev = to_mdev(ibdev);
927         struct mlx5_core_dev *mdev = dev->mdev;
928
929         switch (mlx5_get_vport_access_method(ibdev)) {
930         case MLX5_VPORT_ACCESS_METHOD_MAD:
931                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
932
933         case MLX5_VPORT_ACCESS_METHOD_HCA:
934         case MLX5_VPORT_ACCESS_METHOD_NIC:
935                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
936                                                  pkey);
937         default:
938                 return -EINVAL;
939         }
940 }
941
942 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
943                                  struct ib_device_modify *props)
944 {
945         struct mlx5_ib_dev *dev = to_mdev(ibdev);
946         struct mlx5_reg_node_desc in;
947         struct mlx5_reg_node_desc out;
948         int err;
949
950         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
951                 return -EOPNOTSUPP;
952
953         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
954                 return 0;
955
956         /*
957          * If possible, pass node desc to FW, so it can generate
958          * a 144 trap.  If cmd fails, just ignore.
959          */
960         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
961         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
962                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
963         if (err)
964                 return err;
965
966         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
967
968         return err;
969 }
970
971 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
972                                struct ib_port_modify *props)
973 {
974         struct mlx5_ib_dev *dev = to_mdev(ibdev);
975         struct ib_port_attr attr;
976         u32 tmp;
977         int err;
978
979         mutex_lock(&dev->cap_mask_mutex);
980
981         err = mlx5_ib_query_port(ibdev, port, &attr);
982         if (err)
983                 goto out;
984
985         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
986                 ~props->clr_port_cap_mask;
987
988         err = mlx5_set_port_caps(dev->mdev, port, tmp);
989
990 out:
991         mutex_unlock(&dev->cap_mask_mutex);
992         return err;
993 }
994
995 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
996                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
997                              u32 *num_sys_pages)
998 {
999         int uars_per_sys_page;
1000         int bfregs_per_sys_page;
1001         int ref_bfregs = req->total_num_bfregs;
1002
1003         if (req->total_num_bfregs == 0)
1004                 return -EINVAL;
1005
1006         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1007         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1008
1009         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1010                 return -ENOMEM;
1011
1012         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1013         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1014         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1015         *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1016
1017         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1018                 return -EINVAL;
1019
1020         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1021                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1022                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1023                     req->total_num_bfregs, *num_sys_pages);
1024
1025         return 0;
1026 }
1027
1028 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1029 {
1030         struct mlx5_bfreg_info *bfregi;
1031         int err;
1032         int i;
1033
1034         bfregi = &context->bfregi;
1035         for (i = 0; i < bfregi->num_sys_pages; i++) {
1036                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1037                 if (err)
1038                         goto error;
1039
1040                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1041         }
1042         return 0;
1043
1044 error:
1045         for (--i; i >= 0; i--)
1046                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1047                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1048
1049         return err;
1050 }
1051
1052 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1053 {
1054         struct mlx5_bfreg_info *bfregi;
1055         int err;
1056         int i;
1057
1058         bfregi = &context->bfregi;
1059         for (i = 0; i < bfregi->num_sys_pages; i++) {
1060                 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1061                 if (err) {
1062                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1063                         return err;
1064                 }
1065         }
1066         return 0;
1067 }
1068
1069 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1070                                                   struct ib_udata *udata)
1071 {
1072         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1073         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1074         struct mlx5_ib_alloc_ucontext_resp resp = {};
1075         struct mlx5_ib_ucontext *context;
1076         struct mlx5_bfreg_info *bfregi;
1077         int ver;
1078         int err;
1079         size_t reqlen;
1080         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1081                                      max_cqe_version);
1082         bool lib_uar_4k;
1083
1084         if (!dev->ib_active)
1085                 return ERR_PTR(-EAGAIN);
1086
1087         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1088                 return ERR_PTR(-EINVAL);
1089
1090         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1091         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1092                 ver = 0;
1093         else if (reqlen >= min_req_v2)
1094                 ver = 2;
1095         else
1096                 return ERR_PTR(-EINVAL);
1097
1098         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1099         if (err)
1100                 return ERR_PTR(err);
1101
1102         if (req.flags)
1103                 return ERR_PTR(-EINVAL);
1104
1105         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1106                 return ERR_PTR(-EOPNOTSUPP);
1107
1108         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1109                                     MLX5_NON_FP_BFREGS_PER_UAR);
1110         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1111                 return ERR_PTR(-EINVAL);
1112
1113         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1114         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1115                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1116         resp.cache_line_size = cache_line_size();
1117         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1118         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1119         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1120         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1121         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1122         resp.cqe_version = min_t(__u8,
1123                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1124                                  req.max_cqe_version);
1125         resp.response_length = min(offsetof(typeof(resp), response_length) +
1126                                    sizeof(resp.response_length), udata->outlen);
1127
1128         context = kzalloc(sizeof(*context), GFP_KERNEL);
1129         if (!context)
1130                 return ERR_PTR(-ENOMEM);
1131
1132         lib_uar_4k = false;
1133         bfregi = &context->bfregi;
1134
1135         /* updates req->total_num_bfregs */
1136         err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1137         if (err)
1138                 goto out_ctx;
1139
1140         mutex_init(&bfregi->lock);
1141         bfregi->lib_uar_4k = lib_uar_4k;
1142         bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
1143                                 GFP_KERNEL);
1144         if (!bfregi->count) {
1145                 err = -ENOMEM;
1146                 goto out_ctx;
1147         }
1148
1149         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1150                                     sizeof(*bfregi->sys_pages),
1151                                     GFP_KERNEL);
1152         if (!bfregi->sys_pages) {
1153                 err = -ENOMEM;
1154                 goto out_count;
1155         }
1156
1157         err = allocate_uars(dev, context);
1158         if (err)
1159                 goto out_sys_pages;
1160
1161 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1162         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1163 #endif
1164
1165         context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1166         if (!context->upd_xlt_page) {
1167                 err = -ENOMEM;
1168                 goto out_uars;
1169         }
1170         mutex_init(&context->upd_xlt_page_mutex);
1171
1172         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1173                 err = mlx5_core_alloc_transport_domain(dev->mdev,
1174                                                        &context->tdn);
1175                 if (err)
1176                         goto out_page;
1177         }
1178
1179         INIT_LIST_HEAD(&context->vma_private_list);
1180         INIT_LIST_HEAD(&context->db_page_list);
1181         mutex_init(&context->db_page_mutex);
1182
1183         resp.tot_bfregs = req.total_num_bfregs;
1184         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1185
1186         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1187                 resp.response_length += sizeof(resp.cqe_version);
1188
1189         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1190                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1191                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1192                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1193         }
1194
1195         /*
1196          * We don't want to expose information from the PCI bar that is located
1197          * after 4096 bytes, so if the arch only supports larger pages, let's
1198          * pretend we don't support reading the HCA's core clock. This is also
1199          * forced by mmap function.
1200          */
1201         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1202                 if (PAGE_SIZE <= 4096) {
1203                         resp.comp_mask |=
1204                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1205                         resp.hca_core_clock_offset =
1206                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1207                 }
1208                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1209                                         sizeof(resp.reserved2);
1210         }
1211
1212         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1213         if (err)
1214                 goto out_td;
1215
1216         bfregi->ver = ver;
1217         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1218         context->cqe_version = resp.cqe_version;
1219         context->lib_caps = false;
1220
1221         return &context->ibucontext;
1222
1223 out_td:
1224         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1225                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1226
1227 out_page:
1228         free_page(context->upd_xlt_page);
1229
1230 out_uars:
1231         deallocate_uars(dev, context);
1232
1233 out_sys_pages:
1234         kfree(bfregi->sys_pages);
1235
1236 out_count:
1237         kfree(bfregi->count);
1238
1239 out_ctx:
1240         kfree(context);
1241
1242         return ERR_PTR(err);
1243 }
1244
1245 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1246 {
1247         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1248         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1249         struct mlx5_bfreg_info *bfregi;
1250
1251         bfregi = &context->bfregi;
1252         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1253                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1254
1255         free_page(context->upd_xlt_page);
1256         deallocate_uars(dev, context);
1257         kfree(bfregi->sys_pages);
1258         kfree(bfregi->count);
1259         kfree(context);
1260
1261         return 0;
1262 }
1263
1264 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1265                                  struct mlx5_bfreg_info *bfregi,
1266                                  int idx)
1267 {
1268         int fw_uars_per_page;
1269
1270         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1271
1272         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1273                         bfregi->sys_pages[idx] / fw_uars_per_page;
1274 }
1275
1276 static int get_command(unsigned long offset)
1277 {
1278         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1279 }
1280
1281 static int get_arg(unsigned long offset)
1282 {
1283         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1284 }
1285
1286 static int get_index(unsigned long offset)
1287 {
1288         return get_arg(offset);
1289 }
1290
1291 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1292 {
1293         /* vma_open is called when a new VMA is created on top of our VMA.  This
1294          * is done through either mremap flow or split_vma (usually due to
1295          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1296          * as this VMA is strongly hardware related.  Therefore we set the
1297          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1298          * calling us again and trying to do incorrect actions.  We assume that
1299          * the original VMA size is exactly a single page, and therefore all
1300          * "splitting" operation will not happen to it.
1301          */
1302         area->vm_ops = NULL;
1303 }
1304
1305 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1306 {
1307         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1308
1309         /* It's guaranteed that all VMAs opened on a FD are closed before the
1310          * file itself is closed, therefore no sync is needed with the regular
1311          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1312          * However need a sync with accessing the vma as part of
1313          * mlx5_ib_disassociate_ucontext.
1314          * The close operation is usually called under mm->mmap_sem except when
1315          * process is exiting.
1316          * The exiting case is handled explicitly as part of
1317          * mlx5_ib_disassociate_ucontext.
1318          */
1319         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1320
1321         /* setting the vma context pointer to null in the mlx5_ib driver's
1322          * private data, to protect a race condition in
1323          * mlx5_ib_disassociate_ucontext().
1324          */
1325         mlx5_ib_vma_priv_data->vma = NULL;
1326         list_del(&mlx5_ib_vma_priv_data->list);
1327         kfree(mlx5_ib_vma_priv_data);
1328 }
1329
1330 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1331         .open = mlx5_ib_vma_open,
1332         .close = mlx5_ib_vma_close
1333 };
1334
1335 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1336                                 struct mlx5_ib_ucontext *ctx)
1337 {
1338         struct mlx5_ib_vma_private_data *vma_prv;
1339         struct list_head *vma_head = &ctx->vma_private_list;
1340
1341         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1342         if (!vma_prv)
1343                 return -ENOMEM;
1344
1345         vma_prv->vma = vma;
1346         vma->vm_private_data = vma_prv;
1347         vma->vm_ops =  &mlx5_ib_vm_ops;
1348
1349         list_add(&vma_prv->list, vma_head);
1350
1351         return 0;
1352 }
1353
1354 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1355 {
1356         int ret;
1357         struct vm_area_struct *vma;
1358         struct mlx5_ib_vma_private_data *vma_private, *n;
1359         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1360         struct task_struct *owning_process  = NULL;
1361         struct mm_struct   *owning_mm       = NULL;
1362
1363         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1364         if (!owning_process)
1365                 return;
1366
1367         owning_mm = get_task_mm(owning_process);
1368         if (!owning_mm) {
1369                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1370                 while (1) {
1371                         put_task_struct(owning_process);
1372                         usleep_range(1000, 2000);
1373                         owning_process = get_pid_task(ibcontext->tgid,
1374                                                       PIDTYPE_PID);
1375                         if (!owning_process ||
1376                             owning_process->state == TASK_DEAD) {
1377                                 pr_info("disassociate ucontext done, task was terminated\n");
1378                                 /* in case task was dead need to release the
1379                                  * task struct.
1380                                  */
1381                                 if (owning_process)
1382                                         put_task_struct(owning_process);
1383                                 return;
1384                         }
1385                 }
1386         }
1387
1388         /* need to protect from a race on closing the vma as part of
1389          * mlx5_ib_vma_close.
1390          */
1391         down_read(&owning_mm->mmap_sem);
1392         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1393                                  list) {
1394                 vma = vma_private->vma;
1395                 ret = zap_vma_ptes(vma, vma->vm_start,
1396                                    PAGE_SIZE);
1397                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1398                 /* context going to be destroyed, should
1399                  * not access ops any more.
1400                  */
1401                 vma->vm_ops = NULL;
1402                 list_del(&vma_private->list);
1403                 kfree(vma_private);
1404         }
1405         up_read(&owning_mm->mmap_sem);
1406         mmput(owning_mm);
1407         put_task_struct(owning_process);
1408 }
1409
1410 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1411 {
1412         switch (cmd) {
1413         case MLX5_IB_MMAP_WC_PAGE:
1414                 return "WC";
1415         case MLX5_IB_MMAP_REGULAR_PAGE:
1416                 return "best effort WC";
1417         case MLX5_IB_MMAP_NC_PAGE:
1418                 return "NC";
1419         default:
1420                 return NULL;
1421         }
1422 }
1423
1424 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1425                     struct vm_area_struct *vma,
1426                     struct mlx5_ib_ucontext *context)
1427 {
1428         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1429         int err;
1430         unsigned long idx;
1431         phys_addr_t pfn, pa;
1432         pgprot_t prot;
1433         int uars_per_page;
1434
1435         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1436                 return -EINVAL;
1437
1438         uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1439         idx = get_index(vma->vm_pgoff);
1440         if (idx % uars_per_page ||
1441             idx * uars_per_page >= bfregi->num_sys_pages) {
1442                 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1443                 return -EINVAL;
1444         }
1445
1446         switch (cmd) {
1447         case MLX5_IB_MMAP_WC_PAGE:
1448 /* Some architectures don't support WC memory */
1449 #if defined(CONFIG_X86)
1450                 if (!pat_enabled())
1451                         return -EPERM;
1452 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1453                         return -EPERM;
1454 #endif
1455         /* fall through */
1456         case MLX5_IB_MMAP_REGULAR_PAGE:
1457                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1458                 prot = pgprot_writecombine(vma->vm_page_prot);
1459                 break;
1460         case MLX5_IB_MMAP_NC_PAGE:
1461                 prot = pgprot_noncached(vma->vm_page_prot);
1462                 break;
1463         default:
1464                 return -EINVAL;
1465         }
1466
1467         pfn = uar_index2pfn(dev, bfregi, idx);
1468         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1469
1470         vma->vm_page_prot = prot;
1471         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1472                                  PAGE_SIZE, vma->vm_page_prot);
1473         if (err) {
1474                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1475                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1476                 return -EAGAIN;
1477         }
1478
1479         pa = pfn << PAGE_SHIFT;
1480         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1481                     vma->vm_start, &pa);
1482
1483         return mlx5_ib_set_vma_data(vma, context);
1484 }
1485
1486 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1487 {
1488         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1489         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1490         unsigned long command;
1491         phys_addr_t pfn;
1492
1493         command = get_command(vma->vm_pgoff);
1494         switch (command) {
1495         case MLX5_IB_MMAP_WC_PAGE:
1496         case MLX5_IB_MMAP_NC_PAGE:
1497         case MLX5_IB_MMAP_REGULAR_PAGE:
1498                 return uar_mmap(dev, command, vma, context);
1499
1500         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1501                 return -ENOSYS;
1502
1503         case MLX5_IB_MMAP_CORE_CLOCK:
1504                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1505                         return -EINVAL;
1506
1507                 if (vma->vm_flags & VM_WRITE)
1508                         return -EPERM;
1509
1510                 /* Don't expose to user-space information it shouldn't have */
1511                 if (PAGE_SIZE > 4096)
1512                         return -EOPNOTSUPP;
1513
1514                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1515                 pfn = (dev->mdev->iseg_base +
1516                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1517                         PAGE_SHIFT;
1518                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1519                                        PAGE_SIZE, vma->vm_page_prot))
1520                         return -EAGAIN;
1521
1522                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1523                             vma->vm_start,
1524                             (unsigned long long)pfn << PAGE_SHIFT);
1525                 break;
1526
1527         default:
1528                 return -EINVAL;
1529         }
1530
1531         return 0;
1532 }
1533
1534 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1535                                       struct ib_ucontext *context,
1536                                       struct ib_udata *udata)
1537 {
1538         struct mlx5_ib_alloc_pd_resp resp;
1539         struct mlx5_ib_pd *pd;
1540         int err;
1541
1542         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1543         if (!pd)
1544                 return ERR_PTR(-ENOMEM);
1545
1546         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1547         if (err) {
1548                 kfree(pd);
1549                 return ERR_PTR(err);
1550         }
1551
1552         if (context) {
1553                 resp.pdn = pd->pdn;
1554                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1555                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1556                         kfree(pd);
1557                         return ERR_PTR(-EFAULT);
1558                 }
1559         }
1560
1561         return &pd->ibpd;
1562 }
1563
1564 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1565 {
1566         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1567         struct mlx5_ib_pd *mpd = to_mpd(pd);
1568
1569         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1570         kfree(mpd);
1571
1572         return 0;
1573 }
1574
1575 enum {
1576         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1577         MATCH_CRITERIA_ENABLE_MISC_BIT,
1578         MATCH_CRITERIA_ENABLE_INNER_BIT
1579 };
1580
1581 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1582         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1583                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1584
1585 static u8 get_match_criteria_enable(u32 *match_criteria)
1586 {
1587         u8 match_criteria_enable;
1588
1589         match_criteria_enable =
1590                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1591                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1592         match_criteria_enable |=
1593                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1594                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1595         match_criteria_enable |=
1596                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1597                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1598
1599         return match_criteria_enable;
1600 }
1601
1602 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1603 {
1604         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1605         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1606 }
1607
1608 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1609                            bool inner)
1610 {
1611         if (inner) {
1612                 MLX5_SET(fte_match_set_misc,
1613                          misc_c, inner_ipv6_flow_label, mask);
1614                 MLX5_SET(fte_match_set_misc,
1615                          misc_v, inner_ipv6_flow_label, val);
1616         } else {
1617                 MLX5_SET(fte_match_set_misc,
1618                          misc_c, outer_ipv6_flow_label, mask);
1619                 MLX5_SET(fte_match_set_misc,
1620                          misc_v, outer_ipv6_flow_label, val);
1621         }
1622 }
1623
1624 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1625 {
1626         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1627         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1628         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1629         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1630 }
1631
1632 #define LAST_ETH_FIELD vlan_tag
1633 #define LAST_IB_FIELD sl
1634 #define LAST_IPV4_FIELD tos
1635 #define LAST_IPV6_FIELD traffic_class
1636 #define LAST_TCP_UDP_FIELD src_port
1637 #define LAST_TUNNEL_FIELD tunnel_id
1638
1639 /* Field is the last supported field */
1640 #define FIELDS_NOT_SUPPORTED(filter, field)\
1641         memchr_inv((void *)&filter.field  +\
1642                    sizeof(filter.field), 0,\
1643                    sizeof(filter) -\
1644                    offsetof(typeof(filter), field) -\
1645                    sizeof(filter.field))
1646
1647 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1648                            const union ib_flow_spec *ib_spec)
1649 {
1650         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1651                                            misc_parameters);
1652         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1653                                            misc_parameters);
1654         void *headers_c;
1655         void *headers_v;
1656
1657         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1658                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1659                                          inner_headers);
1660                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1661                                          inner_headers);
1662         } else {
1663                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1664                                          outer_headers);
1665                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1666                                          outer_headers);
1667         }
1668
1669         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1670         case IB_FLOW_SPEC_ETH:
1671                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1672                         return -ENOTSUPP;
1673
1674                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1675                                              dmac_47_16),
1676                                 ib_spec->eth.mask.dst_mac);
1677                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1678                                              dmac_47_16),
1679                                 ib_spec->eth.val.dst_mac);
1680
1681                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1682                                              smac_47_16),
1683                                 ib_spec->eth.mask.src_mac);
1684                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1685                                              smac_47_16),
1686                                 ib_spec->eth.val.src_mac);
1687
1688                 if (ib_spec->eth.mask.vlan_tag) {
1689                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1690                                  vlan_tag, 1);
1691                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1692                                  vlan_tag, 1);
1693
1694                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1695                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1696                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1697                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1698
1699                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1700                                  first_cfi,
1701                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1702                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1703                                  first_cfi,
1704                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1705
1706                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1707                                  first_prio,
1708                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1709                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1710                                  first_prio,
1711                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1712                 }
1713                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1714                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1715                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1716                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1717                 break;
1718         case IB_FLOW_SPEC_IPV4:
1719                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1720                         return -ENOTSUPP;
1721
1722                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1723                          ethertype, 0xffff);
1724                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1725                          ethertype, ETH_P_IP);
1726
1727                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1728                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1729                        &ib_spec->ipv4.mask.src_ip,
1730                        sizeof(ib_spec->ipv4.mask.src_ip));
1731                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1732                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1733                        &ib_spec->ipv4.val.src_ip,
1734                        sizeof(ib_spec->ipv4.val.src_ip));
1735                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1736                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1737                        &ib_spec->ipv4.mask.dst_ip,
1738                        sizeof(ib_spec->ipv4.mask.dst_ip));
1739                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1740                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1741                        &ib_spec->ipv4.val.dst_ip,
1742                        sizeof(ib_spec->ipv4.val.dst_ip));
1743
1744                 set_tos(headers_c, headers_v,
1745                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1746
1747                 set_proto(headers_c, headers_v,
1748                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1749                 break;
1750         case IB_FLOW_SPEC_IPV6:
1751                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1752                         return -ENOTSUPP;
1753
1754                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1755                          ethertype, 0xffff);
1756                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1757                          ethertype, ETH_P_IPV6);
1758
1759                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1760                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1761                        &ib_spec->ipv6.mask.src_ip,
1762                        sizeof(ib_spec->ipv6.mask.src_ip));
1763                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1764                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1765                        &ib_spec->ipv6.val.src_ip,
1766                        sizeof(ib_spec->ipv6.val.src_ip));
1767                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1768                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1769                        &ib_spec->ipv6.mask.dst_ip,
1770                        sizeof(ib_spec->ipv6.mask.dst_ip));
1771                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1772                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1773                        &ib_spec->ipv6.val.dst_ip,
1774                        sizeof(ib_spec->ipv6.val.dst_ip));
1775
1776                 set_tos(headers_c, headers_v,
1777                         ib_spec->ipv6.mask.traffic_class,
1778                         ib_spec->ipv6.val.traffic_class);
1779
1780                 set_proto(headers_c, headers_v,
1781                           ib_spec->ipv6.mask.next_hdr,
1782                           ib_spec->ipv6.val.next_hdr);
1783
1784                 set_flow_label(misc_params_c, misc_params_v,
1785                                ntohl(ib_spec->ipv6.mask.flow_label),
1786                                ntohl(ib_spec->ipv6.val.flow_label),
1787                                ib_spec->type & IB_FLOW_SPEC_INNER);
1788
1789                 break;
1790         case IB_FLOW_SPEC_TCP:
1791                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1792                                          LAST_TCP_UDP_FIELD))
1793                         return -ENOTSUPP;
1794
1795                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1796                          0xff);
1797                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1798                          IPPROTO_TCP);
1799
1800                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
1801                          ntohs(ib_spec->tcp_udp.mask.src_port));
1802                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1803                          ntohs(ib_spec->tcp_udp.val.src_port));
1804
1805                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
1806                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1807                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1808                          ntohs(ib_spec->tcp_udp.val.dst_port));
1809                 break;
1810         case IB_FLOW_SPEC_UDP:
1811                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1812                                          LAST_TCP_UDP_FIELD))
1813                         return -ENOTSUPP;
1814
1815                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1816                          0xff);
1817                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1818                          IPPROTO_UDP);
1819
1820                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
1821                          ntohs(ib_spec->tcp_udp.mask.src_port));
1822                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1823                          ntohs(ib_spec->tcp_udp.val.src_port));
1824
1825                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
1826                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1827                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1828                          ntohs(ib_spec->tcp_udp.val.dst_port));
1829                 break;
1830         case IB_FLOW_SPEC_VXLAN_TUNNEL:
1831                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1832                                          LAST_TUNNEL_FIELD))
1833                         return -ENOTSUPP;
1834
1835                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
1836                          ntohl(ib_spec->tunnel.mask.tunnel_id));
1837                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
1838                          ntohl(ib_spec->tunnel.val.tunnel_id));
1839                 break;
1840         default:
1841                 return -EINVAL;
1842         }
1843
1844         return 0;
1845 }
1846
1847 /* If a flow could catch both multicast and unicast packets,
1848  * it won't fall into the multicast flow steering table and this rule
1849  * could steal other multicast packets.
1850  */
1851 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1852 {
1853         struct ib_flow_spec_eth *eth_spec;
1854
1855         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1856             ib_attr->size < sizeof(struct ib_flow_attr) +
1857             sizeof(struct ib_flow_spec_eth) ||
1858             ib_attr->num_of_specs < 1)
1859                 return false;
1860
1861         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1862         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1863             eth_spec->size != sizeof(*eth_spec))
1864                 return false;
1865
1866         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1867                is_multicast_ether_addr(eth_spec->val.dst_mac);
1868 }
1869
1870 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1871 {
1872         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1873         bool has_ipv4_spec = false;
1874         bool eth_type_ipv4 = true;
1875         unsigned int spec_index;
1876
1877         /* Validate that ethertype is correct */
1878         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1879                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1880                     ib_spec->eth.mask.ether_type) {
1881                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1882                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1883                                 eth_type_ipv4 = false;
1884                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1885                         has_ipv4_spec = true;
1886                 }
1887                 ib_spec = (void *)ib_spec + ib_spec->size;
1888         }
1889         return !has_ipv4_spec || eth_type_ipv4;
1890 }
1891
1892 static void put_flow_table(struct mlx5_ib_dev *dev,
1893                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1894 {
1895         prio->refcount -= !!ft_added;
1896         if (!prio->refcount) {
1897                 mlx5_destroy_flow_table(prio->flow_table);
1898                 prio->flow_table = NULL;
1899         }
1900 }
1901
1902 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1903 {
1904         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1905         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1906                                                           struct mlx5_ib_flow_handler,
1907                                                           ibflow);
1908         struct mlx5_ib_flow_handler *iter, *tmp;
1909
1910         mutex_lock(&dev->flow_db.lock);
1911
1912         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1913                 mlx5_del_flow_rules(iter->rule);
1914                 put_flow_table(dev, iter->prio, true);
1915                 list_del(&iter->list);
1916                 kfree(iter);
1917         }
1918
1919         mlx5_del_flow_rules(handler->rule);
1920         put_flow_table(dev, handler->prio, true);
1921         mutex_unlock(&dev->flow_db.lock);
1922
1923         kfree(handler);
1924
1925         return 0;
1926 }
1927
1928 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1929 {
1930         priority *= 2;
1931         if (!dont_trap)
1932                 priority++;
1933         return priority;
1934 }
1935
1936 enum flow_table_type {
1937         MLX5_IB_FT_RX,
1938         MLX5_IB_FT_TX
1939 };
1940
1941 #define MLX5_FS_MAX_TYPES        10
1942 #define MLX5_FS_MAX_ENTRIES      32000UL
1943 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1944                                                 struct ib_flow_attr *flow_attr,
1945                                                 enum flow_table_type ft_type)
1946 {
1947         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1948         struct mlx5_flow_namespace *ns = NULL;
1949         struct mlx5_ib_flow_prio *prio;
1950         struct mlx5_flow_table *ft;
1951         int num_entries;
1952         int num_groups;
1953         int priority;
1954         int err = 0;
1955
1956         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1957                 if (flow_is_multicast_only(flow_attr) &&
1958                     !dont_trap)
1959                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1960                 else
1961                         priority = ib_prio_to_core_prio(flow_attr->priority,
1962                                                         dont_trap);
1963                 ns = mlx5_get_flow_namespace(dev->mdev,
1964                                              MLX5_FLOW_NAMESPACE_BYPASS);
1965                 num_entries = MLX5_FS_MAX_ENTRIES;
1966                 num_groups = MLX5_FS_MAX_TYPES;
1967                 prio = &dev->flow_db.prios[priority];
1968         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1969                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1970                 ns = mlx5_get_flow_namespace(dev->mdev,
1971                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1972                 build_leftovers_ft_param(&priority,
1973                                          &num_entries,
1974                                          &num_groups);
1975                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1976         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1977                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1978                                         allow_sniffer_and_nic_rx_shared_tir))
1979                         return ERR_PTR(-ENOTSUPP);
1980
1981                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1982                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1983                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1984
1985                 prio = &dev->flow_db.sniffer[ft_type];
1986                 priority = 0;
1987                 num_entries = 1;
1988                 num_groups = 1;
1989         }
1990
1991         if (!ns)
1992                 return ERR_PTR(-ENOTSUPP);
1993
1994         ft = prio->flow_table;
1995         if (!ft) {
1996                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1997                                                          num_entries,
1998                                                          num_groups,
1999                                                          0, 0);
2000
2001                 if (!IS_ERR(ft)) {
2002                         prio->refcount = 0;
2003                         prio->flow_table = ft;
2004                 } else {
2005                         err = PTR_ERR(ft);
2006                 }
2007         }
2008
2009         return err ? ERR_PTR(err) : prio;
2010 }
2011
2012 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2013                                                      struct mlx5_ib_flow_prio *ft_prio,
2014                                                      const struct ib_flow_attr *flow_attr,
2015                                                      struct mlx5_flow_destination *dst)
2016 {
2017         struct mlx5_flow_table  *ft = ft_prio->flow_table;
2018         struct mlx5_ib_flow_handler *handler;
2019         struct mlx5_flow_act flow_act = {0};
2020         struct mlx5_flow_spec *spec;
2021         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2022         unsigned int spec_index;
2023         int err = 0;
2024
2025         if (!is_valid_attr(flow_attr))
2026                 return ERR_PTR(-EINVAL);
2027
2028         spec = mlx5_vzalloc(sizeof(*spec));
2029         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2030         if (!handler || !spec) {
2031                 err = -ENOMEM;
2032                 goto free;
2033         }
2034
2035         INIT_LIST_HEAD(&handler->list);
2036
2037         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2038                 err = parse_flow_attr(spec->match_criteria,
2039                                       spec->match_value, ib_flow);
2040                 if (err < 0)
2041                         goto free;
2042
2043                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2044         }
2045
2046         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2047         flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2048                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2049         flow_act.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2050         handler->rule = mlx5_add_flow_rules(ft, spec,
2051                                             &flow_act,
2052                                             dst, 1);
2053
2054         if (IS_ERR(handler->rule)) {
2055                 err = PTR_ERR(handler->rule);
2056                 goto free;
2057         }
2058
2059         ft_prio->refcount++;
2060         handler->prio = ft_prio;
2061
2062         ft_prio->flow_table = ft;
2063 free:
2064         if (err)
2065                 kfree(handler);
2066         kvfree(spec);
2067         return err ? ERR_PTR(err) : handler;
2068 }
2069
2070 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2071                                                           struct mlx5_ib_flow_prio *ft_prio,
2072                                                           struct ib_flow_attr *flow_attr,
2073                                                           struct mlx5_flow_destination *dst)
2074 {
2075         struct mlx5_ib_flow_handler *handler_dst = NULL;
2076         struct mlx5_ib_flow_handler *handler = NULL;
2077
2078         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2079         if (!IS_ERR(handler)) {
2080                 handler_dst = create_flow_rule(dev, ft_prio,
2081                                                flow_attr, dst);
2082                 if (IS_ERR(handler_dst)) {
2083                         mlx5_del_flow_rules(handler->rule);
2084                         ft_prio->refcount--;
2085                         kfree(handler);
2086                         handler = handler_dst;
2087                 } else {
2088                         list_add(&handler_dst->list, &handler->list);
2089                 }
2090         }
2091
2092         return handler;
2093 }
2094 enum {
2095         LEFTOVERS_MC,
2096         LEFTOVERS_UC,
2097 };
2098
2099 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2100                                                           struct mlx5_ib_flow_prio *ft_prio,
2101                                                           struct ib_flow_attr *flow_attr,
2102                                                           struct mlx5_flow_destination *dst)
2103 {
2104         struct mlx5_ib_flow_handler *handler_ucast = NULL;
2105         struct mlx5_ib_flow_handler *handler = NULL;
2106
2107         static struct {
2108                 struct ib_flow_attr     flow_attr;
2109                 struct ib_flow_spec_eth eth_flow;
2110         } leftovers_specs[] = {
2111                 [LEFTOVERS_MC] = {
2112                         .flow_attr = {
2113                                 .num_of_specs = 1,
2114                                 .size = sizeof(leftovers_specs[0])
2115                         },
2116                         .eth_flow = {
2117                                 .type = IB_FLOW_SPEC_ETH,
2118                                 .size = sizeof(struct ib_flow_spec_eth),
2119                                 .mask = {.dst_mac = {0x1} },
2120                                 .val =  {.dst_mac = {0x1} }
2121                         }
2122                 },
2123                 [LEFTOVERS_UC] = {
2124                         .flow_attr = {
2125                                 .num_of_specs = 1,
2126                                 .size = sizeof(leftovers_specs[0])
2127                         },
2128                         .eth_flow = {
2129                                 .type = IB_FLOW_SPEC_ETH,
2130                                 .size = sizeof(struct ib_flow_spec_eth),
2131                                 .mask = {.dst_mac = {0x1} },
2132                                 .val = {.dst_mac = {} }
2133                         }
2134                 }
2135         };
2136
2137         handler = create_flow_rule(dev, ft_prio,
2138                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2139                                    dst);
2140         if (!IS_ERR(handler) &&
2141             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2142                 handler_ucast = create_flow_rule(dev, ft_prio,
2143                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2144                                                  dst);
2145                 if (IS_ERR(handler_ucast)) {
2146                         mlx5_del_flow_rules(handler->rule);
2147                         ft_prio->refcount--;
2148                         kfree(handler);
2149                         handler = handler_ucast;
2150                 } else {
2151                         list_add(&handler_ucast->list, &handler->list);
2152                 }
2153         }
2154
2155         return handler;
2156 }
2157
2158 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2159                                                         struct mlx5_ib_flow_prio *ft_rx,
2160                                                         struct mlx5_ib_flow_prio *ft_tx,
2161                                                         struct mlx5_flow_destination *dst)
2162 {
2163         struct mlx5_ib_flow_handler *handler_rx;
2164         struct mlx5_ib_flow_handler *handler_tx;
2165         int err;
2166         static const struct ib_flow_attr flow_attr  = {
2167                 .num_of_specs = 0,
2168                 .size = sizeof(flow_attr)
2169         };
2170
2171         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2172         if (IS_ERR(handler_rx)) {
2173                 err = PTR_ERR(handler_rx);
2174                 goto err;
2175         }
2176
2177         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2178         if (IS_ERR(handler_tx)) {
2179                 err = PTR_ERR(handler_tx);
2180                 goto err_tx;
2181         }
2182
2183         list_add(&handler_tx->list, &handler_rx->list);
2184
2185         return handler_rx;
2186
2187 err_tx:
2188         mlx5_del_flow_rules(handler_rx->rule);
2189         ft_rx->refcount--;
2190         kfree(handler_rx);
2191 err:
2192         return ERR_PTR(err);
2193 }
2194
2195 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2196                                            struct ib_flow_attr *flow_attr,
2197                                            int domain)
2198 {
2199         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2200         struct mlx5_ib_qp *mqp = to_mqp(qp);
2201         struct mlx5_ib_flow_handler *handler = NULL;
2202         struct mlx5_flow_destination *dst = NULL;
2203         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2204         struct mlx5_ib_flow_prio *ft_prio;
2205         int err;
2206
2207         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2208                 return ERR_PTR(-ENOSPC);
2209
2210         if (domain != IB_FLOW_DOMAIN_USER ||
2211             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2212             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2213                 return ERR_PTR(-EINVAL);
2214
2215         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2216         if (!dst)
2217                 return ERR_PTR(-ENOMEM);
2218
2219         mutex_lock(&dev->flow_db.lock);
2220
2221         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2222         if (IS_ERR(ft_prio)) {
2223                 err = PTR_ERR(ft_prio);
2224                 goto unlock;
2225         }
2226         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2227                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2228                 if (IS_ERR(ft_prio_tx)) {
2229                         err = PTR_ERR(ft_prio_tx);
2230                         ft_prio_tx = NULL;
2231                         goto destroy_ft;
2232                 }
2233         }
2234
2235         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2236         if (mqp->flags & MLX5_IB_QP_RSS)
2237                 dst->tir_num = mqp->rss_qp.tirn;
2238         else
2239                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2240
2241         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2242                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2243                         handler = create_dont_trap_rule(dev, ft_prio,
2244                                                         flow_attr, dst);
2245                 } else {
2246                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2247                                                    dst);
2248                 }
2249         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2250                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2251                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2252                                                 dst);
2253         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2254                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2255         } else {
2256                 err = -EINVAL;
2257                 goto destroy_ft;
2258         }
2259
2260         if (IS_ERR(handler)) {
2261                 err = PTR_ERR(handler);
2262                 handler = NULL;
2263                 goto destroy_ft;
2264         }
2265
2266         mutex_unlock(&dev->flow_db.lock);
2267         kfree(dst);
2268
2269         return &handler->ibflow;
2270
2271 destroy_ft:
2272         put_flow_table(dev, ft_prio, false);
2273         if (ft_prio_tx)
2274                 put_flow_table(dev, ft_prio_tx, false);
2275 unlock:
2276         mutex_unlock(&dev->flow_db.lock);
2277         kfree(dst);
2278         kfree(handler);
2279         return ERR_PTR(err);
2280 }
2281
2282 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2283 {
2284         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2285         int err;
2286
2287         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2288         if (err)
2289                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2290                              ibqp->qp_num, gid->raw);
2291
2292         return err;
2293 }
2294
2295 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2296 {
2297         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2298         int err;
2299
2300         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2301         if (err)
2302                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2303                              ibqp->qp_num, gid->raw);
2304
2305         return err;
2306 }
2307
2308 static int init_node_data(struct mlx5_ib_dev *dev)
2309 {
2310         int err;
2311
2312         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2313         if (err)
2314                 return err;
2315
2316         dev->mdev->rev_id = dev->mdev->pdev->revision;
2317
2318         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2319 }
2320
2321 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2322                              char *buf)
2323 {
2324         struct mlx5_ib_dev *dev =
2325                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2326
2327         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2328 }
2329
2330 static ssize_t show_reg_pages(struct device *device,
2331                               struct device_attribute *attr, char *buf)
2332 {
2333         struct mlx5_ib_dev *dev =
2334                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2335
2336         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2337 }
2338
2339 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2340                         char *buf)
2341 {
2342         struct mlx5_ib_dev *dev =
2343                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2344         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2345 }
2346
2347 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2348                         char *buf)
2349 {
2350         struct mlx5_ib_dev *dev =
2351                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2352         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2353 }
2354
2355 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2356                           char *buf)
2357 {
2358         struct mlx5_ib_dev *dev =
2359                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2360         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2361                        dev->mdev->board_id);
2362 }
2363
2364 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2365 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2366 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2367 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2368 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2369
2370 static struct device_attribute *mlx5_class_attributes[] = {
2371         &dev_attr_hw_rev,
2372         &dev_attr_hca_type,
2373         &dev_attr_board_id,
2374         &dev_attr_fw_pages,
2375         &dev_attr_reg_pages,
2376 };
2377
2378 static void pkey_change_handler(struct work_struct *work)
2379 {
2380         struct mlx5_ib_port_resources *ports =
2381                 container_of(work, struct mlx5_ib_port_resources,
2382                              pkey_change_work);
2383
2384         mutex_lock(&ports->devr->mutex);
2385         mlx5_ib_gsi_pkey_change(ports->gsi);
2386         mutex_unlock(&ports->devr->mutex);
2387 }
2388
2389 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2390 {
2391         struct mlx5_ib_qp *mqp;
2392         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2393         struct mlx5_core_cq *mcq;
2394         struct list_head cq_armed_list;
2395         unsigned long flags_qp;
2396         unsigned long flags_cq;
2397         unsigned long flags;
2398
2399         INIT_LIST_HEAD(&cq_armed_list);
2400
2401         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2402         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2403         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2404                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2405                 if (mqp->sq.tail != mqp->sq.head) {
2406                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2407                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2408                         if (send_mcq->mcq.comp &&
2409                             mqp->ibqp.send_cq->comp_handler) {
2410                                 if (!send_mcq->mcq.reset_notify_added) {
2411                                         send_mcq->mcq.reset_notify_added = 1;
2412                                         list_add_tail(&send_mcq->mcq.reset_notify,
2413                                                       &cq_armed_list);
2414                                 }
2415                         }
2416                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2417                 }
2418                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2419                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2420                 /* no handling is needed for SRQ */
2421                 if (!mqp->ibqp.srq) {
2422                         if (mqp->rq.tail != mqp->rq.head) {
2423                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2424                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2425                                 if (recv_mcq->mcq.comp &&
2426                                     mqp->ibqp.recv_cq->comp_handler) {
2427                                         if (!recv_mcq->mcq.reset_notify_added) {
2428                                                 recv_mcq->mcq.reset_notify_added = 1;
2429                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2430                                                               &cq_armed_list);
2431                                         }
2432                                 }
2433                                 spin_unlock_irqrestore(&recv_mcq->lock,
2434                                                        flags_cq);
2435                         }
2436                 }
2437                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2438         }
2439         /*At that point all inflight post send were put to be executed as of we
2440          * lock/unlock above locks Now need to arm all involved CQs.
2441          */
2442         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2443                 mcq->comp(mcq);
2444         }
2445         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2446 }
2447
2448 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2449                           enum mlx5_dev_event event, unsigned long param)
2450 {
2451         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2452         struct ib_event ibev;
2453         bool fatal = false;
2454         u8 port = 0;
2455
2456         switch (event) {
2457         case MLX5_DEV_EVENT_SYS_ERROR:
2458                 ibev.event = IB_EVENT_DEVICE_FATAL;
2459                 mlx5_ib_handle_internal_error(ibdev);
2460                 fatal = true;
2461                 break;
2462
2463         case MLX5_DEV_EVENT_PORT_UP:
2464         case MLX5_DEV_EVENT_PORT_DOWN:
2465         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2466                 port = (u8)param;
2467
2468                 /* In RoCE, port up/down events are handled in
2469                  * mlx5_netdev_event().
2470                  */
2471                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2472                         IB_LINK_LAYER_ETHERNET)
2473                         return;
2474
2475                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2476                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2477                 break;
2478
2479         case MLX5_DEV_EVENT_LID_CHANGE:
2480                 ibev.event = IB_EVENT_LID_CHANGE;
2481                 port = (u8)param;
2482                 break;
2483
2484         case MLX5_DEV_EVENT_PKEY_CHANGE:
2485                 ibev.event = IB_EVENT_PKEY_CHANGE;
2486                 port = (u8)param;
2487
2488                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2489                 break;
2490
2491         case MLX5_DEV_EVENT_GUID_CHANGE:
2492                 ibev.event = IB_EVENT_GID_CHANGE;
2493                 port = (u8)param;
2494                 break;
2495
2496         case MLX5_DEV_EVENT_CLIENT_REREG:
2497                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2498                 port = (u8)param;
2499                 break;
2500         default:
2501                 return;
2502         }
2503
2504         ibev.device           = &ibdev->ib_dev;
2505         ibev.element.port_num = port;
2506
2507         if (port < 1 || port > ibdev->num_ports) {
2508                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2509                 return;
2510         }
2511
2512         if (ibdev->ib_active)
2513                 ib_dispatch_event(&ibev);
2514
2515         if (fatal)
2516                 ibdev->ib_active = false;
2517 }
2518
2519 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2520 {
2521         int port;
2522
2523         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2524                 mlx5_query_ext_port_caps(dev, port);
2525 }
2526
2527 static int get_port_caps(struct mlx5_ib_dev *dev)
2528 {
2529         struct ib_device_attr *dprops = NULL;
2530         struct ib_port_attr *pprops = NULL;
2531         int err = -ENOMEM;
2532         int port;
2533         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2534
2535         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2536         if (!pprops)
2537                 goto out;
2538
2539         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2540         if (!dprops)
2541                 goto out;
2542
2543         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2544         if (err) {
2545                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2546                 goto out;
2547         }
2548
2549         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2550                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2551                 if (err) {
2552                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2553                                      port, err);
2554                         break;
2555                 }
2556                 dev->mdev->port_caps[port - 1].pkey_table_len =
2557                                                 dprops->max_pkeys;
2558                 dev->mdev->port_caps[port - 1].gid_table_len =
2559                                                 pprops->gid_tbl_len;
2560                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2561                             dprops->max_pkeys, pprops->gid_tbl_len);
2562         }
2563
2564 out:
2565         kfree(pprops);
2566         kfree(dprops);
2567
2568         return err;
2569 }
2570
2571 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2572 {
2573         int err;
2574
2575         err = mlx5_mr_cache_cleanup(dev);
2576         if (err)
2577                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2578
2579         mlx5_ib_destroy_qp(dev->umrc.qp);
2580         ib_free_cq(dev->umrc.cq);
2581         ib_dealloc_pd(dev->umrc.pd);
2582 }
2583
2584 enum {
2585         MAX_UMR_WR = 128,
2586 };
2587
2588 static int create_umr_res(struct mlx5_ib_dev *dev)
2589 {
2590         struct ib_qp_init_attr *init_attr = NULL;
2591         struct ib_qp_attr *attr = NULL;
2592         struct ib_pd *pd;
2593         struct ib_cq *cq;
2594         struct ib_qp *qp;
2595         int ret;
2596
2597         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2598         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2599         if (!attr || !init_attr) {
2600                 ret = -ENOMEM;
2601                 goto error_0;
2602         }
2603
2604         pd = ib_alloc_pd(&dev->ib_dev, 0);
2605         if (IS_ERR(pd)) {
2606                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2607                 ret = PTR_ERR(pd);
2608                 goto error_0;
2609         }
2610
2611         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2612         if (IS_ERR(cq)) {
2613                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2614                 ret = PTR_ERR(cq);
2615                 goto error_2;
2616         }
2617
2618         init_attr->send_cq = cq;
2619         init_attr->recv_cq = cq;
2620         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2621         init_attr->cap.max_send_wr = MAX_UMR_WR;
2622         init_attr->cap.max_send_sge = 1;
2623         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2624         init_attr->port_num = 1;
2625         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2626         if (IS_ERR(qp)) {
2627                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2628                 ret = PTR_ERR(qp);
2629                 goto error_3;
2630         }
2631         qp->device     = &dev->ib_dev;
2632         qp->real_qp    = qp;
2633         qp->uobject    = NULL;
2634         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2635
2636         attr->qp_state = IB_QPS_INIT;
2637         attr->port_num = 1;
2638         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2639                                 IB_QP_PORT, NULL);
2640         if (ret) {
2641                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2642                 goto error_4;
2643         }
2644
2645         memset(attr, 0, sizeof(*attr));
2646         attr->qp_state = IB_QPS_RTR;
2647         attr->path_mtu = IB_MTU_256;
2648
2649         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2650         if (ret) {
2651                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2652                 goto error_4;
2653         }
2654
2655         memset(attr, 0, sizeof(*attr));
2656         attr->qp_state = IB_QPS_RTS;
2657         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2658         if (ret) {
2659                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2660                 goto error_4;
2661         }
2662
2663         dev->umrc.qp = qp;
2664         dev->umrc.cq = cq;
2665         dev->umrc.pd = pd;
2666
2667         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2668         ret = mlx5_mr_cache_init(dev);
2669         if (ret) {
2670                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2671                 goto error_4;
2672         }
2673
2674         kfree(attr);
2675         kfree(init_attr);
2676
2677         return 0;
2678
2679 error_4:
2680         mlx5_ib_destroy_qp(qp);
2681
2682 error_3:
2683         ib_free_cq(cq);
2684
2685 error_2:
2686         ib_dealloc_pd(pd);
2687
2688 error_0:
2689         kfree(attr);
2690         kfree(init_attr);
2691         return ret;
2692 }
2693
2694 static int create_dev_resources(struct mlx5_ib_resources *devr)
2695 {
2696         struct ib_srq_init_attr attr;
2697         struct mlx5_ib_dev *dev;
2698         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2699         int port;
2700         int ret = 0;
2701
2702         dev = container_of(devr, struct mlx5_ib_dev, devr);
2703
2704         mutex_init(&devr->mutex);
2705
2706         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2707         if (IS_ERR(devr->p0)) {
2708                 ret = PTR_ERR(devr->p0);
2709                 goto error0;
2710         }
2711         devr->p0->device  = &dev->ib_dev;
2712         devr->p0->uobject = NULL;
2713         atomic_set(&devr->p0->usecnt, 0);
2714
2715         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2716         if (IS_ERR(devr->c0)) {
2717                 ret = PTR_ERR(devr->c0);
2718                 goto error1;
2719         }
2720         devr->c0->device        = &dev->ib_dev;
2721         devr->c0->uobject       = NULL;
2722         devr->c0->comp_handler  = NULL;
2723         devr->c0->event_handler = NULL;
2724         devr->c0->cq_context    = NULL;
2725         atomic_set(&devr->c0->usecnt, 0);
2726
2727         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2728         if (IS_ERR(devr->x0)) {
2729                 ret = PTR_ERR(devr->x0);
2730                 goto error2;
2731         }
2732         devr->x0->device = &dev->ib_dev;
2733         devr->x0->inode = NULL;
2734         atomic_set(&devr->x0->usecnt, 0);
2735         mutex_init(&devr->x0->tgt_qp_mutex);
2736         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2737
2738         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2739         if (IS_ERR(devr->x1)) {
2740                 ret = PTR_ERR(devr->x1);
2741                 goto error3;
2742         }
2743         devr->x1->device = &dev->ib_dev;
2744         devr->x1->inode = NULL;
2745         atomic_set(&devr->x1->usecnt, 0);
2746         mutex_init(&devr->x1->tgt_qp_mutex);
2747         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2748
2749         memset(&attr, 0, sizeof(attr));
2750         attr.attr.max_sge = 1;
2751         attr.attr.max_wr = 1;
2752         attr.srq_type = IB_SRQT_XRC;
2753         attr.ext.xrc.cq = devr->c0;
2754         attr.ext.xrc.xrcd = devr->x0;
2755
2756         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2757         if (IS_ERR(devr->s0)) {
2758                 ret = PTR_ERR(devr->s0);
2759                 goto error4;
2760         }
2761         devr->s0->device        = &dev->ib_dev;
2762         devr->s0->pd            = devr->p0;
2763         devr->s0->uobject       = NULL;
2764         devr->s0->event_handler = NULL;
2765         devr->s0->srq_context   = NULL;
2766         devr->s0->srq_type      = IB_SRQT_XRC;
2767         devr->s0->ext.xrc.xrcd  = devr->x0;
2768         devr->s0->ext.xrc.cq    = devr->c0;
2769         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2770         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2771         atomic_inc(&devr->p0->usecnt);
2772         atomic_set(&devr->s0->usecnt, 0);
2773
2774         memset(&attr, 0, sizeof(attr));
2775         attr.attr.max_sge = 1;
2776         attr.attr.max_wr = 1;
2777         attr.srq_type = IB_SRQT_BASIC;
2778         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2779         if (IS_ERR(devr->s1)) {
2780                 ret = PTR_ERR(devr->s1);
2781                 goto error5;
2782         }
2783         devr->s1->device        = &dev->ib_dev;
2784         devr->s1->pd            = devr->p0;
2785         devr->s1->uobject       = NULL;
2786         devr->s1->event_handler = NULL;
2787         devr->s1->srq_context   = NULL;
2788         devr->s1->srq_type      = IB_SRQT_BASIC;
2789         devr->s1->ext.xrc.cq    = devr->c0;
2790         atomic_inc(&devr->p0->usecnt);
2791         atomic_set(&devr->s0->usecnt, 0);
2792
2793         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2794                 INIT_WORK(&devr->ports[port].pkey_change_work,
2795                           pkey_change_handler);
2796                 devr->ports[port].devr = devr;
2797         }
2798
2799         return 0;
2800
2801 error5:
2802         mlx5_ib_destroy_srq(devr->s0);
2803 error4:
2804         mlx5_ib_dealloc_xrcd(devr->x1);
2805 error3:
2806         mlx5_ib_dealloc_xrcd(devr->x0);
2807 error2:
2808         mlx5_ib_destroy_cq(devr->c0);
2809 error1:
2810         mlx5_ib_dealloc_pd(devr->p0);
2811 error0:
2812         return ret;
2813 }
2814
2815 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2816 {
2817         struct mlx5_ib_dev *dev =
2818                 container_of(devr, struct mlx5_ib_dev, devr);
2819         int port;
2820
2821         mlx5_ib_destroy_srq(devr->s1);
2822         mlx5_ib_destroy_srq(devr->s0);
2823         mlx5_ib_dealloc_xrcd(devr->x0);
2824         mlx5_ib_dealloc_xrcd(devr->x1);
2825         mlx5_ib_destroy_cq(devr->c0);
2826         mlx5_ib_dealloc_pd(devr->p0);
2827
2828         /* Make sure no change P_Key work items are still executing */
2829         for (port = 0; port < dev->num_ports; ++port)
2830                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2831 }
2832
2833 static u32 get_core_cap_flags(struct ib_device *ibdev)
2834 {
2835         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2836         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2837         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2838         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2839         u32 ret = 0;
2840
2841         if (ll == IB_LINK_LAYER_INFINIBAND)
2842                 return RDMA_CORE_PORT_IBA_IB;
2843
2844         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2845                 return 0;
2846
2847         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2848                 return 0;
2849
2850         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2851                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2852
2853         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2854                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2855
2856         return ret;
2857 }
2858
2859 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2860                                struct ib_port_immutable *immutable)
2861 {
2862         struct ib_port_attr attr;
2863         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2864         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2865         int err;
2866
2867         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2868         if (err)
2869                 return err;
2870
2871         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2872         immutable->gid_tbl_len = attr.gid_tbl_len;
2873         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2874         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
2875                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2876
2877         return 0;
2878 }
2879
2880 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2881                            size_t str_len)
2882 {
2883         struct mlx5_ib_dev *dev =
2884                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2885         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2886                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2887 }
2888
2889 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
2890 {
2891         struct mlx5_core_dev *mdev = dev->mdev;
2892         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2893                                                                  MLX5_FLOW_NAMESPACE_LAG);
2894         struct mlx5_flow_table *ft;
2895         int err;
2896
2897         if (!ns || !mlx5_lag_is_active(mdev))
2898                 return 0;
2899
2900         err = mlx5_cmd_create_vport_lag(mdev);
2901         if (err)
2902                 return err;
2903
2904         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2905         if (IS_ERR(ft)) {
2906                 err = PTR_ERR(ft);
2907                 goto err_destroy_vport_lag;
2908         }
2909
2910         dev->flow_db.lag_demux_ft = ft;
2911         return 0;
2912
2913 err_destroy_vport_lag:
2914         mlx5_cmd_destroy_vport_lag(mdev);
2915         return err;
2916 }
2917
2918 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
2919 {
2920         struct mlx5_core_dev *mdev = dev->mdev;
2921
2922         if (dev->flow_db.lag_demux_ft) {
2923                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2924                 dev->flow_db.lag_demux_ft = NULL;
2925
2926                 mlx5_cmd_destroy_vport_lag(mdev);
2927         }
2928 }
2929
2930 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
2931 {
2932         int err;
2933
2934         dev->roce.nb.notifier_call = mlx5_netdev_event;
2935         err = register_netdevice_notifier(&dev->roce.nb);
2936         if (err) {
2937                 dev->roce.nb.notifier_call = NULL;
2938                 return err;
2939         }
2940
2941         return 0;
2942 }
2943
2944 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
2945 {
2946         if (dev->roce.nb.notifier_call) {
2947                 unregister_netdevice_notifier(&dev->roce.nb);
2948                 dev->roce.nb.notifier_call = NULL;
2949         }
2950 }
2951
2952 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
2953 {
2954         int err;
2955
2956         err = mlx5_add_netdev_notifier(dev);
2957         if (err)
2958                 return err;
2959
2960         if (MLX5_CAP_GEN(dev->mdev, roce)) {
2961                 err = mlx5_nic_vport_enable_roce(dev->mdev);
2962                 if (err)
2963                         goto err_unregister_netdevice_notifier;
2964         }
2965
2966         err = mlx5_eth_lag_init(dev);
2967         if (err)
2968                 goto err_disable_roce;
2969
2970         return 0;
2971
2972 err_disable_roce:
2973         if (MLX5_CAP_GEN(dev->mdev, roce))
2974                 mlx5_nic_vport_disable_roce(dev->mdev);
2975
2976 err_unregister_netdevice_notifier:
2977         mlx5_remove_netdev_notifier(dev);
2978         return err;
2979 }
2980
2981 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
2982 {
2983         mlx5_eth_lag_cleanup(dev);
2984         if (MLX5_CAP_GEN(dev->mdev, roce))
2985                 mlx5_nic_vport_disable_roce(dev->mdev);
2986 }
2987
2988 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2989 {
2990         unsigned int i;
2991
2992         for (i = 0; i < dev->num_ports; i++)
2993                 mlx5_core_dealloc_q_counter(dev->mdev,
2994                                             dev->port[i].q_cnt_id);
2995 }
2996
2997 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2998 {
2999         int i;
3000         int ret;
3001
3002         for (i = 0; i < dev->num_ports; i++) {
3003                 ret = mlx5_core_alloc_q_counter(dev->mdev,
3004                                                 &dev->port[i].q_cnt_id);
3005                 if (ret) {
3006                         mlx5_ib_warn(dev,
3007                                      "couldn't allocate queue counter for port %d, err %d\n",
3008                                      i + 1, ret);
3009                         goto dealloc_counters;
3010                 }
3011         }
3012
3013         return 0;
3014
3015 dealloc_counters:
3016         while (--i >= 0)
3017                 mlx5_core_dealloc_q_counter(dev->mdev,
3018                                             dev->port[i].q_cnt_id);
3019
3020         return ret;
3021 }
3022
3023 static const char * const names[] = {
3024         "rx_write_requests",
3025         "rx_read_requests",
3026         "rx_atomic_requests",
3027         "out_of_buffer",
3028         "out_of_sequence",
3029         "duplicate_request",
3030         "rnr_nak_retry_err",
3031         "packet_seq_err",
3032         "implied_nak_seq_err",
3033         "local_ack_timeout_err",
3034 };
3035
3036 static const size_t stats_offsets[] = {
3037         MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
3038         MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
3039         MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
3040         MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
3041         MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
3042         MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
3043         MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
3044         MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
3045         MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
3046         MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
3047 };
3048
3049 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3050                                                     u8 port_num)
3051 {
3052         BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
3053
3054         /* We support only per port stats */
3055         if (port_num == 0)
3056                 return NULL;
3057
3058         return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
3059                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
3060 }
3061
3062 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3063                                 struct rdma_hw_stats *stats,
3064                                 u8 port, int index)
3065 {
3066         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3067         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3068         void *out;
3069         __be32 val;
3070         int ret;
3071         int i;
3072
3073         if (!port || !stats)
3074                 return -ENOSYS;
3075
3076         out = mlx5_vzalloc(outlen);
3077         if (!out)
3078                 return -ENOMEM;
3079
3080         ret = mlx5_core_query_q_counter(dev->mdev,
3081                                         dev->port[port - 1].q_cnt_id, 0,
3082                                         out, outlen);
3083         if (ret)
3084                 goto free;
3085
3086         for (i = 0; i < ARRAY_SIZE(names); i++) {
3087                 val = *(__be32 *)(out + stats_offsets[i]);
3088                 stats->value[i] = (u64)be32_to_cpu(val);
3089         }
3090 free:
3091         kvfree(out);
3092         return ARRAY_SIZE(names);
3093 }
3094