2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #if defined(CONFIG_X86)
44 #include <linux/sched.h>
45 #include <linux/sched/mm.h>
46 #include <linux/sched/task.h>
47 #include <linux/delay.h>
48 #include <rdma/ib_user_verbs.h>
49 #include <rdma/ib_addr.h>
50 #include <rdma/ib_cache.h>
51 #include <linux/mlx5/port.h>
52 #include <linux/mlx5/vport.h>
53 #include <linux/mlx5/fs.h>
54 #include <linux/list.h>
55 #include <rdma/ib_smi.h>
56 #include <rdma/ib_umem.h>
58 #include <linux/etherdevice.h>
62 #define DRIVER_NAME "mlx5_ib"
63 #define DRIVER_VERSION "5.0-0"
65 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67 MODULE_LICENSE("Dual BSD/GPL");
69 static char mlx5_version[] =
70 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73 struct mlx5_ib_event_work {
74 struct work_struct work;
75 struct mlx5_core_dev *dev;
77 enum mlx5_dev_event event;
82 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
85 static struct workqueue_struct *mlx5_ib_event_wq;
86 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
87 static LIST_HEAD(mlx5_ib_dev_list);
89 * This mutex should be held when accessing either of the above lists
91 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
93 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
95 struct mlx5_ib_dev *dev;
97 mutex_lock(&mlx5_ib_multiport_mutex);
99 mutex_unlock(&mlx5_ib_multiport_mutex);
103 static enum rdma_link_layer
104 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
106 switch (port_type_cap) {
107 case MLX5_CAP_PORT_TYPE_IB:
108 return IB_LINK_LAYER_INFINIBAND;
109 case MLX5_CAP_PORT_TYPE_ETH:
110 return IB_LINK_LAYER_ETHERNET;
112 return IB_LINK_LAYER_UNSPECIFIED;
116 static enum rdma_link_layer
117 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
119 struct mlx5_ib_dev *dev = to_mdev(device);
120 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
122 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
125 static int get_port_state(struct ib_device *ibdev,
127 enum ib_port_state *state)
129 struct ib_port_attr attr;
132 memset(&attr, 0, sizeof(attr));
133 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
139 static int mlx5_netdev_event(struct notifier_block *this,
140 unsigned long event, void *ptr)
142 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
143 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
144 u8 port_num = roce->native_port_num;
145 struct mlx5_core_dev *mdev;
146 struct mlx5_ib_dev *ibdev;
149 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
154 case NETDEV_REGISTER:
155 case NETDEV_UNREGISTER:
156 write_lock(&roce->netdev_lock);
158 if (ndev->dev.parent == &mdev->pdev->dev)
159 roce->netdev = (event == NETDEV_UNREGISTER) ?
161 write_unlock(&roce->netdev_lock);
167 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
168 struct net_device *upper = NULL;
171 upper = netdev_master_upper_dev_get(lag_ndev);
175 if ((upper == ndev || (!upper && ndev == roce->netdev))
176 && ibdev->ib_active) {
177 struct ib_event ibev = { };
178 enum ib_port_state port_state;
180 if (get_port_state(&ibdev->ib_dev, port_num,
184 if (roce->last_port_state == port_state)
187 roce->last_port_state = port_state;
188 ibev.device = &ibdev->ib_dev;
189 if (port_state == IB_PORT_DOWN)
190 ibev.event = IB_EVENT_PORT_ERR;
191 else if (port_state == IB_PORT_ACTIVE)
192 ibev.event = IB_EVENT_PORT_ACTIVE;
196 ibev.element.port_num = port_num;
197 ib_dispatch_event(&ibev);
206 mlx5_ib_put_native_port_mdev(ibdev, port_num);
210 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
213 struct mlx5_ib_dev *ibdev = to_mdev(device);
214 struct net_device *ndev;
215 struct mlx5_core_dev *mdev;
217 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
221 ndev = mlx5_lag_get_roce_netdev(mdev);
225 /* Ensure ndev does not disappear before we invoke dev_hold()
227 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
228 ndev = ibdev->roce[port_num - 1].netdev;
231 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
234 mlx5_ib_put_native_port_mdev(ibdev, port_num);
238 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
242 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
244 struct mlx5_core_dev *mdev = NULL;
245 struct mlx5_ib_multiport_info *mpi;
246 struct mlx5_ib_port *port;
249 *native_port_num = 1;
251 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
254 port = &ibdev->port[ib_port_num - 1];
258 spin_lock(&port->mp.mpi_lock);
259 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
260 if (mpi && !mpi->unaffiliate) {
262 /* If it's the master no need to refcount, it'll exist
263 * as long as the ib_dev exists.
268 spin_unlock(&port->mp.mpi_lock);
273 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
275 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
277 struct mlx5_ib_multiport_info *mpi;
278 struct mlx5_ib_port *port;
280 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
283 port = &ibdev->port[port_num - 1];
285 spin_lock(&port->mp.mpi_lock);
286 mpi = ibdev->port[port_num - 1].mp.mpi;
291 if (mpi->unaffiliate)
292 complete(&mpi->unref_comp);
294 spin_unlock(&port->mp.mpi_lock);
297 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
300 switch (eth_proto_oper) {
301 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
302 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
303 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
304 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
305 *active_width = IB_WIDTH_1X;
306 *active_speed = IB_SPEED_SDR;
308 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
309 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
310 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
311 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
312 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
313 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
314 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
315 *active_width = IB_WIDTH_1X;
316 *active_speed = IB_SPEED_QDR;
318 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
319 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
320 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
321 *active_width = IB_WIDTH_1X;
322 *active_speed = IB_SPEED_EDR;
324 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
325 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
326 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
327 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
328 *active_width = IB_WIDTH_4X;
329 *active_speed = IB_SPEED_QDR;
331 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
332 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
333 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_HDR;
337 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
338 *active_width = IB_WIDTH_4X;
339 *active_speed = IB_SPEED_FDR;
341 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
342 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
343 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
344 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
345 *active_width = IB_WIDTH_4X;
346 *active_speed = IB_SPEED_EDR;
355 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
356 struct ib_port_attr *props)
358 struct mlx5_ib_dev *dev = to_mdev(device);
359 struct mlx5_core_dev *mdev;
360 struct net_device *ndev, *upper;
361 enum ib_mtu ndev_ib_mtu;
362 bool put_mdev = true;
368 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
370 /* This means the port isn't affiliated yet. Get the
371 * info for the master port instead.
379 /* Possible bad flows are checked before filling out props so in case
380 * of an error it will still be zeroed out.
382 err = mlx5_query_port_eth_proto_oper(mdev, ð_prot_oper,
387 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
388 &props->active_width);
390 props->port_cap_flags |= IB_PORT_CM_SUP;
391 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
393 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
394 roce_address_table_size);
395 props->max_mtu = IB_MTU_4096;
396 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
397 props->pkey_tbl_len = 1;
398 props->state = IB_PORT_DOWN;
399 props->phys_state = 3;
401 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
402 props->qkey_viol_cntr = qkey_viol_cntr;
404 /* If this is a stub query for an unaffiliated port stop here */
408 ndev = mlx5_ib_get_netdev(device, port_num);
412 if (mlx5_lag_is_active(dev->mdev)) {
414 upper = netdev_master_upper_dev_get_rcu(ndev);
423 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
424 props->state = IB_PORT_ACTIVE;
425 props->phys_state = 5;
428 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
432 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
435 mlx5_ib_put_native_port_mdev(dev, port_num);
439 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
440 unsigned int index, const union ib_gid *gid,
441 const struct ib_gid_attr *attr)
443 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
451 gid_type = attr->gid_type;
452 ether_addr_copy(mac, attr->ndev->dev_addr);
454 if (is_vlan_dev(attr->ndev)) {
456 vlan_id = vlan_dev_vlan_id(attr->ndev);
462 roce_version = MLX5_ROCE_VERSION_1;
464 case IB_GID_TYPE_ROCE_UDP_ENCAP:
465 roce_version = MLX5_ROCE_VERSION_2;
466 if (ipv6_addr_v4mapped((void *)gid))
467 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
469 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
473 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
476 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
477 roce_l3_type, gid->raw, mac, vlan,
481 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
482 unsigned int index, const union ib_gid *gid,
483 const struct ib_gid_attr *attr,
484 __always_unused void **context)
486 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
489 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
490 unsigned int index, __always_unused void **context)
492 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
495 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
498 struct ib_gid_attr attr;
501 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
509 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
512 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
515 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
516 int index, enum ib_gid_type *gid_type)
518 struct ib_gid_attr attr;
522 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
531 *gid_type = attr.gid_type;
536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
549 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
561 static void get_atomic_caps(struct mlx5_ib_dev *dev,
563 struct ib_device_attr *props)
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
567 u8 atomic_req_8B_endianness_mode =
568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
579 props->atomic_cap = IB_ATOMIC_NONE;
583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
588 get_atomic_caps(dev, atomic_size_qp, props);
591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
596 get_atomic_caps(dev, atomic_size_qp, props);
599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
601 struct ib_device_attr props = {};
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
606 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
632 *sys_image_guid = cpu_to_be64(tmp);
638 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
659 static int mlx5_query_vendor_id(struct ib_device *ibdev,
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
700 *node_guid = cpu_to_be64(tmp);
705 struct mlx5_reg_node_desc {
706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
711 struct mlx5_reg_node_desc in;
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
716 memset(&in, 0, sizeof(in));
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
723 static int mlx5_ib_query_device(struct ib_device *ibdev,
724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
728 struct mlx5_core_dev *mdev = dev->mdev;
733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
734 bool raw_support = !mlx5_core_mp_enabled(mdev);
735 struct mlx5_ib_query_device_resp resp = {};
739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
740 if (uhw->outlen && uhw->outlen < resp_len)
743 resp.response_length = resp_len;
745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
748 memset(props, 0, sizeof(*props));
749 err = mlx5_query_system_image_guid(ibdev,
750 &props->sys_image_guid);
754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
763 (fw_rev_min(dev->mdev) << 16) |
764 fw_rev_sub(dev->mdev);
765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
766 IB_DEVICE_PORT_ACTIVE_EVENT |
767 IB_DEVICE_SYS_IMAGE_GUID |
768 IB_DEVICE_RC_RNR_NAK_GEN;
770 if (MLX5_CAP_GEN(mdev, pkv))
771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
772 if (MLX5_CAP_GEN(mdev, qkv))
773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
774 if (MLX5_CAP_GEN(mdev, apm))
775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
776 if (MLX5_CAP_GEN(mdev, xrc))
777 props->device_cap_flags |= IB_DEVICE_XRC;
778 if (MLX5_CAP_GEN(mdev, imaicl)) {
779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
780 IB_DEVICE_MEM_WINDOW_TYPE_2B;
781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
782 /* We support 'Gappy' memory registration too */
783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
786 if (MLX5_CAP_GEN(mdev, sho)) {
787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
788 /* At this stage no support for signature handover */
789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
790 IB_PROT_T10DIF_TYPE_2 |
791 IB_PROT_T10DIF_TYPE_3;
792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
793 IB_GUARD_T10DIF_CSUM;
795 if (MLX5_CAP_GEN(mdev, block_lb_mc))
796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
799 if (MLX5_CAP_ETH(mdev, csum_cap)) {
800 /* Legacy bit to support old userspace libraries */
801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
806 props->raw_packet_caps |=
807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
812 resp.tso_caps.max_tso = 1 << max_tso;
813 resp.tso_caps.supported_qpts |=
814 1 << IB_QPT_RAW_PACKET;
815 resp.response_length += sizeof(resp.tso_caps);
819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
820 resp.rss_caps.rx_hash_function =
821 MLX5_RX_HASH_FUNC_TOEPLITZ;
822 resp.rss_caps.rx_hash_fields_mask =
823 MLX5_RX_HASH_SRC_IPV4 |
824 MLX5_RX_HASH_DST_IPV4 |
825 MLX5_RX_HASH_SRC_IPV6 |
826 MLX5_RX_HASH_DST_IPV6 |
827 MLX5_RX_HASH_SRC_PORT_TCP |
828 MLX5_RX_HASH_DST_PORT_TCP |
829 MLX5_RX_HASH_SRC_PORT_UDP |
830 MLX5_RX_HASH_DST_PORT_UDP |
832 resp.response_length += sizeof(resp.rss_caps);
835 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
836 resp.response_length += sizeof(resp.tso_caps);
837 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
838 resp.response_length += sizeof(resp.rss_caps);
841 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
842 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
843 props->device_cap_flags |= IB_DEVICE_UD_TSO;
846 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
847 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
849 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
851 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
852 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
853 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
855 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
856 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
858 /* Legacy bit to support old userspace libraries */
859 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
860 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
863 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
864 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
866 if (MLX5_CAP_GEN(mdev, end_pad))
867 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
869 props->vendor_part_id = mdev->pdev->device;
870 props->hw_ver = mdev->pdev->revision;
872 props->max_mr_size = ~0ull;
873 props->page_size_cap = ~(min_page_size - 1);
874 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
875 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
876 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
877 sizeof(struct mlx5_wqe_data_seg);
878 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
879 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
880 sizeof(struct mlx5_wqe_raddr_seg)) /
881 sizeof(struct mlx5_wqe_data_seg);
882 props->max_sge = min(max_rq_sg, max_sq_sg);
883 props->max_sge_rd = MLX5_MAX_SGE_RD;
884 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
885 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
886 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
887 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
888 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
889 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
890 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
891 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
892 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
893 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
894 props->max_srq_sge = max_rq_sg - 1;
895 props->max_fast_reg_page_list_len =
896 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
897 get_atomic_caps_qp(dev, props);
898 props->masked_atomic_cap = IB_ATOMIC_NONE;
899 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
900 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
901 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
902 props->max_mcast_grp;
903 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
904 props->max_ah = INT_MAX;
905 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
906 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
908 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
909 if (MLX5_CAP_GEN(mdev, pg))
910 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
911 props->odp_caps = dev->odp_caps;
914 if (MLX5_CAP_GEN(mdev, cd))
915 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
917 if (!mlx5_core_is_pf(mdev))
918 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
920 if (mlx5_ib_port_link_layer(ibdev, 1) ==
921 IB_LINK_LAYER_ETHERNET && raw_support) {
922 props->rss_caps.max_rwq_indirection_tables =
923 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
924 props->rss_caps.max_rwq_indirection_table_size =
925 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
926 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
927 props->max_wq_type_rq =
928 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
931 if (MLX5_CAP_GEN(mdev, tag_matching)) {
932 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
933 props->tm_caps.max_num_tags =
934 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
935 props->tm_caps.flags = IB_TM_CAP_RC;
936 props->tm_caps.max_ops =
937 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
938 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
941 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
942 props->cq_caps.max_cq_moderation_count =
944 props->cq_caps.max_cq_moderation_period =
948 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
949 resp.cqe_comp_caps.max_num =
950 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
951 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
952 resp.cqe_comp_caps.supported_format =
953 MLX5_IB_CQE_RES_FORMAT_HASH |
954 MLX5_IB_CQE_RES_FORMAT_CSUM;
955 resp.response_length += sizeof(resp.cqe_comp_caps);
958 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
960 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
961 MLX5_CAP_GEN(mdev, qos)) {
962 resp.packet_pacing_caps.qp_rate_limit_max =
963 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
964 resp.packet_pacing_caps.qp_rate_limit_min =
965 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
966 resp.packet_pacing_caps.supported_qpts |=
967 1 << IB_QPT_RAW_PACKET;
969 resp.response_length += sizeof(resp.packet_pacing_caps);
972 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
974 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
975 resp.mlx5_ib_support_multi_pkt_send_wqes =
978 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
979 resp.mlx5_ib_support_multi_pkt_send_wqes |=
980 MLX5_IB_SUPPORT_EMPW;
982 resp.response_length +=
983 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
986 if (field_avail(typeof(resp), flags, uhw->outlen)) {
987 resp.response_length += sizeof(resp.flags);
989 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
991 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
993 if (MLX5_CAP_GEN(mdev, cqe_128_always))
994 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
997 if (field_avail(typeof(resp), sw_parsing_caps,
999 resp.response_length += sizeof(resp.sw_parsing_caps);
1000 if (MLX5_CAP_ETH(mdev, swp)) {
1001 resp.sw_parsing_caps.sw_parsing_offloads |=
1004 if (MLX5_CAP_ETH(mdev, swp_csum))
1005 resp.sw_parsing_caps.sw_parsing_offloads |=
1006 MLX5_IB_SW_PARSING_CSUM;
1008 if (MLX5_CAP_ETH(mdev, swp_lso))
1009 resp.sw_parsing_caps.sw_parsing_offloads |=
1010 MLX5_IB_SW_PARSING_LSO;
1012 if (resp.sw_parsing_caps.sw_parsing_offloads)
1013 resp.sw_parsing_caps.supported_qpts =
1014 BIT(IB_QPT_RAW_PACKET);
1018 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1020 resp.response_length += sizeof(resp.striding_rq_caps);
1021 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1022 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1023 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1024 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1025 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1026 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1027 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1028 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1029 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1030 resp.striding_rq_caps.supported_qpts =
1031 BIT(IB_QPT_RAW_PACKET);
1035 if (field_avail(typeof(resp), tunnel_offloads_caps,
1037 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1038 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1039 resp.tunnel_offloads_caps |=
1040 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1041 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1042 resp.tunnel_offloads_caps |=
1043 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1044 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1045 resp.tunnel_offloads_caps |=
1046 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1050 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1059 enum mlx5_ib_width {
1060 MLX5_IB_WIDTH_1X = 1 << 0,
1061 MLX5_IB_WIDTH_2X = 1 << 1,
1062 MLX5_IB_WIDTH_4X = 1 << 2,
1063 MLX5_IB_WIDTH_8X = 1 << 3,
1064 MLX5_IB_WIDTH_12X = 1 << 4
1067 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1070 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1073 if (active_width & MLX5_IB_WIDTH_1X) {
1074 *ib_width = IB_WIDTH_1X;
1075 } else if (active_width & MLX5_IB_WIDTH_2X) {
1076 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1079 } else if (active_width & MLX5_IB_WIDTH_4X) {
1080 *ib_width = IB_WIDTH_4X;
1081 } else if (active_width & MLX5_IB_WIDTH_8X) {
1082 *ib_width = IB_WIDTH_8X;
1083 } else if (active_width & MLX5_IB_WIDTH_12X) {
1084 *ib_width = IB_WIDTH_12X;
1086 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1094 static int mlx5_mtu_to_ib_mtu(int mtu)
1099 case 1024: return 3;
1100 case 2048: return 4;
1101 case 4096: return 5;
1103 pr_warn("invalid mtu\n");
1108 enum ib_max_vl_num {
1110 __IB_MAX_VL_0_1 = 2,
1111 __IB_MAX_VL_0_3 = 3,
1112 __IB_MAX_VL_0_7 = 4,
1113 __IB_MAX_VL_0_14 = 5,
1116 enum mlx5_vl_hw_cap {
1125 MLX5_VL_HW_0_14 = 15
1128 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1131 switch (vl_hw_cap) {
1133 *max_vl_num = __IB_MAX_VL_0;
1135 case MLX5_VL_HW_0_1:
1136 *max_vl_num = __IB_MAX_VL_0_1;
1138 case MLX5_VL_HW_0_3:
1139 *max_vl_num = __IB_MAX_VL_0_3;
1141 case MLX5_VL_HW_0_7:
1142 *max_vl_num = __IB_MAX_VL_0_7;
1144 case MLX5_VL_HW_0_14:
1145 *max_vl_num = __IB_MAX_VL_0_14;
1155 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1156 struct ib_port_attr *props)
1158 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1159 struct mlx5_core_dev *mdev = dev->mdev;
1160 struct mlx5_hca_vport_context *rep;
1164 u8 ib_link_width_oper;
1167 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1173 /* props being zeroed by the caller, avoid zeroing it here */
1175 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1179 props->lid = rep->lid;
1180 props->lmc = rep->lmc;
1181 props->sm_lid = rep->sm_lid;
1182 props->sm_sl = rep->sm_sl;
1183 props->state = rep->vport_state;
1184 props->phys_state = rep->port_physical_state;
1185 props->port_cap_flags = rep->cap_mask1;
1186 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1187 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1188 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1189 props->bad_pkey_cntr = rep->pkey_violation_counter;
1190 props->qkey_viol_cntr = rep->qkey_violation_counter;
1191 props->subnet_timeout = rep->subnet_timeout;
1192 props->init_type_reply = rep->init_type_reply;
1193 props->grh_required = rep->grh_required;
1195 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1199 err = translate_active_width(ibdev, ib_link_width_oper,
1200 &props->active_width);
1203 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1207 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1209 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1211 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1213 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1215 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1219 err = translate_max_vl_num(ibdev, vl_hw_cap,
1220 &props->max_vl_num);
1226 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1227 struct ib_port_attr *props)
1232 switch (mlx5_get_vport_access_method(ibdev)) {
1233 case MLX5_VPORT_ACCESS_METHOD_MAD:
1234 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1237 case MLX5_VPORT_ACCESS_METHOD_HCA:
1238 ret = mlx5_query_hca_port(ibdev, port, props);
1241 case MLX5_VPORT_ACCESS_METHOD_NIC:
1242 ret = mlx5_query_port_roce(ibdev, port, props);
1249 if (!ret && props) {
1250 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1251 struct mlx5_core_dev *mdev;
1252 bool put_mdev = true;
1254 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1256 /* If the port isn't affiliated yet query the master.
1257 * The master and slave will have the same values.
1263 count = mlx5_core_reserved_gids_count(mdev);
1265 mlx5_ib_put_native_port_mdev(dev, port);
1266 props->gid_tbl_len -= count;
1271 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1274 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1275 struct mlx5_core_dev *mdev = dev->mdev;
1277 switch (mlx5_get_vport_access_method(ibdev)) {
1278 case MLX5_VPORT_ACCESS_METHOD_MAD:
1279 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1281 case MLX5_VPORT_ACCESS_METHOD_HCA:
1282 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1290 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1291 u16 index, u16 *pkey)
1293 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1294 struct mlx5_core_dev *mdev;
1295 bool put_mdev = true;
1299 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1301 /* The port isn't affiliated yet, get the PKey from the master
1302 * port. For RoCE the PKey tables will be the same.
1309 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1312 mlx5_ib_put_native_port_mdev(dev, port);
1317 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1320 switch (mlx5_get_vport_access_method(ibdev)) {
1321 case MLX5_VPORT_ACCESS_METHOD_MAD:
1322 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1324 case MLX5_VPORT_ACCESS_METHOD_HCA:
1325 case MLX5_VPORT_ACCESS_METHOD_NIC:
1326 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1332 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1333 struct ib_device_modify *props)
1335 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1336 struct mlx5_reg_node_desc in;
1337 struct mlx5_reg_node_desc out;
1340 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1343 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1347 * If possible, pass node desc to FW, so it can generate
1348 * a 144 trap. If cmd fails, just ignore.
1350 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1351 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1352 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1356 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1361 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1364 struct mlx5_hca_vport_context ctx = {};
1365 struct mlx5_core_dev *mdev;
1369 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1373 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1377 if (~ctx.cap_mask1_perm & mask) {
1378 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1379 mask, ctx.cap_mask1_perm);
1384 ctx.cap_mask1 = value;
1385 ctx.cap_mask1_perm = mask;
1386 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1390 mlx5_ib_put_native_port_mdev(dev, port_num);
1395 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1396 struct ib_port_modify *props)
1398 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1399 struct ib_port_attr attr;
1404 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1405 IB_LINK_LAYER_INFINIBAND);
1407 /* CM layer calls ib_modify_port() regardless of the link layer. For
1408 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1413 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1414 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1415 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1416 return set_port_caps_atomic(dev, port, change_mask, value);
1419 mutex_lock(&dev->cap_mask_mutex);
1421 err = ib_query_port(ibdev, port, &attr);
1425 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1426 ~props->clr_port_cap_mask;
1428 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1431 mutex_unlock(&dev->cap_mask_mutex);
1435 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1437 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1438 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1441 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1443 /* Large page with non 4k uar support might limit the dynamic size */
1444 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1445 return MLX5_MIN_DYN_BFREGS;
1447 return MLX5_MAX_DYN_BFREGS;
1450 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1451 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1452 struct mlx5_bfreg_info *bfregi)
1454 int uars_per_sys_page;
1455 int bfregs_per_sys_page;
1456 int ref_bfregs = req->total_num_bfregs;
1458 if (req->total_num_bfregs == 0)
1461 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1462 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1464 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1467 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1468 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1469 /* This holds the required static allocation asked by the user */
1470 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1471 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1474 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1475 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1476 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1477 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1479 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1480 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1481 lib_uar_4k ? "yes" : "no", ref_bfregs,
1482 req->total_num_bfregs, bfregi->total_num_bfregs,
1483 bfregi->num_sys_pages);
1488 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1490 struct mlx5_bfreg_info *bfregi;
1494 bfregi = &context->bfregi;
1495 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1496 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1500 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1503 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1504 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1509 for (--i; i >= 0; i--)
1510 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1511 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1516 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1518 struct mlx5_bfreg_info *bfregi;
1522 bfregi = &context->bfregi;
1523 for (i = 0; i < bfregi->num_sys_pages; i++) {
1524 if (i < bfregi->num_static_sys_pages ||
1525 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1526 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1528 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1537 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1541 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1545 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1546 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1549 mutex_lock(&dev->lb_mutex);
1552 if (dev->user_td == 2)
1553 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1555 mutex_unlock(&dev->lb_mutex);
1559 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1561 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1563 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1564 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1567 mutex_lock(&dev->lb_mutex);
1570 if (dev->user_td < 2)
1571 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1573 mutex_unlock(&dev->lb_mutex);
1576 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1577 struct ib_udata *udata)
1579 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1580 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1581 struct mlx5_ib_alloc_ucontext_resp resp = {};
1582 struct mlx5_core_dev *mdev = dev->mdev;
1583 struct mlx5_ib_ucontext *context;
1584 struct mlx5_bfreg_info *bfregi;
1587 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1591 if (!dev->ib_active)
1592 return ERR_PTR(-EAGAIN);
1594 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1596 else if (udata->inlen >= min_req_v2)
1599 return ERR_PTR(-EINVAL);
1601 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1603 return ERR_PTR(err);
1606 return ERR_PTR(-EINVAL);
1608 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1609 return ERR_PTR(-EOPNOTSUPP);
1611 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1612 MLX5_NON_FP_BFREGS_PER_UAR);
1613 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1614 return ERR_PTR(-EINVAL);
1616 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1617 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1618 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1619 resp.cache_line_size = cache_line_size();
1620 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1621 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1622 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1623 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1624 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1625 resp.cqe_version = min_t(__u8,
1626 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1627 req.max_cqe_version);
1628 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1629 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1630 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1631 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1632 resp.response_length = min(offsetof(typeof(resp), response_length) +
1633 sizeof(resp.response_length), udata->outlen);
1635 context = kzalloc(sizeof(*context), GFP_KERNEL);
1637 return ERR_PTR(-ENOMEM);
1639 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1640 bfregi = &context->bfregi;
1642 /* updates req->total_num_bfregs */
1643 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1647 mutex_init(&bfregi->lock);
1648 bfregi->lib_uar_4k = lib_uar_4k;
1649 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1651 if (!bfregi->count) {
1656 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1657 sizeof(*bfregi->sys_pages),
1659 if (!bfregi->sys_pages) {
1664 err = allocate_uars(dev, context);
1668 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1669 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1672 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1673 if (!context->upd_xlt_page) {
1677 mutex_init(&context->upd_xlt_page_mutex);
1679 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1680 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1685 INIT_LIST_HEAD(&context->vma_private_list);
1686 mutex_init(&context->vma_private_list_mutex);
1687 INIT_LIST_HEAD(&context->db_page_list);
1688 mutex_init(&context->db_page_mutex);
1690 resp.tot_bfregs = req.total_num_bfregs;
1691 resp.num_ports = dev->num_ports;
1693 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1694 resp.response_length += sizeof(resp.cqe_version);
1696 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1697 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1698 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1699 resp.response_length += sizeof(resp.cmds_supp_uhw);
1702 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1703 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1704 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1705 resp.eth_min_inline++;
1707 resp.response_length += sizeof(resp.eth_min_inline);
1710 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1711 if (mdev->clock_info)
1712 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1713 resp.response_length += sizeof(resp.clock_info_versions);
1717 * We don't want to expose information from the PCI bar that is located
1718 * after 4096 bytes, so if the arch only supports larger pages, let's
1719 * pretend we don't support reading the HCA's core clock. This is also
1720 * forced by mmap function.
1722 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1723 if (PAGE_SIZE <= 4096) {
1725 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1726 resp.hca_core_clock_offset =
1727 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1729 resp.response_length += sizeof(resp.hca_core_clock_offset);
1732 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1733 resp.response_length += sizeof(resp.log_uar_size);
1735 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1736 resp.response_length += sizeof(resp.num_uars_per_page);
1738 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1739 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1740 resp.response_length += sizeof(resp.num_dyn_bfregs);
1743 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1748 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1749 context->cqe_version = resp.cqe_version;
1750 context->lib_caps = req.lib_caps;
1751 print_lib_caps(dev, context->lib_caps);
1753 return &context->ibucontext;
1756 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1757 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1760 free_page(context->upd_xlt_page);
1763 deallocate_uars(dev, context);
1766 kfree(bfregi->sys_pages);
1769 kfree(bfregi->count);
1774 return ERR_PTR(err);
1777 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1779 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1780 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1781 struct mlx5_bfreg_info *bfregi;
1783 bfregi = &context->bfregi;
1784 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1785 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1787 free_page(context->upd_xlt_page);
1788 deallocate_uars(dev, context);
1789 kfree(bfregi->sys_pages);
1790 kfree(bfregi->count);
1796 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1799 int fw_uars_per_page;
1801 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1803 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1806 static int get_command(unsigned long offset)
1808 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1811 static int get_arg(unsigned long offset)
1813 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1816 static int get_index(unsigned long offset)
1818 return get_arg(offset);
1821 /* Index resides in an extra byte to enable larger values than 255 */
1822 static int get_extended_index(unsigned long offset)
1824 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1827 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1829 /* vma_open is called when a new VMA is created on top of our VMA. This
1830 * is done through either mremap flow or split_vma (usually due to
1831 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1832 * as this VMA is strongly hardware related. Therefore we set the
1833 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1834 * calling us again and trying to do incorrect actions. We assume that
1835 * the original VMA size is exactly a single page, and therefore all
1836 * "splitting" operation will not happen to it.
1838 area->vm_ops = NULL;
1841 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1843 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1845 /* It's guaranteed that all VMAs opened on a FD are closed before the
1846 * file itself is closed, therefore no sync is needed with the regular
1847 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1848 * However need a sync with accessing the vma as part of
1849 * mlx5_ib_disassociate_ucontext.
1850 * The close operation is usually called under mm->mmap_sem except when
1851 * process is exiting.
1852 * The exiting case is handled explicitly as part of
1853 * mlx5_ib_disassociate_ucontext.
1855 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1857 /* setting the vma context pointer to null in the mlx5_ib driver's
1858 * private data, to protect a race condition in
1859 * mlx5_ib_disassociate_ucontext().
1861 mlx5_ib_vma_priv_data->vma = NULL;
1862 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1863 list_del(&mlx5_ib_vma_priv_data->list);
1864 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1865 kfree(mlx5_ib_vma_priv_data);
1868 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1869 .open = mlx5_ib_vma_open,
1870 .close = mlx5_ib_vma_close
1873 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1874 struct mlx5_ib_ucontext *ctx)
1876 struct mlx5_ib_vma_private_data *vma_prv;
1877 struct list_head *vma_head = &ctx->vma_private_list;
1879 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1884 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1885 vma->vm_private_data = vma_prv;
1886 vma->vm_ops = &mlx5_ib_vm_ops;
1888 mutex_lock(&ctx->vma_private_list_mutex);
1889 list_add(&vma_prv->list, vma_head);
1890 mutex_unlock(&ctx->vma_private_list_mutex);
1895 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1898 struct vm_area_struct *vma;
1899 struct mlx5_ib_vma_private_data *vma_private, *n;
1900 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1901 struct task_struct *owning_process = NULL;
1902 struct mm_struct *owning_mm = NULL;
1904 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1905 if (!owning_process)
1908 owning_mm = get_task_mm(owning_process);
1910 pr_info("no mm, disassociate ucontext is pending task termination\n");
1912 put_task_struct(owning_process);
1913 usleep_range(1000, 2000);
1914 owning_process = get_pid_task(ibcontext->tgid,
1916 if (!owning_process ||
1917 owning_process->state == TASK_DEAD) {
1918 pr_info("disassociate ucontext done, task was terminated\n");
1919 /* in case task was dead need to release the
1923 put_task_struct(owning_process);
1929 /* need to protect from a race on closing the vma as part of
1930 * mlx5_ib_vma_close.
1932 down_write(&owning_mm->mmap_sem);
1933 mutex_lock(&context->vma_private_list_mutex);
1934 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1936 vma = vma_private->vma;
1937 ret = zap_vma_ptes(vma, vma->vm_start,
1939 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1940 /* context going to be destroyed, should
1941 * not access ops any more.
1943 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1945 list_del(&vma_private->list);
1948 mutex_unlock(&context->vma_private_list_mutex);
1949 up_write(&owning_mm->mmap_sem);
1951 put_task_struct(owning_process);
1954 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1957 case MLX5_IB_MMAP_WC_PAGE:
1959 case MLX5_IB_MMAP_REGULAR_PAGE:
1960 return "best effort WC";
1961 case MLX5_IB_MMAP_NC_PAGE:
1968 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1969 struct vm_area_struct *vma,
1970 struct mlx5_ib_ucontext *context)
1975 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1978 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
1981 if (vma->vm_flags & VM_WRITE)
1984 if (!dev->mdev->clock_info_page)
1987 pfn = page_to_pfn(dev->mdev->clock_info_page);
1988 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
1993 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
1995 (unsigned long long)pfn << PAGE_SHIFT);
1997 return mlx5_ib_set_vma_data(vma, context);
2000 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2001 struct vm_area_struct *vma,
2002 struct mlx5_ib_ucontext *context)
2004 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2007 phys_addr_t pfn, pa;
2009 u32 bfreg_dyn_idx = 0;
2011 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2012 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2013 bfregi->num_static_sys_pages;
2015 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2019 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2021 idx = get_index(vma->vm_pgoff);
2023 if (idx >= max_valid_idx) {
2024 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2025 idx, max_valid_idx);
2030 case MLX5_IB_MMAP_WC_PAGE:
2031 case MLX5_IB_MMAP_ALLOC_WC:
2032 /* Some architectures don't support WC memory */
2033 #if defined(CONFIG_X86)
2036 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2040 case MLX5_IB_MMAP_REGULAR_PAGE:
2041 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2042 prot = pgprot_writecombine(vma->vm_page_prot);
2044 case MLX5_IB_MMAP_NC_PAGE:
2045 prot = pgprot_noncached(vma->vm_page_prot);
2054 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2055 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2056 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2057 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2058 bfreg_dyn_idx, bfregi->total_num_bfregs);
2062 mutex_lock(&bfregi->lock);
2063 /* Fail if uar already allocated, first bfreg index of each
2064 * page holds its count.
2066 if (bfregi->count[bfreg_dyn_idx]) {
2067 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2068 mutex_unlock(&bfregi->lock);
2072 bfregi->count[bfreg_dyn_idx]++;
2073 mutex_unlock(&bfregi->lock);
2075 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2077 mlx5_ib_warn(dev, "UAR alloc failed\n");
2081 uar_index = bfregi->sys_pages[idx];
2084 pfn = uar_index2pfn(dev, uar_index);
2085 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2087 vma->vm_page_prot = prot;
2088 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2089 PAGE_SIZE, vma->vm_page_prot);
2091 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2092 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
2097 pa = pfn << PAGE_SHIFT;
2098 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2099 vma->vm_start, &pa);
2101 err = mlx5_ib_set_vma_data(vma, context);
2106 bfregi->sys_pages[idx] = uar_index;
2113 mlx5_cmd_free_uar(dev->mdev, idx);
2116 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2121 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2123 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2124 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2125 unsigned long command;
2128 command = get_command(vma->vm_pgoff);
2130 case MLX5_IB_MMAP_WC_PAGE:
2131 case MLX5_IB_MMAP_NC_PAGE:
2132 case MLX5_IB_MMAP_REGULAR_PAGE:
2133 case MLX5_IB_MMAP_ALLOC_WC:
2134 return uar_mmap(dev, command, vma, context);
2136 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2139 case MLX5_IB_MMAP_CORE_CLOCK:
2140 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2143 if (vma->vm_flags & VM_WRITE)
2146 /* Don't expose to user-space information it shouldn't have */
2147 if (PAGE_SIZE > 4096)
2150 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2151 pfn = (dev->mdev->iseg_base +
2152 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2154 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2155 PAGE_SIZE, vma->vm_page_prot))
2158 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2160 (unsigned long long)pfn << PAGE_SHIFT);
2162 case MLX5_IB_MMAP_CLOCK_INFO:
2163 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2172 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2173 struct ib_ucontext *context,
2174 struct ib_udata *udata)
2176 struct mlx5_ib_alloc_pd_resp resp;
2177 struct mlx5_ib_pd *pd;
2180 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2182 return ERR_PTR(-ENOMEM);
2184 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2187 return ERR_PTR(err);
2192 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2193 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2195 return ERR_PTR(-EFAULT);
2202 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2204 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2205 struct mlx5_ib_pd *mpd = to_mpd(pd);
2207 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2214 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2215 MATCH_CRITERIA_ENABLE_MISC_BIT,
2216 MATCH_CRITERIA_ENABLE_INNER_BIT
2219 #define HEADER_IS_ZERO(match_criteria, headers) \
2220 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2221 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2223 static u8 get_match_criteria_enable(u32 *match_criteria)
2225 u8 match_criteria_enable;
2227 match_criteria_enable =
2228 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2229 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2230 match_criteria_enable |=
2231 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2232 MATCH_CRITERIA_ENABLE_MISC_BIT;
2233 match_criteria_enable |=
2234 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2235 MATCH_CRITERIA_ENABLE_INNER_BIT;
2237 return match_criteria_enable;
2240 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2242 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2243 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2246 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2250 MLX5_SET(fte_match_set_misc,
2251 misc_c, inner_ipv6_flow_label, mask);
2252 MLX5_SET(fte_match_set_misc,
2253 misc_v, inner_ipv6_flow_label, val);
2255 MLX5_SET(fte_match_set_misc,
2256 misc_c, outer_ipv6_flow_label, mask);
2257 MLX5_SET(fte_match_set_misc,
2258 misc_v, outer_ipv6_flow_label, val);
2262 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2264 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2265 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2266 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2267 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2270 #define LAST_ETH_FIELD vlan_tag
2271 #define LAST_IB_FIELD sl
2272 #define LAST_IPV4_FIELD tos
2273 #define LAST_IPV6_FIELD traffic_class
2274 #define LAST_TCP_UDP_FIELD src_port
2275 #define LAST_TUNNEL_FIELD tunnel_id
2276 #define LAST_FLOW_TAG_FIELD tag_id
2277 #define LAST_DROP_FIELD size
2279 /* Field is the last supported field */
2280 #define FIELDS_NOT_SUPPORTED(filter, field)\
2281 memchr_inv((void *)&filter.field +\
2282 sizeof(filter.field), 0,\
2284 offsetof(typeof(filter), field) -\
2285 sizeof(filter.field))
2287 #define IPV4_VERSION 4
2288 #define IPV6_VERSION 6
2289 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2290 u32 *match_v, const union ib_flow_spec *ib_spec,
2291 u32 *tag_id, bool *is_drop)
2293 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2295 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2301 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2302 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2304 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2306 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2307 ft_field_support.inner_ip_version);
2309 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2311 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2313 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2314 ft_field_support.outer_ip_version);
2317 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2318 case IB_FLOW_SPEC_ETH:
2319 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2322 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2324 ib_spec->eth.mask.dst_mac);
2325 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2327 ib_spec->eth.val.dst_mac);
2329 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2331 ib_spec->eth.mask.src_mac);
2332 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2334 ib_spec->eth.val.src_mac);
2336 if (ib_spec->eth.mask.vlan_tag) {
2337 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2339 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2342 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2343 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2344 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2345 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2347 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2349 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2350 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2352 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2354 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2356 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2357 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2359 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2361 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2362 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2363 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2364 ethertype, ntohs(ib_spec->eth.val.ether_type));
2366 case IB_FLOW_SPEC_IPV4:
2367 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2371 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2373 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2374 ip_version, IPV4_VERSION);
2376 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2378 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2379 ethertype, ETH_P_IP);
2382 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2383 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2384 &ib_spec->ipv4.mask.src_ip,
2385 sizeof(ib_spec->ipv4.mask.src_ip));
2386 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2387 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2388 &ib_spec->ipv4.val.src_ip,
2389 sizeof(ib_spec->ipv4.val.src_ip));
2390 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2391 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2392 &ib_spec->ipv4.mask.dst_ip,
2393 sizeof(ib_spec->ipv4.mask.dst_ip));
2394 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2395 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2396 &ib_spec->ipv4.val.dst_ip,
2397 sizeof(ib_spec->ipv4.val.dst_ip));
2399 set_tos(headers_c, headers_v,
2400 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2402 set_proto(headers_c, headers_v,
2403 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2405 case IB_FLOW_SPEC_IPV6:
2406 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2410 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2412 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2413 ip_version, IPV6_VERSION);
2415 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2417 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2418 ethertype, ETH_P_IPV6);
2421 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2422 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2423 &ib_spec->ipv6.mask.src_ip,
2424 sizeof(ib_spec->ipv6.mask.src_ip));
2425 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2426 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2427 &ib_spec->ipv6.val.src_ip,
2428 sizeof(ib_spec->ipv6.val.src_ip));
2429 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2430 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2431 &ib_spec->ipv6.mask.dst_ip,
2432 sizeof(ib_spec->ipv6.mask.dst_ip));
2433 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2434 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2435 &ib_spec->ipv6.val.dst_ip,
2436 sizeof(ib_spec->ipv6.val.dst_ip));
2438 set_tos(headers_c, headers_v,
2439 ib_spec->ipv6.mask.traffic_class,
2440 ib_spec->ipv6.val.traffic_class);
2442 set_proto(headers_c, headers_v,
2443 ib_spec->ipv6.mask.next_hdr,
2444 ib_spec->ipv6.val.next_hdr);
2446 set_flow_label(misc_params_c, misc_params_v,
2447 ntohl(ib_spec->ipv6.mask.flow_label),
2448 ntohl(ib_spec->ipv6.val.flow_label),
2449 ib_spec->type & IB_FLOW_SPEC_INNER);
2452 case IB_FLOW_SPEC_TCP:
2453 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2454 LAST_TCP_UDP_FIELD))
2457 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2459 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2462 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2463 ntohs(ib_spec->tcp_udp.mask.src_port));
2464 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2465 ntohs(ib_spec->tcp_udp.val.src_port));
2467 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2468 ntohs(ib_spec->tcp_udp.mask.dst_port));
2469 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2470 ntohs(ib_spec->tcp_udp.val.dst_port));
2472 case IB_FLOW_SPEC_UDP:
2473 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2474 LAST_TCP_UDP_FIELD))
2477 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2479 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2482 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2483 ntohs(ib_spec->tcp_udp.mask.src_port));
2484 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2485 ntohs(ib_spec->tcp_udp.val.src_port));
2487 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2488 ntohs(ib_spec->tcp_udp.mask.dst_port));
2489 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2490 ntohs(ib_spec->tcp_udp.val.dst_port));
2492 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2493 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2497 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2498 ntohl(ib_spec->tunnel.mask.tunnel_id));
2499 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2500 ntohl(ib_spec->tunnel.val.tunnel_id));
2502 case IB_FLOW_SPEC_ACTION_TAG:
2503 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2504 LAST_FLOW_TAG_FIELD))
2506 if (ib_spec->flow_tag.tag_id >= BIT(24))
2509 *tag_id = ib_spec->flow_tag.tag_id;
2511 case IB_FLOW_SPEC_ACTION_DROP:
2512 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2524 /* If a flow could catch both multicast and unicast packets,
2525 * it won't fall into the multicast flow steering table and this rule
2526 * could steal other multicast packets.
2528 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2530 union ib_flow_spec *flow_spec;
2532 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2533 ib_attr->num_of_specs < 1)
2536 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2537 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2538 struct ib_flow_spec_ipv4 *ipv4_spec;
2540 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2541 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2547 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2548 struct ib_flow_spec_eth *eth_spec;
2550 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2551 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2552 is_multicast_ether_addr(eth_spec->val.dst_mac);
2558 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2559 const struct ib_flow_attr *flow_attr,
2562 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2563 int match_ipv = check_inner ?
2564 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2565 ft_field_support.inner_ip_version) :
2566 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2567 ft_field_support.outer_ip_version);
2568 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2569 bool ipv4_spec_valid, ipv6_spec_valid;
2570 unsigned int ip_spec_type = 0;
2571 bool has_ethertype = false;
2572 unsigned int spec_index;
2573 bool mask_valid = true;
2577 /* Validate that ethertype is correct */
2578 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2579 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2580 ib_spec->eth.mask.ether_type) {
2581 mask_valid = (ib_spec->eth.mask.ether_type ==
2583 has_ethertype = true;
2584 eth_type = ntohs(ib_spec->eth.val.ether_type);
2585 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2586 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2587 ip_spec_type = ib_spec->type;
2589 ib_spec = (void *)ib_spec + ib_spec->size;
2592 type_valid = (!has_ethertype) || (!ip_spec_type);
2593 if (!type_valid && mask_valid) {
2594 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2595 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2596 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2597 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2599 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2600 (((eth_type == ETH_P_MPLS_UC) ||
2601 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2607 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2608 const struct ib_flow_attr *flow_attr)
2610 return is_valid_ethertype(mdev, flow_attr, false) &&
2611 is_valid_ethertype(mdev, flow_attr, true);
2614 static void put_flow_table(struct mlx5_ib_dev *dev,
2615 struct mlx5_ib_flow_prio *prio, bool ft_added)
2617 prio->refcount -= !!ft_added;
2618 if (!prio->refcount) {
2619 mlx5_destroy_flow_table(prio->flow_table);
2620 prio->flow_table = NULL;
2624 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2626 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2627 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2628 struct mlx5_ib_flow_handler,
2630 struct mlx5_ib_flow_handler *iter, *tmp;
2632 mutex_lock(&dev->flow_db.lock);
2634 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2635 mlx5_del_flow_rules(iter->rule);
2636 put_flow_table(dev, iter->prio, true);
2637 list_del(&iter->list);
2641 mlx5_del_flow_rules(handler->rule);
2642 put_flow_table(dev, handler->prio, true);
2643 mutex_unlock(&dev->flow_db.lock);
2650 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2658 enum flow_table_type {
2663 #define MLX5_FS_MAX_TYPES 6
2664 #define MLX5_FS_MAX_ENTRIES BIT(16)
2665 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2666 struct ib_flow_attr *flow_attr,
2667 enum flow_table_type ft_type)
2669 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2670 struct mlx5_flow_namespace *ns = NULL;
2671 struct mlx5_ib_flow_prio *prio;
2672 struct mlx5_flow_table *ft;
2679 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2681 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2682 if (flow_is_multicast_only(flow_attr) &&
2684 priority = MLX5_IB_FLOW_MCAST_PRIO;
2686 priority = ib_prio_to_core_prio(flow_attr->priority,
2688 ns = mlx5_get_flow_namespace(dev->mdev,
2689 MLX5_FLOW_NAMESPACE_BYPASS);
2690 num_entries = MLX5_FS_MAX_ENTRIES;
2691 num_groups = MLX5_FS_MAX_TYPES;
2692 prio = &dev->flow_db.prios[priority];
2693 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2694 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2695 ns = mlx5_get_flow_namespace(dev->mdev,
2696 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2697 build_leftovers_ft_param(&priority,
2700 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2701 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2702 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2703 allow_sniffer_and_nic_rx_shared_tir))
2704 return ERR_PTR(-ENOTSUPP);
2706 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2707 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2708 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2710 prio = &dev->flow_db.sniffer[ft_type];
2717 return ERR_PTR(-ENOTSUPP);
2719 if (num_entries > max_table_size)
2720 return ERR_PTR(-ENOMEM);
2722 ft = prio->flow_table;
2724 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2731 prio->flow_table = ft;
2737 return err ? ERR_PTR(err) : prio;
2740 static void set_underlay_qp(struct mlx5_ib_dev *dev,
2741 struct mlx5_flow_spec *spec,
2744 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2745 spec->match_criteria,
2747 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2751 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2752 ft_field_support.bth_dst_qp)) {
2753 MLX5_SET(fte_match_set_misc,
2754 misc_params_v, bth_dst_qp, underlay_qpn);
2755 MLX5_SET(fte_match_set_misc,
2756 misc_params_c, bth_dst_qp, 0xffffff);
2760 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2761 struct mlx5_ib_flow_prio *ft_prio,
2762 const struct ib_flow_attr *flow_attr,
2763 struct mlx5_flow_destination *dst,
2766 struct mlx5_flow_table *ft = ft_prio->flow_table;
2767 struct mlx5_ib_flow_handler *handler;
2768 struct mlx5_flow_act flow_act = {0};
2769 struct mlx5_flow_spec *spec;
2770 struct mlx5_flow_destination *rule_dst = dst;
2771 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2772 unsigned int spec_index;
2773 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2774 bool is_drop = false;
2778 if (!is_valid_attr(dev->mdev, flow_attr))
2779 return ERR_PTR(-EINVAL);
2781 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2782 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2783 if (!handler || !spec) {
2788 INIT_LIST_HEAD(&handler->list);
2790 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2791 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2793 ib_flow, &flow_tag, &is_drop);
2797 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2800 if (!flow_is_multicast_only(flow_attr))
2801 set_underlay_qp(dev, spec, underlay_qpn);
2803 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2805 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2809 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2810 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2813 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2814 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2815 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2816 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2817 flow_tag, flow_attr->type);
2821 flow_act.flow_tag = flow_tag;
2822 handler->rule = mlx5_add_flow_rules(ft, spec,
2824 rule_dst, dest_num);
2826 if (IS_ERR(handler->rule)) {
2827 err = PTR_ERR(handler->rule);
2831 ft_prio->refcount++;
2832 handler->prio = ft_prio;
2834 ft_prio->flow_table = ft;
2839 return err ? ERR_PTR(err) : handler;
2842 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2843 struct mlx5_ib_flow_prio *ft_prio,
2844 const struct ib_flow_attr *flow_attr,
2845 struct mlx5_flow_destination *dst)
2847 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2850 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2851 struct mlx5_ib_flow_prio *ft_prio,
2852 struct ib_flow_attr *flow_attr,
2853 struct mlx5_flow_destination *dst)
2855 struct mlx5_ib_flow_handler *handler_dst = NULL;
2856 struct mlx5_ib_flow_handler *handler = NULL;
2858 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2859 if (!IS_ERR(handler)) {
2860 handler_dst = create_flow_rule(dev, ft_prio,
2862 if (IS_ERR(handler_dst)) {
2863 mlx5_del_flow_rules(handler->rule);
2864 ft_prio->refcount--;
2866 handler = handler_dst;
2868 list_add(&handler_dst->list, &handler->list);
2879 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2880 struct mlx5_ib_flow_prio *ft_prio,
2881 struct ib_flow_attr *flow_attr,
2882 struct mlx5_flow_destination *dst)
2884 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2885 struct mlx5_ib_flow_handler *handler = NULL;
2888 struct ib_flow_attr flow_attr;
2889 struct ib_flow_spec_eth eth_flow;
2890 } leftovers_specs[] = {
2894 .size = sizeof(leftovers_specs[0])
2897 .type = IB_FLOW_SPEC_ETH,
2898 .size = sizeof(struct ib_flow_spec_eth),
2899 .mask = {.dst_mac = {0x1} },
2900 .val = {.dst_mac = {0x1} }
2906 .size = sizeof(leftovers_specs[0])
2909 .type = IB_FLOW_SPEC_ETH,
2910 .size = sizeof(struct ib_flow_spec_eth),
2911 .mask = {.dst_mac = {0x1} },
2912 .val = {.dst_mac = {} }
2917 handler = create_flow_rule(dev, ft_prio,
2918 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2920 if (!IS_ERR(handler) &&
2921 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2922 handler_ucast = create_flow_rule(dev, ft_prio,
2923 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2925 if (IS_ERR(handler_ucast)) {
2926 mlx5_del_flow_rules(handler->rule);
2927 ft_prio->refcount--;
2929 handler = handler_ucast;
2931 list_add(&handler_ucast->list, &handler->list);
2938 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2939 struct mlx5_ib_flow_prio *ft_rx,
2940 struct mlx5_ib_flow_prio *ft_tx,
2941 struct mlx5_flow_destination *dst)
2943 struct mlx5_ib_flow_handler *handler_rx;
2944 struct mlx5_ib_flow_handler *handler_tx;
2946 static const struct ib_flow_attr flow_attr = {
2948 .size = sizeof(flow_attr)
2951 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2952 if (IS_ERR(handler_rx)) {
2953 err = PTR_ERR(handler_rx);
2957 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2958 if (IS_ERR(handler_tx)) {
2959 err = PTR_ERR(handler_tx);
2963 list_add(&handler_tx->list, &handler_rx->list);
2968 mlx5_del_flow_rules(handler_rx->rule);
2972 return ERR_PTR(err);
2975 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2976 struct ib_flow_attr *flow_attr,
2979 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2980 struct mlx5_ib_qp *mqp = to_mqp(qp);
2981 struct mlx5_ib_flow_handler *handler = NULL;
2982 struct mlx5_flow_destination *dst = NULL;
2983 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2984 struct mlx5_ib_flow_prio *ft_prio;
2988 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2989 return ERR_PTR(-ENOMEM);
2991 if (domain != IB_FLOW_DOMAIN_USER ||
2992 flow_attr->port > dev->num_ports ||
2993 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2994 return ERR_PTR(-EINVAL);
2996 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2998 return ERR_PTR(-ENOMEM);
3000 mutex_lock(&dev->flow_db.lock);
3002 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
3003 if (IS_ERR(ft_prio)) {
3004 err = PTR_ERR(ft_prio);
3007 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3008 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3009 if (IS_ERR(ft_prio_tx)) {
3010 err = PTR_ERR(ft_prio_tx);
3016 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3017 if (mqp->flags & MLX5_IB_QP_RSS)
3018 dst->tir_num = mqp->rss_qp.tirn;
3020 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3022 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3023 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3024 handler = create_dont_trap_rule(dev, ft_prio,
3027 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3028 mqp->underlay_qpn : 0;
3029 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3032 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3033 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3034 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3036 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3037 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3043 if (IS_ERR(handler)) {
3044 err = PTR_ERR(handler);
3049 mutex_unlock(&dev->flow_db.lock);
3052 return &handler->ibflow;
3055 put_flow_table(dev, ft_prio, false);
3057 put_flow_table(dev, ft_prio_tx, false);
3059 mutex_unlock(&dev->flow_db.lock);
3062 return ERR_PTR(err);
3065 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3067 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3068 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
3071 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3072 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3076 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
3078 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3079 ibqp->qp_num, gid->raw);
3084 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3086 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3089 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
3091 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3092 ibqp->qp_num, gid->raw);
3097 static int init_node_data(struct mlx5_ib_dev *dev)
3101 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
3105 dev->mdev->rev_id = dev->mdev->pdev->revision;
3107 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
3110 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3113 struct mlx5_ib_dev *dev =
3114 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3116 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
3119 static ssize_t show_reg_pages(struct device *device,
3120 struct device_attribute *attr, char *buf)
3122 struct mlx5_ib_dev *dev =
3123 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3125 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
3128 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3131 struct mlx5_ib_dev *dev =
3132 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3133 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
3136 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3139 struct mlx5_ib_dev *dev =
3140 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3141 return sprintf(buf, "%x\n", dev->mdev->rev_id);
3144 static ssize_t show_board(struct device *device, struct device_attribute *attr,
3147 struct mlx5_ib_dev *dev =
3148 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3149 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
3150 dev->mdev->board_id);
3153 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
3154 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3155 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3156 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3157 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3159 static struct device_attribute *mlx5_class_attributes[] = {
3164 &dev_attr_reg_pages,
3167 static void pkey_change_handler(struct work_struct *work)
3169 struct mlx5_ib_port_resources *ports =
3170 container_of(work, struct mlx5_ib_port_resources,
3173 mutex_lock(&ports->devr->mutex);
3174 mlx5_ib_gsi_pkey_change(ports->gsi);
3175 mutex_unlock(&ports->devr->mutex);
3178 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3180 struct mlx5_ib_qp *mqp;
3181 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3182 struct mlx5_core_cq *mcq;
3183 struct list_head cq_armed_list;
3184 unsigned long flags_qp;
3185 unsigned long flags_cq;
3186 unsigned long flags;
3188 INIT_LIST_HEAD(&cq_armed_list);
3190 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3191 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3192 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3193 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3194 if (mqp->sq.tail != mqp->sq.head) {
3195 send_mcq = to_mcq(mqp->ibqp.send_cq);
3196 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3197 if (send_mcq->mcq.comp &&
3198 mqp->ibqp.send_cq->comp_handler) {
3199 if (!send_mcq->mcq.reset_notify_added) {
3200 send_mcq->mcq.reset_notify_added = 1;
3201 list_add_tail(&send_mcq->mcq.reset_notify,
3205 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3207 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3208 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3209 /* no handling is needed for SRQ */
3210 if (!mqp->ibqp.srq) {
3211 if (mqp->rq.tail != mqp->rq.head) {
3212 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3213 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3214 if (recv_mcq->mcq.comp &&
3215 mqp->ibqp.recv_cq->comp_handler) {
3216 if (!recv_mcq->mcq.reset_notify_added) {
3217 recv_mcq->mcq.reset_notify_added = 1;
3218 list_add_tail(&recv_mcq->mcq.reset_notify,
3222 spin_unlock_irqrestore(&recv_mcq->lock,
3226 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3228 /*At that point all inflight post send were put to be executed as of we
3229 * lock/unlock above locks Now need to arm all involved CQs.
3231 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3234 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3237 static void delay_drop_handler(struct work_struct *work)
3240 struct mlx5_ib_delay_drop *delay_drop =
3241 container_of(work, struct mlx5_ib_delay_drop,
3244 atomic_inc(&delay_drop->events_cnt);
3246 mutex_lock(&delay_drop->lock);
3247 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3248 delay_drop->timeout);
3250 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3251 delay_drop->timeout);
3252 delay_drop->activate = false;
3254 mutex_unlock(&delay_drop->lock);
3257 static void mlx5_ib_handle_event(struct work_struct *_work)
3259 struct mlx5_ib_event_work *work =
3260 container_of(_work, struct mlx5_ib_event_work, work);
3261 struct mlx5_ib_dev *ibdev;
3262 struct ib_event ibev;
3266 if (mlx5_core_is_mp_slave(work->dev)) {
3267 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3271 ibdev = work->context;
3274 switch (work->event) {
3275 case MLX5_DEV_EVENT_SYS_ERROR:
3276 ibev.event = IB_EVENT_DEVICE_FATAL;
3277 mlx5_ib_handle_internal_error(ibdev);
3281 case MLX5_DEV_EVENT_PORT_UP:
3282 case MLX5_DEV_EVENT_PORT_DOWN:
3283 case MLX5_DEV_EVENT_PORT_INITIALIZED:
3284 port = (u8)work->param;
3286 /* In RoCE, port up/down events are handled in
3287 * mlx5_netdev_event().
3289 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3290 IB_LINK_LAYER_ETHERNET)
3293 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
3294 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3297 case MLX5_DEV_EVENT_LID_CHANGE:
3298 ibev.event = IB_EVENT_LID_CHANGE;
3299 port = (u8)work->param;
3302 case MLX5_DEV_EVENT_PKEY_CHANGE:
3303 ibev.event = IB_EVENT_PKEY_CHANGE;
3304 port = (u8)work->param;
3306 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
3309 case MLX5_DEV_EVENT_GUID_CHANGE:
3310 ibev.event = IB_EVENT_GID_CHANGE;
3311 port = (u8)work->param;
3314 case MLX5_DEV_EVENT_CLIENT_REREG:
3315 ibev.event = IB_EVENT_CLIENT_REREGISTER;
3316 port = (u8)work->param;
3318 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3319 schedule_work(&ibdev->delay_drop.delay_drop_work);
3325 ibev.device = &ibdev->ib_dev;
3326 ibev.element.port_num = port;
3328 if (port < 1 || port > ibdev->num_ports) {
3329 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
3333 if (ibdev->ib_active)
3334 ib_dispatch_event(&ibev);
3337 ibdev->ib_active = false;
3342 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3343 enum mlx5_dev_event event, unsigned long param)
3345 struct mlx5_ib_event_work *work;
3347 work = kmalloc(sizeof(*work), GFP_ATOMIC);
3351 INIT_WORK(&work->work, mlx5_ib_handle_event);
3353 work->param = param;
3354 work->context = context;
3355 work->event = event;
3357 queue_work(mlx5_ib_event_wq, &work->work);
3360 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3362 struct mlx5_hca_vport_context vport_ctx;
3366 for (port = 1; port <= dev->num_ports; port++) {
3367 dev->mdev->port_caps[port - 1].has_smi = false;
3368 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3369 MLX5_CAP_PORT_TYPE_IB) {
3370 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3371 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3375 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3379 dev->mdev->port_caps[port - 1].has_smi =
3382 dev->mdev->port_caps[port - 1].has_smi = true;
3389 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3393 for (port = 1; port <= dev->num_ports; port++)
3394 mlx5_query_ext_port_caps(dev, port);
3397 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
3399 struct ib_device_attr *dprops = NULL;
3400 struct ib_port_attr *pprops = NULL;
3402 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
3404 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3408 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3412 err = set_has_smi_cap(dev);
3416 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
3418 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3422 memset(pprops, 0, sizeof(*pprops));
3423 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3425 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3430 dev->mdev->port_caps[port - 1].pkey_table_len =
3432 dev->mdev->port_caps[port - 1].gid_table_len =
3433 pprops->gid_tbl_len;
3434 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3435 port, dprops->max_pkeys, pprops->gid_tbl_len);
3444 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3448 err = mlx5_mr_cache_cleanup(dev);
3450 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3452 mlx5_ib_destroy_qp(dev->umrc.qp);
3453 ib_free_cq(dev->umrc.cq);
3454 ib_dealloc_pd(dev->umrc.pd);
3461 static int create_umr_res(struct mlx5_ib_dev *dev)
3463 struct ib_qp_init_attr *init_attr = NULL;
3464 struct ib_qp_attr *attr = NULL;
3470 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3471 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3472 if (!attr || !init_attr) {
3477 pd = ib_alloc_pd(&dev->ib_dev, 0);
3479 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3484 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
3486 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3491 init_attr->send_cq = cq;
3492 init_attr->recv_cq = cq;
3493 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3494 init_attr->cap.max_send_wr = MAX_UMR_WR;
3495 init_attr->cap.max_send_sge = 1;
3496 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3497 init_attr->port_num = 1;
3498 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3500 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3504 qp->device = &dev->ib_dev;
3507 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3508 qp->send_cq = init_attr->send_cq;
3509 qp->recv_cq = init_attr->recv_cq;
3511 attr->qp_state = IB_QPS_INIT;
3513 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3516 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3520 memset(attr, 0, sizeof(*attr));
3521 attr->qp_state = IB_QPS_RTR;
3522 attr->path_mtu = IB_MTU_256;
3524 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3526 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3530 memset(attr, 0, sizeof(*attr));
3531 attr->qp_state = IB_QPS_RTS;
3532 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3534 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3542 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3543 ret = mlx5_mr_cache_init(dev);
3545 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3555 mlx5_ib_destroy_qp(qp);
3569 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3571 switch (umr_fence_cap) {
3572 case MLX5_CAP_UMR_FENCE_NONE:
3573 return MLX5_FENCE_MODE_NONE;
3574 case MLX5_CAP_UMR_FENCE_SMALL:
3575 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3577 return MLX5_FENCE_MODE_STRONG_ORDERING;
3581 static int create_dev_resources(struct mlx5_ib_resources *devr)
3583 struct ib_srq_init_attr attr;
3584 struct mlx5_ib_dev *dev;
3585 struct ib_cq_init_attr cq_attr = {.cqe = 1};
3589 dev = container_of(devr, struct mlx5_ib_dev, devr);
3591 mutex_init(&devr->mutex);
3593 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3594 if (IS_ERR(devr->p0)) {
3595 ret = PTR_ERR(devr->p0);
3598 devr->p0->device = &dev->ib_dev;
3599 devr->p0->uobject = NULL;
3600 atomic_set(&devr->p0->usecnt, 0);
3602 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3603 if (IS_ERR(devr->c0)) {
3604 ret = PTR_ERR(devr->c0);
3607 devr->c0->device = &dev->ib_dev;
3608 devr->c0->uobject = NULL;
3609 devr->c0->comp_handler = NULL;
3610 devr->c0->event_handler = NULL;
3611 devr->c0->cq_context = NULL;
3612 atomic_set(&devr->c0->usecnt, 0);
3614 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3615 if (IS_ERR(devr->x0)) {
3616 ret = PTR_ERR(devr->x0);
3619 devr->x0->device = &dev->ib_dev;
3620 devr->x0->inode = NULL;
3621 atomic_set(&devr->x0->usecnt, 0);
3622 mutex_init(&devr->x0->tgt_qp_mutex);
3623 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3625 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3626 if (IS_ERR(devr->x1)) {
3627 ret = PTR_ERR(devr->x1);
3630 devr->x1->device = &dev->ib_dev;
3631 devr->x1->inode = NULL;
3632 atomic_set(&devr->x1->usecnt, 0);
3633 mutex_init(&devr->x1->tgt_qp_mutex);
3634 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3636 memset(&attr, 0, sizeof(attr));
3637 attr.attr.max_sge = 1;
3638 attr.attr.max_wr = 1;
3639 attr.srq_type = IB_SRQT_XRC;
3640 attr.ext.cq = devr->c0;
3641 attr.ext.xrc.xrcd = devr->x0;
3643 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3644 if (IS_ERR(devr->s0)) {
3645 ret = PTR_ERR(devr->s0);
3648 devr->s0->device = &dev->ib_dev;
3649 devr->s0->pd = devr->p0;
3650 devr->s0->uobject = NULL;
3651 devr->s0->event_handler = NULL;
3652 devr->s0->srq_context = NULL;
3653 devr->s0->srq_type = IB_SRQT_XRC;
3654 devr->s0->ext.xrc.xrcd = devr->x0;
3655 devr->s0->ext.cq = devr->c0;
3656 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3657 atomic_inc(&devr->s0->ext.cq->usecnt);
3658 atomic_inc(&devr->p0->usecnt);
3659 atomic_set(&devr->s0->usecnt, 0);
3661 memset(&attr, 0, sizeof(attr));
3662 attr.attr.max_sge = 1;
3663 attr.attr.max_wr = 1;
3664 attr.srq_type = IB_SRQT_BASIC;
3665 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3666 if (IS_ERR(devr->s1)) {
3667 ret = PTR_ERR(devr->s1);
3670 devr->s1->device = &dev->ib_dev;
3671 devr->s1->pd = devr->p0;
3672 devr->s1->uobject = NULL;
3673 devr->s1->event_handler = NULL;
3674 devr->s1->srq_context = NULL;
3675 devr->s1->srq_type = IB_SRQT_BASIC;
3676 devr->s1->ext.cq = devr->c0;
3677 atomic_inc(&devr->p0->usecnt);
3678 atomic_set(&devr->s1->usecnt, 0);
3680 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3681 INIT_WORK(&devr->ports[port].pkey_change_work,
3682 pkey_change_handler);
3683 devr->ports[port].devr = devr;
3689 mlx5_ib_destroy_srq(devr->s0);
3691 mlx5_ib_dealloc_xrcd(devr->x1);
3693 mlx5_ib_dealloc_xrcd(devr->x0);
3695 mlx5_ib_destroy_cq(devr->c0);
3697 mlx5_ib_dealloc_pd(devr->p0);
3702 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3704 struct mlx5_ib_dev *dev =
3705 container_of(devr, struct mlx5_ib_dev, devr);
3708 mlx5_ib_destroy_srq(devr->s1);
3709 mlx5_ib_destroy_srq(devr->s0);
3710 mlx5_ib_dealloc_xrcd(devr->x0);
3711 mlx5_ib_dealloc_xrcd(devr->x1);
3712 mlx5_ib_destroy_cq(devr->c0);
3713 mlx5_ib_dealloc_pd(devr->p0);
3715 /* Make sure no change P_Key work items are still executing */
3716 for (port = 0; port < dev->num_ports; ++port)
3717 cancel_work_sync(&devr->ports[port].pkey_change_work);
3720 static u32 get_core_cap_flags(struct ib_device *ibdev)
3722 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3723 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3724 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3725 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3726 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
3729 if (ll == IB_LINK_LAYER_INFINIBAND)
3730 return RDMA_CORE_PORT_IBA_IB;
3733 ret = RDMA_CORE_PORT_RAW_PACKET;
3735 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3738 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3741 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3742 ret |= RDMA_CORE_PORT_IBA_ROCE;
3744 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3745 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3750 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3751 struct ib_port_immutable *immutable)
3753 struct ib_port_attr attr;
3754 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3755 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3758 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3760 err = ib_query_port(ibdev, port_num, &attr);
3764 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3765 immutable->gid_tbl_len = attr.gid_tbl_len;
3766 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3767 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3768 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3773 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3775 struct mlx5_ib_dev *dev =
3776 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3777 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3778 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3779 fw_rev_sub(dev->mdev));
3782 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3784 struct mlx5_core_dev *mdev = dev->mdev;
3785 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3786 MLX5_FLOW_NAMESPACE_LAG);
3787 struct mlx5_flow_table *ft;
3790 if (!ns || !mlx5_lag_is_active(mdev))
3793 err = mlx5_cmd_create_vport_lag(mdev);
3797 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3800 goto err_destroy_vport_lag;
3803 dev->flow_db.lag_demux_ft = ft;
3806 err_destroy_vport_lag:
3807 mlx5_cmd_destroy_vport_lag(mdev);
3811 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3813 struct mlx5_core_dev *mdev = dev->mdev;
3815 if (dev->flow_db.lag_demux_ft) {
3816 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3817 dev->flow_db.lag_demux_ft = NULL;
3819 mlx5_cmd_destroy_vport_lag(mdev);
3823 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3827 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
3828 err = register_netdevice_notifier(&dev->roce[port_num].nb);
3830 dev->roce[port_num].nb.notifier_call = NULL;
3837 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3839 if (dev->roce[port_num].nb.notifier_call) {
3840 unregister_netdevice_notifier(&dev->roce[port_num].nb);
3841 dev->roce[port_num].nb.notifier_call = NULL;
3845 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
3849 err = mlx5_add_netdev_notifier(dev, port_num);
3853 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3854 err = mlx5_nic_vport_enable_roce(dev->mdev);
3856 goto err_unregister_netdevice_notifier;
3859 err = mlx5_eth_lag_init(dev);
3861 goto err_disable_roce;
3866 if (MLX5_CAP_GEN(dev->mdev, roce))
3867 mlx5_nic_vport_disable_roce(dev->mdev);
3869 err_unregister_netdevice_notifier:
3870 mlx5_remove_netdev_notifier(dev, port_num);
3874 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3876 mlx5_eth_lag_cleanup(dev);
3877 if (MLX5_CAP_GEN(dev->mdev, roce))
3878 mlx5_nic_vport_disable_roce(dev->mdev);
3881 struct mlx5_ib_counter {
3886 #define INIT_Q_COUNTER(_name) \
3887 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3889 static const struct mlx5_ib_counter basic_q_cnts[] = {
3890 INIT_Q_COUNTER(rx_write_requests),
3891 INIT_Q_COUNTER(rx_read_requests),
3892 INIT_Q_COUNTER(rx_atomic_requests),
3893 INIT_Q_COUNTER(out_of_buffer),
3896 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3897 INIT_Q_COUNTER(out_of_sequence),
3900 static const struct mlx5_ib_counter retrans_q_cnts[] = {
3901 INIT_Q_COUNTER(duplicate_request),
3902 INIT_Q_COUNTER(rnr_nak_retry_err),
3903 INIT_Q_COUNTER(packet_seq_err),
3904 INIT_Q_COUNTER(implied_nak_seq_err),
3905 INIT_Q_COUNTER(local_ack_timeout_err),
3908 #define INIT_CONG_COUNTER(_name) \
3909 { .name = #_name, .offset = \
3910 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3912 static const struct mlx5_ib_counter cong_cnts[] = {
3913 INIT_CONG_COUNTER(rp_cnp_ignored),
3914 INIT_CONG_COUNTER(rp_cnp_handled),
3915 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3916 INIT_CONG_COUNTER(np_cnp_sent),
3919 static const struct mlx5_ib_counter extended_err_cnts[] = {
3920 INIT_Q_COUNTER(resp_local_length_error),
3921 INIT_Q_COUNTER(resp_cqe_error),
3922 INIT_Q_COUNTER(req_cqe_error),
3923 INIT_Q_COUNTER(req_remote_invalid_request),
3924 INIT_Q_COUNTER(req_remote_access_errors),
3925 INIT_Q_COUNTER(resp_remote_access_errors),
3926 INIT_Q_COUNTER(resp_cqe_flush_error),
3927 INIT_Q_COUNTER(req_cqe_flush_error),
3930 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3934 for (i = 0; i < dev->num_ports; i++) {
3935 if (dev->port[i].cnts.set_id)
3936 mlx5_core_dealloc_q_counter(dev->mdev,
3937 dev->port[i].cnts.set_id);
3938 kfree(dev->port[i].cnts.names);
3939 kfree(dev->port[i].cnts.offsets);
3943 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3944 struct mlx5_ib_counters *cnts)
3948 num_counters = ARRAY_SIZE(basic_q_cnts);
3950 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3951 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3953 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3954 num_counters += ARRAY_SIZE(retrans_q_cnts);
3956 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3957 num_counters += ARRAY_SIZE(extended_err_cnts);
3959 cnts->num_q_counters = num_counters;
3961 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3962 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3963 num_counters += ARRAY_SIZE(cong_cnts);
3966 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3970 cnts->offsets = kcalloc(num_counters,
3971 sizeof(cnts->offsets), GFP_KERNEL);
3983 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3990 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3991 names[j] = basic_q_cnts[i].name;
3992 offsets[j] = basic_q_cnts[i].offset;
3995 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3996 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3997 names[j] = out_of_seq_q_cnts[i].name;
3998 offsets[j] = out_of_seq_q_cnts[i].offset;
4002 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4003 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4004 names[j] = retrans_q_cnts[i].name;
4005 offsets[j] = retrans_q_cnts[i].offset;
4009 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4010 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4011 names[j] = extended_err_cnts[i].name;
4012 offsets[j] = extended_err_cnts[i].offset;
4016 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4017 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4018 names[j] = cong_cnts[i].name;
4019 offsets[j] = cong_cnts[i].offset;
4024 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
4029 for (i = 0; i < dev->num_ports; i++) {
4030 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4034 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4035 dev->port[i].cnts.offsets);
4037 err = mlx5_core_alloc_q_counter(dev->mdev,
4038 &dev->port[i].cnts.set_id);
4041 "couldn't allocate queue counter for port %d, err %d\n",
4045 dev->port[i].cnts.set_id_valid = true;
4051 mlx5_ib_dealloc_counters(dev);
4055 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4058 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4059 struct mlx5_ib_port *port = &dev->port[port_num - 1];
4061 /* We support only per port stats */
4065 return rdma_alloc_hw_stats_struct(port->cnts.names,
4066 port->cnts.num_q_counters +
4067 port->cnts.num_cong_counters,
4068 RDMA_HW_STATS_DEFAULT_LIFESPAN);
4071 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
4072 struct mlx5_ib_port *port,
4073 struct rdma_hw_stats *stats)
4075 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4080 out = kvzalloc(outlen, GFP_KERNEL);
4084 ret = mlx5_core_query_q_counter(mdev,
4085 port->cnts.set_id, 0,
4090 for (i = 0; i < port->cnts.num_q_counters; i++) {
4091 val = *(__be32 *)(out + port->cnts.offsets[i]);
4092 stats->value[i] = (u64)be32_to_cpu(val);
4100 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4101 struct rdma_hw_stats *stats,
4102 u8 port_num, int index)
4104 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4105 struct mlx5_ib_port *port = &dev->port[port_num - 1];
4106 struct mlx5_core_dev *mdev;
4107 int ret, num_counters;
4113 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4115 /* q_counters are per IB device, query the master mdev */
4116 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
4120 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4121 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4124 /* If port is not affiliated yet, its in down state
4125 * which doesn't have any counters yet, so it would be
4126 * zero. So no need to read from the HCA.
4130 ret = mlx5_lag_query_cong_counters(dev->mdev,
4132 port->cnts.num_q_counters,
4133 port->cnts.num_cong_counters,
4134 port->cnts.offsets +
4135 port->cnts.num_q_counters);
4137 mlx5_ib_put_native_port_mdev(dev, port_num);
4143 return num_counters;
4146 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4148 return mlx5_rdma_netdev_free(netdev);
4151 static struct net_device*
4152 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4154 enum rdma_netdev_t type,
4156 unsigned char name_assign_type,
4157 void (*setup)(struct net_device *))
4159 struct net_device *netdev;
4160 struct rdma_netdev *rn;
4162 if (type != RDMA_NETDEV_IPOIB)
4163 return ERR_PTR(-EOPNOTSUPP);
4165 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4167 if (likely(!IS_ERR_OR_NULL(netdev))) {
4168 rn = netdev_priv(netdev);
4169 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4174 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4176 if (!dev->delay_drop.dbg)
4178 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4179 kfree(dev->delay_drop.dbg);
4180 dev->delay_drop.dbg = NULL;
4183 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4185 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4188 cancel_work_sync(&dev->delay_drop.delay_drop_work);
4189 delay_drop_debugfs_cleanup(dev);
4192 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4193 size_t count, loff_t *pos)
4195 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4199 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4200 return simple_read_from_buffer(buf, count, pos, lbuf, len);
4203 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4204 size_t count, loff_t *pos)
4206 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4210 if (kstrtouint_from_user(buf, count, 0, &var))
4213 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4216 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4219 delay_drop->timeout = timeout;
4224 static const struct file_operations fops_delay_drop_timeout = {
4225 .owner = THIS_MODULE,
4226 .open = simple_open,
4227 .write = delay_drop_timeout_write,
4228 .read = delay_drop_timeout_read,
4231 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4233 struct mlx5_ib_dbg_delay_drop *dbg;
4235 if (!mlx5_debugfs_root)
4238 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4242 dev->delay_drop.dbg = dbg;
4245 debugfs_create_dir("delay_drop",
4246 dev->mdev->priv.dbg_root);
4247 if (!dbg->dir_debugfs)
4250 dbg->events_cnt_debugfs =
4251 debugfs_create_atomic_t("num_timeout_events", 0400,
4253 &dev->delay_drop.events_cnt);
4254 if (!dbg->events_cnt_debugfs)
4257 dbg->rqs_cnt_debugfs =
4258 debugfs_create_atomic_t("num_rqs", 0400,
4260 &dev->delay_drop.rqs_cnt);
4261 if (!dbg->rqs_cnt_debugfs)
4264 dbg->timeout_debugfs =
4265 debugfs_create_file("timeout", 0600,
4268 &fops_delay_drop_timeout);
4269 if (!dbg->timeout_debugfs)
4275 delay_drop_debugfs_cleanup(dev);
4279 static void init_delay_drop(struct mlx5_ib_dev *dev)
4281 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4284 mutex_init(&dev->delay_drop.lock);
4285 dev->delay_drop.dev = dev;
4286 dev->delay_drop.activate = false;
4287 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4288 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4289 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4290 atomic_set(&dev->delay_drop.events_cnt, 0);
4292 if (delay_drop_debugfs_init(dev))
4293 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
4296 static const struct cpumask *
4297 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
4299 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4301 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4304 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4305 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4306 struct mlx5_ib_multiport_info *mpi)
4308 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4309 struct mlx5_ib_port *port = &ibdev->port[port_num];
4314 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4316 spin_lock(&port->mp.mpi_lock);
4318 spin_unlock(&port->mp.mpi_lock);
4323 spin_unlock(&port->mp.mpi_lock);
4324 mlx5_remove_netdev_notifier(ibdev, port_num);
4325 spin_lock(&port->mp.mpi_lock);
4327 comps = mpi->mdev_refcnt;
4329 mpi->unaffiliate = true;
4330 init_completion(&mpi->unref_comp);
4331 spin_unlock(&port->mp.mpi_lock);
4333 for (i = 0; i < comps; i++)
4334 wait_for_completion(&mpi->unref_comp);
4336 spin_lock(&port->mp.mpi_lock);
4337 mpi->unaffiliate = false;
4340 port->mp.mpi = NULL;
4342 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4344 spin_unlock(&port->mp.mpi_lock);
4346 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4348 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4349 /* Log an error, still needed to cleanup the pointers and add
4350 * it back to the list.
4353 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4356 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4359 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4360 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4361 struct mlx5_ib_multiport_info *mpi)
4363 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4366 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4367 if (ibdev->port[port_num].mp.mpi) {
4368 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4370 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4374 ibdev->port[port_num].mp.mpi = mpi;
4376 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4378 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4382 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4386 err = mlx5_add_netdev_notifier(ibdev, port_num);
4388 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4393 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4400 mlx5_ib_unbind_slave_port(ibdev, mpi);
4404 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4406 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4407 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4409 struct mlx5_ib_multiport_info *mpi;
4413 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4416 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4417 &dev->sys_image_guid);
4421 err = mlx5_nic_vport_enable_roce(dev->mdev);
4425 mutex_lock(&mlx5_ib_multiport_mutex);
4426 for (i = 0; i < dev->num_ports; i++) {
4429 /* build a stub multiport info struct for the native port. */
4430 if (i == port_num) {
4431 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4433 mutex_unlock(&mlx5_ib_multiport_mutex);
4434 mlx5_nic_vport_disable_roce(dev->mdev);
4438 mpi->is_master = true;
4439 mpi->mdev = dev->mdev;
4440 mpi->sys_image_guid = dev->sys_image_guid;
4441 dev->port[i].mp.mpi = mpi;
4447 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4449 if (dev->sys_image_guid == mpi->sys_image_guid &&
4450 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4451 bound = mlx5_ib_bind_slave_port(dev, mpi);
4455 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4456 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4457 list_del(&mpi->list);
4462 get_port_caps(dev, i + 1);
4463 mlx5_ib_dbg(dev, "no free port found for port %d\n",
4468 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4469 mutex_unlock(&mlx5_ib_multiport_mutex);
4473 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4475 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4476 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4480 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4483 mutex_lock(&mlx5_ib_multiport_mutex);
4484 for (i = 0; i < dev->num_ports; i++) {
4485 if (dev->port[i].mp.mpi) {
4486 /* Destroy the native port stub */
4487 if (i == port_num) {
4488 kfree(dev->port[i].mp.mpi);
4489 dev->port[i].mp.mpi = NULL;
4491 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4492 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4497 mlx5_ib_dbg(dev, "removing from devlist\n");
4498 list_del(&dev->ib_dev_list);
4499 mutex_unlock(&mlx5_ib_multiport_mutex);
4501 mlx5_nic_vport_disable_roce(dev->mdev);
4504 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
4506 mlx5_ib_cleanup_multiport_master(dev);
4507 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4508 cleanup_srcu_struct(&dev->mr_srcu);
4513 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
4515 struct mlx5_core_dev *mdev = dev->mdev;
4520 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
4525 for (i = 0; i < dev->num_ports; i++) {
4526 spin_lock_init(&dev->port[i].mp.mpi_lock);
4527 rwlock_init(&dev->roce[i].netdev_lock);
4530 err = mlx5_ib_init_multiport_master(dev);
4534 if (!mlx5_core_mp_enabled(mdev)) {
4537 for (i = 1; i <= dev->num_ports; i++) {
4538 err = get_port_caps(dev, i);
4543 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
4548 if (mlx5_use_mad_ifc(dev))
4549 get_ext_port_caps(dev);
4551 if (!mlx5_lag_is_active(mdev))
4554 name = "mlx5_bond_%d";
4556 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
4557 dev->ib_dev.owner = THIS_MODULE;
4558 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
4559 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
4560 dev->ib_dev.phys_port_cnt = dev->num_ports;
4561 dev->ib_dev.num_comp_vectors =
4562 dev->mdev->priv.eq_table.num_comp_vectors;
4563 dev->ib_dev.dev.parent = &mdev->pdev->dev;
4565 mutex_init(&dev->flow_db.lock);
4566 mutex_init(&dev->cap_mask_mutex);
4567 INIT_LIST_HEAD(&dev->qp_list);
4568 spin_lock_init(&dev->reset_flow_resource_lock);
4570 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4571 err = init_srcu_struct(&dev->mr_srcu);
4578 mlx5_ib_cleanup_multiport_master(dev);
4586 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4588 struct mlx5_core_dev *mdev = dev->mdev;
4591 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
4592 dev->ib_dev.uverbs_cmd_mask =
4593 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
4594 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
4595 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
4596 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
4597 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
4598 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
4599 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
4600 (1ull << IB_USER_VERBS_CMD_REG_MR) |
4601 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
4602 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
4603 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4604 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
4605 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
4606 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
4607 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
4608 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
4609 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
4610 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
4611 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
4612 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
4613 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
4614 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
4615 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
4616 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
4617 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
4618 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
4619 dev->ib_dev.uverbs_ex_cmd_mask =
4620 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
4621 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
4622 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
4623 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
4624 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
4626 dev->ib_dev.query_device = mlx5_ib_query_device;
4627 dev->ib_dev.query_port = mlx5_ib_query_port;
4628 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
4629 dev->ib_dev.query_gid = mlx5_ib_query_gid;
4630 dev->ib_dev.add_gid = mlx5_ib_add_gid;
4631 dev->ib_dev.del_gid = mlx5_ib_del_gid;
4632 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
4633 dev->ib_dev.modify_device = mlx5_ib_modify_device;
4634 dev->ib_dev.modify_port = mlx5_ib_modify_port;
4635 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
4636 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
4637 dev->ib_dev.mmap = mlx5_ib_mmap;
4638 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
4639 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4640 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4641 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4642 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4643 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4644 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4645 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4646 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4647 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4648 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4649 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4650 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4651 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4652 dev->ib_dev.post_send = mlx5_ib_post_send;
4653 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4654 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4655 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4656 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4657 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4658 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4659 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4660 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4661 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
4662 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
4663 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4664 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4665 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4666 dev->ib_dev.process_mad = mlx5_ib_process_mad;
4667 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
4668 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
4669 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
4670 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
4671 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
4672 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
4673 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
4674 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
4676 if (mlx5_core_is_pf(mdev)) {
4677 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4678 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4679 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4680 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4683 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4685 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4687 if (MLX5_CAP_GEN(mdev, imaicl)) {
4688 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4689 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4690 dev->ib_dev.uverbs_cmd_mask |=
4691 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4692 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4695 if (MLX5_CAP_GEN(mdev, xrc)) {
4696 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4697 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4698 dev->ib_dev.uverbs_cmd_mask |=
4699 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4700 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4703 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4704 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4705 dev->ib_dev.uverbs_ex_cmd_mask |=
4706 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4707 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4709 err = init_node_data(dev);
4713 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4714 MLX5_CAP_GEN(dev->mdev, disable_local_lb))
4715 mutex_init(&dev->lb_mutex);
4720 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
4722 struct mlx5_core_dev *mdev = dev->mdev;
4723 enum rdma_link_layer ll;
4729 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4730 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4731 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4733 if (ll == IB_LINK_LAYER_ETHERNET) {
4734 for (i = 0; i < dev->num_ports; i++) {
4735 dev->roce[i].dev = dev;
4736 dev->roce[i].native_port_num = i + 1;
4737 dev->roce[i].last_port_state = IB_PORT_DOWN;
4740 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
4741 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4742 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4743 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
4744 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4745 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4746 dev->ib_dev.uverbs_ex_cmd_mask |=
4747 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4748 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4749 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4750 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4751 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
4752 err = mlx5_enable_eth(dev, port_num);
4760 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
4762 struct mlx5_core_dev *mdev = dev->mdev;
4763 enum rdma_link_layer ll;
4767 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4768 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4769 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4771 if (ll == IB_LINK_LAYER_ETHERNET) {
4772 mlx5_disable_eth(dev);
4773 mlx5_remove_netdev_notifier(dev, port_num);
4777 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
4779 return create_dev_resources(&dev->devr);
4782 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
4784 destroy_dev_resources(&dev->devr);
4787 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
4789 mlx5_ib_internal_fill_odp_caps(dev);
4791 return mlx5_ib_odp_init_one(dev);
4794 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
4796 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4797 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4798 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4800 return mlx5_ib_alloc_counters(dev);
4806 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
4808 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4809 mlx5_ib_dealloc_counters(dev);
4812 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4814 return mlx5_ib_init_cong_debugfs(dev,
4815 mlx5_core_native_port_num(dev->mdev) - 1);
4818 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4820 mlx5_ib_cleanup_cong_debugfs(dev,
4821 mlx5_core_native_port_num(dev->mdev) - 1);
4824 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4826 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4827 if (!dev->mdev->priv.uar)
4832 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4834 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4837 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4841 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4845 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4847 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4852 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4854 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4855 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4858 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4860 return ib_register_device(&dev->ib_dev, NULL);
4863 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4865 ib_unregister_device(&dev->ib_dev);
4868 static int mlx5_ib_stage_umr_res_init(struct mlx5_ib_dev *dev)
4870 return create_umr_res(dev);
4873 static void mlx5_ib_stage_umr_res_cleanup(struct mlx5_ib_dev *dev)
4875 destroy_umrc_res(dev);
4878 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4880 init_delay_drop(dev);
4885 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4887 cancel_delay_drop(dev);
4890 static int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
4895 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
4896 err = device_create_file(&dev->ib_dev.dev,
4897 mlx5_class_attributes[i]);
4905 static void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4906 const struct mlx5_ib_profile *profile,
4909 /* Number of stages to cleanup */
4912 if (profile->stage[stage].cleanup)
4913 profile->stage[stage].cleanup(dev);
4916 ib_dealloc_device((struct ib_device *)dev);
4919 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
4921 static void *__mlx5_ib_add(struct mlx5_core_dev *mdev,
4922 const struct mlx5_ib_profile *profile)
4924 struct mlx5_ib_dev *dev;
4928 printk_once(KERN_INFO "%s", mlx5_version);
4930 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
4935 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4936 MLX5_CAP_GEN(mdev, num_vhca_ports));
4938 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4939 if (profile->stage[i].init) {
4940 err = profile->stage[i].init(dev);
4946 dev->profile = profile;
4947 dev->ib_active = true;
4952 __mlx5_ib_remove(dev, profile, i);
4957 static const struct mlx5_ib_profile pf_profile = {
4958 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4959 mlx5_ib_stage_init_init,
4960 mlx5_ib_stage_init_cleanup),
4961 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4962 mlx5_ib_stage_caps_init,
4964 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4965 mlx5_ib_stage_roce_init,
4966 mlx5_ib_stage_roce_cleanup),
4967 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4968 mlx5_ib_stage_dev_res_init,
4969 mlx5_ib_stage_dev_res_cleanup),
4970 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4971 mlx5_ib_stage_odp_init,
4973 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4974 mlx5_ib_stage_counters_init,
4975 mlx5_ib_stage_counters_cleanup),
4976 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4977 mlx5_ib_stage_cong_debugfs_init,
4978 mlx5_ib_stage_cong_debugfs_cleanup),
4979 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4980 mlx5_ib_stage_uar_init,
4981 mlx5_ib_stage_uar_cleanup),
4982 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4983 mlx5_ib_stage_bfrag_init,
4984 mlx5_ib_stage_bfrag_cleanup),
4985 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4986 mlx5_ib_stage_ib_reg_init,
4987 mlx5_ib_stage_ib_reg_cleanup),
4988 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES,
4989 mlx5_ib_stage_umr_res_init,
4990 mlx5_ib_stage_umr_res_cleanup),
4991 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4992 mlx5_ib_stage_delay_drop_init,
4993 mlx5_ib_stage_delay_drop_cleanup),
4994 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
4995 mlx5_ib_stage_class_attr_init,
4999 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5001 struct mlx5_ib_multiport_info *mpi;
5002 struct mlx5_ib_dev *dev;
5006 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5012 err = mlx5_query_nic_vport_system_image_guid(mdev,
5013 &mpi->sys_image_guid);
5019 mutex_lock(&mlx5_ib_multiport_mutex);
5020 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5021 if (dev->sys_image_guid == mpi->sys_image_guid)
5022 bound = mlx5_ib_bind_slave_port(dev, mpi);
5025 rdma_roce_rescan_device(&dev->ib_dev);
5031 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5032 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5034 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5036 mutex_unlock(&mlx5_ib_multiport_mutex);
5041 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5043 enum rdma_link_layer ll;
5046 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5047 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5049 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5050 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5052 return mlx5_ib_add_slave_port(mdev, port_num);
5055 return __mlx5_ib_add(mdev, &pf_profile);
5058 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
5060 struct mlx5_ib_multiport_info *mpi;
5061 struct mlx5_ib_dev *dev;
5063 if (mlx5_core_is_mp_slave(mdev)) {
5065 mutex_lock(&mlx5_ib_multiport_mutex);
5067 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5068 list_del(&mpi->list);
5069 mutex_unlock(&mlx5_ib_multiport_mutex);
5074 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
5077 static struct mlx5_interface mlx5_ib_interface = {
5079 .remove = mlx5_ib_remove,
5080 .event = mlx5_ib_event,
5081 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5082 .pfault = mlx5_ib_pfault,
5084 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
5087 static int __init mlx5_ib_init(void)
5091 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
5092 if (!mlx5_ib_event_wq)
5097 err = mlx5_register_interface(&mlx5_ib_interface);
5102 static void __exit mlx5_ib_cleanup(void)
5104 mlx5_unregister_interface(&mlx5_ib_interface);
5105 destroy_workqueue(mlx5_ib_event_wq);
5108 module_init(mlx5_ib_init);
5109 module_exit(mlx5_ib_cleanup);