Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[sfrench/cifs-2.6.git] / drivers / infiniband / hw / mlx4 / qp.c
1 /*
2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <rdma/ib_cache.h>
34 #include <rdma/ib_pack.h>
35
36 #include <linux/mlx4/qp.h>
37
38 #include "mlx4_ib.h"
39 #include "user.h"
40
41 enum {
42         MLX4_IB_ACK_REQ_FREQ    = 8,
43 };
44
45 enum {
46         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
47         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
48 };
49
50 enum {
51         /*
52          * Largest possible UD header: send with GRH and immediate data.
53          */
54         MLX4_IB_UD_HEADER_SIZE          = 72
55 };
56
57 struct mlx4_ib_sqp {
58         struct mlx4_ib_qp       qp;
59         int                     pkey_index;
60         u32                     qkey;
61         u32                     send_psn;
62         struct ib_ud_header     ud_header;
63         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
64 };
65
66 static const __be32 mlx4_ib_opcode[] = {
67         [IB_WR_SEND]                    = __constant_cpu_to_be32(MLX4_OPCODE_SEND),
68         [IB_WR_SEND_WITH_IMM]           = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM),
69         [IB_WR_RDMA_WRITE]              = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
70         [IB_WR_RDMA_WRITE_WITH_IMM]     = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
71         [IB_WR_RDMA_READ]               = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ),
72         [IB_WR_ATOMIC_CMP_AND_SWP]      = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
73         [IB_WR_ATOMIC_FETCH_AND_ADD]    = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
74 };
75
76 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
77 {
78         return container_of(mqp, struct mlx4_ib_sqp, qp);
79 }
80
81 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
82 {
83         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
84                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
85 }
86
87 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
88 {
89         return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
90                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
91 }
92
93 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
94 {
95         if (qp->buf.nbufs == 1)
96                 return qp->buf.u.direct.buf + offset;
97         else
98                 return qp->buf.u.page_list[offset >> PAGE_SHIFT].buf +
99                         (offset & (PAGE_SIZE - 1));
100 }
101
102 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
103 {
104         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
105 }
106
107 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
108 {
109         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
110 }
111
112 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
113 {
114         struct ib_event event;
115         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
116
117         if (type == MLX4_EVENT_TYPE_PATH_MIG)
118                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
119
120         if (ibqp->event_handler) {
121                 event.device     = ibqp->device;
122                 event.element.qp = ibqp;
123                 switch (type) {
124                 case MLX4_EVENT_TYPE_PATH_MIG:
125                         event.event = IB_EVENT_PATH_MIG;
126                         break;
127                 case MLX4_EVENT_TYPE_COMM_EST:
128                         event.event = IB_EVENT_COMM_EST;
129                         break;
130                 case MLX4_EVENT_TYPE_SQ_DRAINED:
131                         event.event = IB_EVENT_SQ_DRAINED;
132                         break;
133                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
134                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
135                         break;
136                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
137                         event.event = IB_EVENT_QP_FATAL;
138                         break;
139                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
140                         event.event = IB_EVENT_PATH_MIG_ERR;
141                         break;
142                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
143                         event.event = IB_EVENT_QP_REQ_ERR;
144                         break;
145                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
146                         event.event = IB_EVENT_QP_ACCESS_ERR;
147                         break;
148                 default:
149                         printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
150                                "on QP %06x\n", type, qp->qpn);
151                         return;
152                 }
153
154                 ibqp->event_handler(&event, ibqp->qp_context);
155         }
156 }
157
158 static int send_wqe_overhead(enum ib_qp_type type)
159 {
160         /*
161          * UD WQEs must have a datagram segment.
162          * RC and UC WQEs might have a remote address segment.
163          * MLX WQEs need two extra inline data segments (for the UD
164          * header and space for the ICRC).
165          */
166         switch (type) {
167         case IB_QPT_UD:
168                 return sizeof (struct mlx4_wqe_ctrl_seg) +
169                         sizeof (struct mlx4_wqe_datagram_seg);
170         case IB_QPT_UC:
171                 return sizeof (struct mlx4_wqe_ctrl_seg) +
172                         sizeof (struct mlx4_wqe_raddr_seg);
173         case IB_QPT_RC:
174                 return sizeof (struct mlx4_wqe_ctrl_seg) +
175                         sizeof (struct mlx4_wqe_atomic_seg) +
176                         sizeof (struct mlx4_wqe_raddr_seg);
177         case IB_QPT_SMI:
178         case IB_QPT_GSI:
179                 return sizeof (struct mlx4_wqe_ctrl_seg) +
180                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
181                               sizeof (struct mlx4_wqe_inline_seg),
182                               sizeof (struct mlx4_wqe_data_seg)) +
183                         ALIGN(4 +
184                               sizeof (struct mlx4_wqe_inline_seg),
185                               sizeof (struct mlx4_wqe_data_seg));
186         default:
187                 return sizeof (struct mlx4_wqe_ctrl_seg);
188         }
189 }
190
191 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
192                        struct mlx4_ib_qp *qp)
193 {
194         /* Sanity check RQ size before proceeding */
195         if (cap->max_recv_wr  > dev->dev->caps.max_wqes  ||
196             cap->max_recv_sge > dev->dev->caps.max_rq_sg)
197                 return -EINVAL;
198
199         qp->rq.max = cap->max_recv_wr ? roundup_pow_of_two(cap->max_recv_wr) : 0;
200
201         qp->rq.wqe_shift = ilog2(roundup_pow_of_two(cap->max_recv_sge *
202                                                     sizeof (struct mlx4_wqe_data_seg)));
203         qp->rq.max_gs    = (1 << qp->rq.wqe_shift) / sizeof (struct mlx4_wqe_data_seg);
204
205         cap->max_recv_wr  = qp->rq.max;
206         cap->max_recv_sge = qp->rq.max_gs;
207
208         return 0;
209 }
210
211 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
212                               enum ib_qp_type type, struct mlx4_ib_qp *qp)
213 {
214         /* Sanity check SQ size before proceeding */
215         if (cap->max_send_wr     > dev->dev->caps.max_wqes  ||
216             cap->max_send_sge    > dev->dev->caps.max_sq_sg ||
217             cap->max_inline_data + send_wqe_overhead(type) +
218             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
219                 return -EINVAL;
220
221         /*
222          * For MLX transport we need 2 extra S/G entries:
223          * one for the header and one for the checksum at the end
224          */
225         if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
226             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
227                 return -EINVAL;
228
229         qp->sq.max = cap->max_send_wr ? roundup_pow_of_two(cap->max_send_wr) : 1;
230
231         qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
232                                                         sizeof (struct mlx4_wqe_data_seg),
233                                                         cap->max_inline_data +
234                                                         sizeof (struct mlx4_wqe_inline_seg)) +
235                                                     send_wqe_overhead(type)));
236         qp->sq.max_gs    = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
237                 sizeof (struct mlx4_wqe_data_seg);
238
239         qp->buf_size = (qp->rq.max << qp->rq.wqe_shift) +
240                 (qp->sq.max << qp->sq.wqe_shift);
241         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
242                 qp->rq.offset = 0;
243                 qp->sq.offset = qp->rq.max << qp->rq.wqe_shift;
244         } else {
245                 qp->rq.offset = qp->sq.max << qp->sq.wqe_shift;
246                 qp->sq.offset = 0;
247         }
248
249         cap->max_send_wr     = qp->sq.max;
250         cap->max_send_sge    = qp->sq.max_gs;
251         cap->max_inline_data = (1 << qp->sq.wqe_shift) - send_wqe_overhead(type) -
252                 sizeof (struct mlx4_wqe_inline_seg);
253
254         return 0;
255 }
256
257 static int set_user_sq_size(struct mlx4_ib_qp *qp,
258                             struct mlx4_ib_create_qp *ucmd)
259 {
260         qp->sq.max       = 1 << ucmd->log_sq_bb_count;
261         qp->sq.wqe_shift = ucmd->log_sq_stride;
262
263         qp->buf_size = (qp->rq.max << qp->rq.wqe_shift) +
264                 (qp->sq.max << qp->sq.wqe_shift);
265
266         return 0;
267 }
268
269 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
270                             struct ib_qp_init_attr *init_attr,
271                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
272 {
273         int err;
274
275         mutex_init(&qp->mutex);
276         spin_lock_init(&qp->sq.lock);
277         spin_lock_init(&qp->rq.lock);
278
279         qp->state        = IB_QPS_RESET;
280         qp->atomic_rd_en = 0;
281         qp->resp_depth   = 0;
282
283         qp->rq.head         = 0;
284         qp->rq.tail         = 0;
285         qp->sq.head         = 0;
286         qp->sq.tail         = 0;
287
288         err = set_rq_size(dev, &init_attr->cap, qp);
289         if (err)
290                 goto err;
291
292         if (pd->uobject) {
293                 struct mlx4_ib_create_qp ucmd;
294
295                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
296                         err = -EFAULT;
297                         goto err;
298                 }
299
300                 err = set_user_sq_size(qp, &ucmd);
301                 if (err)
302                         goto err;
303
304                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
305                                        qp->buf_size, 0);
306                 if (IS_ERR(qp->umem)) {
307                         err = PTR_ERR(qp->umem);
308                         goto err;
309                 }
310
311                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
312                                     ilog2(qp->umem->page_size), &qp->mtt);
313                 if (err)
314                         goto err_buf;
315
316                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
317                 if (err)
318                         goto err_mtt;
319
320                 if (!init_attr->srq) {
321                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
322                                                   ucmd.db_addr, &qp->db);
323                         if (err)
324                                 goto err_mtt;
325                 }
326         } else {
327                 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
328                 if (err)
329                         goto err;
330
331                 if (!init_attr->srq) {
332                         err = mlx4_ib_db_alloc(dev, &qp->db, 0);
333                         if (err)
334                                 goto err;
335
336                         *qp->db.db = 0;
337                 }
338
339                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
340                         err = -ENOMEM;
341                         goto err_db;
342                 }
343
344                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
345                                     &qp->mtt);
346                 if (err)
347                         goto err_buf;
348
349                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
350                 if (err)
351                         goto err_mtt;
352
353                 qp->sq.wrid  = kmalloc(qp->sq.max * sizeof (u64), GFP_KERNEL);
354                 qp->rq.wrid  = kmalloc(qp->rq.max * sizeof (u64), GFP_KERNEL);
355
356                 if (!qp->sq.wrid || !qp->rq.wrid) {
357                         err = -ENOMEM;
358                         goto err_wrid;
359                 }
360
361                 /* We don't support inline sends for kernel QPs (yet) */
362                 init_attr->cap.max_inline_data = 0;
363         }
364
365         err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp);
366         if (err)
367                 goto err_wrid;
368
369         /*
370          * Hardware wants QPN written in big-endian order (after
371          * shifting) for send doorbell.  Precompute this value to save
372          * a little bit when posting sends.
373          */
374         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
375
376         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
377                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
378         else
379                 qp->sq_signal_bits = 0;
380
381         qp->mqp.event = mlx4_ib_qp_event;
382
383         return 0;
384
385 err_wrid:
386         if (pd->uobject && !init_attr->srq)
387                 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
388         else {
389                 kfree(qp->sq.wrid);
390                 kfree(qp->rq.wrid);
391         }
392
393 err_mtt:
394         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
395
396 err_buf:
397         if (pd->uobject)
398                 ib_umem_release(qp->umem);
399         else
400                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
401
402 err_db:
403         if (!pd->uobject && !init_attr->srq)
404                 mlx4_ib_db_free(dev, &qp->db);
405
406 err:
407         return err;
408 }
409
410 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
411 {
412         switch (state) {
413         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
414         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
415         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
416         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
417         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
418         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
419         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
420         default:                return -1;
421         }
422 }
423
424 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
425 {
426         if (send_cq == recv_cq)
427                 spin_lock_irq(&send_cq->lock);
428         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
429                 spin_lock_irq(&send_cq->lock);
430                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
431         } else {
432                 spin_lock_irq(&recv_cq->lock);
433                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
434         }
435 }
436
437 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
438 {
439         if (send_cq == recv_cq)
440                 spin_unlock_irq(&send_cq->lock);
441         else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
442                 spin_unlock(&recv_cq->lock);
443                 spin_unlock_irq(&send_cq->lock);
444         } else {
445                 spin_unlock(&send_cq->lock);
446                 spin_unlock_irq(&recv_cq->lock);
447         }
448 }
449
450 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
451                               int is_user)
452 {
453         struct mlx4_ib_cq *send_cq, *recv_cq;
454
455         if (qp->state != IB_QPS_RESET)
456                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
457                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
458                         printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
459                                qp->mqp.qpn);
460
461         send_cq = to_mcq(qp->ibqp.send_cq);
462         recv_cq = to_mcq(qp->ibqp.recv_cq);
463
464         mlx4_ib_lock_cqs(send_cq, recv_cq);
465
466         if (!is_user) {
467                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
468                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
469                 if (send_cq != recv_cq)
470                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
471         }
472
473         mlx4_qp_remove(dev->dev, &qp->mqp);
474
475         mlx4_ib_unlock_cqs(send_cq, recv_cq);
476
477         mlx4_qp_free(dev->dev, &qp->mqp);
478         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
479
480         if (is_user) {
481                 if (!qp->ibqp.srq)
482                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
483                                               &qp->db);
484                 ib_umem_release(qp->umem);
485         } else {
486                 kfree(qp->sq.wrid);
487                 kfree(qp->rq.wrid);
488                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
489                 if (!qp->ibqp.srq)
490                         mlx4_ib_db_free(dev, &qp->db);
491         }
492 }
493
494 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
495                                 struct ib_qp_init_attr *init_attr,
496                                 struct ib_udata *udata)
497 {
498         struct mlx4_ib_dev *dev = to_mdev(pd->device);
499         struct mlx4_ib_sqp *sqp;
500         struct mlx4_ib_qp *qp;
501         int err;
502
503         switch (init_attr->qp_type) {
504         case IB_QPT_RC:
505         case IB_QPT_UC:
506         case IB_QPT_UD:
507         {
508                 qp = kmalloc(sizeof *qp, GFP_KERNEL);
509                 if (!qp)
510                         return ERR_PTR(-ENOMEM);
511
512                 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
513                 if (err) {
514                         kfree(qp);
515                         return ERR_PTR(err);
516                 }
517
518                 qp->ibqp.qp_num = qp->mqp.qpn;
519
520                 break;
521         }
522         case IB_QPT_SMI:
523         case IB_QPT_GSI:
524         {
525                 /* Userspace is not allowed to create special QPs: */
526                 if (pd->uobject)
527                         return ERR_PTR(-EINVAL);
528
529                 sqp = kmalloc(sizeof *sqp, GFP_KERNEL);
530                 if (!sqp)
531                         return ERR_PTR(-ENOMEM);
532
533                 qp = &sqp->qp;
534
535                 err = create_qp_common(dev, pd, init_attr, udata,
536                                        dev->dev->caps.sqp_start +
537                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
538                                        init_attr->port_num - 1,
539                                        qp);
540                 if (err) {
541                         kfree(sqp);
542                         return ERR_PTR(err);
543                 }
544
545                 qp->port        = init_attr->port_num;
546                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
547
548                 break;
549         }
550         default:
551                 /* Don't support raw QPs */
552                 return ERR_PTR(-EINVAL);
553         }
554
555         return &qp->ibqp;
556 }
557
558 int mlx4_ib_destroy_qp(struct ib_qp *qp)
559 {
560         struct mlx4_ib_dev *dev = to_mdev(qp->device);
561         struct mlx4_ib_qp *mqp = to_mqp(qp);
562
563         if (is_qp0(dev, mqp))
564                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
565
566         destroy_qp_common(dev, mqp, !!qp->pd->uobject);
567
568         if (is_sqp(dev, mqp))
569                 kfree(to_msqp(mqp));
570         else
571                 kfree(mqp);
572
573         return 0;
574 }
575
576 static void init_port(struct mlx4_ib_dev *dev, int port)
577 {
578         struct mlx4_init_port_param param;
579         int err;
580
581         memset(&param, 0, sizeof param);
582
583         param.port_width_cap = dev->dev->caps.port_width_cap;
584         param.vl_cap         = dev->dev->caps.vl_cap;
585         param.mtu            = ib_mtu_enum_to_int(dev->dev->caps.mtu_cap);
586         param.max_gid        = dev->dev->caps.gid_table_len;
587         param.max_pkey       = dev->dev->caps.pkey_table_len;
588
589         err = mlx4_INIT_PORT(dev->dev, &param, port);
590         if (err)
591                 printk(KERN_WARNING "INIT_PORT failed, return code %d.\n", err);
592 }
593
594 static int to_mlx4_st(enum ib_qp_type type)
595 {
596         switch (type) {
597         case IB_QPT_RC:         return MLX4_QP_ST_RC;
598         case IB_QPT_UC:         return MLX4_QP_ST_UC;
599         case IB_QPT_UD:         return MLX4_QP_ST_UD;
600         case IB_QPT_SMI:
601         case IB_QPT_GSI:        return MLX4_QP_ST_MLX;
602         default:                return -1;
603         }
604 }
605
606 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
607                                    int attr_mask)
608 {
609         u8 dest_rd_atomic;
610         u32 access_flags;
611         u32 hw_access_flags = 0;
612
613         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
614                 dest_rd_atomic = attr->max_dest_rd_atomic;
615         else
616                 dest_rd_atomic = qp->resp_depth;
617
618         if (attr_mask & IB_QP_ACCESS_FLAGS)
619                 access_flags = attr->qp_access_flags;
620         else
621                 access_flags = qp->atomic_rd_en;
622
623         if (!dest_rd_atomic)
624                 access_flags &= IB_ACCESS_REMOTE_WRITE;
625
626         if (access_flags & IB_ACCESS_REMOTE_READ)
627                 hw_access_flags |= MLX4_QP_BIT_RRE;
628         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
629                 hw_access_flags |= MLX4_QP_BIT_RAE;
630         if (access_flags & IB_ACCESS_REMOTE_WRITE)
631                 hw_access_flags |= MLX4_QP_BIT_RWE;
632
633         return cpu_to_be32(hw_access_flags);
634 }
635
636 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
637                             int attr_mask)
638 {
639         if (attr_mask & IB_QP_PKEY_INDEX)
640                 sqp->pkey_index = attr->pkey_index;
641         if (attr_mask & IB_QP_QKEY)
642                 sqp->qkey = attr->qkey;
643         if (attr_mask & IB_QP_SQ_PSN)
644                 sqp->send_psn = attr->sq_psn;
645 }
646
647 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
648 {
649         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
650 }
651
652 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
653                          struct mlx4_qp_path *path, u8 port)
654 {
655         path->grh_mylmc     = ah->src_path_bits & 0x7f;
656         path->rlid          = cpu_to_be16(ah->dlid);
657         if (ah->static_rate) {
658                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
659                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
660                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
661                         --path->static_rate;
662         } else
663                 path->static_rate = 0;
664         path->counter_index = 0xff;
665
666         if (ah->ah_flags & IB_AH_GRH) {
667                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len) {
668                         printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
669                                ah->grh.sgid_index, dev->dev->caps.gid_table_len - 1);
670                         return -1;
671                 }
672
673                 path->grh_mylmc |= 1 << 7;
674                 path->mgid_index = ah->grh.sgid_index;
675                 path->hop_limit  = ah->grh.hop_limit;
676                 path->tclass_flowlabel =
677                         cpu_to_be32((ah->grh.traffic_class << 20) |
678                                     (ah->grh.flow_label));
679                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
680         }
681
682         path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
683                 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
684
685         return 0;
686 }
687
688 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
689                                const struct ib_qp_attr *attr, int attr_mask,
690                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
691 {
692         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
693         struct mlx4_ib_qp *qp = to_mqp(ibqp);
694         struct mlx4_qp_context *context;
695         enum mlx4_qp_optpar optpar = 0;
696         int sqd_event;
697         int err = -EINVAL;
698
699         context = kzalloc(sizeof *context, GFP_KERNEL);
700         if (!context)
701                 return -ENOMEM;
702
703         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
704                                      (to_mlx4_st(ibqp->qp_type) << 16));
705         context->flags     |= cpu_to_be32(1 << 8); /* DE? */
706
707         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
708                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
709         else {
710                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
711                 switch (attr->path_mig_state) {
712                 case IB_MIG_MIGRATED:
713                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
714                         break;
715                 case IB_MIG_REARM:
716                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
717                         break;
718                 case IB_MIG_ARMED:
719                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
720                         break;
721                 }
722         }
723
724         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
725             ibqp->qp_type == IB_QPT_UD)
726                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
727         else if (attr_mask & IB_QP_PATH_MTU) {
728                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
729                         printk(KERN_ERR "path MTU (%u) is invalid\n",
730                                attr->path_mtu);
731                         return -EINVAL;
732                 }
733                 context->mtu_msgmax = (attr->path_mtu << 5) | 31;
734         }
735
736         if (qp->rq.max)
737                 context->rq_size_stride = ilog2(qp->rq.max) << 3;
738         context->rq_size_stride |= qp->rq.wqe_shift - 4;
739
740         if (qp->sq.max)
741                 context->sq_size_stride = ilog2(qp->sq.max) << 3;
742         context->sq_size_stride |= qp->sq.wqe_shift - 4;
743
744         if (qp->ibqp.uobject)
745                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
746         else
747                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
748
749         if (attr_mask & IB_QP_DEST_QPN)
750                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
751
752         if (attr_mask & IB_QP_PORT) {
753                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
754                     !(attr_mask & IB_QP_AV)) {
755                         mlx4_set_sched(&context->pri_path, attr->port_num);
756                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
757                 }
758         }
759
760         if (attr_mask & IB_QP_PKEY_INDEX) {
761                 context->pri_path.pkey_index = attr->pkey_index;
762                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
763         }
764
765         if (attr_mask & IB_QP_RNR_RETRY) {
766                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
767                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
768         }
769
770         if (attr_mask & IB_QP_AV) {
771                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
772                                   attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) {
773                         err = -EINVAL;
774                         goto out;
775                 }
776
777                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
778                            MLX4_QP_OPTPAR_SCHED_QUEUE);
779         }
780
781         if (attr_mask & IB_QP_TIMEOUT) {
782                 context->pri_path.ackto = attr->timeout << 3;
783                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
784         }
785
786         if (attr_mask & IB_QP_ALT_PATH) {
787                 if (attr->alt_pkey_index >= dev->dev->caps.pkey_table_len)
788                         return -EINVAL;
789
790                 if (attr->alt_port_num == 0 ||
791                     attr->alt_port_num > dev->dev->caps.num_ports)
792                         return -EINVAL;
793
794                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
795                                   attr->alt_port_num))
796                         return -EINVAL;
797
798                 context->alt_path.pkey_index = attr->alt_pkey_index;
799                 context->alt_path.ackto = attr->alt_timeout << 3;
800                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
801         }
802
803         context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
804         context->params1    = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
805         if (attr_mask & IB_QP_RETRY_CNT) {
806                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
807                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
808         }
809
810         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
811                 if (attr->max_rd_atomic)
812                         context->params1 |=
813                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
814                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
815         }
816
817         if (attr_mask & IB_QP_SQ_PSN)
818                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
819
820         context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
821
822         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
823                 if (attr->max_dest_rd_atomic)
824                         context->params2 |=
825                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
826                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
827         }
828
829         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
830                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
831                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
832         }
833
834         if (ibqp->srq)
835                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
836
837         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
838                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
839                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
840         }
841         if (attr_mask & IB_QP_RQ_PSN)
842                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
843
844         context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
845
846         if (attr_mask & IB_QP_QKEY) {
847                 context->qkey = cpu_to_be32(attr->qkey);
848                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
849         }
850
851         if (ibqp->srq)
852                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
853
854         if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
855                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
856
857         if (cur_state == IB_QPS_INIT &&
858             new_state == IB_QPS_RTR  &&
859             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
860              ibqp->qp_type == IB_QPT_UD)) {
861                 context->pri_path.sched_queue = (qp->port - 1) << 6;
862                 if (is_qp0(dev, qp))
863                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
864                 else
865                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
866         }
867
868         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
869             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
870                 sqd_event = 1;
871         else
872                 sqd_event = 0;
873
874         /*
875          * Before passing a kernel QP to the HW, make sure that the
876          * ownership bits of the send queue are set so that the
877          * hardware doesn't start processing stale work requests.
878          */
879         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
880                 struct mlx4_wqe_ctrl_seg *ctrl;
881                 int i;
882
883                 for (i = 0; i < qp->sq.max; ++i) {
884                         ctrl = get_send_wqe(qp, i);
885                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
886                 }
887         }
888
889         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
890                              to_mlx4_state(new_state), context, optpar,
891                              sqd_event, &qp->mqp);
892         if (err)
893                 goto out;
894
895         qp->state = new_state;
896
897         if (attr_mask & IB_QP_ACCESS_FLAGS)
898                 qp->atomic_rd_en = attr->qp_access_flags;
899         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
900                 qp->resp_depth = attr->max_dest_rd_atomic;
901         if (attr_mask & IB_QP_PORT)
902                 qp->port = attr->port_num;
903         if (attr_mask & IB_QP_ALT_PATH)
904                 qp->alt_port = attr->alt_port_num;
905
906         if (is_sqp(dev, qp))
907                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
908
909         /*
910          * If we moved QP0 to RTR, bring the IB link up; if we moved
911          * QP0 to RESET or ERROR, bring the link back down.
912          */
913         if (is_qp0(dev, qp)) {
914                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
915                         init_port(dev, qp->port);
916
917                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
918                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
919                         mlx4_CLOSE_PORT(dev->dev, qp->port);
920         }
921
922         /*
923          * If we moved a kernel QP to RESET, clean up all old CQ
924          * entries and reinitialize the QP.
925          */
926         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
927                 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
928                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
929                 if (ibqp->send_cq != ibqp->recv_cq)
930                         mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
931
932                 qp->rq.head = 0;
933                 qp->rq.tail = 0;
934                 qp->sq.head = 0;
935                 qp->sq.tail = 0;
936                 if (!ibqp->srq)
937                         *qp->db.db  = 0;
938         }
939
940 out:
941         kfree(context);
942         return err;
943 }
944
945 static const struct ib_qp_attr mlx4_ib_qp_attr = { .port_num = 1 };
946 static const int mlx4_ib_qp_attr_mask_table[IB_QPT_UD + 1] = {
947                 [IB_QPT_UD]  = (IB_QP_PKEY_INDEX                |
948                                 IB_QP_PORT                      |
949                                 IB_QP_QKEY),
950                 [IB_QPT_UC]  = (IB_QP_PKEY_INDEX                |
951                                 IB_QP_PORT                      |
952                                 IB_QP_ACCESS_FLAGS),
953                 [IB_QPT_RC]  = (IB_QP_PKEY_INDEX                |
954                                 IB_QP_PORT                      |
955                                 IB_QP_ACCESS_FLAGS),
956                 [IB_QPT_SMI] = (IB_QP_PKEY_INDEX                |
957                                 IB_QP_QKEY),
958                 [IB_QPT_GSI] = (IB_QP_PKEY_INDEX                |
959                                 IB_QP_QKEY),
960 };
961
962 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
963                       int attr_mask, struct ib_udata *udata)
964 {
965         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
966         struct mlx4_ib_qp *qp = to_mqp(ibqp);
967         enum ib_qp_state cur_state, new_state;
968         int err = -EINVAL;
969
970         mutex_lock(&qp->mutex);
971
972         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
973         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
974
975         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
976                 goto out;
977
978         if ((attr_mask & IB_QP_PKEY_INDEX) &&
979              attr->pkey_index >= dev->dev->caps.pkey_table_len) {
980                 goto out;
981         }
982
983         if ((attr_mask & IB_QP_PORT) &&
984             (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
985                 goto out;
986         }
987
988         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
989             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
990                 goto out;
991         }
992
993         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
994             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
995                 goto out;
996         }
997
998         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
999                 err = 0;
1000                 goto out;
1001         }
1002
1003         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_ERR) {
1004                 err = __mlx4_ib_modify_qp(ibqp, &mlx4_ib_qp_attr,
1005                                           mlx4_ib_qp_attr_mask_table[ibqp->qp_type],
1006                                           IB_QPS_RESET, IB_QPS_INIT);
1007                 if (err)
1008                         goto out;
1009                 cur_state = IB_QPS_INIT;
1010         }
1011
1012         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1013
1014 out:
1015         mutex_unlock(&qp->mutex);
1016         return err;
1017 }
1018
1019 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1020                             void *wqe)
1021 {
1022         struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1023         struct mlx4_wqe_mlx_seg *mlx = wqe;
1024         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1025         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1026         u16 pkey;
1027         int send_size;
1028         int header_size;
1029         int i;
1030
1031         send_size = 0;
1032         for (i = 0; i < wr->num_sge; ++i)
1033                 send_size += wr->sg_list[i].length;
1034
1035         ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1036
1037         sqp->ud_header.lrh.service_level   =
1038                 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1039         sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1040         sqp->ud_header.lrh.source_lid      = cpu_to_be16(ah->av.g_slid & 0x7f);
1041         if (mlx4_ib_ah_grh_present(ah)) {
1042                 sqp->ud_header.grh.traffic_class =
1043                         (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1044                 sqp->ud_header.grh.flow_label    =
1045                         ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1046                 sqp->ud_header.grh.hop_limit     = ah->av.hop_limit;
1047                 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1048                                   ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1049                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1050                        ah->av.dgid, 16);
1051         }
1052
1053         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1054         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1055                                   (sqp->ud_header.lrh.destination_lid ==
1056                                    IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1057                                   (sqp->ud_header.lrh.service_level << 8));
1058         mlx->rlid   = sqp->ud_header.lrh.destination_lid;
1059
1060         switch (wr->opcode) {
1061         case IB_WR_SEND:
1062                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1063                 sqp->ud_header.immediate_present = 0;
1064                 break;
1065         case IB_WR_SEND_WITH_IMM:
1066                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1067                 sqp->ud_header.immediate_present = 1;
1068                 sqp->ud_header.immediate_data    = wr->imm_data;
1069                 break;
1070         default:
1071                 return -EINVAL;
1072         }
1073
1074         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1075         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1076                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1077         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1078         if (!sqp->qp.ibqp.qp_num)
1079                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1080         else
1081                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1082         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1083         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1084         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1085         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1086                                                sqp->qkey : wr->wr.ud.remote_qkey);
1087         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1088
1089         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1090
1091         if (0) {
1092                 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1093                 for (i = 0; i < header_size / 4; ++i) {
1094                         if (i % 8 == 0)
1095                                 printk("  [%02x] ", i * 4);
1096                         printk(" %08x",
1097                                be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1098                         if ((i + 1) % 8 == 0)
1099                                 printk("\n");
1100                 }
1101                 printk("\n");
1102         }
1103
1104         inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1105         memcpy(inl + 1, sqp->header_buf, header_size);
1106
1107         return ALIGN(sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1108 }
1109
1110 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1111 {
1112         unsigned cur;
1113         struct mlx4_ib_cq *cq;
1114
1115         cur = wq->head - wq->tail;
1116         if (likely(cur + nreq < wq->max))
1117                 return 0;
1118
1119         cq = to_mcq(ib_cq);
1120         spin_lock(&cq->lock);
1121         cur = wq->head - wq->tail;
1122         spin_unlock(&cq->lock);
1123
1124         return cur + nreq >= wq->max;
1125 }
1126
1127 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1128                       struct ib_send_wr **bad_wr)
1129 {
1130         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1131         void *wqe;
1132         struct mlx4_wqe_ctrl_seg *ctrl;
1133         unsigned long flags;
1134         int nreq;
1135         int err = 0;
1136         int ind;
1137         int size;
1138         int i;
1139
1140         spin_lock_irqsave(&qp->rq.lock, flags);
1141
1142         ind = qp->sq.head;
1143
1144         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1145                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1146                         err = -ENOMEM;
1147                         *bad_wr = wr;
1148                         goto out;
1149                 }
1150
1151                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1152                         err = -EINVAL;
1153                         *bad_wr = wr;
1154                         goto out;
1155                 }
1156
1157                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.max - 1));
1158                 qp->sq.wrid[ind & (qp->sq.max - 1)] = wr->wr_id;
1159
1160                 ctrl->srcrb_flags =
1161                         (wr->send_flags & IB_SEND_SIGNALED ?
1162                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1163                         (wr->send_flags & IB_SEND_SOLICITED ?
1164                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1165                         qp->sq_signal_bits;
1166
1167                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1168                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1169                         ctrl->imm = wr->imm_data;
1170                 else
1171                         ctrl->imm = 0;
1172
1173                 wqe += sizeof *ctrl;
1174                 size = sizeof *ctrl / 16;
1175
1176                 switch (ibqp->qp_type) {
1177                 case IB_QPT_RC:
1178                 case IB_QPT_UC:
1179                         switch (wr->opcode) {
1180                         case IB_WR_ATOMIC_CMP_AND_SWP:
1181                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1182                                 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1183                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1184                                 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1185                                         cpu_to_be32(wr->wr.atomic.rkey);
1186                                 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1187
1188                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1189
1190                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1191                                         ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1192                                                 cpu_to_be64(wr->wr.atomic.swap);
1193                                         ((struct mlx4_wqe_atomic_seg *) wqe)->compare =
1194                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1195                                 } else {
1196                                         ((struct mlx4_wqe_atomic_seg *) wqe)->swap_add =
1197                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1198                                         ((struct mlx4_wqe_atomic_seg *) wqe)->compare = 0;
1199                                 }
1200
1201                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
1202                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1203                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1204
1205                                 break;
1206
1207                         case IB_WR_RDMA_READ:
1208                         case IB_WR_RDMA_WRITE:
1209                         case IB_WR_RDMA_WRITE_WITH_IMM:
1210                                 ((struct mlx4_wqe_raddr_seg *) wqe)->raddr =
1211                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1212                                 ((struct mlx4_wqe_raddr_seg *) wqe)->rkey =
1213                                         cpu_to_be32(wr->wr.rdma.rkey);
1214                                 ((struct mlx4_wqe_raddr_seg *) wqe)->reserved = 0;
1215
1216                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
1217                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1218
1219                                 break;
1220
1221                         default:
1222                                 /* No extra segments required for sends */
1223                                 break;
1224                         }
1225                         break;
1226
1227                 case IB_QPT_UD:
1228                         memcpy(((struct mlx4_wqe_datagram_seg *) wqe)->av,
1229                                &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1230                         ((struct mlx4_wqe_datagram_seg *) wqe)->dqpn =
1231                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1232                         ((struct mlx4_wqe_datagram_seg *) wqe)->qkey =
1233                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1234
1235                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
1236                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1237                         break;
1238
1239                 case IB_QPT_SMI:
1240                 case IB_QPT_GSI:
1241                         err = build_mlx_header(to_msqp(qp), wr, ctrl);
1242                         if (err < 0) {
1243                                 *bad_wr = wr;
1244                                 goto out;
1245                         }
1246                         wqe  += err;
1247                         size += err / 16;
1248
1249                         err = 0;
1250                         break;
1251
1252                 default:
1253                         break;
1254                 }
1255
1256                 for (i = 0; i < wr->num_sge; ++i) {
1257                         ((struct mlx4_wqe_data_seg *) wqe)->byte_count =
1258                                 cpu_to_be32(wr->sg_list[i].length);
1259                         ((struct mlx4_wqe_data_seg *) wqe)->lkey =
1260                                 cpu_to_be32(wr->sg_list[i].lkey);
1261                         ((struct mlx4_wqe_data_seg *) wqe)->addr =
1262                                 cpu_to_be64(wr->sg_list[i].addr);
1263
1264                         wqe  += sizeof (struct mlx4_wqe_data_seg);
1265                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1266                 }
1267
1268                 /* Add one more inline data segment for ICRC for MLX sends */
1269                 if (qp->ibqp.qp_type == IB_QPT_SMI || qp->ibqp.qp_type == IB_QPT_GSI) {
1270                         ((struct mlx4_wqe_inline_seg *) wqe)->byte_count =
1271                                 cpu_to_be32((1 << 31) | 4);
1272                         ((u32 *) wqe)[1] = 0;
1273                         wqe  += sizeof (struct mlx4_wqe_data_seg);
1274                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
1275                 }
1276
1277                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1278                                     MLX4_WQE_CTRL_FENCE : 0) | size;
1279
1280                 /*
1281                  * Make sure descriptor is fully written before
1282                  * setting ownership bit (because HW can start
1283                  * executing as soon as we do).
1284                  */
1285                 wmb();
1286
1287                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1288                         err = -EINVAL;
1289                         goto out;
1290                 }
1291
1292                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1293                         (ind & qp->sq.max ? cpu_to_be32(1 << 31) : 0);
1294
1295                 ++ind;
1296         }
1297
1298 out:
1299         if (likely(nreq)) {
1300                 qp->sq.head += nreq;
1301
1302                 /*
1303                  * Make sure that descriptors are written before
1304                  * doorbell record.
1305                  */
1306                 wmb();
1307
1308                 writel(qp->doorbell_qpn,
1309                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1310
1311                 /*
1312                  * Make sure doorbells don't leak out of SQ spinlock
1313                  * and reach the HCA out of order.
1314                  */
1315                 mmiowb();
1316         }
1317
1318         spin_unlock_irqrestore(&qp->rq.lock, flags);
1319
1320         return err;
1321 }
1322
1323 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1324                       struct ib_recv_wr **bad_wr)
1325 {
1326         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1327         struct mlx4_wqe_data_seg *scat;
1328         unsigned long flags;
1329         int err = 0;
1330         int nreq;
1331         int ind;
1332         int i;
1333
1334         spin_lock_irqsave(&qp->rq.lock, flags);
1335
1336         ind = qp->rq.head & (qp->rq.max - 1);
1337
1338         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1339                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1340                         err = -ENOMEM;
1341                         *bad_wr = wr;
1342                         goto out;
1343                 }
1344
1345                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1346                         err = -EINVAL;
1347                         *bad_wr = wr;
1348                         goto out;
1349                 }
1350
1351                 scat = get_recv_wqe(qp, ind);
1352
1353                 for (i = 0; i < wr->num_sge; ++i) {
1354                         scat[i].byte_count = cpu_to_be32(wr->sg_list[i].length);
1355                         scat[i].lkey       = cpu_to_be32(wr->sg_list[i].lkey);
1356                         scat[i].addr       = cpu_to_be64(wr->sg_list[i].addr);
1357                 }
1358
1359                 if (i < qp->rq.max_gs) {
1360                         scat[i].byte_count = 0;
1361                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
1362                         scat[i].addr       = 0;
1363                 }
1364
1365                 qp->rq.wrid[ind] = wr->wr_id;
1366
1367                 ind = (ind + 1) & (qp->rq.max - 1);
1368         }
1369
1370 out:
1371         if (likely(nreq)) {
1372                 qp->rq.head += nreq;
1373
1374                 /*
1375                  * Make sure that descriptors are written before
1376                  * doorbell record.
1377                  */
1378                 wmb();
1379
1380                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1381         }
1382
1383         spin_unlock_irqrestore(&qp->rq.lock, flags);
1384
1385         return err;
1386 }