2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include "t4_values.h"
38 #include "t4fw_ri_api.h"
40 #define T4_MAX_NUM_PD 65536
41 #define T4_MAX_MR_SIZE (~0ULL)
42 #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
43 #define T4_STAG_UNSET 0xffffffff
45 #define PCIE_MA_SYNC_A 0x30b4
47 struct t4_status_page {
48 __be32 rsvd1; /* flit 0 - hw owns */
53 u8 qp_err; /* flit 1 - sw owns */
61 #define T4_EQ_ENTRY_SIZE 64
63 #define T4_SQ_NUM_SLOTS 5
64 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
65 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
66 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
67 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
68 sizeof(struct fw_ri_immd)))
69 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
70 sizeof(struct fw_ri_rdma_write_wr) - \
71 sizeof(struct fw_ri_immd)))
72 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
73 sizeof(struct fw_ri_rdma_write_wr) - \
74 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
75 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
76 sizeof(struct fw_ri_immd)) & ~31UL)
77 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
78 #define T4_MAX_FR_DSGL 1024
79 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
81 static inline int t4_max_fr_depth(int use_dsgl)
83 return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
86 #define T4_RQ_NUM_SLOTS 2
87 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
88 #define T4_MAX_RECV_SGE 4
91 struct fw_ri_res_wr res;
93 struct fw_ri_rdma_write_wr write;
94 struct fw_ri_send_wr send;
95 struct fw_ri_rdma_read_wr read;
96 struct fw_ri_bind_mw_wr bind;
97 struct fw_ri_fr_nsmr_wr fr;
98 struct fw_ri_fr_nsmr_tpte_wr fr_tpte;
99 struct fw_ri_inv_lstag_wr inv;
100 struct t4_status_page status;
101 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
105 struct fw_ri_recv_wr recv;
106 struct t4_status_page status;
107 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
110 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
111 enum fw_wr_opcodes opcode, u8 flags, u8 len16)
113 wqe->send.opcode = (u8)opcode;
114 wqe->send.flags = flags;
115 wqe->send.wrid = wrid;
119 wqe->send.len16 = len16;
122 /* CQE/AE status codes */
123 #define T4_ERR_SUCCESS 0x0
124 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */
125 /* STAG is offlimt, being 0, */
126 /* or STAG_key mismatch */
127 #define T4_ERR_PDID 0x2 /* PDID mismatch */
128 #define T4_ERR_QPID 0x3 /* QPID mismatch */
129 #define T4_ERR_ACCESS 0x4 /* Invalid access right */
130 #define T4_ERR_WRAP 0x5 /* Wrap error */
131 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */
132 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
133 /* shared memory region */
134 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
135 /* shared memory region */
136 #define T4_ERR_ECC 0x9 /* ECC error detected */
137 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
138 /* reading PSTAG for a MW */
140 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
142 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
143 #define T4_ERR_CRC 0x10 /* CRC error */
144 #define T4_ERR_MARKER 0x11 /* Marker error */
145 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
146 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
147 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
148 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
149 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
150 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
151 #define T4_ERR_MSN 0x18 /* MSN error */
152 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
153 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
155 #define T4_ERR_MSN_GAP 0x1B
156 #define T4_ERR_MSN_RANGE 0x1C
157 #define T4_ERR_IRD_OVERFLOW 0x1D
158 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
160 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
188 /* macros for flit 0 of the cqe */
190 #define CQE_QPID_S 12
191 #define CQE_QPID_M 0xFFFFF
192 #define CQE_QPID_G(x) ((((x) >> CQE_QPID_S)) & CQE_QPID_M)
193 #define CQE_QPID_V(x) ((x)<<CQE_QPID_S)
195 #define CQE_SWCQE_S 11
196 #define CQE_SWCQE_M 0x1
197 #define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M)
198 #define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S)
200 #define CQE_DRAIN_S 10
201 #define CQE_DRAIN_M 0x1
202 #define CQE_DRAIN_G(x) ((((x) >> CQE_DRAIN_S)) & CQE_DRAIN_M)
203 #define CQE_DRAIN_V(x) ((x)<<CQE_DRAIN_S)
205 #define CQE_STATUS_S 5
206 #define CQE_STATUS_M 0x1F
207 #define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M)
208 #define CQE_STATUS_V(x) ((x)<<CQE_STATUS_S)
211 #define CQE_TYPE_M 0x1
212 #define CQE_TYPE_G(x) ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M)
213 #define CQE_TYPE_V(x) ((x)<<CQE_TYPE_S)
215 #define CQE_OPCODE_S 0
216 #define CQE_OPCODE_M 0xF
217 #define CQE_OPCODE_G(x) ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M)
218 #define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S)
220 #define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header)))
221 #define DRAIN_CQE(x) (CQE_DRAIN_G(be32_to_cpu((x)->header)))
222 #define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header)))
223 #define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header)))
224 #define SQ_TYPE(x) (CQE_TYPE((x)))
225 #define RQ_TYPE(x) (!CQE_TYPE((x)))
226 #define CQE_STATUS(x) (CQE_STATUS_G(be32_to_cpu((x)->header)))
227 #define CQE_OPCODE(x) (CQE_OPCODE_G(be32_to_cpu((x)->header)))
229 #define CQE_SEND_OPCODE(x)( \
230 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
231 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
232 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
233 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
235 #define CQE_LEN(x) (be32_to_cpu((x)->len))
237 /* used for RQ completion processing */
238 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
239 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
241 /* used for SQ completion processing */
242 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
243 #define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag))
245 /* generic accessor macros */
246 #define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi))
247 #define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low))
248 #define CQE_DRAIN_COOKIE(x) ((x)->u.drain_cookie)
250 /* macros for flit 3 of the cqe */
251 #define CQE_GENBIT_S 63
252 #define CQE_GENBIT_M 0x1
253 #define CQE_GENBIT_G(x) (((x) >> CQE_GENBIT_S) & CQE_GENBIT_M)
254 #define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S)
256 #define CQE_OVFBIT_S 62
257 #define CQE_OVFBIT_M 0x1
258 #define CQE_OVFBIT_G(x) ((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M)
260 #define CQE_IQTYPE_S 60
261 #define CQE_IQTYPE_M 0x3
262 #define CQE_IQTYPE_G(x) ((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M)
264 #define CQE_TS_M 0x0fffffffffffffffULL
265 #define CQE_TS_G(x) ((x) & CQE_TS_M)
267 #define CQE_OVFBIT(x) ((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts)))
268 #define CQE_GENBIT(x) ((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts)))
269 #define CQE_TS(x) (CQE_TS_G(be64_to_cpu((x)->bits_type_ts)))
280 struct timespec host_ts;
284 static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
286 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
287 return pgprot_writecombine(prot);
289 return pgprot_noncached(prot);
294 T4_SQ_ONCHIP = (1<<0),
300 DEFINE_DMA_UNMAP_ADDR(mapping);
301 unsigned long phys_addr;
302 struct t4_swsqe *sw_sq;
303 struct t4_swsqe *oldest_read;
304 void __iomem *bar2_va;
321 struct timespec host_ts;
326 union t4_recv_wr *queue;
328 DEFINE_DMA_UNMAP_ADDR(mapping);
329 struct t4_swrqe *sw_rq;
330 void __iomem *bar2_va;
350 struct c4iw_rdev *rdev;
354 static inline int t4_rqes_posted(struct t4_wq *wq)
356 return wq->rq.in_use;
359 static inline int t4_rq_empty(struct t4_wq *wq)
361 return wq->rq.in_use == 0;
364 static inline int t4_rq_full(struct t4_wq *wq)
366 return wq->rq.in_use == (wq->rq.size - 1);
369 static inline u32 t4_rq_avail(struct t4_wq *wq)
371 return wq->rq.size - 1 - wq->rq.in_use;
374 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
377 if (++wq->rq.pidx == wq->rq.size)
379 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
380 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
381 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
384 static inline void t4_rq_consume(struct t4_wq *wq)
388 if (++wq->rq.cidx == wq->rq.size)
392 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
394 return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
397 static inline u16 t4_rq_wq_size(struct t4_wq *wq)
399 return wq->rq.size * T4_RQ_NUM_SLOTS;
402 static inline int t4_sq_onchip(struct t4_sq *sq)
404 return sq->flags & T4_SQ_ONCHIP;
407 static inline int t4_sq_empty(struct t4_wq *wq)
409 return wq->sq.in_use == 0;
412 static inline int t4_sq_full(struct t4_wq *wq)
414 return wq->sq.in_use == (wq->sq.size - 1);
417 static inline u32 t4_sq_avail(struct t4_wq *wq)
419 return wq->sq.size - 1 - wq->sq.in_use;
422 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
425 if (++wq->sq.pidx == wq->sq.size)
427 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
428 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
429 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
432 static inline void t4_sq_consume(struct t4_wq *wq)
434 if (wq->sq.cidx == wq->sq.flush_cidx)
435 wq->sq.flush_cidx = -1;
437 if (++wq->sq.cidx == wq->sq.size)
441 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
443 return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
446 static inline u16 t4_sq_wq_size(struct t4_wq *wq)
448 return wq->sq.size * T4_SQ_NUM_SLOTS;
451 /* This function copies 64 byte coalesced work request to memory
452 * mapped BAR2 space. For coalesced WRs, the SGE fetches data
453 * from the FIFO instead of from Host.
455 static inline void pio_copy(u64 __iomem *dst, u64 *src)
467 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe)
470 /* Flush host queue memory writes. */
472 if (wq->sq.bar2_va) {
473 if (inc == 1 && wq->sq.bar2_qid == 0 && wqe) {
474 pr_debug("WC wq->sq.pidx = %d\n", wq->sq.pidx);
475 pio_copy((u64 __iomem *)
476 (wq->sq.bar2_va + SGE_UDB_WCDOORBELL),
479 pr_debug("DB wq->sq.pidx = %d\n", wq->sq.pidx);
480 writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid),
481 wq->sq.bar2_va + SGE_UDB_KDOORBELL);
484 /* Flush user doorbell area writes. */
488 writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db);
491 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc,
492 union t4_recv_wr *wqe)
495 /* Flush host queue memory writes. */
497 if (wq->rq.bar2_va) {
498 if (inc == 1 && wq->rq.bar2_qid == 0 && wqe) {
499 pr_debug("WC wq->rq.pidx = %d\n", wq->rq.pidx);
500 pio_copy((u64 __iomem *)
501 (wq->rq.bar2_va + SGE_UDB_WCDOORBELL),
504 pr_debug("DB wq->rq.pidx = %d\n", wq->rq.pidx);
505 writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid),
506 wq->rq.bar2_va + SGE_UDB_KDOORBELL);
509 /* Flush user doorbell area writes. */
513 writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db);
516 static inline int t4_wq_in_error(struct t4_wq *wq)
518 return wq->rq.queue[wq->rq.size].status.qp_err;
521 static inline void t4_set_wq_in_error(struct t4_wq *wq)
523 wq->rq.queue[wq->rq.size].status.qp_err = 1;
526 static inline void t4_disable_wq_db(struct t4_wq *wq)
528 wq->rq.queue[wq->rq.size].status.db_off = 1;
531 static inline void t4_enable_wq_db(struct t4_wq *wq)
533 wq->rq.queue[wq->rq.size].status.db_off = 0;
536 static inline int t4_wq_db_enabled(struct t4_wq *wq)
538 return !wq->rq.queue[wq->rq.size].status.db_off;
546 struct t4_cqe *queue;
548 DEFINE_DMA_UNMAP_ADDR(mapping);
549 struct t4_cqe *sw_queue;
551 void __iomem *bar2_va;
554 struct c4iw_rdev *rdev;
560 u16 size; /* including status page */
571 static inline void write_gts(struct t4_cq *cq, u32 val)
574 writel(val | INGRESSQID_V(cq->bar2_qid),
575 cq->bar2_va + SGE_UDB_GTS);
577 writel(val | INGRESSQID_V(cq->cqid), cq->gts);
580 static inline int t4_clear_cq_armed(struct t4_cq *cq)
582 return test_and_clear_bit(CQ_ARMED, &cq->flags);
585 static inline int t4_arm_cq(struct t4_cq *cq, int se)
589 set_bit(CQ_ARMED, &cq->flags);
590 while (cq->cidx_inc > CIDXINC_M) {
591 val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7);
593 cq->cidx_inc -= CIDXINC_M;
595 val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6);
601 static inline void t4_swcq_produce(struct t4_cq *cq)
604 if (cq->sw_in_use == cq->size) {
605 pr_warn("%s cxgb4 sw cq overflow cqid %u\n",
611 if (++cq->sw_pidx == cq->size)
615 static inline void t4_swcq_consume(struct t4_cq *cq)
618 if (++cq->sw_cidx == cq->size)
622 static inline void t4_hwcq_consume(struct t4_cq *cq)
624 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
625 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) {
628 val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7);
632 if (++cq->cidx == cq->size) {
638 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
640 return (CQE_GENBIT(cqe) == cq->gen);
643 static inline int t4_cq_notempty(struct t4_cq *cq)
645 return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]);
648 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
654 prev_cidx = cq->size - 1;
656 prev_cidx = cq->cidx - 1;
658 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
661 pr_err("cq overflow cqid %u\n", cq->cqid);
662 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
664 /* Ensure CQE is flushed to memory */
666 *cqe = &cq->queue[cq->cidx];
673 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
675 if (cq->sw_in_use == cq->size) {
676 pr_warn("%s cxgb4 sw cq overflow cqid %u\n",
682 return &cq->sw_queue[cq->sw_cidx];
686 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
692 else if (cq->sw_in_use)
693 *cqe = &cq->sw_queue[cq->sw_cidx];
695 ret = t4_next_hw_cqe(cq, cqe);
699 static inline int t4_cq_in_error(struct t4_cq *cq)
701 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
704 static inline void t4_set_cq_in_error(struct t4_cq *cq)
706 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
710 struct t4_dev_status_page {