Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland...
[sfrench/cifs-2.6.git] / drivers / infiniband / hw / cxgb4 / qp.c
1 /*
2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #include "iw_cxgb4.h"
33
34 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
35                       struct c4iw_dev_ucontext *uctx)
36 {
37         /*
38          * uP clears EQ contexts when the connection exits rdma mode,
39          * so no need to post a RESET WR for these EQs.
40          */
41         dma_free_coherent(&(rdev->lldi.pdev->dev),
42                           wq->rq.memsize, wq->rq.queue,
43                           dma_unmap_addr(&wq->rq, mapping));
44         dma_free_coherent(&(rdev->lldi.pdev->dev),
45                           wq->sq.memsize, wq->sq.queue,
46                           dma_unmap_addr(&wq->sq, mapping));
47         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
48         kfree(wq->rq.sw_rq);
49         kfree(wq->sq.sw_sq);
50         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
51         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
52         return 0;
53 }
54
55 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
56                      struct t4_cq *rcq, struct t4_cq *scq,
57                      struct c4iw_dev_ucontext *uctx)
58 {
59         int user = (uctx != &rdev->uctx);
60         struct fw_ri_res_wr *res_wr;
61         struct fw_ri_res *res;
62         int wr_len;
63         struct c4iw_wr_wait wr_wait;
64         struct sk_buff *skb;
65         int ret;
66         int eqsize;
67
68         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
69         if (!wq->sq.qid)
70                 return -ENOMEM;
71
72         wq->rq.qid = c4iw_get_qpid(rdev, uctx);
73         if (!wq->rq.qid)
74                 goto err1;
75
76         if (!user) {
77                 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
78                                  GFP_KERNEL);
79                 if (!wq->sq.sw_sq)
80                         goto err2;
81
82                 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
83                                  GFP_KERNEL);
84                 if (!wq->rq.sw_rq)
85                         goto err3;
86         }
87
88         /*
89          * RQT must be a power of 2.
90          */
91         wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
92         wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
93         if (!wq->rq.rqt_hwaddr)
94                 goto err4;
95
96         wq->sq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
97                                           wq->sq.memsize, &(wq->sq.dma_addr),
98                                           GFP_KERNEL);
99         if (!wq->sq.queue)
100                 goto err5;
101         memset(wq->sq.queue, 0, wq->sq.memsize);
102         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
103
104         wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
105                                           wq->rq.memsize, &(wq->rq.dma_addr),
106                                           GFP_KERNEL);
107         if (!wq->rq.queue)
108                 goto err6;
109         PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
110                 __func__, wq->sq.queue,
111                 (unsigned long long)virt_to_phys(wq->sq.queue),
112                 wq->rq.queue,
113                 (unsigned long long)virt_to_phys(wq->rq.queue));
114         memset(wq->rq.queue, 0, wq->rq.memsize);
115         dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
116
117         wq->db = rdev->lldi.db_reg;
118         wq->gts = rdev->lldi.gts_reg;
119         if (user) {
120                 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
121                                         (wq->sq.qid << rdev->qpshift);
122                 wq->sq.udb &= PAGE_MASK;
123                 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
124                                         (wq->rq.qid << rdev->qpshift);
125                 wq->rq.udb &= PAGE_MASK;
126         }
127         wq->rdev = rdev;
128         wq->rq.msn = 1;
129
130         /* build fw_ri_res_wr */
131         wr_len = sizeof *res_wr + 2 * sizeof *res;
132
133         skb = alloc_skb(wr_len, GFP_KERNEL);
134         if (!skb) {
135                 ret = -ENOMEM;
136                 goto err7;
137         }
138         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
139
140         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
141         memset(res_wr, 0, wr_len);
142         res_wr->op_nres = cpu_to_be32(
143                         FW_WR_OP(FW_RI_RES_WR) |
144                         V_FW_RI_RES_WR_NRES(2) |
145                         FW_WR_COMPL(1));
146         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
147         res_wr->cookie = (u64)&wr_wait;
148         res = res_wr->res;
149         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
150         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
151
152         /*
153          * eqsize is the number of 64B entries plus the status page size.
154          */
155         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
156
157         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
158                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
159                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
160                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
161                 V_FW_RI_RES_WR_IQID(scq->cqid));
162         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
163                 V_FW_RI_RES_WR_DCAEN(0) |
164                 V_FW_RI_RES_WR_DCACPU(0) |
165                 V_FW_RI_RES_WR_FBMIN(2) |
166                 V_FW_RI_RES_WR_FBMAX(3) |
167                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
168                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
169                 V_FW_RI_RES_WR_EQSIZE(eqsize));
170         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
171         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
172         res++;
173         res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
174         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
175
176         /*
177          * eqsize is the number of 64B entries plus the status page size.
178          */
179         eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
180         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
181                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
182                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
183                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
184                 V_FW_RI_RES_WR_IQID(rcq->cqid));
185         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
186                 V_FW_RI_RES_WR_DCAEN(0) |
187                 V_FW_RI_RES_WR_DCACPU(0) |
188                 V_FW_RI_RES_WR_FBMIN(2) |
189                 V_FW_RI_RES_WR_FBMAX(3) |
190                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
191                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
192                 V_FW_RI_RES_WR_EQSIZE(eqsize));
193         res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
194         res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
195
196         c4iw_init_wr_wait(&wr_wait);
197
198         ret = c4iw_ofld_send(rdev, skb);
199         if (ret)
200                 goto err7;
201         wait_event_timeout(wr_wait.wait, wr_wait.done, C4IW_WR_TO);
202         if (!wr_wait.done) {
203                 printk(KERN_ERR MOD "Device %s not responding!\n",
204                        pci_name(rdev->lldi.pdev));
205                 rdev->flags = T4_FATAL_ERROR;
206                 ret = -EIO;
207         } else
208                 ret = wr_wait.ret;
209         if (ret)
210                 goto err7;
211
212         PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
213              __func__, wq->sq.qid, wq->rq.qid, wq->db,
214              (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
215
216         return 0;
217 err7:
218         dma_free_coherent(&(rdev->lldi.pdev->dev),
219                           wq->rq.memsize, wq->rq.queue,
220                           dma_unmap_addr(&wq->rq, mapping));
221 err6:
222         dma_free_coherent(&(rdev->lldi.pdev->dev),
223                           wq->sq.memsize, wq->sq.queue,
224                           dma_unmap_addr(&wq->sq, mapping));
225 err5:
226         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
227 err4:
228         kfree(wq->rq.sw_rq);
229 err3:
230         kfree(wq->sq.sw_sq);
231 err2:
232         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
233 err1:
234         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
235         return -ENOMEM;
236 }
237
238 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
239                       struct ib_send_wr *wr, int max, u32 *plenp)
240 {
241         u8 *dstp, *srcp;
242         u32 plen = 0;
243         int i;
244         int rem, len;
245
246         dstp = (u8 *)immdp->data;
247         for (i = 0; i < wr->num_sge; i++) {
248                 if ((plen + wr->sg_list[i].length) > max)
249                         return -EMSGSIZE;
250                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
251                 plen += wr->sg_list[i].length;
252                 rem = wr->sg_list[i].length;
253                 while (rem) {
254                         if (dstp == (u8 *)&sq->queue[sq->size])
255                                 dstp = (u8 *)sq->queue;
256                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
257                                 len = rem;
258                         else
259                                 len = (u8 *)&sq->queue[sq->size] - dstp;
260                         memcpy(dstp, srcp, len);
261                         dstp += len;
262                         srcp += len;
263                         rem -= len;
264                 }
265         }
266         immdp->op = FW_RI_DATA_IMMD;
267         immdp->r1 = 0;
268         immdp->r2 = 0;
269         immdp->immdlen = cpu_to_be32(plen);
270         *plenp = plen;
271         return 0;
272 }
273
274 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
275                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
276                       int num_sge, u32 *plenp)
277
278 {
279         int i;
280         u32 plen = 0;
281         __be64 *flitp = (__be64 *)isglp->sge;
282
283         for (i = 0; i < num_sge; i++) {
284                 if ((plen + sg_list[i].length) < plen)
285                         return -EMSGSIZE;
286                 plen += sg_list[i].length;
287                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
288                                      sg_list[i].length);
289                 if (++flitp == queue_end)
290                         flitp = queue_start;
291                 *flitp = cpu_to_be64(sg_list[i].addr);
292                 if (++flitp == queue_end)
293                         flitp = queue_start;
294         }
295         isglp->op = FW_RI_DATA_ISGL;
296         isglp->r1 = 0;
297         isglp->nsge = cpu_to_be16(num_sge);
298         isglp->r2 = 0;
299         if (plenp)
300                 *plenp = plen;
301         return 0;
302 }
303
304 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
305                            struct ib_send_wr *wr, u8 *len16)
306 {
307         u32 plen;
308         int size;
309         int ret;
310
311         if (wr->num_sge > T4_MAX_SEND_SGE)
312                 return -EINVAL;
313         switch (wr->opcode) {
314         case IB_WR_SEND:
315                 if (wr->send_flags & IB_SEND_SOLICITED)
316                         wqe->send.sendop_pkd = cpu_to_be32(
317                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
318                 else
319                         wqe->send.sendop_pkd = cpu_to_be32(
320                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
321                 wqe->send.stag_inv = 0;
322                 break;
323         case IB_WR_SEND_WITH_INV:
324                 if (wr->send_flags & IB_SEND_SOLICITED)
325                         wqe->send.sendop_pkd = cpu_to_be32(
326                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
327                 else
328                         wqe->send.sendop_pkd = cpu_to_be32(
329                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
330                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
331                 break;
332
333         default:
334                 return -EINVAL;
335         }
336
337         plen = 0;
338         if (wr->num_sge) {
339                 if (wr->send_flags & IB_SEND_INLINE) {
340                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
341                                          T4_MAX_SEND_INLINE, &plen);
342                         if (ret)
343                                 return ret;
344                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
345                                plen;
346                 } else {
347                         ret = build_isgl((__be64 *)sq->queue,
348                                          (__be64 *)&sq->queue[sq->size],
349                                          wqe->send.u.isgl_src,
350                                          wr->sg_list, wr->num_sge, &plen);
351                         if (ret)
352                                 return ret;
353                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
354                                wr->num_sge * sizeof(struct fw_ri_sge);
355                 }
356         } else {
357                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
358                 wqe->send.u.immd_src[0].r1 = 0;
359                 wqe->send.u.immd_src[0].r2 = 0;
360                 wqe->send.u.immd_src[0].immdlen = 0;
361                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
362                 plen = 0;
363         }
364         *len16 = DIV_ROUND_UP(size, 16);
365         wqe->send.plen = cpu_to_be32(plen);
366         return 0;
367 }
368
369 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
370                             struct ib_send_wr *wr, u8 *len16)
371 {
372         u32 plen;
373         int size;
374         int ret;
375
376         if (wr->num_sge > T4_MAX_SEND_SGE)
377                 return -EINVAL;
378         wqe->write.r2 = 0;
379         wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
380         wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
381         if (wr->num_sge) {
382                 if (wr->send_flags & IB_SEND_INLINE) {
383                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
384                                          T4_MAX_WRITE_INLINE, &plen);
385                         if (ret)
386                                 return ret;
387                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
388                                plen;
389                 } else {
390                         ret = build_isgl((__be64 *)sq->queue,
391                                          (__be64 *)&sq->queue[sq->size],
392                                          wqe->write.u.isgl_src,
393                                          wr->sg_list, wr->num_sge, &plen);
394                         if (ret)
395                                 return ret;
396                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
397                                wr->num_sge * sizeof(struct fw_ri_sge);
398                 }
399         } else {
400                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
401                 wqe->write.u.immd_src[0].r1 = 0;
402                 wqe->write.u.immd_src[0].r2 = 0;
403                 wqe->write.u.immd_src[0].immdlen = 0;
404                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
405                 plen = 0;
406         }
407         *len16 = DIV_ROUND_UP(size, 16);
408         wqe->write.plen = cpu_to_be32(plen);
409         return 0;
410 }
411
412 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
413 {
414         if (wr->num_sge > 1)
415                 return -EINVAL;
416         if (wr->num_sge) {
417                 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
418                 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
419                                                         >> 32));
420                 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
421                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
422                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
423                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
424                                                          >> 32));
425                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
426         } else {
427                 wqe->read.stag_src = cpu_to_be32(2);
428                 wqe->read.to_src_hi = 0;
429                 wqe->read.to_src_lo = 0;
430                 wqe->read.stag_sink = cpu_to_be32(2);
431                 wqe->read.plen = 0;
432                 wqe->read.to_sink_hi = 0;
433                 wqe->read.to_sink_lo = 0;
434         }
435         wqe->read.r2 = 0;
436         wqe->read.r5 = 0;
437         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
438         return 0;
439 }
440
441 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
442                            struct ib_recv_wr *wr, u8 *len16)
443 {
444         int ret;
445
446         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
447                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
448                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
449         if (ret)
450                 return ret;
451         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
452                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
453         return 0;
454 }
455
456 static int build_fastreg(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
457 {
458
459         struct fw_ri_immd *imdp;
460         __be64 *p;
461         int i;
462         int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
463
464         if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
465                 return -EINVAL;
466
467         wqe->fr.qpbinde_to_dcacpu = 0;
468         wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
469         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
470         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
471         wqe->fr.len_hi = 0;
472         wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
473         wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
474         wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
475         wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
476                                         0xffffffff);
477         if (pbllen > T4_MAX_FR_IMMD) {
478                 struct c4iw_fr_page_list *c4pl =
479                                 to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
480                 struct fw_ri_dsgl *sglp;
481
482                 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
483                 sglp->op = FW_RI_DATA_DSGL;
484                 sglp->r1 = 0;
485                 sglp->nsge = cpu_to_be16(1);
486                 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
487                 sglp->len0 = cpu_to_be32(pbllen);
488
489                 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *sglp, 16);
490         } else {
491                 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
492                 imdp->op = FW_RI_DATA_IMMD;
493                 imdp->r1 = 0;
494                 imdp->r2 = 0;
495                 imdp->immdlen = cpu_to_be32(pbllen);
496                 p = (__be64 *)(imdp + 1);
497                 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++, p++)
498                         *p = cpu_to_be64(
499                                 (u64)wr->wr.fast_reg.page_list->page_list[i]);
500                 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen,
501                                       16);
502         }
503         return 0;
504 }
505
506 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
507                           u8 *len16)
508 {
509         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
510         wqe->inv.r2 = 0;
511         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
512         return 0;
513 }
514
515 void c4iw_qp_add_ref(struct ib_qp *qp)
516 {
517         PDBG("%s ib_qp %p\n", __func__, qp);
518         atomic_inc(&(to_c4iw_qp(qp)->refcnt));
519 }
520
521 void c4iw_qp_rem_ref(struct ib_qp *qp)
522 {
523         PDBG("%s ib_qp %p\n", __func__, qp);
524         if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
525                 wake_up(&(to_c4iw_qp(qp)->wait));
526 }
527
528 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
529                    struct ib_send_wr **bad_wr)
530 {
531         int err = 0;
532         u8 len16 = 0;
533         enum fw_wr_opcodes fw_opcode = 0;
534         enum fw_ri_wr_flags fw_flags;
535         struct c4iw_qp *qhp;
536         union t4_wr *wqe;
537         u32 num_wrs;
538         struct t4_swsqe *swsqe;
539         unsigned long flag;
540         u16 idx = 0;
541
542         qhp = to_c4iw_qp(ibqp);
543         spin_lock_irqsave(&qhp->lock, flag);
544         if (t4_wq_in_error(&qhp->wq)) {
545                 spin_unlock_irqrestore(&qhp->lock, flag);
546                 return -EINVAL;
547         }
548         num_wrs = t4_sq_avail(&qhp->wq);
549         if (num_wrs == 0) {
550                 spin_unlock_irqrestore(&qhp->lock, flag);
551                 return -ENOMEM;
552         }
553         while (wr) {
554                 if (num_wrs == 0) {
555                         err = -ENOMEM;
556                         *bad_wr = wr;
557                         break;
558                 }
559                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
560                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
561
562                 fw_flags = 0;
563                 if (wr->send_flags & IB_SEND_SOLICITED)
564                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
565                 if (wr->send_flags & IB_SEND_SIGNALED)
566                         fw_flags |= FW_RI_COMPLETION_FLAG;
567                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
568                 switch (wr->opcode) {
569                 case IB_WR_SEND_WITH_INV:
570                 case IB_WR_SEND:
571                         if (wr->send_flags & IB_SEND_FENCE)
572                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
573                         fw_opcode = FW_RI_SEND_WR;
574                         if (wr->opcode == IB_WR_SEND)
575                                 swsqe->opcode = FW_RI_SEND;
576                         else
577                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
578                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
579                         break;
580                 case IB_WR_RDMA_WRITE:
581                         fw_opcode = FW_RI_RDMA_WRITE_WR;
582                         swsqe->opcode = FW_RI_RDMA_WRITE;
583                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
584                         break;
585                 case IB_WR_RDMA_READ:
586                 case IB_WR_RDMA_READ_WITH_INV:
587                         fw_opcode = FW_RI_RDMA_READ_WR;
588                         swsqe->opcode = FW_RI_READ_REQ;
589                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
590                                 fw_flags |= FW_RI_RDMA_READ_INVALIDATE;
591                         else
592                                 fw_flags = 0;
593                         err = build_rdma_read(wqe, wr, &len16);
594                         if (err)
595                                 break;
596                         swsqe->read_len = wr->sg_list[0].length;
597                         if (!qhp->wq.sq.oldest_read)
598                                 qhp->wq.sq.oldest_read = swsqe;
599                         break;
600                 case IB_WR_FAST_REG_MR:
601                         fw_opcode = FW_RI_FR_NSMR_WR;
602                         swsqe->opcode = FW_RI_FAST_REGISTER;
603                         err = build_fastreg(wqe, wr, &len16);
604                         break;
605                 case IB_WR_LOCAL_INV:
606                         if (wr->send_flags & IB_SEND_FENCE)
607                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
608                         fw_opcode = FW_RI_INV_LSTAG_WR;
609                         swsqe->opcode = FW_RI_LOCAL_INV;
610                         err = build_inv_stag(wqe, wr, &len16);
611                         break;
612                 default:
613                         PDBG("%s post of type=%d TBD!\n", __func__,
614                              wr->opcode);
615                         err = -EINVAL;
616                 }
617                 if (err) {
618                         *bad_wr = wr;
619                         break;
620                 }
621                 swsqe->idx = qhp->wq.sq.pidx;
622                 swsqe->complete = 0;
623                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
624                 swsqe->wr_id = wr->wr_id;
625
626                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
627
628                 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
629                      __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
630                      swsqe->opcode, swsqe->read_len);
631                 wr = wr->next;
632                 num_wrs--;
633                 t4_sq_produce(&qhp->wq, len16);
634                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
635         }
636         if (t4_wq_db_enabled(&qhp->wq))
637                 t4_ring_sq_db(&qhp->wq, idx);
638         spin_unlock_irqrestore(&qhp->lock, flag);
639         return err;
640 }
641
642 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
643                       struct ib_recv_wr **bad_wr)
644 {
645         int err = 0;
646         struct c4iw_qp *qhp;
647         union t4_recv_wr *wqe;
648         u32 num_wrs;
649         u8 len16 = 0;
650         unsigned long flag;
651         u16 idx = 0;
652
653         qhp = to_c4iw_qp(ibqp);
654         spin_lock_irqsave(&qhp->lock, flag);
655         if (t4_wq_in_error(&qhp->wq)) {
656                 spin_unlock_irqrestore(&qhp->lock, flag);
657                 return -EINVAL;
658         }
659         num_wrs = t4_rq_avail(&qhp->wq);
660         if (num_wrs == 0) {
661                 spin_unlock_irqrestore(&qhp->lock, flag);
662                 return -ENOMEM;
663         }
664         while (wr) {
665                 if (wr->num_sge > T4_MAX_RECV_SGE) {
666                         err = -EINVAL;
667                         *bad_wr = wr;
668                         break;
669                 }
670                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
671                                            qhp->wq.rq.wq_pidx *
672                                            T4_EQ_ENTRY_SIZE);
673                 if (num_wrs)
674                         err = build_rdma_recv(qhp, wqe, wr, &len16);
675                 else
676                         err = -ENOMEM;
677                 if (err) {
678                         *bad_wr = wr;
679                         break;
680                 }
681
682                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
683
684                 wqe->recv.opcode = FW_RI_RECV_WR;
685                 wqe->recv.r1 = 0;
686                 wqe->recv.wrid = qhp->wq.rq.pidx;
687                 wqe->recv.r2[0] = 0;
688                 wqe->recv.r2[1] = 0;
689                 wqe->recv.r2[2] = 0;
690                 wqe->recv.len16 = len16;
691                 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
692                      (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
693                 t4_rq_produce(&qhp->wq, len16);
694                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
695                 wr = wr->next;
696                 num_wrs--;
697         }
698         if (t4_wq_db_enabled(&qhp->wq))
699                 t4_ring_rq_db(&qhp->wq, idx);
700         spin_unlock_irqrestore(&qhp->lock, flag);
701         return err;
702 }
703
704 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
705 {
706         return -ENOSYS;
707 }
708
709 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
710                                     u8 *ecode)
711 {
712         int status;
713         int tagged;
714         int opcode;
715         int rqtype;
716         int send_inv;
717
718         if (!err_cqe) {
719                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
720                 *ecode = 0;
721                 return;
722         }
723
724         status = CQE_STATUS(err_cqe);
725         opcode = CQE_OPCODE(err_cqe);
726         rqtype = RQ_TYPE(err_cqe);
727         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
728                    (opcode == FW_RI_SEND_WITH_SE_INV);
729         tagged = (opcode == FW_RI_RDMA_WRITE) ||
730                  (rqtype && (opcode == FW_RI_READ_RESP));
731
732         switch (status) {
733         case T4_ERR_STAG:
734                 if (send_inv) {
735                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
736                         *ecode = RDMAP_CANT_INV_STAG;
737                 } else {
738                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
739                         *ecode = RDMAP_INV_STAG;
740                 }
741                 break;
742         case T4_ERR_PDID:
743                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
744                 if ((opcode == FW_RI_SEND_WITH_INV) ||
745                     (opcode == FW_RI_SEND_WITH_SE_INV))
746                         *ecode = RDMAP_CANT_INV_STAG;
747                 else
748                         *ecode = RDMAP_STAG_NOT_ASSOC;
749                 break;
750         case T4_ERR_QPID:
751                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
752                 *ecode = RDMAP_STAG_NOT_ASSOC;
753                 break;
754         case T4_ERR_ACCESS:
755                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
756                 *ecode = RDMAP_ACC_VIOL;
757                 break;
758         case T4_ERR_WRAP:
759                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
760                 *ecode = RDMAP_TO_WRAP;
761                 break;
762         case T4_ERR_BOUND:
763                 if (tagged) {
764                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
765                         *ecode = DDPT_BASE_BOUNDS;
766                 } else {
767                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
768                         *ecode = RDMAP_BASE_BOUNDS;
769                 }
770                 break;
771         case T4_ERR_INVALIDATE_SHARED_MR:
772         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
773                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
774                 *ecode = RDMAP_CANT_INV_STAG;
775                 break;
776         case T4_ERR_ECC:
777         case T4_ERR_ECC_PSTAG:
778         case T4_ERR_INTERNAL_ERR:
779                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
780                 *ecode = 0;
781                 break;
782         case T4_ERR_OUT_OF_RQE:
783                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
784                 *ecode = DDPU_INV_MSN_NOBUF;
785                 break;
786         case T4_ERR_PBL_ADDR_BOUND:
787                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
788                 *ecode = DDPT_BASE_BOUNDS;
789                 break;
790         case T4_ERR_CRC:
791                 *layer_type = LAYER_MPA|DDP_LLP;
792                 *ecode = MPA_CRC_ERR;
793                 break;
794         case T4_ERR_MARKER:
795                 *layer_type = LAYER_MPA|DDP_LLP;
796                 *ecode = MPA_MARKER_ERR;
797                 break;
798         case T4_ERR_PDU_LEN_ERR:
799                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
800                 *ecode = DDPU_MSG_TOOBIG;
801                 break;
802         case T4_ERR_DDP_VERSION:
803                 if (tagged) {
804                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
805                         *ecode = DDPT_INV_VERS;
806                 } else {
807                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
808                         *ecode = DDPU_INV_VERS;
809                 }
810                 break;
811         case T4_ERR_RDMA_VERSION:
812                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
813                 *ecode = RDMAP_INV_VERS;
814                 break;
815         case T4_ERR_OPCODE:
816                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
817                 *ecode = RDMAP_INV_OPCODE;
818                 break;
819         case T4_ERR_DDP_QUEUE_NUM:
820                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
821                 *ecode = DDPU_INV_QN;
822                 break;
823         case T4_ERR_MSN:
824         case T4_ERR_MSN_GAP:
825         case T4_ERR_MSN_RANGE:
826         case T4_ERR_IRD_OVERFLOW:
827                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
828                 *ecode = DDPU_INV_MSN_RANGE;
829                 break;
830         case T4_ERR_TBIT:
831                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
832                 *ecode = 0;
833                 break;
834         case T4_ERR_MO:
835                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
836                 *ecode = DDPU_INV_MO;
837                 break;
838         default:
839                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
840                 *ecode = 0;
841                 break;
842         }
843 }
844
845 int c4iw_post_zb_read(struct c4iw_qp *qhp)
846 {
847         union t4_wr *wqe;
848         struct sk_buff *skb;
849         u8 len16;
850
851         PDBG("%s enter\n", __func__);
852         skb = alloc_skb(40, GFP_KERNEL);
853         if (!skb) {
854                 printk(KERN_ERR "%s cannot send zb_read!!\n", __func__);
855                 return -ENOMEM;
856         }
857         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
858
859         wqe = (union t4_wr *)skb_put(skb, sizeof wqe->read);
860         memset(wqe, 0, sizeof wqe->read);
861         wqe->read.r2 = cpu_to_be64(0);
862         wqe->read.stag_sink = cpu_to_be32(1);
863         wqe->read.to_sink_hi = cpu_to_be32(0);
864         wqe->read.to_sink_lo = cpu_to_be32(1);
865         wqe->read.stag_src = cpu_to_be32(1);
866         wqe->read.plen = cpu_to_be32(0);
867         wqe->read.to_src_hi = cpu_to_be32(0);
868         wqe->read.to_src_lo = cpu_to_be32(1);
869         len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
870         init_wr_hdr(wqe, 0, FW_RI_RDMA_READ_WR, FW_RI_COMPLETION_FLAG, len16);
871
872         return c4iw_ofld_send(&qhp->rhp->rdev, skb);
873 }
874
875 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
876                            gfp_t gfp)
877 {
878         struct fw_ri_wr *wqe;
879         struct sk_buff *skb;
880         struct terminate_message *term;
881
882         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
883              qhp->ep->hwtid);
884
885         skb = alloc_skb(sizeof *wqe, gfp);
886         if (!skb)
887                 return;
888         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
889
890         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
891         memset(wqe, 0, sizeof *wqe);
892         wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
893         wqe->flowid_len16 = cpu_to_be32(
894                 FW_WR_FLOWID(qhp->ep->hwtid) |
895                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
896
897         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
898         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
899         term = (struct terminate_message *)wqe->u.terminate.termmsg;
900         build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
901         c4iw_ofld_send(&qhp->rhp->rdev, skb);
902 }
903
904 /*
905  * Assumes qhp lock is held.
906  */
907 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
908                        struct c4iw_cq *schp, unsigned long *flag)
909 {
910         int count;
911         int flushed;
912
913         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
914         /* take a ref on the qhp since we must release the lock */
915         atomic_inc(&qhp->refcnt);
916         spin_unlock_irqrestore(&qhp->lock, *flag);
917
918         /* locking hierarchy: cq lock first, then qp lock. */
919         spin_lock_irqsave(&rchp->lock, *flag);
920         spin_lock(&qhp->lock);
921         c4iw_flush_hw_cq(&rchp->cq);
922         c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
923         flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
924         spin_unlock(&qhp->lock);
925         spin_unlock_irqrestore(&rchp->lock, *flag);
926         if (flushed)
927                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
928
929         /* locking hierarchy: cq lock first, then qp lock. */
930         spin_lock_irqsave(&schp->lock, *flag);
931         spin_lock(&qhp->lock);
932         c4iw_flush_hw_cq(&schp->cq);
933         c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
934         flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
935         spin_unlock(&qhp->lock);
936         spin_unlock_irqrestore(&schp->lock, *flag);
937         if (flushed)
938                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
939
940         /* deref */
941         if (atomic_dec_and_test(&qhp->refcnt))
942                 wake_up(&qhp->wait);
943
944         spin_lock_irqsave(&qhp->lock, *flag);
945 }
946
947 static void flush_qp(struct c4iw_qp *qhp, unsigned long *flag)
948 {
949         struct c4iw_cq *rchp, *schp;
950
951         rchp = get_chp(qhp->rhp, qhp->attr.rcq);
952         schp = get_chp(qhp->rhp, qhp->attr.scq);
953
954         if (qhp->ibqp.uobject) {
955                 t4_set_wq_in_error(&qhp->wq);
956                 t4_set_cq_in_error(&rchp->cq);
957                 if (schp != rchp)
958                         t4_set_cq_in_error(&schp->cq);
959                 return;
960         }
961         __flush_qp(qhp, rchp, schp, flag);
962 }
963
964 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
965                      struct c4iw_ep *ep)
966 {
967         struct fw_ri_wr *wqe;
968         int ret;
969         struct c4iw_wr_wait wr_wait;
970         struct sk_buff *skb;
971
972         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
973              ep->hwtid);
974
975         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
976         if (!skb)
977                 return -ENOMEM;
978         set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
979
980         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
981         memset(wqe, 0, sizeof *wqe);
982         wqe->op_compl = cpu_to_be32(
983                 FW_WR_OP(FW_RI_INIT_WR) |
984                 FW_WR_COMPL(1));
985         wqe->flowid_len16 = cpu_to_be32(
986                 FW_WR_FLOWID(ep->hwtid) |
987                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
988         wqe->cookie = (u64)&wr_wait;
989
990         wqe->u.fini.type = FW_RI_TYPE_FINI;
991         c4iw_init_wr_wait(&wr_wait);
992         ret = c4iw_ofld_send(&rhp->rdev, skb);
993         if (ret)
994                 goto out;
995
996         wait_event_timeout(wr_wait.wait, wr_wait.done, C4IW_WR_TO);
997         if (!wr_wait.done) {
998                 printk(KERN_ERR MOD "Device %s not responding!\n",
999                        pci_name(rhp->rdev.lldi.pdev));
1000                 rhp->rdev.flags = T4_FATAL_ERROR;
1001                 ret = -EIO;
1002         } else {
1003                 ret = wr_wait.ret;
1004                 if (ret)
1005                         printk(KERN_WARNING MOD
1006                                "%s: Abnormal close qpid %d ret %u\n",
1007                                pci_name(rhp->rdev.lldi.pdev), qhp->wq.sq.qid,
1008                                ret);
1009         }
1010 out:
1011         PDBG("%s ret %d\n", __func__, ret);
1012         return ret;
1013 }
1014
1015 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1016 {
1017         memset(&init->u, 0, sizeof init->u);
1018         switch (p2p_type) {
1019         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1020                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1021                 init->u.write.stag_sink = cpu_to_be32(1);
1022                 init->u.write.to_sink = cpu_to_be64(1);
1023                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1024                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1025                                                    sizeof(struct fw_ri_immd),
1026                                                    16);
1027                 break;
1028         case FW_RI_INIT_P2PTYPE_READ_REQ:
1029                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1030                 init->u.read.stag_src = cpu_to_be32(1);
1031                 init->u.read.to_src_lo = cpu_to_be32(1);
1032                 init->u.read.stag_sink = cpu_to_be32(1);
1033                 init->u.read.to_sink_lo = cpu_to_be32(1);
1034                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1035                 break;
1036         }
1037 }
1038
1039 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1040 {
1041         struct fw_ri_wr *wqe;
1042         int ret;
1043         struct c4iw_wr_wait wr_wait;
1044         struct sk_buff *skb;
1045
1046         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1047              qhp->ep->hwtid);
1048
1049         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1050         if (!skb)
1051                 return -ENOMEM;
1052         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1053
1054         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1055         memset(wqe, 0, sizeof *wqe);
1056         wqe->op_compl = cpu_to_be32(
1057                 FW_WR_OP(FW_RI_INIT_WR) |
1058                 FW_WR_COMPL(1));
1059         wqe->flowid_len16 = cpu_to_be32(
1060                 FW_WR_FLOWID(qhp->ep->hwtid) |
1061                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1062
1063         wqe->cookie = (u64)&wr_wait;
1064
1065         wqe->u.init.type = FW_RI_TYPE_INIT;
1066         wqe->u.init.mpareqbit_p2ptype =
1067                 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1068                 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1069         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1070         if (qhp->attr.mpa_attr.recv_marker_enabled)
1071                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1072         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1073                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1074         if (qhp->attr.mpa_attr.crc_enabled)
1075                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1076
1077         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1078                             FW_RI_QP_RDMA_WRITE_ENABLE |
1079                             FW_RI_QP_BIND_ENABLE;
1080         if (!qhp->ibqp.uobject)
1081                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1082                                      FW_RI_QP_STAG0_ENABLE;
1083         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1084         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1085         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1086         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1087         wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1088         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1089         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1090         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1091         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1092         wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1093         wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1094         wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1095         wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1096                                          rhp->rdev.lldi.vr->rq.start);
1097         if (qhp->attr.mpa_attr.initiator)
1098                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1099
1100         c4iw_init_wr_wait(&wr_wait);
1101         ret = c4iw_ofld_send(&rhp->rdev, skb);
1102         if (ret)
1103                 goto out;
1104
1105         wait_event_timeout(wr_wait.wait, wr_wait.done, C4IW_WR_TO);
1106         if (!wr_wait.done) {
1107                 printk(KERN_ERR MOD "Device %s not responding!\n",
1108                        pci_name(rhp->rdev.lldi.pdev));
1109                 rhp->rdev.flags = T4_FATAL_ERROR;
1110                 ret = -EIO;
1111         } else
1112                 ret = wr_wait.ret;
1113 out:
1114         PDBG("%s ret %d\n", __func__, ret);
1115         return ret;
1116 }
1117
1118 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1119                    enum c4iw_qp_attr_mask mask,
1120                    struct c4iw_qp_attributes *attrs,
1121                    int internal)
1122 {
1123         int ret = 0;
1124         struct c4iw_qp_attributes newattr = qhp->attr;
1125         unsigned long flag;
1126         int disconnect = 0;
1127         int terminate = 0;
1128         int abort = 0;
1129         int free = 0;
1130         struct c4iw_ep *ep = NULL;
1131
1132         PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1133              qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1134              (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1135
1136         spin_lock_irqsave(&qhp->lock, flag);
1137
1138         /* Process attr changes if in IDLE */
1139         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1140                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1141                         ret = -EIO;
1142                         goto out;
1143                 }
1144                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1145                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1146                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1147                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1148                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1149                         newattr.enable_bind = attrs->enable_bind;
1150                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1151                         if (attrs->max_ord > c4iw_max_read_depth) {
1152                                 ret = -EINVAL;
1153                                 goto out;
1154                         }
1155                         newattr.max_ord = attrs->max_ord;
1156                 }
1157                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1158                         if (attrs->max_ird > c4iw_max_read_depth) {
1159                                 ret = -EINVAL;
1160                                 goto out;
1161                         }
1162                         newattr.max_ird = attrs->max_ird;
1163                 }
1164                 qhp->attr = newattr;
1165         }
1166
1167         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1168                 goto out;
1169         if (qhp->attr.state == attrs->next_state)
1170                 goto out;
1171
1172         switch (qhp->attr.state) {
1173         case C4IW_QP_STATE_IDLE:
1174                 switch (attrs->next_state) {
1175                 case C4IW_QP_STATE_RTS:
1176                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1177                                 ret = -EINVAL;
1178                                 goto out;
1179                         }
1180                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1181                                 ret = -EINVAL;
1182                                 goto out;
1183                         }
1184                         qhp->attr.mpa_attr = attrs->mpa_attr;
1185                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1186                         qhp->ep = qhp->attr.llp_stream_handle;
1187                         qhp->attr.state = C4IW_QP_STATE_RTS;
1188
1189                         /*
1190                          * Ref the endpoint here and deref when we
1191                          * disassociate the endpoint from the QP.  This
1192                          * happens in CLOSING->IDLE transition or *->ERROR
1193                          * transition.
1194                          */
1195                         c4iw_get_ep(&qhp->ep->com);
1196                         spin_unlock_irqrestore(&qhp->lock, flag);
1197                         ret = rdma_init(rhp, qhp);
1198                         spin_lock_irqsave(&qhp->lock, flag);
1199                         if (ret)
1200                                 goto err;
1201                         break;
1202                 case C4IW_QP_STATE_ERROR:
1203                         qhp->attr.state = C4IW_QP_STATE_ERROR;
1204                         flush_qp(qhp, &flag);
1205                         break;
1206                 default:
1207                         ret = -EINVAL;
1208                         goto out;
1209                 }
1210                 break;
1211         case C4IW_QP_STATE_RTS:
1212                 switch (attrs->next_state) {
1213                 case C4IW_QP_STATE_CLOSING:
1214                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1215                         qhp->attr.state = C4IW_QP_STATE_CLOSING;
1216                         ep = qhp->ep;
1217                         if (!internal) {
1218                                 abort = 0;
1219                                 disconnect = 1;
1220                                 c4iw_get_ep(&ep->com);
1221                         }
1222                         spin_unlock_irqrestore(&qhp->lock, flag);
1223                         ret = rdma_fini(rhp, qhp, ep);
1224                         spin_lock_irqsave(&qhp->lock, flag);
1225                         if (ret) {
1226                                 c4iw_get_ep(&ep->com);
1227                                 disconnect = abort = 1;
1228                                 goto err;
1229                         }
1230                         break;
1231                 case C4IW_QP_STATE_TERMINATE:
1232                         qhp->attr.state = C4IW_QP_STATE_TERMINATE;
1233                         if (qhp->ibqp.uobject)
1234                                 t4_set_wq_in_error(&qhp->wq);
1235                         ep = qhp->ep;
1236                         c4iw_get_ep(&ep->com);
1237                         terminate = 1;
1238                         disconnect = 1;
1239                         break;
1240                 case C4IW_QP_STATE_ERROR:
1241                         qhp->attr.state = C4IW_QP_STATE_ERROR;
1242                         if (!internal) {
1243                                 abort = 1;
1244                                 disconnect = 1;
1245                                 ep = qhp->ep;
1246                                 c4iw_get_ep(&ep->com);
1247                         }
1248                         goto err;
1249                         break;
1250                 default:
1251                         ret = -EINVAL;
1252                         goto out;
1253                 }
1254                 break;
1255         case C4IW_QP_STATE_CLOSING:
1256                 if (!internal) {
1257                         ret = -EINVAL;
1258                         goto out;
1259                 }
1260                 switch (attrs->next_state) {
1261                 case C4IW_QP_STATE_IDLE:
1262                         flush_qp(qhp, &flag);
1263                         qhp->attr.state = C4IW_QP_STATE_IDLE;
1264                         qhp->attr.llp_stream_handle = NULL;
1265                         c4iw_put_ep(&qhp->ep->com);
1266                         qhp->ep = NULL;
1267                         wake_up(&qhp->wait);
1268                         break;
1269                 case C4IW_QP_STATE_ERROR:
1270                         goto err;
1271                 default:
1272                         ret = -EINVAL;
1273                         goto err;
1274                 }
1275                 break;
1276         case C4IW_QP_STATE_ERROR:
1277                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1278                         ret = -EINVAL;
1279                         goto out;
1280                 }
1281                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1282                         ret = -EINVAL;
1283                         goto out;
1284                 }
1285                 qhp->attr.state = C4IW_QP_STATE_IDLE;
1286                 break;
1287         case C4IW_QP_STATE_TERMINATE:
1288                 if (!internal) {
1289                         ret = -EINVAL;
1290                         goto out;
1291                 }
1292                 goto err;
1293                 break;
1294         default:
1295                 printk(KERN_ERR "%s in a bad state %d\n",
1296                        __func__, qhp->attr.state);
1297                 ret = -EINVAL;
1298                 goto err;
1299                 break;
1300         }
1301         goto out;
1302 err:
1303         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1304              qhp->wq.sq.qid);
1305
1306         /* disassociate the LLP connection */
1307         qhp->attr.llp_stream_handle = NULL;
1308         ep = qhp->ep;
1309         qhp->ep = NULL;
1310         qhp->attr.state = C4IW_QP_STATE_ERROR;
1311         free = 1;
1312         wake_up(&qhp->wait);
1313         BUG_ON(!ep);
1314         flush_qp(qhp, &flag);
1315 out:
1316         spin_unlock_irqrestore(&qhp->lock, flag);
1317
1318         if (terminate)
1319                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1320
1321         /*
1322          * If disconnect is 1, then we need to initiate a disconnect
1323          * on the EP.  This can be a normal close (RTS->CLOSING) or
1324          * an abnormal close (RTS/CLOSING->ERROR).
1325          */
1326         if (disconnect) {
1327                 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1328                                                          GFP_KERNEL);
1329                 c4iw_put_ep(&ep->com);
1330         }
1331
1332         /*
1333          * If free is 1, then we've disassociated the EP from the QP
1334          * and we need to dereference the EP.
1335          */
1336         if (free)
1337                 c4iw_put_ep(&ep->com);
1338
1339         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1340         return ret;
1341 }
1342
1343 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1344 {
1345         struct c4iw_dev *rhp;
1346         struct c4iw_qp *qhp;
1347         struct c4iw_qp_attributes attrs;
1348         struct c4iw_ucontext *ucontext;
1349
1350         qhp = to_c4iw_qp(ib_qp);
1351         rhp = qhp->rhp;
1352
1353         attrs.next_state = C4IW_QP_STATE_ERROR;
1354         c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1355         wait_event(qhp->wait, !qhp->ep);
1356
1357         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1358         atomic_dec(&qhp->refcnt);
1359         wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1360
1361         ucontext = ib_qp->uobject ?
1362                    to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1363         destroy_qp(&rhp->rdev, &qhp->wq,
1364                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1365
1366         PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1367         kfree(qhp);
1368         return 0;
1369 }
1370
1371 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1372                              struct ib_udata *udata)
1373 {
1374         struct c4iw_dev *rhp;
1375         struct c4iw_qp *qhp;
1376         struct c4iw_pd *php;
1377         struct c4iw_cq *schp;
1378         struct c4iw_cq *rchp;
1379         struct c4iw_create_qp_resp uresp;
1380         int sqsize, rqsize;
1381         struct c4iw_ucontext *ucontext;
1382         int ret;
1383         struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4;
1384
1385         PDBG("%s ib_pd %p\n", __func__, pd);
1386
1387         if (attrs->qp_type != IB_QPT_RC)
1388                 return ERR_PTR(-EINVAL);
1389
1390         php = to_c4iw_pd(pd);
1391         rhp = php->rhp;
1392         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1393         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1394         if (!schp || !rchp)
1395                 return ERR_PTR(-EINVAL);
1396
1397         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1398                 return ERR_PTR(-EINVAL);
1399
1400         rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1401         if (rqsize > T4_MAX_RQ_SIZE)
1402                 return ERR_PTR(-E2BIG);
1403
1404         sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1405         if (sqsize > T4_MAX_SQ_SIZE)
1406                 return ERR_PTR(-E2BIG);
1407
1408         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1409
1410
1411         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1412         if (!qhp)
1413                 return ERR_PTR(-ENOMEM);
1414         qhp->wq.sq.size = sqsize;
1415         qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1416         qhp->wq.rq.size = rqsize;
1417         qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1418
1419         if (ucontext) {
1420                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1421                 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1422         }
1423
1424         PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1425              __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1426
1427         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1428                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1429         if (ret)
1430                 goto err1;
1431
1432         attrs->cap.max_recv_wr = rqsize - 1;
1433         attrs->cap.max_send_wr = sqsize - 1;
1434         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1435
1436         qhp->rhp = rhp;
1437         qhp->attr.pd = php->pdid;
1438         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1439         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1440         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1441         qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1442         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1443         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1444         qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1445         qhp->attr.state = C4IW_QP_STATE_IDLE;
1446         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1447         qhp->attr.enable_rdma_read = 1;
1448         qhp->attr.enable_rdma_write = 1;
1449         qhp->attr.enable_bind = 1;
1450         qhp->attr.max_ord = 1;
1451         qhp->attr.max_ird = 1;
1452         spin_lock_init(&qhp->lock);
1453         init_waitqueue_head(&qhp->wait);
1454         atomic_set(&qhp->refcnt, 1);
1455
1456         ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1457         if (ret)
1458                 goto err2;
1459
1460         if (udata) {
1461                 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1462                 if (!mm1) {
1463                         ret = -ENOMEM;
1464                         goto err3;
1465                 }
1466                 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1467                 if (!mm2) {
1468                         ret = -ENOMEM;
1469                         goto err4;
1470                 }
1471                 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1472                 if (!mm3) {
1473                         ret = -ENOMEM;
1474                         goto err5;
1475                 }
1476                 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1477                 if (!mm4) {
1478                         ret = -ENOMEM;
1479                         goto err6;
1480                 }
1481
1482                 uresp.qid_mask = rhp->rdev.qpmask;
1483                 uresp.sqid = qhp->wq.sq.qid;
1484                 uresp.sq_size = qhp->wq.sq.size;
1485                 uresp.sq_memsize = qhp->wq.sq.memsize;
1486                 uresp.rqid = qhp->wq.rq.qid;
1487                 uresp.rq_size = qhp->wq.rq.size;
1488                 uresp.rq_memsize = qhp->wq.rq.memsize;
1489                 spin_lock(&ucontext->mmap_lock);
1490                 uresp.sq_key = ucontext->key;
1491                 ucontext->key += PAGE_SIZE;
1492                 uresp.rq_key = ucontext->key;
1493                 ucontext->key += PAGE_SIZE;
1494                 uresp.sq_db_gts_key = ucontext->key;
1495                 ucontext->key += PAGE_SIZE;
1496                 uresp.rq_db_gts_key = ucontext->key;
1497                 ucontext->key += PAGE_SIZE;
1498                 spin_unlock(&ucontext->mmap_lock);
1499                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1500                 if (ret)
1501                         goto err7;
1502                 mm1->key = uresp.sq_key;
1503                 mm1->addr = virt_to_phys(qhp->wq.sq.queue);
1504                 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1505                 insert_mmap(ucontext, mm1);
1506                 mm2->key = uresp.rq_key;
1507                 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1508                 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1509                 insert_mmap(ucontext, mm2);
1510                 mm3->key = uresp.sq_db_gts_key;
1511                 mm3->addr = qhp->wq.sq.udb;
1512                 mm3->len = PAGE_SIZE;
1513                 insert_mmap(ucontext, mm3);
1514                 mm4->key = uresp.rq_db_gts_key;
1515                 mm4->addr = qhp->wq.rq.udb;
1516                 mm4->len = PAGE_SIZE;
1517                 insert_mmap(ucontext, mm4);
1518         }
1519         qhp->ibqp.qp_num = qhp->wq.sq.qid;
1520         init_timer(&(qhp->timer));
1521         PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1522              __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1523              qhp->wq.sq.qid);
1524         return &qhp->ibqp;
1525 err7:
1526         kfree(mm4);
1527 err6:
1528         kfree(mm3);
1529 err5:
1530         kfree(mm2);
1531 err4:
1532         kfree(mm1);
1533 err3:
1534         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1535 err2:
1536         destroy_qp(&rhp->rdev, &qhp->wq,
1537                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1538 err1:
1539         kfree(qhp);
1540         return ERR_PTR(ret);
1541 }
1542
1543 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1544                       int attr_mask, struct ib_udata *udata)
1545 {
1546         struct c4iw_dev *rhp;
1547         struct c4iw_qp *qhp;
1548         enum c4iw_qp_attr_mask mask = 0;
1549         struct c4iw_qp_attributes attrs;
1550
1551         PDBG("%s ib_qp %p\n", __func__, ibqp);
1552
1553         /* iwarp does not support the RTR state */
1554         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1555                 attr_mask &= ~IB_QP_STATE;
1556
1557         /* Make sure we still have something left to do */
1558         if (!attr_mask)
1559                 return 0;
1560
1561         memset(&attrs, 0, sizeof attrs);
1562         qhp = to_c4iw_qp(ibqp);
1563         rhp = qhp->rhp;
1564
1565         attrs.next_state = c4iw_convert_state(attr->qp_state);
1566         attrs.enable_rdma_read = (attr->qp_access_flags &
1567                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
1568         attrs.enable_rdma_write = (attr->qp_access_flags &
1569                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1570         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1571
1572
1573         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1574         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1575                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1576                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1577                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1578
1579         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1580 }
1581
1582 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1583 {
1584         PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1585         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1586 }