drivers/infiniband/hw/cxgb3/iwch_qp.c

   1 /*
   2  * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/sched.h>
  33 #include "iwch_provider.h"
  34 #include "iwch.h"
  35 #include "iwch_cm.h"
  36 #include "cxio_hal.h"
  37 #include "cxio_resource.h"
  38
  39 #define NO_SUPPORT -1
  40
  41 static int build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
  42                                 u8 * flit_cnt)
  43 {
  44         int i;
  45         u32 plen;
  46
  47         switch (wr->opcode) {
  48         case IB_WR_SEND:
  49                 if (wr->send_flags & IB_SEND_SOLICITED)
  50                         wqe->send.rdmaop = T3_SEND_WITH_SE;
  51                 else
  52                         wqe->send.rdmaop = T3_SEND;
  53                 wqe->send.rem_stag = 0;
  54                 break;
  55         case IB_WR_SEND_WITH_INV:
  56                 if (wr->send_flags & IB_SEND_SOLICITED)
  57                         wqe->send.rdmaop = T3_SEND_WITH_SE_INV;
  58                 else
  59                         wqe->send.rdmaop = T3_SEND_WITH_INV;
  60                 wqe->send.rem_stag = cpu_to_be32(wr->ex.invalidate_rkey);
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65         if (wr->num_sge > T3_MAX_SGE)
  66                 return -EINVAL;
  67         wqe->send.reserved[0] = 0;
  68         wqe->send.reserved[1] = 0;
  69         wqe->send.reserved[2] = 0;
  70         plen = 0;
  71         for (i = 0; i < wr->num_sge; i++) {
  72                 if ((plen + wr->sg_list[i].length) < plen)
  73                         return -EMSGSIZE;
  74
  75                 plen += wr->sg_list[i].length;
  76                 wqe->send.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
  77                 wqe->send.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
  78                 wqe->send.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
  79         }
  80         wqe->send.num_sgle = cpu_to_be32(wr->num_sge);
  81         *flit_cnt = 4 + ((wr->num_sge) << 1);
  82         wqe->send.plen = cpu_to_be32(plen);
  83         return 0;
  84 }
  85
  86 static int build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
  87                                  u8 *flit_cnt)
  88 {
  89         int i;
  90         u32 plen;
  91         if (wr->num_sge > T3_MAX_SGE)
  92                 return -EINVAL;
  93         wqe->write.rdmaop = T3_RDMA_WRITE;
  94         wqe->write.reserved[0] = 0;
  95         wqe->write.reserved[1] = 0;
  96         wqe->write.reserved[2] = 0;
  97         wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
  98         wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
  99
 100         if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
 101                 plen = 4;
 102                 wqe->write.sgl[0].stag = wr->ex.imm_data;
 103                 wqe->write.sgl[0].len = cpu_to_be32(0);
 104                 wqe->write.num_sgle = cpu_to_be32(0);
 105                 *flit_cnt = 6;
 106         } else {
 107                 plen = 0;
 108                 for (i = 0; i < wr->num_sge; i++) {
 109                         if ((plen + wr->sg_list[i].length) < plen) {
 110                                 return -EMSGSIZE;
 111                         }
 112                         plen += wr->sg_list[i].length;
 113                         wqe->write.sgl[i].stag =
 114                             cpu_to_be32(wr->sg_list[i].lkey);
 115                         wqe->write.sgl[i].len =
 116                             cpu_to_be32(wr->sg_list[i].length);
 117                         wqe->write.sgl[i].to =
 118                             cpu_to_be64(wr->sg_list[i].addr);
 119                 }
 120                 wqe->write.num_sgle = cpu_to_be32(wr->num_sge);
 121                 *flit_cnt = 5 + ((wr->num_sge) << 1);
 122         }
 123         wqe->write.plen = cpu_to_be32(plen);
 124         return 0;
 125 }
 126
 127 static int build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
 128                                 u8 *flit_cnt)
 129 {
 130         if (wr->num_sge > 1)
 131                 return -EINVAL;
 132         wqe->read.rdmaop = T3_READ_REQ;
 133         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
 134                 wqe->read.local_inv = 1;
 135         else
 136                 wqe->read.local_inv = 0;
 137         wqe->read.reserved[0] = 0;
 138         wqe->read.reserved[1] = 0;
 139         wqe->read.rem_stag = cpu_to_be32(wr->wr.rdma.rkey);
 140         wqe->read.rem_to = cpu_to_be64(wr->wr.rdma.remote_addr);
 141         wqe->read.local_stag = cpu_to_be32(wr->sg_list[0].lkey);
 142         wqe->read.local_len = cpu_to_be32(wr->sg_list[0].length);
 143         wqe->read.local_to = cpu_to_be64(wr->sg_list[0].addr);
 144         *flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
 145         return 0;
 146 }
 147
 148 static int build_fastreg(union t3_wr *wqe, struct ib_send_wr *wr,
 149                                 u8 *flit_cnt, int *wr_cnt, struct t3_wq *wq)
 150 {
 151         int i;
 152         __be64 *p;
 153
 154         if (wr->wr.fast_reg.page_list_len > T3_MAX_FASTREG_DEPTH)
 155                 return -EINVAL;
 156         *wr_cnt = 1;
 157         wqe->fastreg.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
 158         wqe->fastreg.len = cpu_to_be32(wr->wr.fast_reg.length);
 159         wqe->fastreg.va_base_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
 160         wqe->fastreg.va_base_lo_fbo =
 161                                 cpu_to_be32(wr->wr.fast_reg.iova_start & 0xffffffff);
 162         wqe->fastreg.page_type_perms = cpu_to_be32(
 163                 V_FR_PAGE_COUNT(wr->wr.fast_reg.page_list_len) |
 164                 V_FR_PAGE_SIZE(wr->wr.fast_reg.page_shift-12) |
 165                 V_FR_TYPE(TPT_VATO) |
 166                 V_FR_PERMS(iwch_ib_to_tpt_access(wr->wr.fast_reg.access_flags)));
 167         p = &wqe->fastreg.pbl_addrs[0];
 168         for (i = 0; i < wr->wr.fast_reg.page_list_len; i++, p++) {
 169
 170                 /* If we need a 2nd WR, then set it up */
 171                 if (i == T3_MAX_FASTREG_FRAG) {
 172                         *wr_cnt = 2;
 173                         wqe = (union t3_wr *)(wq->queue +
 174                                 Q_PTR2IDX((wq->wptr+1), wq->size_log2));
 175                         build_fw_riwrh((void *)wqe, T3_WR_FASTREG, 0,
 176                                Q_GENBIT(wq->wptr + 1, wq->size_log2),
 177                                0, 1 + wr->wr.fast_reg.page_list_len - T3_MAX_FASTREG_FRAG,
 178                                T3_EOP);
 179
 180                         p = &wqe->pbl_frag.pbl_addrs[0];
 181                 }
 182                 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
 183         }
 184         *flit_cnt = 5 + wr->wr.fast_reg.page_list_len;
 185         if (*flit_cnt > 15)
 186                 *flit_cnt = 15;
 187         return 0;
 188 }
 189
 190 static int build_inv_stag(union t3_wr *wqe, struct ib_send_wr *wr,
 191                                 u8 *flit_cnt)
 192 {
 193         wqe->local_inv.stag = cpu_to_be32(wr->ex.invalidate_rkey);
 194         wqe->local_inv.reserved = 0;
 195         *flit_cnt = sizeof(struct t3_local_inv_wr) >> 3;
 196         return 0;
 197 }
 198
 199 static int iwch_sgl2pbl_map(struct iwch_dev *rhp, struct ib_sge *sg_list,
 200                             u32 num_sgle, u32 * pbl_addr, u8 * page_size)
 201 {
 202         int i;
 203         struct iwch_mr *mhp;
 204         u64 offset;
 205         for (i = 0; i < num_sgle; i++) {
 206
 207                 mhp = get_mhp(rhp, (sg_list[i].lkey) >> 8);
 208                 if (!mhp) {
 209                         PDBG("%s %d\n", __func__, __LINE__);
 210                         return -EIO;
 211                 }
 212                 if (!mhp->attr.state) {
 213                         PDBG("%s %d\n", __func__, __LINE__);
 214                         return -EIO;
 215                 }
 216                 if (mhp->attr.zbva) {
 217                         PDBG("%s %d\n", __func__, __LINE__);
 218                         return -EIO;
 219                 }
 220
 221                 if (sg_list[i].addr < mhp->attr.va_fbo) {
 222                         PDBG("%s %d\n", __func__, __LINE__);
 223                         return -EINVAL;
 224                 }
 225                 if (sg_list[i].addr + ((u64) sg_list[i].length) <
 226                     sg_list[i].addr) {
 227                         PDBG("%s %d\n", __func__, __LINE__);
 228                         return -EINVAL;
 229                 }
 230                 if (sg_list[i].addr + ((u64) sg_list[i].length) >
 231                     mhp->attr.va_fbo + ((u64) mhp->attr.len)) {
 232                         PDBG("%s %d\n", __func__, __LINE__);
 233                         return -EINVAL;
 234                 }
 235                 offset = sg_list[i].addr - mhp->attr.va_fbo;
 236                 offset += mhp->attr.va_fbo &
 237                           ((1UL << (12 + mhp->attr.page_size)) - 1);
 238                 pbl_addr[i] = ((mhp->attr.pbl_addr -
 239                                 rhp->rdev.rnic_info.pbl_base) >> 3) +
 240                               (offset >> (12 + mhp->attr.page_size));
 241                 page_size[i] = mhp->attr.page_size;
 242         }
 243         return 0;
 244 }
 245
 246 static int build_rdma_recv(struct iwch_qp *qhp, union t3_wr *wqe,
 247                                 struct ib_recv_wr *wr)
 248 {
 249         int i, err = 0;
 250         u32 pbl_addr[T3_MAX_SGE];
 251         u8 page_size[T3_MAX_SGE];
 252
 253         err = iwch_sgl2pbl_map(qhp->rhp, wr->sg_list, wr->num_sge, pbl_addr,
 254                                page_size);
 255         if (err)
 256                 return err;
 257         wqe->recv.pagesz[0] = page_size[0];
 258         wqe->recv.pagesz[1] = page_size[1];
 259         wqe->recv.pagesz[2] = page_size[2];
 260         wqe->recv.pagesz[3] = page_size[3];
 261         wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
 262         for (i = 0; i < wr->num_sge; i++) {
 263                 wqe->recv.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
 264                 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
 265
 266                 /* to in the WQE == the offset into the page */
 267                 wqe->recv.sgl[i].to = cpu_to_be64(((u32)wr->sg_list[i].addr) &
 268                                 ((1UL << (12 + page_size[i])) - 1));
 269
 270                 /* pbl_addr is the adapters address in the PBL */
 271                 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_addr[i]);
 272         }
 273         for (; i < T3_MAX_SGE; i++) {
 274                 wqe->recv.sgl[i].stag = 0;
 275                 wqe->recv.sgl[i].len = 0;
 276                 wqe->recv.sgl[i].to = 0;
 277                 wqe->recv.pbl_addr[i] = 0;
 278         }
 279         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
 280                              qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
 281         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
 282                              qhp->wq.rq_size_log2)].pbl_addr = 0;
 283         return 0;
 284 }
 285
 286 static int build_zero_stag_recv(struct iwch_qp *qhp, union t3_wr *wqe,
 287                                 struct ib_recv_wr *wr)
 288 {
 289         int i;
 290         u32 pbl_addr;
 291         u32 pbl_offset;
 292
 293
 294         /*
 295          * The T3 HW requires the PBL in the HW recv descriptor to reference
 296          * a PBL entry.  So we allocate the max needed PBL memory here and pass
 297          * it to the uP in the recv WR.  The uP will build the PBL and setup
 298          * the HW recv descriptor.
 299          */
 300         pbl_addr = cxio_hal_pblpool_alloc(&qhp->rhp->rdev, T3_STAG0_PBL_SIZE);
 301         if (!pbl_addr)
 302                 return -ENOMEM;
 303
 304         /*
 305          * Compute the 8B aligned offset.
 306          */
 307         pbl_offset = (pbl_addr - qhp->rhp->rdev.rnic_info.pbl_base) >> 3;
 308
 309         wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
 310
 311         for (i = 0; i < wr->num_sge; i++) {
 312
 313                 /*
 314                  * Use a 128MB page size. This and an imposed 128MB
 315                  * sge length limit allows us to require only a 2-entry HW
 316                  * PBL for each SGE.  This restriction is acceptable since
 317                  * since it is not possible to allocate 128MB of contiguous
 318                  * DMA coherent memory!
 319                  */
 320                 if (wr->sg_list[i].length > T3_STAG0_MAX_PBE_LEN)
 321                         return -EINVAL;
 322                 wqe->recv.pagesz[i] = T3_STAG0_PAGE_SHIFT;
 323
 324                 /*
 325                  * T3 restricts a recv to all zero-stag or all non-zero-stag.
 326                  */
 327                 if (wr->sg_list[i].lkey != 0)
 328                         return -EINVAL;
 329                 wqe->recv.sgl[i].stag = 0;
 330                 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
 331                 wqe->recv.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
 332                 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_offset);
 333                 pbl_offset += 2;
 334         }
 335         for (; i < T3_MAX_SGE; i++) {
 336                 wqe->recv.pagesz[i] = 0;
 337                 wqe->recv.sgl[i].stag = 0;
 338                 wqe->recv.sgl[i].len = 0;
 339                 wqe->recv.sgl[i].to = 0;
 340                 wqe->recv.pbl_addr[i] = 0;
 341         }
 342         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
 343                              qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
 344         qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
 345                              qhp->wq.rq_size_log2)].pbl_addr = pbl_addr;
 346         return 0;
 347 }
 348
 349 int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 350                       struct ib_send_wr **bad_wr)
 351 {
 352         int err = 0;
 353         u8 uninitialized_var(t3_wr_flit_cnt);
 354         enum t3_wr_opcode t3_wr_opcode = 0;
 355         enum t3_wr_flags t3_wr_flags;
 356         struct iwch_qp *qhp;
 357         u32 idx;
 358         union t3_wr *wqe;
 359         u32 num_wrs;
 360         unsigned long flag;
 361         struct t3_swsq *sqp;
 362         int wr_cnt = 1;
 363
 364         qhp = to_iwch_qp(ibqp);
 365         spin_lock_irqsave(&qhp->lock, flag);
 366         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
 367                 spin_unlock_irqrestore(&qhp->lock, flag);
 368                 return -EINVAL;
 369         }
 370         num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
 371                   qhp->wq.sq_size_log2);
 372         if (num_wrs <= 0) {
 373                 spin_unlock_irqrestore(&qhp->lock, flag);
 374                 return -ENOMEM;
 375         }
 376         while (wr) {
 377                 if (num_wrs == 0) {
 378                         err = -ENOMEM;
 379                         *bad_wr = wr;
 380                         break;
 381                 }
 382                 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
 383                 wqe = (union t3_wr *) (qhp->wq.queue + idx);
 384                 t3_wr_flags = 0;
 385                 if (wr->send_flags & IB_SEND_SOLICITED)
 386                         t3_wr_flags |= T3_SOLICITED_EVENT_FLAG;
 387                 if (wr->send_flags & IB_SEND_SIGNALED)
 388                         t3_wr_flags |= T3_COMPLETION_FLAG;
 389                 sqp = qhp->wq.sq +
 390                       Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
 391                 switch (wr->opcode) {
 392                 case IB_WR_SEND:
 393                 case IB_WR_SEND_WITH_INV:
 394                         if (wr->send_flags & IB_SEND_FENCE)
 395                                 t3_wr_flags |= T3_READ_FENCE_FLAG;
 396                         t3_wr_opcode = T3_WR_SEND;
 397                         err = build_rdma_send(wqe, wr, &t3_wr_flit_cnt);
 398                         break;
 399                 case IB_WR_RDMA_WRITE:
 400                 case IB_WR_RDMA_WRITE_WITH_IMM:
 401                         t3_wr_opcode = T3_WR_WRITE;
 402                         err = build_rdma_write(wqe, wr, &t3_wr_flit_cnt);
 403                         break;
 404                 case IB_WR_RDMA_READ:
 405                 case IB_WR_RDMA_READ_WITH_INV:
 406                         t3_wr_opcode = T3_WR_READ;
 407                         t3_wr_flags = 0; /* T3 reads are always signaled */
 408                         err = build_rdma_read(wqe, wr, &t3_wr_flit_cnt);
 409                         if (err)
 410                                 break;
 411                         sqp->read_len = wqe->read.local_len;
 412                         if (!qhp->wq.oldest_read)
 413                                 qhp->wq.oldest_read = sqp;
 414                         break;
 415                 case IB_WR_FAST_REG_MR:
 416                         t3_wr_opcode = T3_WR_FASTREG;
 417                         err = build_fastreg(wqe, wr, &t3_wr_flit_cnt,
 418                                                  &wr_cnt, &qhp->wq);
 419                         break;
 420                 case IB_WR_LOCAL_INV:
 421                         if (wr->send_flags & IB_SEND_FENCE)
 422                                 t3_wr_flags |= T3_LOCAL_FENCE_FLAG;
 423                         t3_wr_opcode = T3_WR_INV_STAG;
 424                         err = build_inv_stag(wqe, wr, &t3_wr_flit_cnt);
 425                         break;
 426                 default:
 427                         PDBG("%s post of type=%d TBD!\n", __func__,
 428                              wr->opcode);
 429                         err = -EINVAL;
 430                 }
 431                 if (err) {
 432                         *bad_wr = wr;
 433                         break;
 434                 }
 435                 wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
 436                 sqp->wr_id = wr->wr_id;
 437                 sqp->opcode = wr2opcode(t3_wr_opcode);
 438                 sqp->sq_wptr = qhp->wq.sq_wptr;
 439                 sqp->complete = 0;
 440                 sqp->signaled = (wr->send_flags & IB_SEND_SIGNALED);
 441
 442                 build_fw_riwrh((void *) wqe, t3_wr_opcode, t3_wr_flags,
 443                                Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
 444                                0, t3_wr_flit_cnt,
 445                                (wr_cnt == 1) ? T3_SOPEOP : T3_SOP);
 446                 PDBG("%s cookie 0x%llx wq idx 0x%x swsq idx %ld opcode %d\n",
 447                      __func__, (unsigned long long) wr->wr_id, idx,
 448                      Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2),
 449                      sqp->opcode);
 450                 wr = wr->next;
 451                 num_wrs--;
 452                 qhp->wq.wptr += wr_cnt;
 453                 ++(qhp->wq.sq_wptr);
 454         }
 455         spin_unlock_irqrestore(&qhp->lock, flag);
 456         ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
 457         return err;
 458 }
 459
 460 int iwch_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 461                       struct ib_recv_wr **bad_wr)
 462 {
 463         int err = 0;
 464         struct iwch_qp *qhp;
 465         u32 idx;
 466         union t3_wr *wqe;
 467         u32 num_wrs;
 468         unsigned long flag;
 469
 470         qhp = to_iwch_qp(ibqp);
 471         spin_lock_irqsave(&qhp->lock, flag);
 472         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
 473                 spin_unlock_irqrestore(&qhp->lock, flag);
 474                 return -EINVAL;
 475         }
 476         num_wrs = Q_FREECNT(qhp->wq.rq_rptr, qhp->wq.rq_wptr,
 477                             qhp->wq.rq_size_log2) - 1;
 478         if (!wr) {
 479                 spin_unlock_irqrestore(&qhp->lock, flag);
 480                 return -EINVAL;
 481         }
 482         while (wr) {
 483                 if (wr->num_sge > T3_MAX_SGE) {
 484                         err = -EINVAL;
 485                         *bad_wr = wr;
 486                         break;
 487                 }
 488                 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
 489                 wqe = (union t3_wr *) (qhp->wq.queue + idx);
 490                 if (num_wrs)
 491                         if (wr->sg_list[0].lkey)
 492                                 err = build_rdma_recv(qhp, wqe, wr);
 493                         else
 494                                 err = build_zero_stag_recv(qhp, wqe, wr);
 495                 else
 496                         err = -ENOMEM;
 497                 if (err) {
 498                         *bad_wr = wr;
 499                         break;
 500                 }
 501                 build_fw_riwrh((void *) wqe, T3_WR_RCV, T3_COMPLETION_FLAG,
 502                                Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
 503                                0, sizeof(struct t3_receive_wr) >> 3, T3_SOPEOP);
 504                 PDBG("%s cookie 0x%llx idx 0x%x rq_wptr 0x%x rw_rptr 0x%x "
 505                      "wqe %p \n", __func__, (unsigned long long) wr->wr_id,
 506                      idx, qhp->wq.rq_wptr, qhp->wq.rq_rptr, wqe);
 507                 ++(qhp->wq.rq_wptr);
 508                 ++(qhp->wq.wptr);
 509                 wr = wr->next;
 510                 num_wrs--;
 511         }
 512         spin_unlock_irqrestore(&qhp->lock, flag);
 513         ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
 514         return err;
 515 }
 516
 517 int iwch_bind_mw(struct ib_qp *qp,
 518                              struct ib_mw *mw,
 519                              struct ib_mw_bind *mw_bind)
 520 {
 521         struct iwch_dev *rhp;
 522         struct iwch_mw *mhp;
 523         struct iwch_qp *qhp;
 524         union t3_wr *wqe;
 525         u32 pbl_addr;
 526         u8 page_size;
 527         u32 num_wrs;
 528         unsigned long flag;
 529         struct ib_sge sgl;
 530         int err=0;
 531         enum t3_wr_flags t3_wr_flags;
 532         u32 idx;
 533         struct t3_swsq *sqp;
 534
 535         qhp = to_iwch_qp(qp);
 536         mhp = to_iwch_mw(mw);
 537         rhp = qhp->rhp;
 538
 539         spin_lock_irqsave(&qhp->lock, flag);
 540         if (qhp->attr.state > IWCH_QP_STATE_RTS) {
 541                 spin_unlock_irqrestore(&qhp->lock, flag);
 542                 return -EINVAL;
 543         }
 544         num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
 545                             qhp->wq.sq_size_log2);
 546         if ((num_wrs) <= 0) {
 547                 spin_unlock_irqrestore(&qhp->lock, flag);
 548                 return -ENOMEM;
 549         }
 550         idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
 551         PDBG("%s: idx 0x%0x, mw 0x%p, mw_bind 0x%p\n", __func__, idx,
 552              mw, mw_bind);
 553         wqe = (union t3_wr *) (qhp->wq.queue + idx);
 554
 555         t3_wr_flags = 0;
 556         if (mw_bind->send_flags & IB_SEND_SIGNALED)
 557                 t3_wr_flags = T3_COMPLETION_FLAG;
 558
 559         sgl.addr = mw_bind->addr;
 560         sgl.lkey = mw_bind->mr->lkey;
 561         sgl.length = mw_bind->length;
 562         wqe->bind.reserved = 0;
 563         wqe->bind.type = TPT_VATO;
 564
 565         /* TBD: check perms */
 566         wqe->bind.perms = iwch_ib_to_tpt_bind_access(mw_bind->mw_access_flags);
 567         wqe->bind.mr_stag = cpu_to_be32(mw_bind->mr->lkey);
 568         wqe->bind.mw_stag = cpu_to_be32(mw->rkey);
 569         wqe->bind.mw_len = cpu_to_be32(mw_bind->length);
 570         wqe->bind.mw_va = cpu_to_be64(mw_bind->addr);
 571         err = iwch_sgl2pbl_map(rhp, &sgl, 1, &pbl_addr, &page_size);
 572         if (err) {
 573                 spin_unlock_irqrestore(&qhp->lock, flag);
 574                 return err;
 575         }
 576         wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
 577         sqp = qhp->wq.sq + Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
 578         sqp->wr_id = mw_bind->wr_id;
 579         sqp->opcode = T3_BIND_MW;
 580         sqp->sq_wptr = qhp->wq.sq_wptr;
 581         sqp->complete = 0;
 582         sqp->signaled = (mw_bind->send_flags & IB_SEND_SIGNALED);
 583         wqe->bind.mr_pbl_addr = cpu_to_be32(pbl_addr);
 584         wqe->bind.mr_pagesz = page_size;
 585         build_fw_riwrh((void *)wqe, T3_WR_BIND, t3_wr_flags,
 586                        Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), 0,
 587                        sizeof(struct t3_bind_mw_wr) >> 3, T3_SOPEOP);
 588         ++(qhp->wq.wptr);
 589         ++(qhp->wq.sq_wptr);
 590         spin_unlock_irqrestore(&qhp->lock, flag);
 591
 592         ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
 593
 594         return err;
 595 }
 596
 597 static inline void build_term_codes(struct respQ_msg_t *rsp_msg,
 598                                     u8 *layer_type, u8 *ecode)
 599 {
 600         int status = TPT_ERR_INTERNAL_ERR;
 601         int tagged = 0;
 602         int opcode = -1;
 603         int rqtype = 0;
 604         int send_inv = 0;
 605
 606         if (rsp_msg) {
 607                 status = CQE_STATUS(rsp_msg->cqe);
 608                 opcode = CQE_OPCODE(rsp_msg->cqe);
 609                 rqtype = RQ_TYPE(rsp_msg->cqe);
 610                 send_inv = (opcode == T3_SEND_WITH_INV) ||
 611                            (opcode == T3_SEND_WITH_SE_INV);
 612                 tagged = (opcode == T3_RDMA_WRITE) ||
 613                          (rqtype && (opcode == T3_READ_RESP));
 614         }
 615
 616         switch (status) {
 617         case TPT_ERR_STAG:
 618                 if (send_inv) {
 619                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 620                         *ecode = RDMAP_CANT_INV_STAG;
 621                 } else {
 622                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 623                         *ecode = RDMAP_INV_STAG;
 624                 }
 625                 break;
 626         case TPT_ERR_PDID:
 627                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 628                 if ((opcode == T3_SEND_WITH_INV) ||
 629                     (opcode == T3_SEND_WITH_SE_INV))
 630                         *ecode = RDMAP_CANT_INV_STAG;
 631                 else
 632                         *ecode = RDMAP_STAG_NOT_ASSOC;
 633                 break;
 634         case TPT_ERR_QPID:
 635                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 636                 *ecode = RDMAP_STAG_NOT_ASSOC;
 637                 break;
 638         case TPT_ERR_ACCESS:
 639                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 640                 *ecode = RDMAP_ACC_VIOL;
 641                 break;
 642         case TPT_ERR_WRAP:
 643                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 644                 *ecode = RDMAP_TO_WRAP;
 645                 break;
 646         case TPT_ERR_BOUND:
 647                 if (tagged) {
 648                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 649                         *ecode = DDPT_BASE_BOUNDS;
 650                 } else {
 651                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 652                         *ecode = RDMAP_BASE_BOUNDS;
 653                 }
 654                 break;
 655         case TPT_ERR_INVALIDATE_SHARED_MR:
 656         case TPT_ERR_INVALIDATE_MR_WITH_MW_BOUND:
 657                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 658                 *ecode = RDMAP_CANT_INV_STAG;
 659                 break;
 660         case TPT_ERR_ECC:
 661         case TPT_ERR_ECC_PSTAG:
 662         case TPT_ERR_INTERNAL_ERR:
 663                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
 664                 *ecode = 0;
 665                 break;
 666         case TPT_ERR_OUT_OF_RQE:
 667                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 668                 *ecode = DDPU_INV_MSN_NOBUF;
 669                 break;
 670         case TPT_ERR_PBL_ADDR_BOUND:
 671                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 672                 *ecode = DDPT_BASE_BOUNDS;
 673                 break;
 674         case TPT_ERR_CRC:
 675                 *layer_type = LAYER_MPA|DDP_LLP;
 676                 *ecode = MPA_CRC_ERR;
 677                 break;
 678         case TPT_ERR_MARKER:
 679                 *layer_type = LAYER_MPA|DDP_LLP;
 680                 *ecode = MPA_MARKER_ERR;
 681                 break;
 682         case TPT_ERR_PDU_LEN_ERR:
 683                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 684                 *ecode = DDPU_MSG_TOOBIG;
 685                 break;
 686         case TPT_ERR_DDP_VERSION:
 687                 if (tagged) {
 688                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 689                         *ecode = DDPT_INV_VERS;
 690                 } else {
 691                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 692                         *ecode = DDPU_INV_VERS;
 693                 }
 694                 break;
 695         case TPT_ERR_RDMA_VERSION:
 696                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 697                 *ecode = RDMAP_INV_VERS;
 698                 break;
 699         case TPT_ERR_OPCODE:
 700                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 701                 *ecode = RDMAP_INV_OPCODE;
 702                 break;
 703         case TPT_ERR_DDP_QUEUE_NUM:
 704                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 705                 *ecode = DDPU_INV_QN;
 706                 break;
 707         case TPT_ERR_MSN:
 708         case TPT_ERR_MSN_GAP:
 709         case TPT_ERR_MSN_RANGE:
 710         case TPT_ERR_IRD_OVERFLOW:
 711                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 712                 *ecode = DDPU_INV_MSN_RANGE;
 713                 break;
 714         case TPT_ERR_TBIT:
 715                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
 716                 *ecode = 0;
 717                 break;
 718         case TPT_ERR_MO:
 719                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 720                 *ecode = DDPU_INV_MO;
 721                 break;
 722         default:
 723                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 724                 *ecode = 0;
 725                 break;
 726         }
 727 }
 728
 729 int iwch_post_zb_read(struct iwch_qp *qhp)
 730 {
 731         union t3_wr *wqe;
 732         struct sk_buff *skb;
 733         u8 flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
 734
 735         PDBG("%s enter\n", __func__);
 736         skb = alloc_skb(40, GFP_KERNEL);
 737         if (!skb) {
 738                 printk(KERN_ERR "%s cannot send zb_read!!\n", __func__);
 739                 return -ENOMEM;
 740         }
 741         wqe = (union t3_wr *)skb_put(skb, sizeof(struct t3_rdma_read_wr));
 742         memset(wqe, 0, sizeof(struct t3_rdma_read_wr));
 743         wqe->read.rdmaop = T3_READ_REQ;
 744         wqe->read.reserved[0] = 0;
 745         wqe->read.reserved[1] = 0;
 746         wqe->read.rem_stag = cpu_to_be32(1);
 747         wqe->read.rem_to = cpu_to_be64(1);
 748         wqe->read.local_stag = cpu_to_be32(1);
 749         wqe->read.local_len = cpu_to_be32(0);
 750         wqe->read.local_to = cpu_to_be64(1);
 751         wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_READ));
 752         wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid)|
 753                                                 V_FW_RIWR_LEN(flit_cnt));
 754         skb->priority = CPL_PRIORITY_DATA;
 755         return iwch_cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
 756 }
 757
 758 /*
 759  * This posts a TERMINATE with layer=RDMA, type=catastrophic.
 760  */
 761 int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg)
 762 {
 763         union t3_wr *wqe;
 764         struct terminate_message *term;
 765         struct sk_buff *skb;
 766
 767         PDBG("%s %d\n", __func__, __LINE__);
 768         skb = alloc_skb(40, GFP_ATOMIC);
 769         if (!skb) {
 770                 printk(KERN_ERR "%s cannot send TERMINATE!\n", __func__);
 771                 return -ENOMEM;
 772         }
 773         wqe = (union t3_wr *)skb_put(skb, 40);
 774         memset(wqe, 0, 40);
 775         wqe->send.rdmaop = T3_TERMINATE;
 776
 777         /* immediate data length */
 778         wqe->send.plen = htonl(4);
 779
 780         /* immediate data starts here. */
 781         term = (struct terminate_message *)wqe->send.sgl;
 782         build_term_codes(rsp_msg, &term->layer_etype, &term->ecode);
 783         wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_SEND) |
 784                          V_FW_RIWR_FLAGS(T3_COMPLETION_FLAG | T3_NOTIFY_FLAG));
 785         wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid));
 786         skb->priority = CPL_PRIORITY_DATA;
 787         return iwch_cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
 788 }
 789
 790 /*
 791  * Assumes qhp lock is held.
 792  */
 793 static void __flush_qp(struct iwch_qp *qhp, unsigned long *flag)
 794 {
 795         struct iwch_cq *rchp, *schp;
 796         int count;
 797         int flushed;
 798
 799         rchp = get_chp(qhp->rhp, qhp->attr.rcq);
 800         schp = get_chp(qhp->rhp, qhp->attr.scq);
 801
 802         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
 803         /* take a ref on the qhp since we must release the lock */
 804         atomic_inc(&qhp->refcnt);
 805         spin_unlock_irqrestore(&qhp->lock, *flag);
 806
 807         /* locking heirarchy: cq lock first, then qp lock. */
 808         spin_lock_irqsave(&rchp->lock, *flag);
 809         spin_lock(&qhp->lock);
 810         cxio_flush_hw_cq(&rchp->cq);
 811         cxio_count_rcqes(&rchp->cq, &qhp->wq, &count);
 812         flushed = cxio_flush_rq(&qhp->wq, &rchp->cq, count);
 813         spin_unlock(&qhp->lock);
 814         spin_unlock_irqrestore(&rchp->lock, *flag);
 815         if (flushed)
 816                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
 817
 818         /* locking heirarchy: cq lock first, then qp lock. */
 819         spin_lock_irqsave(&schp->lock, *flag);
 820         spin_lock(&qhp->lock);
 821         cxio_flush_hw_cq(&schp->cq);
 822         cxio_count_scqes(&schp->cq, &qhp->wq, &count);
 823         flushed = cxio_flush_sq(&qhp->wq, &schp->cq, count);
 824         spin_unlock(&qhp->lock);
 825         spin_unlock_irqrestore(&schp->lock, *flag);
 826         if (flushed)
 827                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
 828
 829         /* deref */
 830         if (atomic_dec_and_test(&qhp->refcnt))
 831                 wake_up(&qhp->wait);
 832
 833         spin_lock_irqsave(&qhp->lock, *flag);
 834 }
 835
 836 static void flush_qp(struct iwch_qp *qhp, unsigned long *flag)
 837 {
 838         if (qhp->ibqp.uobject)
 839                 cxio_set_wq_in_error(&qhp->wq);
 840         else
 841                 __flush_qp(qhp, flag);
 842 }
 843
 844
 845 /*
 846  * Return count of RECV WRs posted
 847  */
 848 u16 iwch_rqes_posted(struct iwch_qp *qhp)
 849 {
 850         union t3_wr *wqe = qhp->wq.queue;
 851         u16 count = 0;
 852         while ((count+1) != 0 && fw_riwrh_opcode((struct fw_riwrh *)wqe) == T3_WR_RCV) {
 853                 count++;
 854                 wqe++;
 855         }
 856         PDBG("%s qhp %p count %u\n", __func__, qhp, count);
 857         return count;
 858 }
 859
 860 static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp,
 861                                 enum iwch_qp_attr_mask mask,
 862                                 struct iwch_qp_attributes *attrs)
 863 {
 864         struct t3_rdma_init_attr init_attr;
 865         int ret;
 866
 867         init_attr.tid = qhp->ep->hwtid;
 868         init_attr.qpid = qhp->wq.qpid;
 869         init_attr.pdid = qhp->attr.pd;
 870         init_attr.scqid = qhp->attr.scq;
 871         init_attr.rcqid = qhp->attr.rcq;
 872         init_attr.rq_addr = qhp->wq.rq_addr;
 873         init_attr.rq_size = 1 << qhp->wq.rq_size_log2;
 874         init_attr.mpaattrs = uP_RI_MPA_IETF_ENABLE |
 875                 qhp->attr.mpa_attr.recv_marker_enabled |
 876                 (qhp->attr.mpa_attr.xmit_marker_enabled << 1) |
 877                 (qhp->attr.mpa_attr.crc_enabled << 2);
 878
 879         init_attr.qpcaps = uP_RI_QP_RDMA_READ_ENABLE |
 880                            uP_RI_QP_RDMA_WRITE_ENABLE |
 881                            uP_RI_QP_BIND_ENABLE;
 882         if (!qhp->ibqp.uobject)
 883                 init_attr.qpcaps |= uP_RI_QP_STAG0_ENABLE |
 884                                     uP_RI_QP_FAST_REGISTER_ENABLE;
 885
 886         init_attr.tcp_emss = qhp->ep->emss;
 887         init_attr.ord = qhp->attr.max_ord;
 888         init_attr.ird = qhp->attr.max_ird;
 889         init_attr.qp_dma_addr = qhp->wq.dma_addr;
 890         init_attr.qp_dma_size = (1UL << qhp->wq.size_log2);
 891         init_attr.rqe_count = iwch_rqes_posted(qhp);
 892         init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0;
 893         init_attr.chan = qhp->ep->l2t->smt_idx;
 894         if (peer2peer) {
 895                 init_attr.rtr_type = RTR_READ;
 896                 if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator)
 897                         init_attr.ord = 1;
 898                 if (init_attr.ird == 0 && !qhp->attr.mpa_attr.initiator)
 899                         init_attr.ird = 1;
 900         } else
 901                 init_attr.rtr_type = 0;
 902         init_attr.irs = qhp->ep->rcv_seq;
 903         PDBG("%s init_attr.rq_addr 0x%x init_attr.rq_size = %d "
 904              "flags 0x%x qpcaps 0x%x\n", __func__,
 905              init_attr.rq_addr, init_attr.rq_size,
 906              init_attr.flags, init_attr.qpcaps);
 907         ret = cxio_rdma_init(&rhp->rdev, &init_attr);
 908         PDBG("%s ret %d\n", __func__, ret);
 909         return ret;
 910 }
 911
 912 int iwch_modify_qp(struct iwch_dev *rhp, struct iwch_qp *qhp,
 913                                 enum iwch_qp_attr_mask mask,
 914                                 struct iwch_qp_attributes *attrs,
 915                                 int internal)
 916 {
 917         int ret = 0;
 918         struct iwch_qp_attributes newattr = qhp->attr;
 919         unsigned long flag;
 920         int disconnect = 0;
 921         int terminate = 0;
 922         int abort = 0;
 923         int free = 0;
 924         struct iwch_ep *ep = NULL;
 925
 926         PDBG("%s qhp %p qpid 0x%x ep %p state %d -> %d\n", __func__,
 927              qhp, qhp->wq.qpid, qhp->ep, qhp->attr.state,
 928              (mask & IWCH_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
 929
 930         spin_lock_irqsave(&qhp->lock, flag);
 931
 932         /* Process attr changes if in IDLE */
 933         if (mask & IWCH_QP_ATTR_VALID_MODIFY) {
 934                 if (qhp->attr.state != IWCH_QP_STATE_IDLE) {
 935                         ret = -EIO;
 936                         goto out;
 937                 }
 938                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_READ)
 939                         newattr.enable_rdma_read = attrs->enable_rdma_read;
 940                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_WRITE)
 941                         newattr.enable_rdma_write = attrs->enable_rdma_write;
 942                 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_BIND)
 943                         newattr.enable_bind = attrs->enable_bind;
 944                 if (mask & IWCH_QP_ATTR_MAX_ORD) {
 945                         if (attrs->max_ord >
 946                             rhp->attr.max_rdma_read_qp_depth) {
 947                                 ret = -EINVAL;
 948                                 goto out;
 949                         }
 950                         newattr.max_ord = attrs->max_ord;
 951                 }
 952                 if (mask & IWCH_QP_ATTR_MAX_IRD) {
 953                         if (attrs->max_ird >
 954                             rhp->attr.max_rdma_reads_per_qp) {
 955                                 ret = -EINVAL;
 956                                 goto out;
 957                         }
 958                         newattr.max_ird = attrs->max_ird;
 959                 }
 960                 qhp->attr = newattr;
 961         }
 962
 963         if (!(mask & IWCH_QP_ATTR_NEXT_STATE))
 964                 goto out;
 965         if (qhp->attr.state == attrs->next_state)
 966                 goto out;
 967
 968         switch (qhp->attr.state) {
 969         case IWCH_QP_STATE_IDLE:
 970                 switch (attrs->next_state) {
 971                 case IWCH_QP_STATE_RTS:
 972                         if (!(mask & IWCH_QP_ATTR_LLP_STREAM_HANDLE)) {
 973                                 ret = -EINVAL;
 974                                 goto out;
 975                         }
 976                         if (!(mask & IWCH_QP_ATTR_MPA_ATTR)) {
 977                                 ret = -EINVAL;
 978                                 goto out;
 979                         }
 980                         qhp->attr.mpa_attr = attrs->mpa_attr;
 981                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
 982                         qhp->ep = qhp->attr.llp_stream_handle;
 983                         qhp->attr.state = IWCH_QP_STATE_RTS;
 984
 985                         /*
 986                          * Ref the endpoint here and deref when we
 987                          * disassociate the endpoint from the QP.  This
 988                          * happens in CLOSING->IDLE transition or *->ERROR
 989                          * transition.
 990                          */
 991                         get_ep(&qhp->ep->com);
 992                         spin_unlock_irqrestore(&qhp->lock, flag);
 993                         ret = rdma_init(rhp, qhp, mask, attrs);
 994                         spin_lock_irqsave(&qhp->lock, flag);
 995                         if (ret)
 996                                 goto err;
 997                         break;
 998                 case IWCH_QP_STATE_ERROR:
 999                         qhp->attr.state = IWCH_QP_STATE_ERROR;
1000                         flush_qp(qhp, &flag);
1001                         break;
1002                 default:
1003                         ret = -EINVAL;
1004                         goto out;
1005                 }
1006                 break;
1007         case IWCH_QP_STATE_RTS:
1008                 switch (attrs->next_state) {
1009                 case IWCH_QP_STATE_CLOSING:
1010                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1011                         qhp->attr.state = IWCH_QP_STATE_CLOSING;
1012                         if (!internal) {
1013                                 abort=0;
1014                                 disconnect = 1;
1015                                 ep = qhp->ep;
1016                                 get_ep(&ep->com);
1017                         }
1018                         break;
1019                 case IWCH_QP_STATE_TERMINATE:
1020                         qhp->attr.state = IWCH_QP_STATE_TERMINATE;
1021                         if (qhp->ibqp.uobject)
1022                                 cxio_set_wq_in_error(&qhp->wq);
1023                         if (!internal)
1024                                 terminate = 1;
1025                         break;
1026                 case IWCH_QP_STATE_ERROR:
1027                         qhp->attr.state = IWCH_QP_STATE_ERROR;
1028                         if (!internal) {
1029                                 abort=1;
1030                                 disconnect = 1;
1031                                 ep = qhp->ep;
1032                                 get_ep(&ep->com);
1033                         }
1034                         goto err;
1035                         break;
1036                 default:
1037                         ret = -EINVAL;
1038                         goto out;
1039                 }
1040                 break;
1041         case IWCH_QP_STATE_CLOSING:
1042                 if (!internal) {
1043                         ret = -EINVAL;
1044                         goto out;
1045                 }
1046                 switch (attrs->next_state) {
1047                         case IWCH_QP_STATE_IDLE:
1048                                 flush_qp(qhp, &flag);
1049                                 qhp->attr.state = IWCH_QP_STATE_IDLE;
1050                                 qhp->attr.llp_stream_handle = NULL;
1051                                 put_ep(&qhp->ep->com);
1052                                 qhp->ep = NULL;
1053                                 wake_up(&qhp->wait);
1054                                 break;
1055                         case IWCH_QP_STATE_ERROR:
1056                                 goto err;
1057                         default:
1058                                 ret = -EINVAL;
1059                                 goto err;
1060                 }
1061                 break;
1062         case IWCH_QP_STATE_ERROR:
1063                 if (attrs->next_state != IWCH_QP_STATE_IDLE) {
1064                         ret = -EINVAL;
1065                         goto out;
1066                 }
1067
1068                 if (!Q_EMPTY(qhp->wq.sq_rptr, qhp->wq.sq_wptr) ||
1069                     !Q_EMPTY(qhp->wq.rq_rptr, qhp->wq.rq_wptr)) {
1070                         ret = -EINVAL;
1071                         goto out;
1072                 }
1073                 qhp->attr.state = IWCH_QP_STATE_IDLE;
1074                 break;
1075         case IWCH_QP_STATE_TERMINATE:
1076                 if (!internal) {
1077                         ret = -EINVAL;
1078                         goto out;
1079                 }
1080                 goto err;
1081                 break;
1082         default:
1083                 printk(KERN_ERR "%s in a bad state %d\n",
1084                        __func__, qhp->attr.state);
1085                 ret = -EINVAL;
1086                 goto err;
1087                 break;
1088         }
1089         goto out;
1090 err:
1091         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1092              qhp->wq.qpid);
1093
1094         /* disassociate the LLP connection */
1095         qhp->attr.llp_stream_handle = NULL;
1096         ep = qhp->ep;
1097         qhp->ep = NULL;
1098         qhp->attr.state = IWCH_QP_STATE_ERROR;
1099         free=1;
1100         wake_up(&qhp->wait);
1101         BUG_ON(!ep);
1102         flush_qp(qhp, &flag);
1103 out:
1104         spin_unlock_irqrestore(&qhp->lock, flag);
1105
1106         if (terminate)
1107                 iwch_post_terminate(qhp, NULL);
1108
1109         /*
1110          * If disconnect is 1, then we need to initiate a disconnect
1111          * on the EP.  This can be a normal close (RTS->CLOSING) or
1112          * an abnormal close (RTS/CLOSING->ERROR).
1113          */
1114         if (disconnect) {
1115                 iwch_ep_disconnect(ep, abort, GFP_KERNEL);
1116                 put_ep(&ep->com);
1117         }
1118
1119         /*
1120          * If free is 1, then we've disassociated the EP from the QP
1121          * and we need to dereference the EP.
1122          */
1123         if (free)
1124                 put_ep(&ep->com);
1125
1126         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1127         return ret;
1128 }
1129
1130 static int quiesce_qp(struct iwch_qp *qhp)
1131 {
1132         spin_lock_irq(&qhp->lock);
1133         iwch_quiesce_tid(qhp->ep);
1134         qhp->flags |= QP_QUIESCED;
1135         spin_unlock_irq(&qhp->lock);
1136         return 0;
1137 }
1138
1139 static int resume_qp(struct iwch_qp *qhp)
1140 {
1141         spin_lock_irq(&qhp->lock);
1142         iwch_resume_tid(qhp->ep);
1143         qhp->flags &= ~QP_QUIESCED;
1144         spin_unlock_irq(&qhp->lock);
1145         return 0;
1146 }
1147
1148 int iwch_quiesce_qps(struct iwch_cq *chp)
1149 {
1150         int i;
1151         struct iwch_qp *qhp;
1152
1153         for (i=0; i < T3_MAX_NUM_QP; i++) {
1154                 qhp = get_qhp(chp->rhp, i);
1155                 if (!qhp)
1156                         continue;
1157                 if ((qhp->attr.rcq == chp->cq.cqid) && !qp_quiesced(qhp)) {
1158                         quiesce_qp(qhp);
1159                         continue;
1160                 }
1161                 if ((qhp->attr.scq == chp->cq.cqid) && !qp_quiesced(qhp))
1162                         quiesce_qp(qhp);
1163         }
1164         return 0;
1165 }
1166
1167 int iwch_resume_qps(struct iwch_cq *chp)
1168 {
1169         int i;
1170         struct iwch_qp *qhp;
1171
1172         for (i=0; i < T3_MAX_NUM_QP; i++) {
1173                 qhp = get_qhp(chp->rhp, i);
1174                 if (!qhp)
1175                         continue;
1176                 if ((qhp->attr.rcq == chp->cq.cqid) && qp_quiesced(qhp)) {
1177                         resume_qp(qhp);
1178                         continue;
1179                 }
1180                 if ((qhp->attr.scq == chp->cq.cqid) && qp_quiesced(qhp))
1181                         resume_qp(qhp);
1182         }
1183         return 0;
1184 }