1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Invensense, Inc.
6 #include <linux/module.h>
7 #include <linux/slab.h>
10 #include <linux/delay.h>
11 #include <linux/sysfs.h>
12 #include <linux/jiffies.h>
13 #include <linux/irq.h>
14 #include <linux/interrupt.h>
15 #include <linux/iio/iio.h>
16 #include <linux/acpi.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include "inv_mpu_iio.h"
22 * this is the gyro scale translated from dynamic range plus/minus
23 * {250, 500, 1000, 2000} to rad/s
25 static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
28 * this is the accel scale translated from dynamic range plus/minus
29 * {2, 4, 8, 16} to m/s^2
31 static const int accel_scale[] = {598, 1196, 2392, 4785};
33 static const struct inv_mpu6050_reg_map reg_set_icm20602 = {
34 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
35 .lpf = INV_MPU6050_REG_CONFIG,
36 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
37 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
38 .fifo_en = INV_MPU6050_REG_FIFO_EN,
39 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
40 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
41 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
42 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
43 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
44 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
45 .temperature = INV_MPU6050_REG_TEMPERATURE,
46 .int_enable = INV_MPU6050_REG_INT_ENABLE,
47 .int_status = INV_MPU6050_REG_INT_STATUS,
48 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
49 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
50 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
51 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
52 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
53 .i2c_if = INV_ICM20602_REG_I2C_IF,
56 static const struct inv_mpu6050_reg_map reg_set_6500 = {
57 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
58 .lpf = INV_MPU6050_REG_CONFIG,
59 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
60 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
61 .fifo_en = INV_MPU6050_REG_FIFO_EN,
62 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
63 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
64 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
65 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
66 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
67 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
68 .temperature = INV_MPU6050_REG_TEMPERATURE,
69 .int_enable = INV_MPU6050_REG_INT_ENABLE,
70 .int_status = INV_MPU6050_REG_INT_STATUS,
71 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
72 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
73 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
74 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
75 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
79 static const struct inv_mpu6050_reg_map reg_set_6050 = {
80 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
81 .lpf = INV_MPU6050_REG_CONFIG,
82 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
83 .fifo_en = INV_MPU6050_REG_FIFO_EN,
84 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
85 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
86 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
87 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
88 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
89 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
90 .temperature = INV_MPU6050_REG_TEMPERATURE,
91 .int_enable = INV_MPU6050_REG_INT_ENABLE,
92 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
93 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
94 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
95 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
96 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
100 static const struct inv_mpu6050_chip_config chip_config_6050 = {
101 .fsr = INV_MPU6050_FSR_2000DPS,
102 .lpf = INV_MPU6050_FILTER_20HZ,
103 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(INV_MPU6050_INIT_FIFO_RATE),
104 .gyro_fifo_enable = false,
105 .accl_fifo_enable = false,
106 .accl_fs = INV_MPU6050_FS_02G,
110 /* Indexed by enum inv_devices */
111 static const struct inv_mpu6050_hw hw_info[] = {
113 .whoami = INV_MPU6050_WHOAMI_VALUE,
115 .reg = ®_set_6050,
116 .config = &chip_config_6050,
119 .whoami = INV_MPU6500_WHOAMI_VALUE,
121 .reg = ®_set_6500,
122 .config = &chip_config_6050,
125 .whoami = INV_MPU6515_WHOAMI_VALUE,
127 .reg = ®_set_6500,
128 .config = &chip_config_6050,
131 .whoami = INV_MPU6000_WHOAMI_VALUE,
133 .reg = ®_set_6050,
134 .config = &chip_config_6050,
137 .whoami = INV_MPU9150_WHOAMI_VALUE,
139 .reg = ®_set_6050,
140 .config = &chip_config_6050,
143 .whoami = INV_MPU9250_WHOAMI_VALUE,
145 .reg = ®_set_6500,
146 .config = &chip_config_6050,
149 .whoami = INV_MPU9255_WHOAMI_VALUE,
151 .reg = ®_set_6500,
152 .config = &chip_config_6050,
155 .whoami = INV_ICM20608_WHOAMI_VALUE,
157 .reg = ®_set_6500,
158 .config = &chip_config_6050,
161 .whoami = INV_ICM20602_WHOAMI_VALUE,
163 .reg = ®_set_icm20602,
164 .config = &chip_config_6050,
168 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask)
170 unsigned int d, mgmt_1;
173 * switch clock needs to be careful. Only when gyro is on, can
174 * clock source be switched to gyro. Otherwise, it must be set to
177 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
178 result = regmap_read(st->map, st->reg->pwr_mgmt_1, &mgmt_1);
182 mgmt_1 &= ~INV_MPU6050_BIT_CLK_MASK;
185 if ((mask == INV_MPU6050_BIT_PWR_GYRO_STBY) && (!en)) {
187 * turning off gyro requires switch to internal clock first.
188 * Then turn off gyro engine
190 mgmt_1 |= INV_CLK_INTERNAL;
191 result = regmap_write(st->map, st->reg->pwr_mgmt_1, mgmt_1);
196 result = regmap_read(st->map, st->reg->pwr_mgmt_2, &d);
203 result = regmap_write(st->map, st->reg->pwr_mgmt_2, d);
208 /* Wait for output to stabilize */
209 msleep(INV_MPU6050_TEMP_UP_TIME);
210 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
211 /* switch internal clock to PLL */
212 mgmt_1 |= INV_CLK_PLL;
213 result = regmap_write(st->map,
214 st->reg->pwr_mgmt_1, mgmt_1);
223 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on)
228 if (!st->powerup_count) {
229 result = regmap_write(st->map, st->reg->pwr_mgmt_1, 0);
232 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
233 INV_MPU6050_REG_UP_TIME_MAX);
237 if (st->powerup_count == 1) {
238 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
239 INV_MPU6050_BIT_SLEEP);
246 dev_dbg(regmap_get_device(st->map), "set power %d, count=%u\n",
247 power_on, st->powerup_count);
251 EXPORT_SYMBOL_GPL(inv_mpu6050_set_power_itg);
254 * inv_mpu6050_set_lpf_regs() - set low pass filter registers, chip dependent
256 * MPU60xx/MPU9150 use only 1 register for accelerometer + gyroscope
257 * MPU6500 and above have a dedicated register for accelerometer
259 static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
260 enum inv_mpu6050_filter_e val)
264 result = regmap_write(st->map, st->reg->lpf, val);
268 switch (st->chip_type) {
272 /* old chips, nothing to do */
277 result = regmap_write(st->map, st->reg->accel_lpf, val);
285 * inv_mpu6050_init_config() - Initialize hardware, disable FIFO.
287 * Initial configuration:
291 * Clock source: Gyro PLL
293 static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
297 struct inv_mpu6050_state *st = iio_priv(indio_dev);
299 result = inv_mpu6050_set_power_itg(st, true);
302 d = (INV_MPU6050_FSR_2000DPS << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
303 result = regmap_write(st->map, st->reg->gyro_config, d);
305 goto error_power_off;
307 result = inv_mpu6050_set_lpf_regs(st, INV_MPU6050_FILTER_20HZ);
309 goto error_power_off;
311 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(INV_MPU6050_INIT_FIFO_RATE);
312 result = regmap_write(st->map, st->reg->sample_rate_div, d);
314 goto error_power_off;
316 d = (INV_MPU6050_FS_02G << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
317 result = regmap_write(st->map, st->reg->accl_config, d);
319 goto error_power_off;
321 result = regmap_write(st->map, st->reg->int_pin_cfg, st->irq_mask);
325 memcpy(&st->chip_config, hw_info[st->chip_type].config,
326 sizeof(struct inv_mpu6050_chip_config));
329 * Internal chip period is 1ms (1kHz).
330 * Let's use at the beginning the theorical value before measuring
331 * with interrupt timestamps.
333 st->chip_period = NSEC_PER_MSEC;
335 return inv_mpu6050_set_power_itg(st, false);
338 inv_mpu6050_set_power_itg(st, false);
342 static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
346 __be16 d = cpu_to_be16(val);
348 ind = (axis - IIO_MOD_X) * 2;
349 result = regmap_bulk_write(st->map, reg + ind, (u8 *)&d, 2);
356 static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
362 ind = (axis - IIO_MOD_X) * 2;
363 result = regmap_bulk_read(st->map, reg + ind, (u8 *)&d, 2);
366 *val = (short)be16_to_cpup(&d);
371 static int inv_mpu6050_read_channel_data(struct iio_dev *indio_dev,
372 struct iio_chan_spec const *chan,
375 struct inv_mpu6050_state *st = iio_priv(indio_dev);
379 result = inv_mpu6050_set_power_itg(st, true);
383 switch (chan->type) {
385 result = inv_mpu6050_switch_engine(st, true,
386 INV_MPU6050_BIT_PWR_GYRO_STBY);
388 goto error_power_off;
389 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
390 chan->channel2, val);
391 result = inv_mpu6050_switch_engine(st, false,
392 INV_MPU6050_BIT_PWR_GYRO_STBY);
394 goto error_power_off;
397 result = inv_mpu6050_switch_engine(st, true,
398 INV_MPU6050_BIT_PWR_ACCL_STBY);
400 goto error_power_off;
401 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
402 chan->channel2, val);
403 result = inv_mpu6050_switch_engine(st, false,
404 INV_MPU6050_BIT_PWR_ACCL_STBY);
406 goto error_power_off;
409 /* wait for stablization */
410 msleep(INV_MPU6050_SENSOR_UP_TIME);
411 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
419 result = inv_mpu6050_set_power_itg(st, false);
421 goto error_power_off;
426 inv_mpu6050_set_power_itg(st, false);
431 inv_mpu6050_read_raw(struct iio_dev *indio_dev,
432 struct iio_chan_spec const *chan,
433 int *val, int *val2, long mask)
435 struct inv_mpu6050_state *st = iio_priv(indio_dev);
439 case IIO_CHAN_INFO_RAW:
440 ret = iio_device_claim_direct_mode(indio_dev);
443 mutex_lock(&st->lock);
444 ret = inv_mpu6050_read_channel_data(indio_dev, chan, val);
445 mutex_unlock(&st->lock);
446 iio_device_release_direct_mode(indio_dev);
448 case IIO_CHAN_INFO_SCALE:
449 switch (chan->type) {
451 mutex_lock(&st->lock);
453 *val2 = gyro_scale_6050[st->chip_config.fsr];
454 mutex_unlock(&st->lock);
456 return IIO_VAL_INT_PLUS_NANO;
458 mutex_lock(&st->lock);
460 *val2 = accel_scale[st->chip_config.accl_fs];
461 mutex_unlock(&st->lock);
463 return IIO_VAL_INT_PLUS_MICRO;
466 if (st->chip_type == INV_ICM20602)
467 *val2 = INV_ICM20602_TEMP_SCALE;
469 *val2 = INV_MPU6050_TEMP_SCALE;
471 return IIO_VAL_INT_PLUS_MICRO;
475 case IIO_CHAN_INFO_OFFSET:
476 switch (chan->type) {
478 if (st->chip_type == INV_ICM20602)
479 *val = INV_ICM20602_TEMP_OFFSET;
481 *val = INV_MPU6050_TEMP_OFFSET;
487 case IIO_CHAN_INFO_CALIBBIAS:
488 switch (chan->type) {
490 mutex_lock(&st->lock);
491 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
492 chan->channel2, val);
493 mutex_unlock(&st->lock);
496 mutex_lock(&st->lock);
497 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
498 chan->channel2, val);
499 mutex_unlock(&st->lock);
510 static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val)
515 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
516 if (gyro_scale_6050[i] == val) {
517 d = (i << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
518 result = regmap_write(st->map, st->reg->gyro_config, d);
522 st->chip_config.fsr = i;
530 static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
531 struct iio_chan_spec const *chan, long mask)
534 case IIO_CHAN_INFO_SCALE:
535 switch (chan->type) {
537 return IIO_VAL_INT_PLUS_NANO;
539 return IIO_VAL_INT_PLUS_MICRO;
542 return IIO_VAL_INT_PLUS_MICRO;
548 static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val)
553 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
554 if (accel_scale[i] == val) {
555 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
556 result = regmap_write(st->map, st->reg->accl_config, d);
560 st->chip_config.accl_fs = i;
568 static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
569 struct iio_chan_spec const *chan,
570 int val, int val2, long mask)
572 struct inv_mpu6050_state *st = iio_priv(indio_dev);
576 * we should only update scale when the chip is disabled, i.e.
579 result = iio_device_claim_direct_mode(indio_dev);
583 mutex_lock(&st->lock);
584 result = inv_mpu6050_set_power_itg(st, true);
586 goto error_write_raw_unlock;
589 case IIO_CHAN_INFO_SCALE:
590 switch (chan->type) {
592 result = inv_mpu6050_write_gyro_scale(st, val2);
595 result = inv_mpu6050_write_accel_scale(st, val2);
602 case IIO_CHAN_INFO_CALIBBIAS:
603 switch (chan->type) {
605 result = inv_mpu6050_sensor_set(st,
606 st->reg->gyro_offset,
607 chan->channel2, val);
610 result = inv_mpu6050_sensor_set(st,
611 st->reg->accl_offset,
612 chan->channel2, val);
624 result |= inv_mpu6050_set_power_itg(st, false);
625 error_write_raw_unlock:
626 mutex_unlock(&st->lock);
627 iio_device_release_direct_mode(indio_dev);
633 * inv_mpu6050_set_lpf() - set low pass filer based on fifo rate.
635 * Based on the Nyquist principle, the sampling rate must
636 * exceed twice of the bandwidth of the signal, or there
637 * would be alising. This function basically search for the
638 * correct low pass parameters based on the fifo rate, e.g,
639 * sampling frequency.
641 * lpf is set automatically when setting sampling rate to avoid any aliases.
643 static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
645 static const int hz[] = {188, 98, 42, 20, 10, 5};
646 static const int d[] = {
647 INV_MPU6050_FILTER_188HZ, INV_MPU6050_FILTER_98HZ,
648 INV_MPU6050_FILTER_42HZ, INV_MPU6050_FILTER_20HZ,
649 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ
656 while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))
659 result = inv_mpu6050_set_lpf_regs(st, data);
662 st->chip_config.lpf = data;
668 * inv_mpu6050_fifo_rate_store() - Set fifo rate.
671 inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
672 const char *buf, size_t count)
677 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
678 struct inv_mpu6050_state *st = iio_priv(indio_dev);
680 if (kstrtoint(buf, 10, &fifo_rate))
682 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
683 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
686 result = iio_device_claim_direct_mode(indio_dev);
690 /* compute the chip sample rate divider */
691 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate);
692 /* compute back the fifo rate to handle truncation cases */
693 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(d);
695 mutex_lock(&st->lock);
696 if (d == st->chip_config.divider) {
698 goto fifo_rate_fail_unlock;
700 result = inv_mpu6050_set_power_itg(st, true);
702 goto fifo_rate_fail_unlock;
704 result = regmap_write(st->map, st->reg->sample_rate_div, d);
706 goto fifo_rate_fail_power_off;
707 st->chip_config.divider = d;
709 result = inv_mpu6050_set_lpf(st, fifo_rate);
711 goto fifo_rate_fail_power_off;
713 fifo_rate_fail_power_off:
714 result |= inv_mpu6050_set_power_itg(st, false);
715 fifo_rate_fail_unlock:
716 mutex_unlock(&st->lock);
717 iio_device_release_direct_mode(indio_dev);
725 * inv_fifo_rate_show() - Get the current sampling rate.
728 inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
731 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
734 mutex_lock(&st->lock);
735 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
736 mutex_unlock(&st->lock);
738 return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate);
742 * inv_attr_show() - calling this function will show current
745 * Deprecated in favor of IIO mounting matrix API.
747 * See inv_get_mount_matrix()
749 static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
752 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
753 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
756 switch (this_attr->address) {
758 * In MPU6050, the two matrix are the same because gyro and accel
759 * are integrated in one chip
761 case ATTR_GYRO_MATRIX:
762 case ATTR_ACCL_MATRIX:
763 m = st->plat_data.orientation;
765 return scnprintf(buf, PAGE_SIZE,
766 "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
767 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
774 * inv_mpu6050_validate_trigger() - validate_trigger callback for invensense
776 * @indio_dev: The IIO device
777 * @trig: The new trigger
779 * Returns: 0 if the 'trig' matches the trigger registered by the MPU6050
780 * device, -EINVAL otherwise.
782 static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
783 struct iio_trigger *trig)
785 struct inv_mpu6050_state *st = iio_priv(indio_dev);
787 if (st->trig != trig)
793 static const struct iio_mount_matrix *
794 inv_get_mount_matrix(const struct iio_dev *indio_dev,
795 const struct iio_chan_spec *chan)
797 struct inv_mpu6050_state *data = iio_priv(indio_dev);
799 return &data->orientation;
802 static const struct iio_chan_spec_ext_info inv_ext_info[] = {
803 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
807 #define INV_MPU6050_CHAN(_type, _channel2, _index) \
811 .channel2 = _channel2, \
812 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
813 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
814 BIT(IIO_CHAN_INFO_CALIBBIAS), \
815 .scan_index = _index, \
821 .endianness = IIO_BE, \
823 .ext_info = inv_ext_info, \
826 static const struct iio_chan_spec inv_mpu_channels[] = {
827 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
829 * Note that temperature should only be via polled reading only,
830 * not the final scan elements output.
834 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)
835 | BIT(IIO_CHAN_INFO_OFFSET)
836 | BIT(IIO_CHAN_INFO_SCALE),
839 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
840 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
841 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
843 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
844 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
845 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
848 static const unsigned long inv_mpu_scan_masks[] = {
850 BIT(INV_MPU6050_SCAN_ACCL_X)
851 | BIT(INV_MPU6050_SCAN_ACCL_Y)
852 | BIT(INV_MPU6050_SCAN_ACCL_Z),
854 BIT(INV_MPU6050_SCAN_GYRO_X)
855 | BIT(INV_MPU6050_SCAN_GYRO_Y)
856 | BIT(INV_MPU6050_SCAN_GYRO_Z),
857 /* 6-axis accel + gyro */
858 BIT(INV_MPU6050_SCAN_ACCL_X)
859 | BIT(INV_MPU6050_SCAN_ACCL_Y)
860 | BIT(INV_MPU6050_SCAN_ACCL_Z)
861 | BIT(INV_MPU6050_SCAN_GYRO_X)
862 | BIT(INV_MPU6050_SCAN_GYRO_Y)
863 | BIT(INV_MPU6050_SCAN_GYRO_Z),
867 static const struct iio_chan_spec inv_icm20602_channels[] = {
868 IIO_CHAN_SOFT_TIMESTAMP(INV_ICM20602_SCAN_TIMESTAMP),
871 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)
872 | BIT(IIO_CHAN_INFO_OFFSET)
873 | BIT(IIO_CHAN_INFO_SCALE),
874 .scan_index = INV_ICM20602_SCAN_TEMP,
880 .endianness = IIO_BE,
884 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_ICM20602_SCAN_GYRO_X),
885 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_ICM20602_SCAN_GYRO_Y),
886 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_ICM20602_SCAN_GYRO_Z),
888 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_ICM20602_SCAN_ACCL_Y),
889 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_ICM20602_SCAN_ACCL_X),
890 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_ICM20602_SCAN_ACCL_Z),
893 static const unsigned long inv_icm20602_scan_masks[] = {
894 /* 3-axis accel + temp (mandatory) */
895 BIT(INV_ICM20602_SCAN_ACCL_X)
896 | BIT(INV_ICM20602_SCAN_ACCL_Y)
897 | BIT(INV_ICM20602_SCAN_ACCL_Z)
898 | BIT(INV_ICM20602_SCAN_TEMP),
899 /* 3-axis gyro + temp (mandatory) */
900 BIT(INV_ICM20602_SCAN_GYRO_X)
901 | BIT(INV_ICM20602_SCAN_GYRO_Y)
902 | BIT(INV_ICM20602_SCAN_GYRO_Z)
903 | BIT(INV_ICM20602_SCAN_TEMP),
904 /* 6-axis accel + gyro + temp (mandatory) */
905 BIT(INV_ICM20602_SCAN_ACCL_X)
906 | BIT(INV_ICM20602_SCAN_ACCL_Y)
907 | BIT(INV_ICM20602_SCAN_ACCL_Z)
908 | BIT(INV_ICM20602_SCAN_GYRO_X)
909 | BIT(INV_ICM20602_SCAN_GYRO_Y)
910 | BIT(INV_ICM20602_SCAN_GYRO_Z)
911 | BIT(INV_ICM20602_SCAN_TEMP),
916 * The user can choose any frequency between INV_MPU6050_MIN_FIFO_RATE and
917 * INV_MPU6050_MAX_FIFO_RATE, but only these frequencies are matched by the
918 * low-pass filter. Specifically, each of these sampling rates are about twice
919 * the bandwidth of a corresponding low-pass filter, which should eliminate
920 * aliasing following the Nyquist principle. By picking a frequency different
921 * from these, the user risks aliasing effects.
923 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
924 static IIO_CONST_ATTR(in_anglvel_scale_available,
925 "0.000133090 0.000266181 0.000532362 0.001064724");
926 static IIO_CONST_ATTR(in_accel_scale_available,
927 "0.000598 0.001196 0.002392 0.004785");
928 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
929 inv_mpu6050_fifo_rate_store);
931 /* Deprecated: kept for userspace backward compatibility. */
932 static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
934 static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
937 static struct attribute *inv_attributes[] = {
938 &iio_dev_attr_in_gyro_matrix.dev_attr.attr, /* deprecated */
939 &iio_dev_attr_in_accel_matrix.dev_attr.attr, /* deprecated */
940 &iio_dev_attr_sampling_frequency.dev_attr.attr,
941 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
942 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
943 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
947 static const struct attribute_group inv_attribute_group = {
948 .attrs = inv_attributes
951 static const struct iio_info mpu_info = {
952 .read_raw = &inv_mpu6050_read_raw,
953 .write_raw = &inv_mpu6050_write_raw,
954 .write_raw_get_fmt = &inv_write_raw_get_fmt,
955 .attrs = &inv_attribute_group,
956 .validate_trigger = inv_mpu6050_validate_trigger,
960 * inv_check_and_setup_chip() - check and setup chip.
962 static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
968 st->hw = &hw_info[st->chip_type];
969 st->reg = hw_info[st->chip_type].reg;
971 /* check chip self-identification */
972 result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val);
975 if (regval != st->hw->whoami) {
976 /* check whoami against all possible values */
977 for (i = 0; i < INV_NUM_PARTS; ++i) {
978 if (regval == hw_info[i].whoami) {
979 dev_warn(regmap_get_device(st->map),
980 "whoami mismatch got %#02x (%s)"
981 "expected %#02hhx (%s)\n",
982 regval, hw_info[i].name,
983 st->hw->whoami, st->hw->name);
987 if (i >= INV_NUM_PARTS) {
988 dev_err(regmap_get_device(st->map),
989 "invalid whoami %#02x expected %#02hhx (%s)\n",
990 regval, st->hw->whoami, st->hw->name);
995 /* reset to make sure previous state are not there */
996 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
997 INV_MPU6050_BIT_H_RESET);
1000 msleep(INV_MPU6050_POWER_UP_TIME);
1003 * Turn power on. After reset, the sleep bit could be on
1004 * or off depending on the OTP settings. Turning power on
1005 * make it in a definite state as well as making the hardware
1006 * state align with the software state
1008 result = inv_mpu6050_set_power_itg(st, true);
1012 result = inv_mpu6050_switch_engine(st, false,
1013 INV_MPU6050_BIT_PWR_ACCL_STBY);
1015 goto error_power_off;
1016 result = inv_mpu6050_switch_engine(st, false,
1017 INV_MPU6050_BIT_PWR_GYRO_STBY);
1019 goto error_power_off;
1021 return inv_mpu6050_set_power_itg(st, false);
1024 inv_mpu6050_set_power_itg(st, false);
1028 static int inv_mpu_core_enable_regulator(struct inv_mpu6050_state *st)
1032 result = regulator_enable(st->vddio_supply);
1034 dev_err(regmap_get_device(st->map),
1035 "Failed to enable regulator: %d\n", result);
1037 /* Give the device a little bit of time to start up. */
1038 usleep_range(35000, 70000);
1044 static int inv_mpu_core_disable_regulator(struct inv_mpu6050_state *st)
1048 result = regulator_disable(st->vddio_supply);
1050 dev_err(regmap_get_device(st->map),
1051 "Failed to disable regulator: %d\n", result);
1056 static void inv_mpu_core_disable_regulator_action(void *_data)
1058 inv_mpu_core_disable_regulator(_data);
1061 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
1062 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
1064 struct inv_mpu6050_state *st;
1065 struct iio_dev *indio_dev;
1066 struct inv_mpu6050_platform_data *pdata;
1067 struct device *dev = regmap_get_device(regmap);
1069 struct irq_data *desc;
1072 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1076 BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
1077 if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
1078 dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
1082 st = iio_priv(indio_dev);
1083 mutex_init(&st->lock);
1084 st->chip_type = chip_type;
1085 st->powerup_count = 0;
1089 pdata = dev_get_platdata(dev);
1091 result = iio_read_mount_matrix(dev, "mount-matrix",
1094 dev_err(dev, "Failed to retrieve mounting matrix %d\n",
1099 st->plat_data = *pdata;
1102 desc = irq_get_irq_data(irq);
1104 dev_err(dev, "Could not find IRQ %d\n", irq);
1108 irq_type = irqd_get_trigger_type(desc);
1110 irq_type = IRQF_TRIGGER_RISING;
1111 if (irq_type == IRQF_TRIGGER_RISING)
1112 st->irq_mask = INV_MPU6050_ACTIVE_HIGH;
1113 else if (irq_type == IRQF_TRIGGER_FALLING)
1114 st->irq_mask = INV_MPU6050_ACTIVE_LOW;
1115 else if (irq_type == IRQF_TRIGGER_HIGH)
1116 st->irq_mask = INV_MPU6050_ACTIVE_HIGH |
1117 INV_MPU6050_LATCH_INT_EN;
1118 else if (irq_type == IRQF_TRIGGER_LOW)
1119 st->irq_mask = INV_MPU6050_ACTIVE_LOW |
1120 INV_MPU6050_LATCH_INT_EN;
1122 dev_err(dev, "Invalid interrupt type 0x%x specified\n",
1127 st->vddio_supply = devm_regulator_get(dev, "vddio");
1128 if (IS_ERR(st->vddio_supply)) {
1129 if (PTR_ERR(st->vddio_supply) != -EPROBE_DEFER)
1130 dev_err(dev, "Failed to get vddio regulator %d\n",
1131 (int)PTR_ERR(st->vddio_supply));
1133 return PTR_ERR(st->vddio_supply);
1136 result = inv_mpu_core_enable_regulator(st);
1140 result = devm_add_action(dev, inv_mpu_core_disable_regulator_action,
1143 inv_mpu_core_disable_regulator_action(st);
1144 dev_err(dev, "Failed to setup regulator cleanup action %d\n",
1149 /* power is turned on inside check chip type*/
1150 result = inv_check_and_setup_chip(st);
1154 result = inv_mpu6050_init_config(indio_dev);
1156 dev_err(dev, "Could not initialize device.\n");
1160 if (inv_mpu_bus_setup)
1161 inv_mpu_bus_setup(indio_dev);
1163 dev_set_drvdata(dev, indio_dev);
1164 indio_dev->dev.parent = dev;
1165 /* name will be NULL when enumerated via ACPI */
1167 indio_dev->name = name;
1169 indio_dev->name = dev_name(dev);
1171 if (chip_type == INV_ICM20602) {
1172 indio_dev->channels = inv_icm20602_channels;
1173 indio_dev->num_channels = ARRAY_SIZE(inv_icm20602_channels);
1174 indio_dev->available_scan_masks = inv_icm20602_scan_masks;
1176 indio_dev->channels = inv_mpu_channels;
1177 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1178 indio_dev->available_scan_masks = inv_mpu_scan_masks;
1181 indio_dev->info = &mpu_info;
1182 indio_dev->modes = INDIO_BUFFER_TRIGGERED;
1184 result = devm_iio_triggered_buffer_setup(dev, indio_dev,
1185 iio_pollfunc_store_time,
1186 inv_mpu6050_read_fifo,
1189 dev_err(dev, "configure buffer fail %d\n", result);
1192 result = inv_mpu6050_probe_trigger(indio_dev, irq_type);
1194 dev_err(dev, "trigger probe fail %d\n", result);
1198 result = devm_iio_device_register(dev, indio_dev);
1200 dev_err(dev, "IIO register fail %d\n", result);
1206 EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
1208 #ifdef CONFIG_PM_SLEEP
1210 static int inv_mpu_resume(struct device *dev)
1212 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1215 mutex_lock(&st->lock);
1216 result = inv_mpu_core_enable_regulator(st);
1220 result = inv_mpu6050_set_power_itg(st, true);
1222 mutex_unlock(&st->lock);
1227 static int inv_mpu_suspend(struct device *dev)
1229 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1232 mutex_lock(&st->lock);
1233 result = inv_mpu6050_set_power_itg(st, false);
1234 inv_mpu_core_disable_regulator(st);
1235 mutex_unlock(&st->lock);
1239 #endif /* CONFIG_PM_SLEEP */
1241 SIMPLE_DEV_PM_OPS(inv_mpu_pmops, inv_mpu_suspend, inv_mpu_resume);
1242 EXPORT_SYMBOL_GPL(inv_mpu_pmops);
1244 MODULE_AUTHOR("Invensense Corporation");
1245 MODULE_DESCRIPTION("Invensense device MPU6050 driver");
1246 MODULE_LICENSE("GPL");