2 * BMG160 Gyro Sensor driver
3 * Copyright (c) 2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/acpi.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/trigger.h>
26 #include <linux/iio/events.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/regmap.h>
30 #include <linux/delay.h>
33 #define BMG160_IRQ_NAME "bmg160_event"
35 #define BMG160_REG_CHIP_ID 0x00
36 #define BMG160_CHIP_ID_VAL 0x0F
38 #define BMG160_REG_PMU_LPW 0x11
39 #define BMG160_MODE_NORMAL 0x00
40 #define BMG160_MODE_DEEP_SUSPEND 0x20
41 #define BMG160_MODE_SUSPEND 0x80
43 #define BMG160_REG_RANGE 0x0F
45 #define BMG160_RANGE_2000DPS 0
46 #define BMG160_RANGE_1000DPS 1
47 #define BMG160_RANGE_500DPS 2
48 #define BMG160_RANGE_250DPS 3
49 #define BMG160_RANGE_125DPS 4
51 #define BMG160_REG_PMU_BW 0x10
52 #define BMG160_NO_FILTER 0
53 #define BMG160_DEF_BW 100
54 #define BMG160_REG_PMU_BW_RES BIT(7)
56 #define BMG160_GYRO_REG_RESET 0x14
57 #define BMG160_GYRO_RESET_VAL 0xb6
59 #define BMG160_REG_INT_MAP_0 0x17
60 #define BMG160_INT_MAP_0_BIT_ANY BIT(1)
62 #define BMG160_REG_INT_MAP_1 0x18
63 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0)
65 #define BMG160_REG_INT_RST_LATCH 0x21
66 #define BMG160_INT_MODE_LATCH_RESET 0x80
67 #define BMG160_INT_MODE_LATCH_INT 0x0F
68 #define BMG160_INT_MODE_NON_LATCH_INT 0x00
70 #define BMG160_REG_INT_EN_0 0x15
71 #define BMG160_DATA_ENABLE_INT BIT(7)
73 #define BMG160_REG_INT_EN_1 0x16
74 #define BMG160_INT1_BIT_OD BIT(1)
76 #define BMG160_REG_XOUT_L 0x02
77 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2))
79 #define BMG160_REG_SLOPE_THRES 0x1B
80 #define BMG160_SLOPE_THRES_MASK 0x0F
82 #define BMG160_REG_MOTION_INTR 0x1C
83 #define BMG160_INT_MOTION_X BIT(0)
84 #define BMG160_INT_MOTION_Y BIT(1)
85 #define BMG160_INT_MOTION_Z BIT(2)
86 #define BMG160_ANY_DUR_MASK 0x30
87 #define BMG160_ANY_DUR_SHIFT 4
89 #define BMG160_REG_INT_STATUS_2 0x0B
90 #define BMG160_ANY_MOTION_MASK 0x07
91 #define BMG160_ANY_MOTION_BIT_X BIT(0)
92 #define BMG160_ANY_MOTION_BIT_Y BIT(1)
93 #define BMG160_ANY_MOTION_BIT_Z BIT(2)
95 #define BMG160_REG_TEMP 0x08
96 #define BMG160_TEMP_CENTER_VAL 23
98 #define BMG160_MAX_STARTUP_TIME_MS 80
100 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000
103 struct regmap *regmap;
104 struct iio_trigger *dready_trig;
105 struct iio_trigger *motion_trig;
111 bool dready_trigger_on;
112 bool motion_trigger_on;
123 static const struct {
127 } bmg160_samp_freq_table[] = { {100, 32, 0x07},
135 static const struct {
138 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS},
139 { 532, BMG160_RANGE_1000DPS},
140 { 266, BMG160_RANGE_500DPS},
141 { 133, BMG160_RANGE_250DPS},
142 { 66, BMG160_RANGE_125DPS} };
144 static int bmg160_set_mode(struct bmg160_data *data, u8 mode)
146 struct device *dev = regmap_get_device(data->regmap);
149 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode);
151 dev_err(dev, "Error writing reg_pmu_lpw\n");
158 static int bmg160_convert_freq_to_bit(int val)
162 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
163 if (bmg160_samp_freq_table[i].odr == val)
164 return bmg160_samp_freq_table[i].bw_bits;
170 static int bmg160_set_bw(struct bmg160_data *data, int val)
172 struct device *dev = regmap_get_device(data->regmap);
176 bw_bits = bmg160_convert_freq_to_bit(val);
180 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits);
182 dev_err(dev, "Error writing reg_pmu_bw\n");
189 static int bmg160_get_filter(struct bmg160_data *data, int *val)
191 struct device *dev = regmap_get_device(data->regmap);
194 unsigned int bw_bits;
196 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
198 dev_err(dev, "Error reading reg_pmu_bw\n");
202 /* Ignore the readonly reserved bit. */
203 bw_bits &= ~BMG160_REG_PMU_BW_RES;
205 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
206 if (bmg160_samp_freq_table[i].bw_bits == bw_bits)
210 *val = bmg160_samp_freq_table[i].filter;
212 return ret ? ret : IIO_VAL_INT;
216 static int bmg160_set_filter(struct bmg160_data *data, int val)
218 struct device *dev = regmap_get_device(data->regmap);
222 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
223 if (bmg160_samp_freq_table[i].filter == val)
227 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW,
228 bmg160_samp_freq_table[i].bw_bits);
230 dev_err(dev, "Error writing reg_pmu_bw\n");
237 static int bmg160_chip_init(struct bmg160_data *data)
239 struct device *dev = regmap_get_device(data->regmap);
244 * Reset chip to get it in a known good state. A delay of 30ms after
245 * reset is required according to the datasheet.
247 regmap_write(data->regmap, BMG160_GYRO_REG_RESET,
248 BMG160_GYRO_RESET_VAL);
249 usleep_range(30000, 30700);
251 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val);
253 dev_err(dev, "Error reading reg_chip_id\n");
257 dev_dbg(dev, "Chip Id %x\n", val);
258 if (val != BMG160_CHIP_ID_VAL) {
259 dev_err(dev, "invalid chip %x\n", val);
263 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
267 /* Wait upto 500 ms to be ready after changing mode */
268 usleep_range(500, 1000);
271 ret = bmg160_set_bw(data, BMG160_DEF_BW);
275 /* Set Default Range */
276 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS);
278 dev_err(dev, "Error writing reg_range\n");
281 data->dps_range = BMG160_RANGE_500DPS;
283 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val);
285 dev_err(dev, "Error reading reg_slope_thres\n");
288 data->slope_thres = val;
290 /* Set default interrupt mode */
291 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1,
292 BMG160_INT1_BIT_OD, 0);
294 dev_err(dev, "Error updating bits in reg_int_en_1\n");
298 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
299 BMG160_INT_MODE_LATCH_INT |
300 BMG160_INT_MODE_LATCH_RESET);
303 "Error writing reg_motion_intr\n");
310 static int bmg160_set_power_state(struct bmg160_data *data, bool on)
313 struct device *dev = regmap_get_device(data->regmap);
317 ret = pm_runtime_get_sync(dev);
319 pm_runtime_mark_last_busy(dev);
320 ret = pm_runtime_put_autosuspend(dev);
324 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on);
327 pm_runtime_put_noidle(dev);
336 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data,
339 struct device *dev = regmap_get_device(data->regmap);
342 /* Enable/Disable INT_MAP0 mapping */
343 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0,
344 BMG160_INT_MAP_0_BIT_ANY,
345 (status ? BMG160_INT_MAP_0_BIT_ANY : 0));
347 dev_err(dev, "Error updating bits reg_int_map0\n");
351 /* Enable/Disable slope interrupts */
353 /* Update slope thres */
354 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES,
357 dev_err(dev, "Error writing reg_slope_thres\n");
361 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR,
362 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y |
363 BMG160_INT_MOTION_Z);
365 dev_err(dev, "Error writing reg_motion_intr\n");
370 * New data interrupt is always non-latched,
371 * which will have higher priority, so no need
372 * to set latched mode, we will be flooded anyway with INTR
374 if (!data->dready_trigger_on) {
375 ret = regmap_write(data->regmap,
376 BMG160_REG_INT_RST_LATCH,
377 BMG160_INT_MODE_LATCH_INT |
378 BMG160_INT_MODE_LATCH_RESET);
380 dev_err(dev, "Error writing reg_rst_latch\n");
385 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
386 BMG160_DATA_ENABLE_INT);
389 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
393 dev_err(dev, "Error writing reg_int_en0\n");
400 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data,
403 struct device *dev = regmap_get_device(data->regmap);
406 /* Enable/Disable INT_MAP1 mapping */
407 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1,
408 BMG160_INT_MAP_1_BIT_NEW_DATA,
409 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0));
411 dev_err(dev, "Error updating bits in reg_int_map1\n");
416 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
417 BMG160_INT_MODE_NON_LATCH_INT |
418 BMG160_INT_MODE_LATCH_RESET);
420 dev_err(dev, "Error writing reg_rst_latch\n");
424 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
425 BMG160_DATA_ENABLE_INT);
428 /* Restore interrupt mode */
429 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
430 BMG160_INT_MODE_LATCH_INT |
431 BMG160_INT_MODE_LATCH_RESET);
433 dev_err(dev, "Error writing reg_rst_latch\n");
437 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
441 dev_err(dev, "Error writing reg_int_en0\n");
448 static int bmg160_get_bw(struct bmg160_data *data, int *val)
450 struct device *dev = regmap_get_device(data->regmap);
452 unsigned int bw_bits;
455 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
457 dev_err(dev, "Error reading reg_pmu_bw\n");
461 /* Ignore the readonly reserved bit. */
462 bw_bits &= ~BMG160_REG_PMU_BW_RES;
464 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
465 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) {
466 *val = bmg160_samp_freq_table[i].odr;
474 static int bmg160_set_scale(struct bmg160_data *data, int val)
476 struct device *dev = regmap_get_device(data->regmap);
479 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
480 if (bmg160_scale_table[i].scale == val) {
481 ret = regmap_write(data->regmap, BMG160_REG_RANGE,
482 bmg160_scale_table[i].dps_range);
484 dev_err(dev, "Error writing reg_range\n");
487 data->dps_range = bmg160_scale_table[i].dps_range;
495 static int bmg160_get_temp(struct bmg160_data *data, int *val)
497 struct device *dev = regmap_get_device(data->regmap);
499 unsigned int raw_val;
501 mutex_lock(&data->mutex);
502 ret = bmg160_set_power_state(data, true);
504 mutex_unlock(&data->mutex);
508 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val);
510 dev_err(dev, "Error reading reg_temp\n");
511 bmg160_set_power_state(data, false);
512 mutex_unlock(&data->mutex);
516 *val = sign_extend32(raw_val, 7);
517 ret = bmg160_set_power_state(data, false);
518 mutex_unlock(&data->mutex);
525 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val)
527 struct device *dev = regmap_get_device(data->regmap);
531 mutex_lock(&data->mutex);
532 ret = bmg160_set_power_state(data, true);
534 mutex_unlock(&data->mutex);
538 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val,
541 dev_err(dev, "Error reading axis %d\n", axis);
542 bmg160_set_power_state(data, false);
543 mutex_unlock(&data->mutex);
547 *val = sign_extend32(le16_to_cpu(raw_val), 15);
548 ret = bmg160_set_power_state(data, false);
549 mutex_unlock(&data->mutex);
556 static int bmg160_read_raw(struct iio_dev *indio_dev,
557 struct iio_chan_spec const *chan,
558 int *val, int *val2, long mask)
560 struct bmg160_data *data = iio_priv(indio_dev);
564 case IIO_CHAN_INFO_RAW:
565 switch (chan->type) {
567 return bmg160_get_temp(data, val);
569 if (iio_buffer_enabled(indio_dev))
572 return bmg160_get_axis(data, chan->scan_index,
577 case IIO_CHAN_INFO_OFFSET:
578 if (chan->type == IIO_TEMP) {
579 *val = BMG160_TEMP_CENTER_VAL;
583 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
584 return bmg160_get_filter(data, val);
585 case IIO_CHAN_INFO_SCALE:
587 switch (chan->type) {
590 return IIO_VAL_INT_PLUS_MICRO;
595 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
596 if (bmg160_scale_table[i].dps_range ==
598 *val2 = bmg160_scale_table[i].scale;
599 return IIO_VAL_INT_PLUS_MICRO;
607 case IIO_CHAN_INFO_SAMP_FREQ:
609 mutex_lock(&data->mutex);
610 ret = bmg160_get_bw(data, val);
611 mutex_unlock(&data->mutex);
618 static int bmg160_write_raw(struct iio_dev *indio_dev,
619 struct iio_chan_spec const *chan,
620 int val, int val2, long mask)
622 struct bmg160_data *data = iio_priv(indio_dev);
626 case IIO_CHAN_INFO_SAMP_FREQ:
627 mutex_lock(&data->mutex);
629 * Section 4.2 of spec
630 * In suspend mode, the only supported operations are reading
631 * registers as well as writing to the (0x14) softreset
632 * register. Since we will be in suspend mode by default, change
633 * mode to power on for other writes.
635 ret = bmg160_set_power_state(data, true);
637 mutex_unlock(&data->mutex);
640 ret = bmg160_set_bw(data, val);
642 bmg160_set_power_state(data, false);
643 mutex_unlock(&data->mutex);
646 ret = bmg160_set_power_state(data, false);
647 mutex_unlock(&data->mutex);
649 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
653 mutex_lock(&data->mutex);
654 ret = bmg160_set_power_state(data, true);
656 bmg160_set_power_state(data, false);
657 mutex_unlock(&data->mutex);
660 ret = bmg160_set_filter(data, val);
662 bmg160_set_power_state(data, false);
663 mutex_unlock(&data->mutex);
666 ret = bmg160_set_power_state(data, false);
667 mutex_unlock(&data->mutex);
669 case IIO_CHAN_INFO_SCALE:
673 mutex_lock(&data->mutex);
674 /* Refer to comments above for the suspend mode ops */
675 ret = bmg160_set_power_state(data, true);
677 mutex_unlock(&data->mutex);
680 ret = bmg160_set_scale(data, val2);
682 bmg160_set_power_state(data, false);
683 mutex_unlock(&data->mutex);
686 ret = bmg160_set_power_state(data, false);
687 mutex_unlock(&data->mutex);
696 static int bmg160_read_event(struct iio_dev *indio_dev,
697 const struct iio_chan_spec *chan,
698 enum iio_event_type type,
699 enum iio_event_direction dir,
700 enum iio_event_info info,
703 struct bmg160_data *data = iio_priv(indio_dev);
707 case IIO_EV_INFO_VALUE:
708 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK;
717 static int bmg160_write_event(struct iio_dev *indio_dev,
718 const struct iio_chan_spec *chan,
719 enum iio_event_type type,
720 enum iio_event_direction dir,
721 enum iio_event_info info,
724 struct bmg160_data *data = iio_priv(indio_dev);
727 case IIO_EV_INFO_VALUE:
728 if (data->ev_enable_state)
730 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK;
731 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK);
740 static int bmg160_read_event_config(struct iio_dev *indio_dev,
741 const struct iio_chan_spec *chan,
742 enum iio_event_type type,
743 enum iio_event_direction dir)
746 struct bmg160_data *data = iio_priv(indio_dev);
748 return data->ev_enable_state;
751 static int bmg160_write_event_config(struct iio_dev *indio_dev,
752 const struct iio_chan_spec *chan,
753 enum iio_event_type type,
754 enum iio_event_direction dir,
757 struct bmg160_data *data = iio_priv(indio_dev);
760 if (state && data->ev_enable_state)
763 mutex_lock(&data->mutex);
765 if (!state && data->motion_trigger_on) {
766 data->ev_enable_state = 0;
767 mutex_unlock(&data->mutex);
771 * We will expect the enable and disable to do operation in
772 * in reverse order. This will happen here anyway as our
773 * resume operation uses sync mode runtime pm calls, the
774 * suspend operation will be delayed by autosuspend delay
775 * So the disable operation will still happen in reverse of
776 * enable operation. When runtime pm is disabled the mode
777 * is always on so sequence doesn't matter
779 ret = bmg160_set_power_state(data, state);
781 mutex_unlock(&data->mutex);
785 ret = bmg160_setup_any_motion_interrupt(data, state);
787 bmg160_set_power_state(data, false);
788 mutex_unlock(&data->mutex);
792 data->ev_enable_state = state;
793 mutex_unlock(&data->mutex);
798 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000");
800 static IIO_CONST_ATTR(in_anglvel_scale_available,
801 "0.001065 0.000532 0.000266 0.000133 0.000066");
803 static struct attribute *bmg160_attributes[] = {
804 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
805 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
809 static const struct attribute_group bmg160_attrs_group = {
810 .attrs = bmg160_attributes,
813 static const struct iio_event_spec bmg160_event = {
814 .type = IIO_EV_TYPE_ROC,
815 .dir = IIO_EV_DIR_EITHER,
816 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
817 BIT(IIO_EV_INFO_ENABLE)
820 #define BMG160_CHANNEL(_axis) { \
821 .type = IIO_ANGL_VEL, \
823 .channel2 = IIO_MOD_##_axis, \
824 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
825 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
826 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
827 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
828 .scan_index = AXIS_##_axis, \
833 .endianness = IIO_LE, \
835 .event_spec = &bmg160_event, \
836 .num_event_specs = 1 \
839 static const struct iio_chan_spec bmg160_channels[] = {
842 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
843 BIT(IIO_CHAN_INFO_SCALE) |
844 BIT(IIO_CHAN_INFO_OFFSET),
850 IIO_CHAN_SOFT_TIMESTAMP(3),
853 static const struct iio_info bmg160_info = {
854 .attrs = &bmg160_attrs_group,
855 .read_raw = bmg160_read_raw,
856 .write_raw = bmg160_write_raw,
857 .read_event_value = bmg160_read_event,
858 .write_event_value = bmg160_write_event,
859 .write_event_config = bmg160_write_event_config,
860 .read_event_config = bmg160_read_event_config,
861 .driver_module = THIS_MODULE,
864 static const unsigned long bmg160_accel_scan_masks[] = {
865 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
868 static irqreturn_t bmg160_trigger_handler(int irq, void *p)
870 struct iio_poll_func *pf = p;
871 struct iio_dev *indio_dev = pf->indio_dev;
872 struct bmg160_data *data = iio_priv(indio_dev);
875 mutex_lock(&data->mutex);
876 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L,
877 data->buffer, AXIS_MAX * 2);
878 mutex_unlock(&data->mutex);
882 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
885 iio_trigger_notify_done(indio_dev->trig);
890 static int bmg160_trig_try_reen(struct iio_trigger *trig)
892 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
893 struct bmg160_data *data = iio_priv(indio_dev);
894 struct device *dev = regmap_get_device(data->regmap);
897 /* new data interrupts don't need ack */
898 if (data->dready_trigger_on)
901 /* Set latched mode interrupt and clear any latched interrupt */
902 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
903 BMG160_INT_MODE_LATCH_INT |
904 BMG160_INT_MODE_LATCH_RESET);
906 dev_err(dev, "Error writing reg_rst_latch\n");
913 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig,
916 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
917 struct bmg160_data *data = iio_priv(indio_dev);
920 mutex_lock(&data->mutex);
922 if (!state && data->ev_enable_state && data->motion_trigger_on) {
923 data->motion_trigger_on = false;
924 mutex_unlock(&data->mutex);
929 * Refer to comment in bmg160_write_event_config for
930 * enable/disable operation order
932 ret = bmg160_set_power_state(data, state);
934 mutex_unlock(&data->mutex);
937 if (data->motion_trig == trig)
938 ret = bmg160_setup_any_motion_interrupt(data, state);
940 ret = bmg160_setup_new_data_interrupt(data, state);
942 bmg160_set_power_state(data, false);
943 mutex_unlock(&data->mutex);
946 if (data->motion_trig == trig)
947 data->motion_trigger_on = state;
949 data->dready_trigger_on = state;
951 mutex_unlock(&data->mutex);
956 static const struct iio_trigger_ops bmg160_trigger_ops = {
957 .set_trigger_state = bmg160_data_rdy_trigger_set_state,
958 .try_reenable = bmg160_trig_try_reen,
959 .owner = THIS_MODULE,
962 static irqreturn_t bmg160_event_handler(int irq, void *private)
964 struct iio_dev *indio_dev = private;
965 struct bmg160_data *data = iio_priv(indio_dev);
966 struct device *dev = regmap_get_device(data->regmap);
971 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val);
973 dev_err(dev, "Error reading reg_int_status2\n");
974 goto ack_intr_status;
978 dir = IIO_EV_DIR_RISING;
980 dir = IIO_EV_DIR_FALLING;
982 if (val & BMG160_ANY_MOTION_BIT_X)
983 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
988 iio_get_time_ns(indio_dev));
989 if (val & BMG160_ANY_MOTION_BIT_Y)
990 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
995 iio_get_time_ns(indio_dev));
996 if (val & BMG160_ANY_MOTION_BIT_Z)
997 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
1002 iio_get_time_ns(indio_dev));
1005 if (!data->dready_trigger_on) {
1006 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
1007 BMG160_INT_MODE_LATCH_INT |
1008 BMG160_INT_MODE_LATCH_RESET);
1010 dev_err(dev, "Error writing reg_rst_latch\n");
1016 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private)
1018 struct iio_dev *indio_dev = private;
1019 struct bmg160_data *data = iio_priv(indio_dev);
1021 if (data->dready_trigger_on)
1022 iio_trigger_poll(data->dready_trig);
1023 else if (data->motion_trigger_on)
1024 iio_trigger_poll(data->motion_trig);
1026 if (data->ev_enable_state)
1027 return IRQ_WAKE_THREAD;
1033 static int bmg160_buffer_preenable(struct iio_dev *indio_dev)
1035 struct bmg160_data *data = iio_priv(indio_dev);
1037 return bmg160_set_power_state(data, true);
1040 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev)
1042 struct bmg160_data *data = iio_priv(indio_dev);
1044 return bmg160_set_power_state(data, false);
1047 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = {
1048 .preenable = bmg160_buffer_preenable,
1049 .postenable = iio_triggered_buffer_postenable,
1050 .predisable = iio_triggered_buffer_predisable,
1051 .postdisable = bmg160_buffer_postdisable,
1054 static const char *bmg160_match_acpi_device(struct device *dev)
1056 const struct acpi_device_id *id;
1058 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1062 return dev_name(dev);
1065 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq,
1068 struct bmg160_data *data;
1069 struct iio_dev *indio_dev;
1072 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1076 data = iio_priv(indio_dev);
1077 dev_set_drvdata(dev, indio_dev);
1079 data->regmap = regmap;
1081 ret = bmg160_chip_init(data);
1085 mutex_init(&data->mutex);
1087 if (ACPI_HANDLE(dev))
1088 name = bmg160_match_acpi_device(dev);
1090 indio_dev->dev.parent = dev;
1091 indio_dev->channels = bmg160_channels;
1092 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels);
1093 indio_dev->name = name;
1094 indio_dev->available_scan_masks = bmg160_accel_scan_masks;
1095 indio_dev->modes = INDIO_DIRECT_MODE;
1096 indio_dev->info = &bmg160_info;
1098 if (data->irq > 0) {
1099 ret = devm_request_threaded_irq(dev,
1101 bmg160_data_rdy_trig_poll,
1102 bmg160_event_handler,
1103 IRQF_TRIGGER_RISING,
1109 data->dready_trig = devm_iio_trigger_alloc(dev,
1113 if (!data->dready_trig)
1116 data->motion_trig = devm_iio_trigger_alloc(dev,
1117 "%s-any-motion-dev%d",
1120 if (!data->motion_trig)
1123 data->dready_trig->dev.parent = dev;
1124 data->dready_trig->ops = &bmg160_trigger_ops;
1125 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1126 ret = iio_trigger_register(data->dready_trig);
1130 data->motion_trig->dev.parent = dev;
1131 data->motion_trig->ops = &bmg160_trigger_ops;
1132 iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1133 ret = iio_trigger_register(data->motion_trig);
1135 data->motion_trig = NULL;
1136 goto err_trigger_unregister;
1140 ret = iio_triggered_buffer_setup(indio_dev,
1141 iio_pollfunc_store_time,
1142 bmg160_trigger_handler,
1143 &bmg160_buffer_setup_ops);
1146 "iio triggered buffer setup failed\n");
1147 goto err_trigger_unregister;
1150 ret = pm_runtime_set_active(dev);
1152 goto err_buffer_cleanup;
1154 pm_runtime_enable(dev);
1155 pm_runtime_set_autosuspend_delay(dev,
1156 BMG160_AUTO_SUSPEND_DELAY_MS);
1157 pm_runtime_use_autosuspend(dev);
1159 ret = iio_device_register(indio_dev);
1161 dev_err(dev, "unable to register iio device\n");
1162 goto err_buffer_cleanup;
1168 iio_triggered_buffer_cleanup(indio_dev);
1169 err_trigger_unregister:
1170 if (data->dready_trig)
1171 iio_trigger_unregister(data->dready_trig);
1172 if (data->motion_trig)
1173 iio_trigger_unregister(data->motion_trig);
1177 EXPORT_SYMBOL_GPL(bmg160_core_probe);
1179 void bmg160_core_remove(struct device *dev)
1181 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1182 struct bmg160_data *data = iio_priv(indio_dev);
1184 iio_device_unregister(indio_dev);
1186 pm_runtime_disable(dev);
1187 pm_runtime_set_suspended(dev);
1188 pm_runtime_put_noidle(dev);
1190 iio_triggered_buffer_cleanup(indio_dev);
1192 if (data->dready_trig) {
1193 iio_trigger_unregister(data->dready_trig);
1194 iio_trigger_unregister(data->motion_trig);
1197 mutex_lock(&data->mutex);
1198 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND);
1199 mutex_unlock(&data->mutex);
1201 EXPORT_SYMBOL_GPL(bmg160_core_remove);
1203 #ifdef CONFIG_PM_SLEEP
1204 static int bmg160_suspend(struct device *dev)
1206 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1207 struct bmg160_data *data = iio_priv(indio_dev);
1209 mutex_lock(&data->mutex);
1210 bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1211 mutex_unlock(&data->mutex);
1216 static int bmg160_resume(struct device *dev)
1218 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1219 struct bmg160_data *data = iio_priv(indio_dev);
1221 mutex_lock(&data->mutex);
1222 if (data->dready_trigger_on || data->motion_trigger_on ||
1223 data->ev_enable_state)
1224 bmg160_set_mode(data, BMG160_MODE_NORMAL);
1225 mutex_unlock(&data->mutex);
1232 static int bmg160_runtime_suspend(struct device *dev)
1234 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1235 struct bmg160_data *data = iio_priv(indio_dev);
1238 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1240 dev_err(dev, "set mode failed\n");
1247 static int bmg160_runtime_resume(struct device *dev)
1249 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1250 struct bmg160_data *data = iio_priv(indio_dev);
1253 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
1257 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS);
1263 const struct dev_pm_ops bmg160_pm_ops = {
1264 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume)
1265 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend,
1266 bmg160_runtime_resume, NULL)
1268 EXPORT_SYMBOL_GPL(bmg160_pm_ops);
1270 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1271 MODULE_LICENSE("GPL v2");
1272 MODULE_DESCRIPTION("BMG160 Gyro driver");