drivers/iio/adc/rockchip_saradc.c

   1 /*
   2  * Rockchip Successive Approximation Register (SAR) A/D Converter
   3  * Copyright (C) 2014 ROCKCHIP, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/completion.h>
  24 #include <linux/delay.h>
  25 #include <linux/reset.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/iio/iio.h>
  28
  29 #define SARADC_DATA                     0x00
  30
  31 #define SARADC_STAS                     0x04
  32 #define SARADC_STAS_BUSY                BIT(0)
  33
  34 #define SARADC_CTRL                     0x08
  35 #define SARADC_CTRL_IRQ_STATUS          BIT(6)
  36 #define SARADC_CTRL_IRQ_ENABLE          BIT(5)
  37 #define SARADC_CTRL_POWER_CTRL          BIT(3)
  38 #define SARADC_CTRL_CHN_MASK            0x7
  39
  40 #define SARADC_DLY_PU_SOC               0x0c
  41 #define SARADC_DLY_PU_SOC_MASK          0x3f
  42
  43 #define SARADC_TIMEOUT                  msecs_to_jiffies(100)
  44
  45 struct rockchip_saradc_data {
  46         int                             num_bits;
  47         const struct iio_chan_spec      *channels;
  48         int                             num_channels;
  49         unsigned long                   clk_rate;
  50 };
  51
  52 struct rockchip_saradc {
  53         void __iomem            *regs;
  54         struct clk              *pclk;
  55         struct clk              *clk;
  56         struct completion       completion;
  57         struct regulator        *vref;
  58         struct reset_control    *reset;
  59         const struct rockchip_saradc_data *data;
  60         u16                     last_val;
  61 };
  62
  63 static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
  64                                     struct iio_chan_spec const *chan,
  65                                     int *val, int *val2, long mask)
  66 {
  67         struct rockchip_saradc *info = iio_priv(indio_dev);
  68         int ret;
  69
  70         switch (mask) {
  71         case IIO_CHAN_INFO_RAW:
  72                 mutex_lock(&indio_dev->mlock);
  73
  74                 reinit_completion(&info->completion);
  75
  76                 /* 8 clock periods as delay between power up and start cmd */
  77                 writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
  78
  79                 /* Select the channel to be used and trigger conversion */
  80                 writel(SARADC_CTRL_POWER_CTRL
  81                                 | (chan->channel & SARADC_CTRL_CHN_MASK)
  82                                 | SARADC_CTRL_IRQ_ENABLE,
  83                        info->regs + SARADC_CTRL);
  84
  85                 if (!wait_for_completion_timeout(&info->completion,
  86                                                  SARADC_TIMEOUT)) {
  87                         writel_relaxed(0, info->regs + SARADC_CTRL);
  88                         mutex_unlock(&indio_dev->mlock);
  89                         return -ETIMEDOUT;
  90                 }
  91
  92                 *val = info->last_val;
  93                 mutex_unlock(&indio_dev->mlock);
  94                 return IIO_VAL_INT;
  95         case IIO_CHAN_INFO_SCALE:
  96                 ret = regulator_get_voltage(info->vref);
  97                 if (ret < 0) {
  98                         dev_err(&indio_dev->dev, "failed to get voltage\n");
  99                         return ret;
 100                 }
 101
 102                 *val = ret / 1000;
 103                 *val2 = info->data->num_bits;
 104                 return IIO_VAL_FRACTIONAL_LOG2;
 105         default:
 106                 return -EINVAL;
 107         }
 108 }
 109
 110 static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
 111 {
 112         struct rockchip_saradc *info = dev_id;
 113
 114         /* Read value */
 115         info->last_val = readl_relaxed(info->regs + SARADC_DATA);
 116         info->last_val &= GENMASK(info->data->num_bits - 1, 0);
 117
 118         /* Clear irq & power down adc */
 119         writel_relaxed(0, info->regs + SARADC_CTRL);
 120
 121         complete(&info->completion);
 122
 123         return IRQ_HANDLED;
 124 }
 125
 126 static const struct iio_info rockchip_saradc_iio_info = {
 127         .read_raw = rockchip_saradc_read_raw,
 128 };
 129
 130 #define ADC_CHANNEL(_index, _id) {                              \
 131         .type = IIO_VOLTAGE,                                    \
 132         .indexed = 1,                                           \
 133         .channel = _index,                                      \
 134         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 135         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 136         .datasheet_name = _id,                                  \
 137 }
 138
 139 static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
 140         ADC_CHANNEL(0, "adc0"),
 141         ADC_CHANNEL(1, "adc1"),
 142         ADC_CHANNEL(2, "adc2"),
 143 };
 144
 145 static const struct rockchip_saradc_data saradc_data = {
 146         .num_bits = 10,
 147         .channels = rockchip_saradc_iio_channels,
 148         .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
 149         .clk_rate = 1000000,
 150 };
 151
 152 static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
 153         ADC_CHANNEL(0, "adc0"),
 154         ADC_CHANNEL(1, "adc1"),
 155 };
 156
 157 static const struct rockchip_saradc_data rk3066_tsadc_data = {
 158         .num_bits = 12,
 159         .channels = rockchip_rk3066_tsadc_iio_channels,
 160         .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
 161         .clk_rate = 50000,
 162 };
 163
 164 static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
 165         ADC_CHANNEL(0, "adc0"),
 166         ADC_CHANNEL(1, "adc1"),
 167         ADC_CHANNEL(2, "adc2"),
 168         ADC_CHANNEL(3, "adc3"),
 169         ADC_CHANNEL(4, "adc4"),
 170         ADC_CHANNEL(5, "adc5"),
 171 };
 172
 173 static const struct rockchip_saradc_data rk3399_saradc_data = {
 174         .num_bits = 10,
 175         .channels = rockchip_rk3399_saradc_iio_channels,
 176         .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
 177         .clk_rate = 1000000,
 178 };
 179
 180 static const struct of_device_id rockchip_saradc_match[] = {
 181         {
 182                 .compatible = "rockchip,saradc",
 183                 .data = &saradc_data,
 184         }, {
 185                 .compatible = "rockchip,rk3066-tsadc",
 186                 .data = &rk3066_tsadc_data,
 187         }, {
 188                 .compatible = "rockchip,rk3399-saradc",
 189                 .data = &rk3399_saradc_data,
 190         },
 191         {},
 192 };
 193 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
 194
 195 /**
 196  * Reset SARADC Controller.
 197  */
 198 static void rockchip_saradc_reset_controller(struct reset_control *reset)
 199 {
 200         reset_control_assert(reset);
 201         usleep_range(10, 20);
 202         reset_control_deassert(reset);
 203 }
 204
 205 static int rockchip_saradc_probe(struct platform_device *pdev)
 206 {
 207         struct rockchip_saradc *info = NULL;
 208         struct device_node *np = pdev->dev.of_node;
 209         struct iio_dev *indio_dev = NULL;
 210         struct resource *mem;
 211         const struct of_device_id *match;
 212         int ret;
 213         int irq;
 214
 215         if (!np)
 216                 return -ENODEV;
 217
 218         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
 219         if (!indio_dev) {
 220                 dev_err(&pdev->dev, "failed allocating iio device\n");
 221                 return -ENOMEM;
 222         }
 223         info = iio_priv(indio_dev);
 224
 225         match = of_match_device(rockchip_saradc_match, &pdev->dev);
 226         if (!match) {
 227                 dev_err(&pdev->dev, "failed to match device\n");
 228                 return -ENODEV;
 229         }
 230
 231         info->data = match->data;
 232
 233         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 234         info->regs = devm_ioremap_resource(&pdev->dev, mem);
 235         if (IS_ERR(info->regs))
 236                 return PTR_ERR(info->regs);
 237
 238         /*
 239          * The reset should be an optional property, as it should work
 240          * with old devicetrees as well
 241          */
 242         info->reset = devm_reset_control_get_exclusive(&pdev->dev,
 243                                                        "saradc-apb");
 244         if (IS_ERR(info->reset)) {
 245                 ret = PTR_ERR(info->reset);
 246                 if (ret != -ENOENT)
 247                         return ret;
 248
 249                 dev_dbg(&pdev->dev, "no reset control found\n");
 250                 info->reset = NULL;
 251         }
 252
 253         init_completion(&info->completion);
 254
 255         irq = platform_get_irq(pdev, 0);
 256         if (irq < 0) {
 257                 dev_err(&pdev->dev, "no irq resource?\n");
 258                 return irq;
 259         }
 260
 261         ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
 262                                0, dev_name(&pdev->dev), info);
 263         if (ret < 0) {
 264                 dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
 265                 return ret;
 266         }
 267
 268         info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 269         if (IS_ERR(info->pclk)) {
 270                 dev_err(&pdev->dev, "failed to get pclk\n");
 271                 return PTR_ERR(info->pclk);
 272         }
 273
 274         info->clk = devm_clk_get(&pdev->dev, "saradc");
 275         if (IS_ERR(info->clk)) {
 276                 dev_err(&pdev->dev, "failed to get adc clock\n");
 277                 return PTR_ERR(info->clk);
 278         }
 279
 280         info->vref = devm_regulator_get(&pdev->dev, "vref");
 281         if (IS_ERR(info->vref)) {
 282                 dev_err(&pdev->dev, "failed to get regulator, %ld\n",
 283                         PTR_ERR(info->vref));
 284                 return PTR_ERR(info->vref);
 285         }
 286
 287         if (info->reset)
 288                 rockchip_saradc_reset_controller(info->reset);
 289
 290         /*
 291          * Use a default value for the converter clock.
 292          * This may become user-configurable in the future.
 293          */
 294         ret = clk_set_rate(info->clk, info->data->clk_rate);
 295         if (ret < 0) {
 296                 dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
 297                 return ret;
 298         }
 299
 300         ret = regulator_enable(info->vref);
 301         if (ret < 0) {
 302                 dev_err(&pdev->dev, "failed to enable vref regulator\n");
 303                 return ret;
 304         }
 305
 306         ret = clk_prepare_enable(info->pclk);
 307         if (ret < 0) {
 308                 dev_err(&pdev->dev, "failed to enable pclk\n");
 309                 goto err_reg_voltage;
 310         }
 311
 312         ret = clk_prepare_enable(info->clk);
 313         if (ret < 0) {
 314                 dev_err(&pdev->dev, "failed to enable converter clock\n");
 315                 goto err_pclk;
 316         }
 317
 318         platform_set_drvdata(pdev, indio_dev);
 319
 320         indio_dev->name = dev_name(&pdev->dev);
 321         indio_dev->dev.parent = &pdev->dev;
 322         indio_dev->dev.of_node = pdev->dev.of_node;
 323         indio_dev->info = &rockchip_saradc_iio_info;
 324         indio_dev->modes = INDIO_DIRECT_MODE;
 325
 326         indio_dev->channels = info->data->channels;
 327         indio_dev->num_channels = info->data->num_channels;
 328
 329         ret = iio_device_register(indio_dev);
 330         if (ret)
 331                 goto err_clk;
 332
 333         return 0;
 334
 335 err_clk:
 336         clk_disable_unprepare(info->clk);
 337 err_pclk:
 338         clk_disable_unprepare(info->pclk);
 339 err_reg_voltage:
 340         regulator_disable(info->vref);
 341         return ret;
 342 }
 343
 344 static int rockchip_saradc_remove(struct platform_device *pdev)
 345 {
 346         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 347         struct rockchip_saradc *info = iio_priv(indio_dev);
 348
 349         iio_device_unregister(indio_dev);
 350         clk_disable_unprepare(info->clk);
 351         clk_disable_unprepare(info->pclk);
 352         regulator_disable(info->vref);
 353
 354         return 0;
 355 }
 356
 357 #ifdef CONFIG_PM_SLEEP
 358 static int rockchip_saradc_suspend(struct device *dev)
 359 {
 360         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 361         struct rockchip_saradc *info = iio_priv(indio_dev);
 362
 363         clk_disable_unprepare(info->clk);
 364         clk_disable_unprepare(info->pclk);
 365         regulator_disable(info->vref);
 366
 367         return 0;
 368 }
 369
 370 static int rockchip_saradc_resume(struct device *dev)
 371 {
 372         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 373         struct rockchip_saradc *info = iio_priv(indio_dev);
 374         int ret;
 375
 376         ret = regulator_enable(info->vref);
 377         if (ret)
 378                 return ret;
 379
 380         ret = clk_prepare_enable(info->pclk);
 381         if (ret)
 382                 return ret;
 383
 384         ret = clk_prepare_enable(info->clk);
 385         if (ret)
 386                 return ret;
 387
 388         return ret;
 389 }
 390 #endif
 391
 392 static SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
 393                          rockchip_saradc_suspend, rockchip_saradc_resume);
 394
 395 static struct platform_driver rockchip_saradc_driver = {
 396         .probe          = rockchip_saradc_probe,
 397         .remove         = rockchip_saradc_remove,
 398         .driver         = {
 399                 .name   = "rockchip-saradc",
 400                 .of_match_table = rockchip_saradc_match,
 401                 .pm     = &rockchip_saradc_pm_ops,
 402         },
 403 };
 404
 405 module_platform_driver(rockchip_saradc_driver);
 406
 407 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
 408 MODULE_DESCRIPTION("Rockchip SARADC driver");
 409 MODULE_LICENSE("GPL v2");