drivers/iio/adc/at91-sama5d2_adc.c

   1 /*
   2  * Atmel ADC driver for SAMA5D2 devices and compatible.
   3  *
   4  * Copyright (C) 2015 Atmel,
   5  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/bitops.h>
  18 #include <linux/clk.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/module.h>
  22 #include <linux/of_device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/sched.h>
  25 #include <linux/wait.h>
  26 #include <linux/iio/iio.h>
  27 #include <linux/iio/sysfs.h>
  28 #include <linux/iio/buffer.h>
  29 #include <linux/iio/trigger.h>
  30 #include <linux/iio/trigger_consumer.h>
  31 #include <linux/iio/triggered_buffer.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #include <linux/regulator/consumer.h>
  34
  35 /* Control Register */
  36 #define AT91_SAMA5D2_CR         0x00
  37 /* Software Reset */
  38 #define AT91_SAMA5D2_CR_SWRST           BIT(0)
  39 /* Start Conversion */
  40 #define AT91_SAMA5D2_CR_START           BIT(1)
  41 /* Touchscreen Calibration */
  42 #define AT91_SAMA5D2_CR_TSCALIB         BIT(2)
  43 /* Comparison Restart */
  44 #define AT91_SAMA5D2_CR_CMPRST          BIT(4)
  45
  46 /* Mode Register */
  47 #define AT91_SAMA5D2_MR         0x04
  48 /* Trigger Selection */
  49 #define AT91_SAMA5D2_MR_TRGSEL(v)       ((v) << 1)
  50 /* ADTRG */
  51 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0    0
  52 /* TIOA0 */
  53 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1    1
  54 /* TIOA1 */
  55 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2    2
  56 /* TIOA2 */
  57 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3    3
  58 /* PWM event line 0 */
  59 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4    4
  60 /* PWM event line 1 */
  61 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5    5
  62 /* TIOA3 */
  63 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6    6
  64 /* RTCOUT0 */
  65 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7    7
  66 /* Sleep Mode */
  67 #define AT91_SAMA5D2_MR_SLEEP           BIT(5)
  68 /* Fast Wake Up */
  69 #define AT91_SAMA5D2_MR_FWUP            BIT(6)
  70 /* Prescaler Rate Selection */
  71 #define AT91_SAMA5D2_MR_PRESCAL(v)      ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
  72 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET  8
  73 #define AT91_SAMA5D2_MR_PRESCAL_MAX     0xff
  74 #define AT91_SAMA5D2_MR_PRESCAL_MASK    GENMASK(15, 8)
  75 /* Startup Time */
  76 #define AT91_SAMA5D2_MR_STARTUP(v)      ((v) << 16)
  77 #define AT91_SAMA5D2_MR_STARTUP_MASK    GENMASK(19, 16)
  78 /* Analog Change */
  79 #define AT91_SAMA5D2_MR_ANACH           BIT(23)
  80 /* Tracking Time */
  81 #define AT91_SAMA5D2_MR_TRACKTIM(v)     ((v) << 24)
  82 #define AT91_SAMA5D2_MR_TRACKTIM_MAX    0xff
  83 /* Transfer Time */
  84 #define AT91_SAMA5D2_MR_TRANSFER(v)     ((v) << 28)
  85 #define AT91_SAMA5D2_MR_TRANSFER_MAX    0x3
  86 /* Use Sequence Enable */
  87 #define AT91_SAMA5D2_MR_USEQ            BIT(31)
  88
  89 /* Channel Sequence Register 1 */
  90 #define AT91_SAMA5D2_SEQR1      0x08
  91 /* Channel Sequence Register 2 */
  92 #define AT91_SAMA5D2_SEQR2      0x0c
  93 /* Channel Enable Register */
  94 #define AT91_SAMA5D2_CHER       0x10
  95 /* Channel Disable Register */
  96 #define AT91_SAMA5D2_CHDR       0x14
  97 /* Channel Status Register */
  98 #define AT91_SAMA5D2_CHSR       0x18
  99 /* Last Converted Data Register */
 100 #define AT91_SAMA5D2_LCDR       0x20
 101 /* Interrupt Enable Register */
 102 #define AT91_SAMA5D2_IER        0x24
 103 /* Interrupt Disable Register */
 104 #define AT91_SAMA5D2_IDR        0x28
 105 /* Interrupt Mask Register */
 106 #define AT91_SAMA5D2_IMR        0x2c
 107 /* Interrupt Status Register */
 108 #define AT91_SAMA5D2_ISR        0x30
 109 /* Last Channel Trigger Mode Register */
 110 #define AT91_SAMA5D2_LCTMR      0x34
 111 /* Last Channel Compare Window Register */
 112 #define AT91_SAMA5D2_LCCWR      0x38
 113 /* Overrun Status Register */
 114 #define AT91_SAMA5D2_OVER       0x3c
 115 /* Extended Mode Register */
 116 #define AT91_SAMA5D2_EMR        0x40
 117 /* Compare Window Register */
 118 #define AT91_SAMA5D2_CWR        0x44
 119 /* Channel Gain Register */
 120 #define AT91_SAMA5D2_CGR        0x48
 121
 122 /* Channel Offset Register */
 123 #define AT91_SAMA5D2_COR        0x4c
 124 #define AT91_SAMA5D2_COR_DIFF_OFFSET    16
 125
 126 /* Channel Data Register 0 */
 127 #define AT91_SAMA5D2_CDR0       0x50
 128 /* Analog Control Register */
 129 #define AT91_SAMA5D2_ACR        0x94
 130 /* Touchscreen Mode Register */
 131 #define AT91_SAMA5D2_TSMR       0xb0
 132 /* Touchscreen X Position Register */
 133 #define AT91_SAMA5D2_XPOSR      0xb4
 134 /* Touchscreen Y Position Register */
 135 #define AT91_SAMA5D2_YPOSR      0xb8
 136 /* Touchscreen Pressure Register */
 137 #define AT91_SAMA5D2_PRESSR     0xbc
 138 /* Trigger Register */
 139 #define AT91_SAMA5D2_TRGR       0xc0
 140 /* Mask for TRGMOD field of TRGR register */
 141 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
 142 /* No trigger, only software trigger can start conversions */
 143 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
 144 /* Trigger Mode external trigger rising edge */
 145 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
 146 /* Trigger Mode external trigger falling edge */
 147 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
 148 /* Trigger Mode external trigger any edge */
 149 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
 150
 151 /* Correction Select Register */
 152 #define AT91_SAMA5D2_COSR       0xd0
 153 /* Correction Value Register */
 154 #define AT91_SAMA5D2_CVR        0xd4
 155 /* Channel Error Correction Register */
 156 #define AT91_SAMA5D2_CECR       0xd8
 157 /* Write Protection Mode Register */
 158 #define AT91_SAMA5D2_WPMR       0xe4
 159 /* Write Protection Status Register */
 160 #define AT91_SAMA5D2_WPSR       0xe8
 161 /* Version Register */
 162 #define AT91_SAMA5D2_VERSION    0xfc
 163
 164 #define AT91_SAMA5D2_HW_TRIG_CNT 3
 165 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
 166 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
 167
 168 /*
 169  * Maximum number of bytes to hold conversion from all channels
 170  * plus the timestamp
 171  */
 172 #define AT91_BUFFER_MAX_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT +          \
 173                                 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2 + 8)
 174
 175 #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2)
 176
 177 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr)                             \
 178         {                                                               \
 179                 .type = IIO_VOLTAGE,                                    \
 180                 .channel = num,                                         \
 181                 .address = addr,                                        \
 182                 .scan_index = num,                                      \
 183                 .scan_type = {                                          \
 184                         .sign = 'u',                                    \
 185                         .realbits = 12,                                 \
 186                         .storagebits = 16,                              \
 187                 },                                                      \
 188                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 189                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 190                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
 191                 .datasheet_name = "CH"#num,                             \
 192                 .indexed = 1,                                           \
 193         }
 194
 195 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr)                         \
 196         {                                                               \
 197                 .type = IIO_VOLTAGE,                                    \
 198                 .differential = 1,                                      \
 199                 .channel = num,                                         \
 200                 .channel2 = num2,                                       \
 201                 .address = addr,                                        \
 202                 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT,       \
 203                 .scan_type = {                                          \
 204                         .sign = 's',                                    \
 205                         .realbits = 12,                                 \
 206                         .storagebits = 16,                              \
 207                 },                                                      \
 208                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 209                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 210                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
 211                 .datasheet_name = "CH"#num"-CH"#num2,                   \
 212                 .indexed = 1,                                           \
 213         }
 214
 215 #define at91_adc_readl(st, reg)         readl_relaxed(st->base + reg)
 216 #define at91_adc_writel(st, reg, val)   writel_relaxed(val, st->base + reg)
 217
 218 struct at91_adc_soc_info {
 219         unsigned                        startup_time;
 220         unsigned                        min_sample_rate;
 221         unsigned                        max_sample_rate;
 222 };
 223
 224 struct at91_adc_trigger {
 225         char                            *name;
 226         unsigned int                    trgmod_value;
 227         unsigned int                    edge_type;
 228 };
 229
 230 struct at91_adc_state {
 231         void __iomem                    *base;
 232         int                             irq;
 233         struct clk                      *per_clk;
 234         struct regulator                *reg;
 235         struct regulator                *vref;
 236         int                             vref_uv;
 237         struct iio_trigger              *trig;
 238         const struct at91_adc_trigger   *selected_trig;
 239         const struct iio_chan_spec      *chan;
 240         bool                            conversion_done;
 241         u32                             conversion_value;
 242         struct at91_adc_soc_info        soc_info;
 243         wait_queue_head_t               wq_data_available;
 244         u16                             buffer[AT91_BUFFER_MAX_HWORDS];
 245         /*
 246          * lock to prevent concurrent 'single conversion' requests through
 247          * sysfs.
 248          */
 249         struct mutex                    lock;
 250 };
 251
 252 static const struct at91_adc_trigger at91_adc_trigger_list[] = {
 253         {
 254                 .name = "external_rising",
 255                 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
 256                 .edge_type = IRQ_TYPE_EDGE_RISING,
 257         },
 258         {
 259                 .name = "external_falling",
 260                 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
 261                 .edge_type = IRQ_TYPE_EDGE_FALLING,
 262         },
 263         {
 264                 .name = "external_any",
 265                 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
 266                 .edge_type = IRQ_TYPE_EDGE_BOTH,
 267         },
 268 };
 269
 270 static const struct iio_chan_spec at91_adc_channels[] = {
 271         AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
 272         AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
 273         AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
 274         AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
 275         AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
 276         AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
 277         AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
 278         AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
 279         AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
 280         AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
 281         AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
 282         AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
 283         AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
 284         AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
 285         AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
 286         AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
 287         AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
 288         AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
 289         IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_SINGLE_CHAN_CNT
 290                                 + AT91_SAMA5D2_DIFF_CHAN_CNT + 1),
 291 };
 292
 293 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
 294 {
 295         struct iio_dev *indio = iio_trigger_get_drvdata(trig);
 296         struct at91_adc_state *st = iio_priv(indio);
 297         u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
 298         u8 bit;
 299
 300         /* clear TRGMOD */
 301         status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
 302
 303         if (state)
 304                 status |= st->selected_trig->trgmod_value;
 305
 306         /* set/unset hw trigger */
 307         at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
 308
 309         for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
 310                 struct iio_chan_spec const *chan = indio->channels + bit;
 311
 312                 if (state) {
 313                         at91_adc_writel(st, AT91_SAMA5D2_CHER,
 314                                         BIT(chan->channel));
 315                         at91_adc_writel(st, AT91_SAMA5D2_IER,
 316                                         BIT(chan->channel));
 317                 } else {
 318                         at91_adc_writel(st, AT91_SAMA5D2_IDR,
 319                                         BIT(chan->channel));
 320                         at91_adc_writel(st, AT91_SAMA5D2_CHDR,
 321                                         BIT(chan->channel));
 322                 }
 323         }
 324
 325         return 0;
 326 }
 327
 328 static int at91_adc_reenable_trigger(struct iio_trigger *trig)
 329 {
 330         struct iio_dev *indio = iio_trigger_get_drvdata(trig);
 331         struct at91_adc_state *st = iio_priv(indio);
 332
 333         enable_irq(st->irq);
 334
 335         /* Needed to ACK the DRDY interruption */
 336         at91_adc_readl(st, AT91_SAMA5D2_LCDR);
 337         return 0;
 338 }
 339
 340 static const struct iio_trigger_ops at91_adc_trigger_ops = {
 341         .owner = THIS_MODULE,
 342         .set_trigger_state = &at91_adc_configure_trigger,
 343         .try_reenable = &at91_adc_reenable_trigger,
 344 };
 345
 346 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
 347                                                      char *trigger_name)
 348 {
 349         struct iio_trigger *trig;
 350         int ret;
 351
 352         trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
 353                                       indio->id, trigger_name);
 354         if (!trig)
 355                 return NULL;
 356
 357         trig->dev.parent = indio->dev.parent;
 358         iio_trigger_set_drvdata(trig, indio);
 359         trig->ops = &at91_adc_trigger_ops;
 360
 361         ret = devm_iio_trigger_register(&indio->dev, trig);
 362         if (ret)
 363                 return ERR_PTR(ret);
 364
 365         return trig;
 366 }
 367
 368 static int at91_adc_trigger_init(struct iio_dev *indio)
 369 {
 370         struct at91_adc_state *st = iio_priv(indio);
 371
 372         st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
 373         if (IS_ERR(st->trig)) {
 374                 dev_err(&indio->dev,
 375                         "could not allocate trigger\n");
 376                 return PTR_ERR(st->trig);
 377         }
 378
 379         return 0;
 380 }
 381
 382 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
 383 {
 384         struct iio_poll_func *pf = p;
 385         struct iio_dev *indio = pf->indio_dev;
 386         struct at91_adc_state *st = iio_priv(indio);
 387         int i = 0;
 388         u8 bit;
 389
 390         for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
 391                 struct iio_chan_spec const *chan = indio->channels + bit;
 392
 393                 st->buffer[i] = at91_adc_readl(st, chan->address);
 394                 i++;
 395         }
 396
 397         iio_push_to_buffers_with_timestamp(indio, st->buffer, pf->timestamp);
 398
 399         iio_trigger_notify_done(indio->trig);
 400
 401         return IRQ_HANDLED;
 402 }
 403
 404 static int at91_adc_buffer_init(struct iio_dev *indio)
 405 {
 406         return devm_iio_triggered_buffer_setup(&indio->dev, indio,
 407                         &iio_pollfunc_store_time,
 408                         &at91_adc_trigger_handler, NULL);
 409 }
 410
 411 static unsigned at91_adc_startup_time(unsigned startup_time_min,
 412                                       unsigned adc_clk_khz)
 413 {
 414         static const unsigned int startup_lookup[] = {
 415                   0,   8,  16,  24,
 416                  64,  80,  96, 112,
 417                 512, 576, 640, 704,
 418                 768, 832, 896, 960
 419                 };
 420         unsigned ticks_min, i;
 421
 422         /*
 423          * Since the adc frequency is checked before, there is no reason
 424          * to not meet the startup time constraint.
 425          */
 426
 427         ticks_min = startup_time_min * adc_clk_khz / 1000;
 428         for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
 429                 if (startup_lookup[i] > ticks_min)
 430                         break;
 431
 432         return i;
 433 }
 434
 435 static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq)
 436 {
 437         struct iio_dev *indio_dev = iio_priv_to_dev(st);
 438         unsigned f_per, prescal, startup, mr;
 439
 440         f_per = clk_get_rate(st->per_clk);
 441         prescal = (f_per / (2 * freq)) - 1;
 442
 443         startup = at91_adc_startup_time(st->soc_info.startup_time,
 444                                         freq / 1000);
 445
 446         mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
 447         mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
 448         mr |= AT91_SAMA5D2_MR_STARTUP(startup);
 449         mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
 450         at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
 451
 452         dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
 453                 freq, startup, prescal);
 454 }
 455
 456 static unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
 457 {
 458         unsigned f_adc, f_per = clk_get_rate(st->per_clk);
 459         unsigned mr, prescal;
 460
 461         mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
 462         prescal = (mr >> AT91_SAMA5D2_MR_PRESCAL_OFFSET)
 463                   & AT91_SAMA5D2_MR_PRESCAL_MAX;
 464         f_adc = f_per / (2 * (prescal + 1));
 465
 466         return f_adc;
 467 }
 468
 469 static irqreturn_t at91_adc_interrupt(int irq, void *private)
 470 {
 471         struct iio_dev *indio = private;
 472         struct at91_adc_state *st = iio_priv(indio);
 473         u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
 474         u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
 475
 476         if (!(status & imr))
 477                 return IRQ_NONE;
 478
 479         if (iio_buffer_enabled(indio)) {
 480                 disable_irq_nosync(irq);
 481                 iio_trigger_poll(indio->trig);
 482         } else {
 483                 st->conversion_value = at91_adc_readl(st, st->chan->address);
 484                 st->conversion_done = true;
 485                 wake_up_interruptible(&st->wq_data_available);
 486         }
 487         return IRQ_HANDLED;
 488 }
 489
 490 static int at91_adc_read_raw(struct iio_dev *indio_dev,
 491                              struct iio_chan_spec const *chan,
 492                              int *val, int *val2, long mask)
 493 {
 494         struct at91_adc_state *st = iio_priv(indio_dev);
 495         u32 cor = 0;
 496         int ret;
 497
 498         switch (mask) {
 499         case IIO_CHAN_INFO_RAW:
 500                 /* we cannot use software trigger if hw trigger enabled */
 501                 ret = iio_device_claim_direct_mode(indio_dev);
 502                 if (ret)
 503                         return ret;
 504
 505                 mutex_lock(&st->lock);
 506
 507                 st->chan = chan;
 508
 509                 if (chan->differential)
 510                         cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
 511                               AT91_SAMA5D2_COR_DIFF_OFFSET;
 512
 513                 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
 514                 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
 515                 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
 516                 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
 517
 518                 ret = wait_event_interruptible_timeout(st->wq_data_available,
 519                                                        st->conversion_done,
 520                                                        msecs_to_jiffies(1000));
 521                 if (ret == 0)
 522                         ret = -ETIMEDOUT;
 523
 524                 if (ret > 0) {
 525                         *val = st->conversion_value;
 526                         if (chan->scan_type.sign == 's')
 527                                 *val = sign_extend32(*val, 11);
 528                         ret = IIO_VAL_INT;
 529                         st->conversion_done = false;
 530                 }
 531
 532                 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
 533                 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
 534
 535                 mutex_unlock(&st->lock);
 536
 537                 iio_device_release_direct_mode(indio_dev);
 538                 return ret;
 539
 540         case IIO_CHAN_INFO_SCALE:
 541                 *val = st->vref_uv / 1000;
 542                 if (chan->differential)
 543                         *val *= 2;
 544                 *val2 = chan->scan_type.realbits;
 545                 return IIO_VAL_FRACTIONAL_LOG2;
 546
 547         case IIO_CHAN_INFO_SAMP_FREQ:
 548                 *val = at91_adc_get_sample_freq(st);
 549                 return IIO_VAL_INT;
 550
 551         default:
 552                 return -EINVAL;
 553         }
 554 }
 555
 556 static int at91_adc_write_raw(struct iio_dev *indio_dev,
 557                               struct iio_chan_spec const *chan,
 558                               int val, int val2, long mask)
 559 {
 560         struct at91_adc_state *st = iio_priv(indio_dev);
 561
 562         if (mask != IIO_CHAN_INFO_SAMP_FREQ)
 563                 return -EINVAL;
 564
 565         if (val < st->soc_info.min_sample_rate ||
 566             val > st->soc_info.max_sample_rate)
 567                 return -EINVAL;
 568
 569         at91_adc_setup_samp_freq(st, val);
 570
 571         return 0;
 572 }
 573
 574 static const struct iio_info at91_adc_info = {
 575         .read_raw = &at91_adc_read_raw,
 576         .write_raw = &at91_adc_write_raw,
 577         .driver_module = THIS_MODULE,
 578 };
 579
 580 static void at91_adc_hw_init(struct at91_adc_state *st)
 581 {
 582         at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
 583         at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
 584         /*
 585          * Transfer field must be set to 2 according to the datasheet and
 586          * allows different analog settings for each channel.
 587          */
 588         at91_adc_writel(st, AT91_SAMA5D2_MR,
 589                         AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
 590
 591         at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate);
 592 }
 593
 594 static int at91_adc_probe(struct platform_device *pdev)
 595 {
 596         struct iio_dev *indio_dev;
 597         struct at91_adc_state *st;
 598         struct resource *res;
 599         int ret, i;
 600         u32 edge_type;
 601
 602         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
 603         if (!indio_dev)
 604                 return -ENOMEM;
 605
 606         indio_dev->dev.parent = &pdev->dev;
 607         indio_dev->name = dev_name(&pdev->dev);
 608         indio_dev->modes = INDIO_DIRECT_MODE;
 609         indio_dev->info = &at91_adc_info;
 610         indio_dev->channels = at91_adc_channels;
 611         indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
 612
 613         st = iio_priv(indio_dev);
 614
 615         ret = of_property_read_u32(pdev->dev.of_node,
 616                                    "atmel,min-sample-rate-hz",
 617                                    &st->soc_info.min_sample_rate);
 618         if (ret) {
 619                 dev_err(&pdev->dev,
 620                         "invalid or missing value for atmel,min-sample-rate-hz\n");
 621                 return ret;
 622         }
 623
 624         ret = of_property_read_u32(pdev->dev.of_node,
 625                                    "atmel,max-sample-rate-hz",
 626                                    &st->soc_info.max_sample_rate);
 627         if (ret) {
 628                 dev_err(&pdev->dev,
 629                         "invalid or missing value for atmel,max-sample-rate-hz\n");
 630                 return ret;
 631         }
 632
 633         ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
 634                                    &st->soc_info.startup_time);
 635         if (ret) {
 636                 dev_err(&pdev->dev,
 637                         "invalid or missing value for atmel,startup-time-ms\n");
 638                 return ret;
 639         }
 640
 641         ret = of_property_read_u32(pdev->dev.of_node,
 642                                    "atmel,trigger-edge-type", &edge_type);
 643         if (ret) {
 644                 dev_err(&pdev->dev,
 645                         "invalid or missing value for atmel,trigger-edge-type\n");
 646                 return ret;
 647         }
 648
 649         st->selected_trig = NULL;
 650
 651         for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT; i++)
 652                 if (at91_adc_trigger_list[i].edge_type == edge_type) {
 653                         st->selected_trig = &at91_adc_trigger_list[i];
 654                         break;
 655                 }
 656
 657         if (!st->selected_trig) {
 658                 dev_err(&pdev->dev, "invalid external trigger edge value\n");
 659                 return -EINVAL;
 660         }
 661
 662         init_waitqueue_head(&st->wq_data_available);
 663         mutex_init(&st->lock);
 664
 665         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 666         if (!res)
 667                 return -EINVAL;
 668
 669         st->base = devm_ioremap_resource(&pdev->dev, res);
 670         if (IS_ERR(st->base))
 671                 return PTR_ERR(st->base);
 672
 673         st->irq = platform_get_irq(pdev, 0);
 674         if (st->irq <= 0) {
 675                 if (!st->irq)
 676                         st->irq = -ENXIO;
 677
 678                 return st->irq;
 679         }
 680
 681         st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
 682         if (IS_ERR(st->per_clk))
 683                 return PTR_ERR(st->per_clk);
 684
 685         st->reg = devm_regulator_get(&pdev->dev, "vddana");
 686         if (IS_ERR(st->reg))
 687                 return PTR_ERR(st->reg);
 688
 689         st->vref = devm_regulator_get(&pdev->dev, "vref");
 690         if (IS_ERR(st->vref))
 691                 return PTR_ERR(st->vref);
 692
 693         ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
 694                                pdev->dev.driver->name, indio_dev);
 695         if (ret)
 696                 return ret;
 697
 698         ret = regulator_enable(st->reg);
 699         if (ret)
 700                 return ret;
 701
 702         ret = regulator_enable(st->vref);
 703         if (ret)
 704                 goto reg_disable;
 705
 706         st->vref_uv = regulator_get_voltage(st->vref);
 707         if (st->vref_uv <= 0) {
 708                 ret = -EINVAL;
 709                 goto vref_disable;
 710         }
 711
 712         at91_adc_hw_init(st);
 713
 714         ret = clk_prepare_enable(st->per_clk);
 715         if (ret)
 716                 goto vref_disable;
 717
 718         platform_set_drvdata(pdev, indio_dev);
 719
 720         ret = at91_adc_buffer_init(indio_dev);
 721         if (ret < 0) {
 722                 dev_err(&pdev->dev, "couldn't initialize the buffer.\n");
 723                 goto per_clk_disable_unprepare;
 724         }
 725
 726         ret = at91_adc_trigger_init(indio_dev);
 727         if (ret < 0) {
 728                 dev_err(&pdev->dev, "couldn't setup the triggers.\n");
 729                 goto per_clk_disable_unprepare;
 730         }
 731
 732         ret = iio_device_register(indio_dev);
 733         if (ret < 0)
 734                 goto per_clk_disable_unprepare;
 735
 736         dev_info(&pdev->dev, "setting up trigger as %s\n",
 737                  st->selected_trig->name);
 738
 739         dev_info(&pdev->dev, "version: %x\n",
 740                  readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
 741
 742         return 0;
 743
 744 per_clk_disable_unprepare:
 745         clk_disable_unprepare(st->per_clk);
 746 vref_disable:
 747         regulator_disable(st->vref);
 748 reg_disable:
 749         regulator_disable(st->reg);
 750         return ret;
 751 }
 752
 753 static int at91_adc_remove(struct platform_device *pdev)
 754 {
 755         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 756         struct at91_adc_state *st = iio_priv(indio_dev);
 757
 758         iio_device_unregister(indio_dev);
 759
 760         clk_disable_unprepare(st->per_clk);
 761
 762         regulator_disable(st->vref);
 763         regulator_disable(st->reg);
 764
 765         return 0;
 766 }
 767
 768 static __maybe_unused int at91_adc_suspend(struct device *dev)
 769 {
 770         struct iio_dev *indio_dev =
 771                         platform_get_drvdata(to_platform_device(dev));
 772         struct at91_adc_state *st = iio_priv(indio_dev);
 773
 774         /*
 775          * Do a sofware reset of the ADC before we go to suspend.
 776          * this will ensure that all pins are free from being muxed by the ADC
 777          * and can be used by for other devices.
 778          * Otherwise, ADC will hog them and we can't go to suspend mode.
 779          */
 780         at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
 781
 782         clk_disable_unprepare(st->per_clk);
 783         regulator_disable(st->vref);
 784         regulator_disable(st->reg);
 785
 786         return pinctrl_pm_select_sleep_state(dev);
 787 }
 788
 789 static __maybe_unused int at91_adc_resume(struct device *dev)
 790 {
 791         struct iio_dev *indio_dev =
 792                         platform_get_drvdata(to_platform_device(dev));
 793         struct at91_adc_state *st = iio_priv(indio_dev);
 794         int ret;
 795
 796         ret = pinctrl_pm_select_default_state(dev);
 797         if (ret)
 798                 goto resume_failed;
 799
 800         ret = regulator_enable(st->reg);
 801         if (ret)
 802                 goto resume_failed;
 803
 804         ret = regulator_enable(st->vref);
 805         if (ret)
 806                 goto reg_disable_resume;
 807
 808         ret = clk_prepare_enable(st->per_clk);
 809         if (ret)
 810                 goto vref_disable_resume;
 811
 812         at91_adc_hw_init(st);
 813
 814         /* reconfiguring trigger hardware state */
 815         if (iio_buffer_enabled(indio_dev))
 816                 at91_adc_configure_trigger(st->trig, true);
 817
 818         return 0;
 819
 820 vref_disable_resume:
 821         regulator_disable(st->vref);
 822 reg_disable_resume:
 823         regulator_disable(st->reg);
 824 resume_failed:
 825         dev_err(&indio_dev->dev, "failed to resume\n");
 826         return ret;
 827 }
 828
 829 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
 830
 831 static const struct of_device_id at91_adc_dt_match[] = {
 832         {
 833                 .compatible = "atmel,sama5d2-adc",
 834         }, {
 835                 /* sentinel */
 836         }
 837 };
 838 MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
 839
 840 static struct platform_driver at91_adc_driver = {
 841         .probe = at91_adc_probe,
 842         .remove = at91_adc_remove,
 843         .driver = {
 844                 .name = "at91-sama5d2_adc",
 845                 .of_match_table = at91_adc_dt_match,
 846                 .pm = &at91_adc_pm_ops,
 847         },
 848 };
 849 module_platform_driver(at91_adc_driver)
 850
 851 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
 852 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
 853 MODULE_LICENSE("GPL v2");