drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 1.02    Apr 18, 2007
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  * Portions Copyright (C) 2005-2007     MontaVista Software, Inc.
   8  *
   9  * Thanks to HighPoint Technologies for their assistance, and hardware.
  10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12  * development and support.
  13  *
  14  *
  15  * HighPoint has its own drivers (open source except for the RAID part)
  16  * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  17  * This may be useful to anyone wanting to work on this driver, however  do not
  18  * trust  them too much since the code tends to become less and less meaningful
  19  * as the time passes... :-/
  20  *
  21  * Note that final HPT370 support was done by force extraction of GPL.
  22  *
  23  * - add function for getting/setting power status of drive
  24  * - the HPT370's state machine can get confused. reset it before each dma
  25  *   xfer to prevent that from happening.
  26  * - reset state engine whenever we get an error.
  27  * - check for busmaster state at end of dma.
  28  * - use new highpoint timings.
  29  * - detect bus speed using highpoint register.
  30  * - use pll if we don't have a clock table. added a 66MHz table that's
  31  *   just 2x the 33MHz table.
  32  * - removed turnaround. NOTE: we never want to switch between pll and
  33  *   pci clocks as the chip can glitch in those cases. the highpoint
  34  *   approved workaround slows everything down too much to be useful. in
  35  *   addition, we would have to serialize access to each chip.
  36  *      Adrian Sun <a.sun@sun.com>
  37  *
  38  * add drive timings for 66MHz PCI bus,
  39  * fix ATA Cable signal detection, fix incorrect /proc info
  40  * add /proc display for per-drive PIO/DMA/UDMA mode and
  41  * per-channel ATA-33/66 Cable detect.
  42  *      Duncan Laurie <void@sun.com>
  43  *
  44  * fixup /proc output for multiple controllers
  45  *      Tim Hockin <thockin@sun.com>
  46  *
  47  * On hpt366:
  48  * Reset the hpt366 on error, reset on dma
  49  * Fix disabling Fast Interrupt hpt366.
  50  *      Mike Waychison <crlf@sun.com>
  51  *
  52  * Added support for 372N clocking and clock switching. The 372N needs
  53  * different clocks on read/write. This requires overloading rw_disk and
  54  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55  * keeping me sane.
  56  *              Alan Cox <alan@redhat.com>
  57  *
  58  * - fix the clock turnaround code: it was writing to the wrong ports when
  59  *   called for the secondary channel, caching the current clock mode per-
  60  *   channel caused the cached register value to get out of sync with the
  61  *   actual one, the channels weren't serialized, the turnaround shouldn't
  62  *   be done on 66 MHz PCI bus
  63  * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
  64  *   does not allow for this speed anyway
  65  * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
  66  *   their primary channel is kind of virtual, it isn't tied to any pins)
  67  * - fix/remove bad/unused timing tables and use one set of tables for the whole
  68  *   HPT37x chip family; save space by introducing the separate transfer mode
  69  *   table in which the mode lookup is done
  70  * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
  71  *   the wrong PCI frequency since DPLL has already been calibrated by BIOS
  72  * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
  73  *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  74  * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  75  *   they tamper with its fields
  76  * - pass  to the init_setup handlers a copy of the ide_pci_device_t structure
  77  *   since they may tamper with its fields
  78  * - prefix the driver startup messages with the real chip name
  79  * - claim the extra 240 bytes of I/O space for all chips
  80  * - optimize the rate masking/filtering and the drive list lookup code
  81  * - use pci_get_slot() to get to the function 1 of HPT36x/374
  82  * - cache offset of the channel's misc. control registers (MCRs) being used
  83  *   throughout the driver
  84  * - only touch the relevant MCR when detecting the cable type on HPT374's
  85  *   function 1
  86  * - rename all the register related variables consistently
  87  * - move all the interrupt twiddling code from the speedproc handlers into
  88  *   init_hwif_hpt366(), also grouping all the DMA related code together there
  89  * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
  90  *   separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
  91  *   when setting an UltraDMA mode
  92  * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
  93  *   the best possible one
  94  * - clean up DMA timeout handling for HPT370
  95  * - switch to using the enumeration type to differ between the numerous chip
  96  *   variants, matching PCI device/revision ID with the chip type early, at the
  97  *   init_setup stage
  98  * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
  99  *   stop duplicating it for each channel by storing the pointer in the pci_dev
 100  *   structure: first, at the init_setup stage, point it to a static "template"
 101  *   with only the chip type and its specific base DPLL frequency, the highest
 102  *   supported DMA mode, and the chip settings table pointer filled, then, at
 103  *   the init_chipset stage, allocate per-chip instance  and fill it with the
 104  *   rest of the necessary information
 105  * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
 106  *   switch  to calculating  PCI clock frequency based on the chip's base DPLL
 107  *   frequency
 108  * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on
 109  *   anything  newer than HPT370/A
 110  * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
 111  *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
 112  *   unify HPT36x/37x timing setup code and the speedproc handlers by joining
 113  *   the register setting lists into the table indexed by the clock selected
 114  *      Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
 115  */
 116
 117 #include <linux/types.h>
 118 #include <linux/module.h>
 119 #include <linux/kernel.h>
 120 #include <linux/delay.h>
 121 #include <linux/timer.h>
 122 #include <linux/mm.h>
 123 #include <linux/ioport.h>
 124 #include <linux/blkdev.h>
 125 #include <linux/hdreg.h>
 126
 127 #include <linux/interrupt.h>
 128 #include <linux/pci.h>
 129 #include <linux/init.h>
 130 #include <linux/ide.h>
 131
 132 #include <asm/uaccess.h>
 133 #include <asm/io.h>
 134 #include <asm/irq.h>
 135
 136 /* various tuning parameters */
 137 #define HPT_RESET_STATE_ENGINE
 138 #undef  HPT_DELAY_INTERRUPT
 139 #define HPT_SERIALIZE_IO        0
 140
 141 static const char *quirk_drives[] = {
 142         "QUANTUM FIREBALLlct08 08",
 143         "QUANTUM FIREBALLP KA6.4",
 144         "QUANTUM FIREBALLP LM20.4",
 145         "QUANTUM FIREBALLP LM20.5",
 146         NULL
 147 };
 148
 149 static const char *bad_ata100_5[] = {
 150         "IBM-DTLA-307075",
 151         "IBM-DTLA-307060",
 152         "IBM-DTLA-307045",
 153         "IBM-DTLA-307030",
 154         "IBM-DTLA-307020",
 155         "IBM-DTLA-307015",
 156         "IBM-DTLA-305040",
 157         "IBM-DTLA-305030",
 158         "IBM-DTLA-305020",
 159         "IC35L010AVER07-0",
 160         "IC35L020AVER07-0",
 161         "IC35L030AVER07-0",
 162         "IC35L040AVER07-0",
 163         "IC35L060AVER07-0",
 164         "WDC AC310200R",
 165         NULL
 166 };
 167
 168 static const char *bad_ata66_4[] = {
 169         "IBM-DTLA-307075",
 170         "IBM-DTLA-307060",
 171         "IBM-DTLA-307045",
 172         "IBM-DTLA-307030",
 173         "IBM-DTLA-307020",
 174         "IBM-DTLA-307015",
 175         "IBM-DTLA-305040",
 176         "IBM-DTLA-305030",
 177         "IBM-DTLA-305020",
 178         "IC35L010AVER07-0",
 179         "IC35L020AVER07-0",
 180         "IC35L030AVER07-0",
 181         "IC35L040AVER07-0",
 182         "IC35L060AVER07-0",
 183         "WDC AC310200R",
 184         NULL
 185 };
 186
 187 static const char *bad_ata66_3[] = {
 188         "WDC AC310200R",
 189         NULL
 190 };
 191
 192 static const char *bad_ata33[] = {
 193         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 194         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 195         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 196         "Maxtor 90510D4",
 197         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 198         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 199         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 200         NULL
 201 };
 202
 203 static u8 xfer_speeds[] = {
 204         XFER_UDMA_6,
 205         XFER_UDMA_5,
 206         XFER_UDMA_4,
 207         XFER_UDMA_3,
 208         XFER_UDMA_2,
 209         XFER_UDMA_1,
 210         XFER_UDMA_0,
 211
 212         XFER_MW_DMA_2,
 213         XFER_MW_DMA_1,
 214         XFER_MW_DMA_0,
 215
 216         XFER_PIO_4,
 217         XFER_PIO_3,
 218         XFER_PIO_2,
 219         XFER_PIO_1,
 220         XFER_PIO_0
 221 };
 222
 223 /* Key for bus clock timings
 224  * 36x   37x
 225  * bits  bits
 226  * 0:3   0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 227  *              cycles = value + 1
 228  * 4:7   4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 229  *              cycles = value + 1
 230  * 8:11  9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 231  *              register access.
 232  * 12:15 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 233  *              register access.
 234  * 16:18 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 235  * -     21     CLK frequency: 0=ATA clock, 1=dual ATA clock.
 236  * 19:21 22:24  pre_high_time. Time to initialize the 1st cycle for PIO and
 237  *              MW DMA xfer.
 238  * 22:24 25:27  cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 239  *              task file register access.
 240  * 28    28     UDMA enable.
 241  * 29    29     DMA  enable.
 242  * 30    30     PIO MST enable. If set, the chip is in bus master mode during
 243  *              PIO xfer.
 244  * 31    31     FIFO enable.
 245  */
 246
 247 static u32 forty_base_hpt36x[] = {
 248         /* XFER_UDMA_6 */       0x900fd943,
 249         /* XFER_UDMA_5 */       0x900fd943,
 250         /* XFER_UDMA_4 */       0x900fd943,
 251         /* XFER_UDMA_3 */       0x900ad943,
 252         /* XFER_UDMA_2 */       0x900bd943,
 253         /* XFER_UDMA_1 */       0x9008d943,
 254         /* XFER_UDMA_0 */       0x9008d943,
 255
 256         /* XFER_MW_DMA_2 */     0xa008d943,
 257         /* XFER_MW_DMA_1 */     0xa010d955,
 258         /* XFER_MW_DMA_0 */     0xa010d9fc,
 259
 260         /* XFER_PIO_4 */        0xc008d963,
 261         /* XFER_PIO_3 */        0xc010d974,
 262         /* XFER_PIO_2 */        0xc010d997,
 263         /* XFER_PIO_1 */        0xc010d9c7,
 264         /* XFER_PIO_0 */        0xc018d9d9
 265 };
 266
 267 static u32 thirty_three_base_hpt36x[] = {
 268         /* XFER_UDMA_6 */       0x90c9a731,
 269         /* XFER_UDMA_5 */       0x90c9a731,
 270         /* XFER_UDMA_4 */       0x90c9a731,
 271         /* XFER_UDMA_3 */       0x90cfa731,
 272         /* XFER_UDMA_2 */       0x90caa731,
 273         /* XFER_UDMA_1 */       0x90cba731,
 274         /* XFER_UDMA_0 */       0x90c8a731,
 275
 276         /* XFER_MW_DMA_2 */     0xa0c8a731,
 277         /* XFER_MW_DMA_1 */     0xa0c8a732,     /* 0xa0c8a733 */
 278         /* XFER_MW_DMA_0 */     0xa0c8a797,
 279
 280         /* XFER_PIO_4 */        0xc0c8a731,
 281         /* XFER_PIO_3 */        0xc0c8a742,
 282         /* XFER_PIO_2 */        0xc0d0a753,
 283         /* XFER_PIO_1 */        0xc0d0a7a3,     /* 0xc0d0a793 */
 284         /* XFER_PIO_0 */        0xc0d0a7aa      /* 0xc0d0a7a7 */
 285 };
 286
 287 static u32 twenty_five_base_hpt36x[] = {
 288         /* XFER_UDMA_6 */       0x90c98521,
 289         /* XFER_UDMA_5 */       0x90c98521,
 290         /* XFER_UDMA_4 */       0x90c98521,
 291         /* XFER_UDMA_3 */       0x90cf8521,
 292         /* XFER_UDMA_2 */       0x90cf8521,
 293         /* XFER_UDMA_1 */       0x90cb8521,
 294         /* XFER_UDMA_0 */       0x90cb8521,
 295
 296         /* XFER_MW_DMA_2 */     0xa0ca8521,
 297         /* XFER_MW_DMA_1 */     0xa0ca8532,
 298         /* XFER_MW_DMA_0 */     0xa0ca8575,
 299
 300         /* XFER_PIO_4 */        0xc0ca8521,
 301         /* XFER_PIO_3 */        0xc0ca8532,
 302         /* XFER_PIO_2 */        0xc0ca8542,
 303         /* XFER_PIO_1 */        0xc0d08572,
 304         /* XFER_PIO_0 */        0xc0d08585
 305 };
 306
 307 static u32 thirty_three_base_hpt37x[] = {
 308         /* XFER_UDMA_6 */       0x12446231,     /* 0x12646231 ?? */
 309         /* XFER_UDMA_5 */       0x12446231,
 310         /* XFER_UDMA_4 */       0x12446231,
 311         /* XFER_UDMA_3 */       0x126c6231,
 312         /* XFER_UDMA_2 */       0x12486231,
 313         /* XFER_UDMA_1 */       0x124c6233,
 314         /* XFER_UDMA_0 */       0x12506297,
 315
 316         /* XFER_MW_DMA_2 */     0x22406c31,
 317         /* XFER_MW_DMA_1 */     0x22406c33,
 318         /* XFER_MW_DMA_0 */     0x22406c97,
 319
 320         /* XFER_PIO_4 */        0x06414e31,
 321         /* XFER_PIO_3 */        0x06414e42,
 322         /* XFER_PIO_2 */        0x06414e53,
 323         /* XFER_PIO_1 */        0x06814e93,
 324         /* XFER_PIO_0 */        0x06814ea7
 325 };
 326
 327 static u32 fifty_base_hpt37x[] = {
 328         /* XFER_UDMA_6 */       0x12848242,
 329         /* XFER_UDMA_5 */       0x12848242,
 330         /* XFER_UDMA_4 */       0x12ac8242,
 331         /* XFER_UDMA_3 */       0x128c8242,
 332         /* XFER_UDMA_2 */       0x120c8242,
 333         /* XFER_UDMA_1 */       0x12148254,
 334         /* XFER_UDMA_0 */       0x121882ea,
 335
 336         /* XFER_MW_DMA_2 */     0x22808242,
 337         /* XFER_MW_DMA_1 */     0x22808254,
 338         /* XFER_MW_DMA_0 */     0x228082ea,
 339
 340         /* XFER_PIO_4 */        0x0a81f442,
 341         /* XFER_PIO_3 */        0x0a81f443,
 342         /* XFER_PIO_2 */        0x0a81f454,
 343         /* XFER_PIO_1 */        0x0ac1f465,
 344         /* XFER_PIO_0 */        0x0ac1f48a
 345 };
 346
 347 static u32 sixty_six_base_hpt37x[] = {
 348         /* XFER_UDMA_6 */       0x1c869c62,
 349         /* XFER_UDMA_5 */       0x1cae9c62,     /* 0x1c8a9c62 */
 350         /* XFER_UDMA_4 */       0x1c8a9c62,
 351         /* XFER_UDMA_3 */       0x1c8e9c62,
 352         /* XFER_UDMA_2 */       0x1c929c62,
 353         /* XFER_UDMA_1 */       0x1c9a9c62,
 354         /* XFER_UDMA_0 */       0x1c829c62,
 355
 356         /* XFER_MW_DMA_2 */     0x2c829c62,
 357         /* XFER_MW_DMA_1 */     0x2c829c66,
 358         /* XFER_MW_DMA_0 */     0x2c829d2e,
 359
 360         /* XFER_PIO_4 */        0x0c829c62,
 361         /* XFER_PIO_3 */        0x0c829c84,
 362         /* XFER_PIO_2 */        0x0c829ca6,
 363         /* XFER_PIO_1 */        0x0d029d26,
 364         /* XFER_PIO_0 */        0x0d029d5e
 365 };
 366
 367 #define HPT366_DEBUG_DRIVE_INFO         0
 368 #define HPT374_ALLOW_ATA133_6           1
 369 #define HPT371_ALLOW_ATA133_6           1
 370 #define HPT302_ALLOW_ATA133_6           1
 371 #define HPT372_ALLOW_ATA133_6           1
 372 #define HPT370_ALLOW_ATA100_5           0
 373 #define HPT366_ALLOW_ATA66_4            1
 374 #define HPT366_ALLOW_ATA66_3            1
 375 #define HPT366_MAX_DEVS                 8
 376
 377 /* Supported ATA clock frequencies */
 378 enum ata_clock {
 379         ATA_CLOCK_25MHZ,
 380         ATA_CLOCK_33MHZ,
 381         ATA_CLOCK_40MHZ,
 382         ATA_CLOCK_50MHZ,
 383         ATA_CLOCK_66MHZ,
 384         NUM_ATA_CLOCKS
 385 };
 386
 387 /*
 388  *      Hold all the HighPoint chip information in one place.
 389  */
 390
 391 struct hpt_info {
 392         u8 chip_type;           /* Chip type */
 393         u8 max_mode;            /* Speeds allowed */
 394         u8 dpll_clk;            /* DPLL clock in MHz */
 395         u8 pci_clk;             /* PCI  clock in MHz */
 396         u32 **settings;         /* Chipset settings table */
 397 };
 398
 399 /* Supported HighPoint chips */
 400 enum {
 401         HPT36x,
 402         HPT370,
 403         HPT370A,
 404         HPT374,
 405         HPT372,
 406         HPT372A,
 407         HPT302,
 408         HPT371,
 409         HPT372N,
 410         HPT302N,
 411         HPT371N
 412 };
 413
 414 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
 415         twenty_five_base_hpt36x,
 416         thirty_three_base_hpt36x,
 417         forty_base_hpt36x,
 418         NULL,
 419         NULL
 420 };
 421
 422 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
 423         NULL,
 424         thirty_three_base_hpt37x,
 425         NULL,
 426         fifty_base_hpt37x,
 427         sixty_six_base_hpt37x
 428 };
 429
 430 static struct hpt_info hpt36x __devinitdata = {
 431         .chip_type      = HPT36x,
 432         .max_mode       = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1,
 433         .dpll_clk       = 0,    /* no DPLL */
 434         .settings       = hpt36x_settings
 435 };
 436
 437 static struct hpt_info hpt370 __devinitdata = {
 438         .chip_type      = HPT370,
 439         .max_mode       = HPT370_ALLOW_ATA100_5 ? 3 : 2,
 440         .dpll_clk       = 48,
 441         .settings       = hpt37x_settings
 442 };
 443
 444 static struct hpt_info hpt370a __devinitdata = {
 445         .chip_type      = HPT370A,
 446         .max_mode       = HPT370_ALLOW_ATA100_5 ? 3 : 2,
 447         .dpll_clk       = 48,
 448         .settings       = hpt37x_settings
 449 };
 450
 451 static struct hpt_info hpt374 __devinitdata = {
 452         .chip_type      = HPT374,
 453         .max_mode       = HPT374_ALLOW_ATA133_6 ? 4 : 3,
 454         .dpll_clk       = 48,
 455         .settings       = hpt37x_settings
 456 };
 457
 458 static struct hpt_info hpt372 __devinitdata = {
 459         .chip_type      = HPT372,
 460         .max_mode       = HPT372_ALLOW_ATA133_6 ? 4 : 3,
 461         .dpll_clk       = 55,
 462         .settings       = hpt37x_settings
 463 };
 464
 465 static struct hpt_info hpt372a __devinitdata = {
 466         .chip_type      = HPT372A,
 467         .max_mode       = HPT372_ALLOW_ATA133_6 ? 4 : 3,
 468         .dpll_clk       = 66,
 469         .settings       = hpt37x_settings
 470 };
 471
 472 static struct hpt_info hpt302 __devinitdata = {
 473         .chip_type      = HPT302,
 474         .max_mode       = HPT302_ALLOW_ATA133_6 ? 4 : 3,
 475         .dpll_clk       = 66,
 476         .settings       = hpt37x_settings
 477 };
 478
 479 static struct hpt_info hpt371 __devinitdata = {
 480         .chip_type      = HPT371,
 481         .max_mode       = HPT371_ALLOW_ATA133_6 ? 4 : 3,
 482         .dpll_clk       = 66,
 483         .settings       = hpt37x_settings
 484 };
 485
 486 static struct hpt_info hpt372n __devinitdata = {
 487         .chip_type      = HPT372N,
 488         .max_mode       = HPT372_ALLOW_ATA133_6 ? 4 : 3,
 489         .dpll_clk       = 77,
 490         .settings       = hpt37x_settings
 491 };
 492
 493 static struct hpt_info hpt302n __devinitdata = {
 494         .chip_type      = HPT302N,
 495         .max_mode       = HPT302_ALLOW_ATA133_6 ? 4 : 3,
 496         .dpll_clk       = 77,
 497         .settings       = hpt37x_settings
 498 };
 499
 500 static struct hpt_info hpt371n __devinitdata = {
 501         .chip_type      = HPT371N,
 502         .max_mode       = HPT371_ALLOW_ATA133_6 ? 4 : 3,
 503         .dpll_clk       = 77,
 504         .settings       = hpt37x_settings
 505 };
 506
 507 static int check_in_drive_list(ide_drive_t *drive, const char **list)
 508 {
 509         struct hd_driveid *id = drive->id;
 510
 511         while (*list)
 512                 if (!strcmp(*list++,id->model))
 513                         return 1;
 514         return 0;
 515 }
 516
 517 static u8 hpt3xx_ratemask(ide_drive_t *drive)
 518 {
 519         struct hpt_info *info   = pci_get_drvdata(HWIF(drive)->pci_dev);
 520         u8 mode                 = info->max_mode;
 521
 522         if (!eighty_ninty_three(drive) && mode)
 523                 mode = min(mode, (u8)1);
 524         return mode;
 525 }
 526
 527 /*
 528  *      Note for the future; the SATA hpt37x we must set
 529  *      either PIO or UDMA modes 0,4,5
 530  */
 531
 532 static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
 533 {
 534         struct hpt_info *info   = pci_get_drvdata(HWIF(drive)->pci_dev);
 535         u8 chip_type            = info->chip_type;
 536         u8 mode                 = hpt3xx_ratemask(drive);
 537
 538         if (drive->media != ide_disk)
 539                 return min(speed, (u8)XFER_PIO_4);
 540
 541         switch (mode) {
 542                 case 0x04:
 543                         speed = min_t(u8, speed, XFER_UDMA_6);
 544                         break;
 545                 case 0x03:
 546                         speed = min_t(u8, speed, XFER_UDMA_5);
 547                         if (chip_type >= HPT374)
 548                                 break;
 549                         if (!check_in_drive_list(drive, bad_ata100_5))
 550                                 goto check_bad_ata33;
 551                         /* fall thru */
 552                 case 0x02:
 553                         speed = min_t(u8, speed, XFER_UDMA_4);
 554
 555                         /*
 556                          * CHECK ME, Does this need to be changed to HPT374 ??
 557                          */
 558                         if (chip_type >= HPT370)
 559                                 goto check_bad_ata33;
 560                         if (HPT366_ALLOW_ATA66_4 &&
 561                             !check_in_drive_list(drive, bad_ata66_4))
 562                                 goto check_bad_ata33;
 563
 564                         speed = min_t(u8, speed, XFER_UDMA_3);
 565                         if (HPT366_ALLOW_ATA66_3 &&
 566                             !check_in_drive_list(drive, bad_ata66_3))
 567                                 goto check_bad_ata33;
 568                         /* fall thru */
 569                 case 0x01:
 570                         speed = min_t(u8, speed, XFER_UDMA_2);
 571
 572                 check_bad_ata33:
 573                         if (chip_type >= HPT370A)
 574                                 break;
 575                         if (!check_in_drive_list(drive, bad_ata33))
 576                                 break;
 577                         /* fall thru */
 578                 case 0x00:
 579                 default:
 580                         speed = min_t(u8, speed, XFER_MW_DMA_2);
 581                         break;
 582         }
 583         return speed;
 584 }
 585
 586 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
 587 {
 588         int i;
 589
 590         /*
 591          * Lookup the transfer mode table to get the index into
 592          * the timing table.
 593          *
 594          * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
 595          */
 596         for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
 597                 if (xfer_speeds[i] == speed)
 598                         break;
 599         /*
 600          * NOTE: info->settings only points to the pointer
 601          * to the list of the actual register values
 602          */
 603         return (*info->settings)[i];
 604 }
 605
 606 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 607 {
 608         ide_hwif_t *hwif        = HWIF(drive);
 609         struct pci_dev  *dev    = hwif->pci_dev;
 610         struct hpt_info *info   = pci_get_drvdata(dev);
 611         u8  speed               = hpt3xx_ratefilter(drive, xferspeed);
 612         u8  itr_addr            = drive->dn ? 0x44 : 0x40;
 613         u32 itr_mask            = speed < XFER_MW_DMA_0 ? 0x30070000 :
 614                                  (speed < XFER_UDMA_0   ? 0xc0070000 : 0xc03800ff);
 615         u32 new_itr             = get_speed_setting(speed, info);
 616         u32 old_itr             = 0;
 617
 618         /*
 619          * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
 620          * to avoid problems handling I/O errors later
 621          */
 622         pci_read_config_dword(dev, itr_addr, &old_itr);
 623         new_itr  = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 624         new_itr &= ~0xc0000000;
 625
 626         pci_write_config_dword(dev, itr_addr, new_itr);
 627
 628         return ide_config_drive_speed(drive, speed);
 629 }
 630
 631 static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 632 {
 633         ide_hwif_t *hwif        = HWIF(drive);
 634         struct pci_dev  *dev    = hwif->pci_dev;
 635         struct hpt_info *info   = pci_get_drvdata(dev);
 636         u8  speed               = hpt3xx_ratefilter(drive, xferspeed);
 637         u8  itr_addr            = 0x40 + (drive->dn * 4);
 638         u32 itr_mask            = speed < XFER_MW_DMA_0 ? 0x303c0000 :
 639                                  (speed < XFER_UDMA_0   ? 0xc03c0000 : 0xc1c001ff);
 640         u32 new_itr             = get_speed_setting(speed, info);
 641         u32 old_itr             = 0;
 642
 643         pci_read_config_dword(dev, itr_addr, &old_itr);
 644         new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 645
 646         if (speed < XFER_MW_DMA_0)
 647                 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 648         pci_write_config_dword(dev, itr_addr, new_itr);
 649
 650         return ide_config_drive_speed(drive, speed);
 651 }
 652
 653 static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
 654 {
 655         ide_hwif_t *hwif        = HWIF(drive);
 656         struct hpt_info *info   = pci_get_drvdata(hwif->pci_dev);
 657
 658         if (info->chip_type >= HPT370)
 659                 return hpt37x_tune_chipset(drive, speed);
 660         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 661                 return hpt36x_tune_chipset(drive, speed);
 662 }
 663
 664 static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
 665 {
 666         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 667         (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
 668 }
 669
 670 /*
 671  * This allows the configuration of ide_pci chipset registers
 672  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 673  * after the drive is reported by the OS.  Initially designed for
 674  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 675  *
 676  */
 677 static int config_chipset_for_dma(ide_drive_t *drive)
 678 {
 679         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 680
 681         if (!speed)
 682                 return 0;
 683
 684         (void) hpt3xx_tune_chipset(drive, speed);
 685         return ide_dma_enable(drive);
 686 }
 687
 688 static int hpt3xx_quirkproc(ide_drive_t *drive)
 689 {
 690         struct hd_driveid *id   = drive->id;
 691         const  char **list      = quirk_drives;
 692
 693         while (*list)
 694                 if (strstr(id->model, *list++))
 695                         return 1;
 696         return 0;
 697 }
 698
 699 static void hpt3xx_intrproc(ide_drive_t *drive)
 700 {
 701         ide_hwif_t *hwif = HWIF(drive);
 702
 703         if (drive->quirk_list)
 704                 return;
 705         /* drives in the quirk_list may not like intr setups/cleanups */
 706         hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
 707 }
 708
 709 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
 710 {
 711         ide_hwif_t *hwif        = HWIF(drive);
 712         struct pci_dev  *dev    = hwif->pci_dev;
 713         struct hpt_info *info   = pci_get_drvdata(dev);
 714
 715         if (drive->quirk_list) {
 716                 if (info->chip_type >= HPT370) {
 717                         u8 scr1 = 0;
 718
 719                         pci_read_config_byte(dev, 0x5a, &scr1);
 720                         if (((scr1 & 0x10) >> 4) != mask) {
 721                                 if (mask)
 722                                         scr1 |=  0x10;
 723                                 else
 724                                         scr1 &= ~0x10;
 725                                 pci_write_config_byte(dev, 0x5a, scr1);
 726                         }
 727                 } else {
 728                         if (mask)
 729                                 disable_irq(hwif->irq);
 730                         else
 731                                 enable_irq (hwif->irq);
 732                 }
 733         } else
 734                 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
 735                            IDE_CONTROL_REG);
 736 }
 737
 738 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
 739 {
 740         drive->init_speed = 0;
 741
 742         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
 743                 return 0;
 744
 745         if (ide_use_fast_pio(drive))
 746                 hpt3xx_tune_drive(drive, 255);
 747
 748         return -1;
 749 }
 750
 751 /*
 752  * This is specific to the HPT366 UDMA chipset
 753  * by HighPoint|Triones Technologies, Inc.
 754  */
 755 static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
 756 {
 757         struct pci_dev *dev = HWIF(drive)->pci_dev;
 758         u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
 759
 760         pci_read_config_byte(dev, 0x50, &mcr1);
 761         pci_read_config_byte(dev, 0x52, &mcr3);
 762         pci_read_config_byte(dev, 0x5a, &scr1);
 763         printk("%s: (%s)  mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
 764                 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
 765         if (scr1 & 0x10)
 766                 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
 767         return __ide_dma_lostirq(drive);
 768 }
 769
 770 static void hpt370_clear_engine(ide_drive_t *drive)
 771 {
 772         ide_hwif_t *hwif = HWIF(drive);
 773
 774         pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
 775         udelay(10);
 776 }
 777
 778 static void hpt370_irq_timeout(ide_drive_t *drive)
 779 {
 780         ide_hwif_t *hwif        = HWIF(drive);
 781         u16 bfifo               = 0;
 782         u8  dma_cmd;
 783
 784         pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
 785         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
 786
 787         /* get DMA command mode */
 788         dma_cmd = hwif->INB(hwif->dma_command);
 789         /* stop DMA */
 790         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 791         hpt370_clear_engine(drive);
 792 }
 793
 794 static void hpt370_ide_dma_start(ide_drive_t *drive)
 795 {
 796 #ifdef HPT_RESET_STATE_ENGINE
 797         hpt370_clear_engine(drive);
 798 #endif
 799         ide_dma_start(drive);
 800 }
 801
 802 static int hpt370_ide_dma_end(ide_drive_t *drive)
 803 {
 804         ide_hwif_t *hwif        = HWIF(drive);
 805         u8  dma_stat            = hwif->INB(hwif->dma_status);
 806
 807         if (dma_stat & 0x01) {
 808                 /* wait a little */
 809                 udelay(20);
 810                 dma_stat = hwif->INB(hwif->dma_status);
 811                 if (dma_stat & 0x01)
 812                         hpt370_irq_timeout(drive);
 813         }
 814         return __ide_dma_end(drive);
 815 }
 816
 817 static int hpt370_ide_dma_timeout(ide_drive_t *drive)
 818 {
 819         hpt370_irq_timeout(drive);
 820         return __ide_dma_timeout(drive);
 821 }
 822
 823 /* returns 1 if DMA IRQ issued, 0 otherwise */
 824 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 825 {
 826         ide_hwif_t *hwif        = HWIF(drive);
 827         u16 bfifo               = 0;
 828         u8  dma_stat;
 829
 830         pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
 831         if (bfifo & 0x1FF) {
 832 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 833                 return 0;
 834         }
 835
 836         dma_stat = inb(hwif->dma_status);
 837         /* return 1 if INTR asserted */
 838         if (dma_stat & 4)
 839                 return 1;
 840
 841         if (!drive->waiting_for_dma)
 842                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 843                                 drive->name, __FUNCTION__);
 844         return 0;
 845 }
 846
 847 static int hpt374_ide_dma_end(ide_drive_t *drive)
 848 {
 849         ide_hwif_t *hwif        = HWIF(drive);
 850         struct pci_dev  *dev    = hwif->pci_dev;
 851         u8 mcr  = 0, mcr_addr   = hwif->select_data;
 852         u8 bwsr = 0, mask       = hwif->channel ? 0x02 : 0x01;
 853
 854         pci_read_config_byte(dev, 0x6a, &bwsr);
 855         pci_read_config_byte(dev, mcr_addr, &mcr);
 856         if (bwsr & mask)
 857                 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
 858         return __ide_dma_end(drive);
 859 }
 860
 861 /**
 862  *      hpt3xxn_set_clock       -       perform clock switching dance
 863  *      @hwif: hwif to switch
 864  *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 865  *
 866  *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 867  */
 868
 869 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 870 {
 871         u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
 872
 873         if ((scr2 & 0x7f) == mode)
 874                 return;
 875
 876         /* Tristate the bus */
 877         hwif->OUTB(0x80, hwif->dma_master + 0x73);
 878         hwif->OUTB(0x80, hwif->dma_master + 0x77);
 879
 880         /* Switch clock and reset channels */
 881         hwif->OUTB(mode, hwif->dma_master + 0x7b);
 882         hwif->OUTB(0xc0, hwif->dma_master + 0x79);
 883
 884         /*
 885          * Reset the state machines.
 886          * NOTE: avoid accidentally enabling the disabled channels.
 887          */
 888         hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
 889                    hwif->dma_master + 0x70);
 890         hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
 891                    hwif->dma_master + 0x74);
 892
 893         /* Complete reset */
 894         hwif->OUTB(0x00, hwif->dma_master + 0x79);
 895
 896         /* Reconnect channels to bus */
 897         hwif->OUTB(0x00, hwif->dma_master + 0x73);
 898         hwif->OUTB(0x00, hwif->dma_master + 0x77);
 899 }
 900
 901 /**
 902  *      hpt3xxn_rw_disk         -       prepare for I/O
 903  *      @drive: drive for command
 904  *      @rq: block request structure
 905  *
 906  *      This is called when a disk I/O is issued to HPT3xxN.
 907  *      We need it because of the clock switching.
 908  */
 909
 910 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 911 {
 912         hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
 913 }
 914
 915 /*
 916  * Set/get power state for a drive.
 917  * NOTE: affects both drives on each channel.
 918  *
 919  * When we turn the power back on, we need to re-initialize things.
 920  */
 921 #define TRISTATE_BIT  0x8000
 922
 923 static int hpt3xx_busproc(ide_drive_t *drive, int state)
 924 {
 925         ide_hwif_t *hwif        = HWIF(drive);
 926         struct pci_dev *dev     = hwif->pci_dev;
 927         u8  mcr_addr            = hwif->select_data + 2;
 928         u8  resetmask           = hwif->channel ? 0x80 : 0x40;
 929         u8  bsr2                = 0;
 930         u16 mcr                 = 0;
 931
 932         hwif->bus_state = state;
 933
 934         /* Grab the status. */
 935         pci_read_config_word(dev, mcr_addr, &mcr);
 936         pci_read_config_byte(dev, 0x59, &bsr2);
 937
 938         /*
 939          * Set the state. We don't set it if we don't need to do so.
 940          * Make sure that the drive knows that it has failed if it's off.
 941          */
 942         switch (state) {
 943         case BUSSTATE_ON:
 944                 if (!(bsr2 & resetmask))
 945                         return 0;
 946                 hwif->drives[0].failures = hwif->drives[1].failures = 0;
 947
 948                 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
 949                 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
 950                 return 0;
 951         case BUSSTATE_OFF:
 952                 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
 953                         return 0;
 954                 mcr &= ~TRISTATE_BIT;
 955                 break;
 956         case BUSSTATE_TRISTATE:
 957                 if ((bsr2 & resetmask) &&  (mcr & TRISTATE_BIT))
 958                         return 0;
 959                 mcr |= TRISTATE_BIT;
 960                 break;
 961         default:
 962                 return -EINVAL;
 963         }
 964
 965         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 966         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 967
 968         pci_write_config_word(dev, mcr_addr, mcr);
 969         pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
 970         return 0;
 971 }
 972
 973 /**
 974  *      hpt37x_calibrate_dpll   -       calibrate the DPLL
 975  *      @dev: PCI device
 976  *
 977  *      Perform a calibration cycle on the DPLL.
 978  *      Returns 1 if this succeeds
 979  */
 980 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
 981 {
 982         u32 dpll = (f_high << 16) | f_low | 0x100;
 983         u8  scr2;
 984         int i;
 985
 986         pci_write_config_dword(dev, 0x5c, dpll);
 987
 988         /* Wait for oscillator ready */
 989         for(i = 0; i < 0x5000; ++i) {
 990                 udelay(50);
 991                 pci_read_config_byte(dev, 0x5b, &scr2);
 992                 if (scr2 & 0x80)
 993                         break;
 994         }
 995         /* See if it stays ready (we'll just bail out if it's not yet) */
 996         for(i = 0; i < 0x1000; ++i) {
 997                 pci_read_config_byte(dev, 0x5b, &scr2);
 998                 /* DPLL destabilized? */
 999                 if(!(scr2 & 0x80))
1000                         return 0;
1001         }
1002         /* Turn off tuning, we have the DPLL set */
1003         pci_read_config_dword (dev, 0x5c, &dpll);
1004         pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
1005         return 1;
1006 }
1007
1008 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1009 {
1010         struct hpt_info *info   = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
1011         unsigned long io_base   = pci_resource_start(dev, 4);
1012         u8 pci_clk,  dpll_clk   = 0;    /* PCI and DPLL clock in MHz */
1013         enum ata_clock  clock;
1014
1015         if (info == NULL) {
1016                 printk(KERN_ERR "%s: out of memory!\n", name);
1017                 return -ENOMEM;
1018         }
1019
1020         /*
1021          * Copy everything from a static "template" structure
1022          * to just allocated per-chip hpt_info structure.
1023          */
1024         *info = *(struct hpt_info *)pci_get_drvdata(dev);
1025
1026         /*
1027          * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1028          * We don't seem to be using it.
1029          */
1030         if (dev->resource[PCI_ROM_RESOURCE].start)
1031                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1032                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1033
1034         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1035         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1036         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1037         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1038
1039         /*
1040          * First, try to estimate the PCI clock frequency...
1041          */
1042         if (info->chip_type >= HPT370) {
1043                 u8  scr1  = 0;
1044                 u16 f_cnt = 0;
1045                 u32 temp  = 0;
1046
1047                 /* Interrupt force enable. */
1048                 pci_read_config_byte(dev, 0x5a, &scr1);
1049                 if (scr1 & 0x10)
1050                         pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1051
1052                 /*
1053                  * HighPoint does this for HPT372A.
1054                  * NOTE: This register is only writeable via I/O space.
1055                  */
1056                 if (info->chip_type == HPT372A)
1057                         outb(0x0e, io_base + 0x9c);
1058
1059                 /*
1060                  * Default to PCI clock. Make sure MA15/16 are set to output
1061                  * to prevent drives having problems with 40-pin cables.
1062                  */
1063                 pci_write_config_byte(dev, 0x5b, 0x23);
1064
1065                 /*
1066                  * We'll have to read f_CNT value in order to determine
1067                  * the PCI clock frequency according to the following ratio:
1068                  *
1069                  * f_CNT = Fpci * 192 / Fdpll
1070                  *
1071                  * First try reading the register in which the HighPoint BIOS
1072                  * saves f_CNT value before  reprogramming the DPLL from its
1073                  * default setting (which differs for the various chips).
1074                  * NOTE: This register is only accessible via I/O space.
1075                  *
1076                  * In case the signature check fails, we'll have to resort to
1077                  * reading the f_CNT register itself in hopes that nobody has
1078                  * touched the DPLL yet...
1079                  */
1080                 temp = inl(io_base + 0x90);
1081                 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1082                         int i;
1083
1084                         printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1085                                name);
1086
1087                         /* Calculate the average value of f_CNT. */
1088                         for (temp = i = 0; i < 128; i++) {
1089                                 pci_read_config_word(dev, 0x78, &f_cnt);
1090                                 temp += f_cnt & 0x1ff;
1091                                 mdelay(1);
1092                         }
1093                         f_cnt = temp / 128;
1094                 } else
1095                         f_cnt = temp & 0x1ff;
1096
1097                 dpll_clk = info->dpll_clk;
1098                 pci_clk  = (f_cnt * dpll_clk) / 192;
1099
1100                 /* Clamp PCI clock to bands. */
1101                 if (pci_clk < 40)
1102                         pci_clk = 33;
1103                 else if(pci_clk < 45)
1104                         pci_clk = 40;
1105                 else if(pci_clk < 55)
1106                         pci_clk = 50;
1107                 else
1108                         pci_clk = 66;
1109
1110                 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1111                        "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1112         } else {
1113                 u32 itr1 = 0;
1114
1115                 pci_read_config_dword(dev, 0x40, &itr1);
1116
1117                 /* Detect PCI clock by looking at cmd_high_time. */
1118                 switch((itr1 >> 8) & 0x07) {
1119                         case 0x09:
1120                                 pci_clk = 40;
1121                                 break;
1122                         case 0x05:
1123                                 pci_clk = 25;
1124                                 break;
1125                         case 0x07:
1126                         default:
1127                                 pci_clk = 33;
1128                                 break;
1129                 }
1130         }
1131
1132         /* Let's assume we'll use PCI clock for the ATA clock... */
1133         switch (pci_clk) {
1134                 case 25:
1135                         clock = ATA_CLOCK_25MHZ;
1136                         break;
1137                 case 33:
1138                 default:
1139                         clock = ATA_CLOCK_33MHZ;
1140                         break;
1141                 case 40:
1142                         clock = ATA_CLOCK_40MHZ;
1143                         break;
1144                 case 50:
1145                         clock = ATA_CLOCK_50MHZ;
1146                         break;
1147                 case 66:
1148                         clock = ATA_CLOCK_66MHZ;
1149                         break;
1150         }
1151
1152         /*
1153          * Only try the DPLL if we don't have a table for the PCI clock that
1154          * we are running at for HPT370/A, always use it  for anything newer...
1155          *
1156          * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1157          * We also  don't like using  the DPLL because this causes glitches
1158          * on PRST-/SRST- when the state engine gets reset...
1159          */
1160         if (info->chip_type >= HPT374 || info->settings[clock] == NULL) {
1161                 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1162                 int adjust;
1163
1164                  /*
1165                   * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1166                   * supported/enabled, use 50 MHz DPLL clock otherwise...
1167                   */
1168                 if (info->max_mode == 0x04) {
1169                         dpll_clk = 66;
1170                         clock = ATA_CLOCK_66MHZ;
1171                 } else if (dpll_clk) {  /* HPT36x chips don't have DPLL */
1172                         dpll_clk = 50;
1173                         clock = ATA_CLOCK_50MHZ;
1174                 }
1175
1176                 if (info->settings[clock] == NULL) {
1177                         printk(KERN_ERR "%s: unknown bus timing!\n", name);
1178                         kfree(info);
1179                         return -EIO;
1180                 }
1181
1182                 /* Select the DPLL clock. */
1183                 pci_write_config_byte(dev, 0x5b, 0x21);
1184
1185                 /*
1186                  * Adjust the DPLL based upon PCI clock, enable it,
1187                  * and wait for stabilization...
1188                  */
1189                 f_low = (pci_clk * 48) / dpll_clk;
1190
1191                 for (adjust = 0; adjust < 8; adjust++) {
1192                         if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1193                                 break;
1194
1195                         /*
1196                          * See if it'll settle at a fractionally different clock
1197                          */
1198                         if (adjust & 1)
1199                                 f_low -= adjust >> 1;
1200                         else
1201                                 f_low += adjust >> 1;
1202                 }
1203                 if (adjust == 8) {
1204                         printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1205                         kfree(info);
1206                         return -EIO;
1207                 }
1208
1209                 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1210         } else {
1211                 /* Mark the fact that we're not using the DPLL. */
1212                 dpll_clk = 0;
1213
1214                 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1215         }
1216
1217         /*
1218          * Advance the table pointer to a slot which points to the list
1219          * of the register values settings matching the clock being used.
1220          */
1221         info->settings += clock;
1222
1223         /* Store the clock frequencies. */
1224         info->dpll_clk  = dpll_clk;
1225         info->pci_clk   = pci_clk;
1226
1227         /* Point to this chip's own instance of the hpt_info structure. */
1228         pci_set_drvdata(dev, info);
1229
1230         if (info->chip_type >= HPT370) {
1231                 u8  mcr1, mcr4;
1232
1233                 /*
1234                  * Reset the state engines.
1235                  * NOTE: Avoid accidentally enabling the disabled channels.
1236                  */
1237                 pci_read_config_byte (dev, 0x50, &mcr1);
1238                 pci_read_config_byte (dev, 0x54, &mcr4);
1239                 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1240                 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1241                 udelay(100);
1242         }
1243
1244         /*
1245          * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1246          * the MISC. register to stretch the UltraDMA Tss timing.
1247          * NOTE: This register is only writeable via I/O space.
1248          */
1249         if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1250
1251                 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1252
1253         return dev->irq;
1254 }
1255
1256 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1257 {
1258         struct pci_dev  *dev            = hwif->pci_dev;
1259         struct hpt_info *info           = pci_get_drvdata(dev);
1260         int serialize                   = HPT_SERIALIZE_IO;
1261         u8  scr1 = 0, ata66             = (hwif->channel) ? 0x01 : 0x02;
1262         u8  chip_type                   = info->chip_type;
1263         u8  new_mcr, old_mcr            = 0;
1264
1265         /* Cache the channel's MISC. control registers' offset */
1266         hwif->select_data               = hwif->channel ? 0x54 : 0x50;
1267
1268         hwif->tuneproc                  = &hpt3xx_tune_drive;
1269         hwif->speedproc                 = &hpt3xx_tune_chipset;
1270         hwif->quirkproc                 = &hpt3xx_quirkproc;
1271         hwif->intrproc                  = &hpt3xx_intrproc;
1272         hwif->maskproc                  = &hpt3xx_maskproc;
1273         hwif->busproc                   = &hpt3xx_busproc;
1274
1275         /*
1276          * HPT3xxN chips have some complications:
1277          *
1278          * - on 33 MHz PCI we must clock switch
1279          * - on 66 MHz PCI we must NOT use the PCI clock
1280          */
1281         if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1282                 /*
1283                  * Clock is shared between the channels,
1284                  * so we'll have to serialize them... :-(
1285                  */
1286                 serialize = 1;
1287                 hwif->rw_disk = &hpt3xxn_rw_disk;
1288         }
1289
1290         /* Serialize access to this device if needed */
1291         if (serialize && hwif->mate)
1292                 hwif->serialized = hwif->mate->serialized = 1;
1293
1294         /*
1295          * Disable the "fast interrupt" prediction.  Don't hold off
1296          * on interrupts. (== 0x01 despite what the docs say)
1297          */
1298         pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1299
1300         if (info->chip_type >= HPT374)
1301                 new_mcr = old_mcr & ~0x07;
1302         else if (info->chip_type >= HPT370) {
1303                 new_mcr = old_mcr;
1304                 new_mcr &= ~0x02;
1305
1306 #ifdef HPT_DELAY_INTERRUPT
1307                 new_mcr &= ~0x01;
1308 #else
1309                 new_mcr |=  0x01;
1310 #endif
1311         } else                                  /* HPT366 and HPT368  */
1312                 new_mcr = old_mcr & ~0x80;
1313
1314         if (new_mcr != old_mcr)
1315                 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1316
1317         if (!hwif->dma_base) {
1318                 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1319                 return;
1320         }
1321
1322         hwif->ultra_mask = 0x7f;
1323         hwif->mwdma_mask = 0x07;
1324
1325         /*
1326          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1327          * address lines to access an external EEPROM.  To read valid
1328          * cable detect state the pins must be enabled as inputs.
1329          */
1330         if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1331                 /*
1332                  * HPT374 PCI function 1
1333                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1334                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1335                  */
1336                 u8  mcr_addr = hwif->select_data + 2;
1337                 u16 mcr;
1338
1339                 pci_read_config_word (dev, mcr_addr, &mcr);
1340                 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1341                 /* now read cable id register */
1342                 pci_read_config_byte (dev, 0x5a, &scr1);
1343                 pci_write_config_word(dev, mcr_addr, mcr);
1344         } else if (chip_type >= HPT370) {
1345                 /*
1346                  * HPT370/372 and 374 pcifn 0
1347                  * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1348                  */
1349                 u8 scr2 = 0;
1350
1351                 pci_read_config_byte (dev, 0x5b, &scr2);
1352                 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1353                 /* now read cable id register */
1354                 pci_read_config_byte (dev, 0x5a, &scr1);
1355                 pci_write_config_byte(dev, 0x5b,  scr2);
1356         } else
1357                 pci_read_config_byte (dev, 0x5a, &scr1);
1358
1359         if (!hwif->udma_four)
1360                 hwif->udma_four = (scr1 & ata66) ? 0 : 1;
1361
1362         hwif->ide_dma_check             = &hpt366_config_drive_xfer_rate;
1363
1364         if (chip_type >= HPT374) {
1365                 hwif->ide_dma_test_irq  = &hpt374_ide_dma_test_irq;
1366                 hwif->ide_dma_end       = &hpt374_ide_dma_end;
1367         } else if (chip_type >= HPT370) {
1368                 hwif->dma_start         = &hpt370_ide_dma_start;
1369                 hwif->ide_dma_end       = &hpt370_ide_dma_end;
1370                 hwif->ide_dma_timeout   = &hpt370_ide_dma_timeout;
1371         } else
1372                 hwif->ide_dma_lostirq   = &hpt366_ide_dma_lostirq;
1373
1374         if (!noautodma)
1375                 hwif->autodma = 1;
1376         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1377 }
1378
1379 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1380 {
1381         struct pci_dev  *dev            = hwif->pci_dev;
1382         u8 masterdma    = 0, slavedma   = 0;
1383         u8 dma_new      = 0, dma_old    = 0;
1384         unsigned long flags;
1385
1386         dma_old = hwif->INB(dmabase + 2);
1387
1388         local_irq_save(flags);
1389
1390         dma_new = dma_old;
1391         pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1392         pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47,  &slavedma);
1393
1394         if (masterdma & 0x30)   dma_new |= 0x20;
1395         if ( slavedma & 0x30)   dma_new |= 0x40;
1396         if (dma_new != dma_old)
1397                 hwif->OUTB(dma_new, dmabase + 2);
1398
1399         local_irq_restore(flags);
1400
1401         ide_setup_dma(hwif, dmabase, 8);
1402 }
1403
1404 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1405 {
1406         struct pci_dev *dev2;
1407
1408         if (PCI_FUNC(dev->devfn) & 1)
1409                 return -ENODEV;
1410
1411         pci_set_drvdata(dev, &hpt374);
1412
1413         if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1414                 int ret;
1415
1416                 pci_set_drvdata(dev2, &hpt374);
1417
1418                 if (dev2->irq != dev->irq) {
1419                         /* FIXME: we need a core pci_set_interrupt() */
1420                         dev2->irq = dev->irq;
1421                         printk(KERN_WARNING "%s: PCI config space interrupt "
1422                                "fixed.\n", d->name);
1423                 }
1424                 ret = ide_setup_pci_devices(dev, dev2, d);
1425                 if (ret < 0)
1426                         pci_dev_put(dev2);
1427                 return ret;
1428         }
1429         return ide_setup_pci_device(dev, d);
1430 }
1431
1432 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1433 {
1434         pci_set_drvdata(dev, &hpt372n);
1435
1436         return ide_setup_pci_device(dev, d);
1437 }
1438
1439 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1440 {
1441         struct hpt_info *info;
1442         u8 rev = 0, mcr1 = 0;
1443
1444         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1445
1446         if (rev > 1) {
1447                 d->name = "HPT371N";
1448
1449                 info = &hpt371n;
1450         } else
1451                 info = &hpt371;
1452
1453         /*
1454          * HPT371 chips physically have only one channel, the secondary one,
1455          * but the primary channel registers do exist!  Go figure...
1456          * So,  we manually disable the non-existing channel here
1457          * (if the BIOS hasn't done this already).
1458          */
1459         pci_read_config_byte(dev, 0x50, &mcr1);
1460         if (mcr1 & 0x04)
1461                 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1462
1463         pci_set_drvdata(dev, info);
1464
1465         return ide_setup_pci_device(dev, d);
1466 }
1467
1468 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1469 {
1470         struct hpt_info *info;
1471         u8 rev = 0;
1472
1473         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1474
1475         if (rev > 1) {
1476                 d->name = "HPT372N";
1477
1478                 info = &hpt372n;
1479         } else
1480                 info = &hpt372a;
1481         pci_set_drvdata(dev, info);
1482
1483         return ide_setup_pci_device(dev, d);
1484 }
1485
1486 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1487 {
1488         struct hpt_info *info;
1489         u8 rev = 0;
1490
1491         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1492
1493         if (rev > 1) {
1494                 d->name = "HPT302N";
1495
1496                 info = &hpt302n;
1497         } else
1498                 info = &hpt302;
1499         pci_set_drvdata(dev, info);
1500
1501         return ide_setup_pci_device(dev, d);
1502 }
1503
1504 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1505 {
1506         struct pci_dev *dev2;
1507         u8 rev = 0;
1508         static char   *chipset_names[] = { "HPT366", "HPT366",  "HPT368",
1509                                            "HPT370", "HPT370A", "HPT372",
1510                                            "HPT372N" };
1511         static struct hpt_info *info[] = { &hpt36x,  &hpt36x,  &hpt36x,
1512                                            &hpt370,  &hpt370a, &hpt372,
1513                                            &hpt372n  };
1514
1515         if (PCI_FUNC(dev->devfn) & 1)
1516                 return -ENODEV;
1517
1518         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1519
1520         if (rev > 6)
1521                 rev = 6;
1522
1523         d->name = chipset_names[rev];
1524
1525         pci_set_drvdata(dev, info[rev]);
1526
1527         if (rev > 2)
1528                 goto init_single;
1529
1530         d->channels = 1;
1531
1532         if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1533                 u8  pin1 = 0, pin2 = 0;
1534                 int ret;
1535
1536                 pci_set_drvdata(dev2, info[rev]);
1537
1538                 pci_read_config_byte(dev,  PCI_INTERRUPT_PIN, &pin1);
1539                 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1540                 if (pin1 != pin2 && dev->irq == dev2->irq) {
1541                         d->bootable = ON_BOARD;
1542                         printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1543                                d->name, pin1, pin2);
1544                 }
1545                 ret = ide_setup_pci_devices(dev, dev2, d);
1546                 if (ret < 0)
1547                         pci_dev_put(dev2);
1548                 return ret;
1549         }
1550 init_single:
1551         return ide_setup_pci_device(dev, d);
1552 }
1553
1554 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1555         {       /* 0 */
1556                 .name           = "HPT366",
1557                 .init_setup     = init_setup_hpt366,
1558                 .init_chipset   = init_chipset_hpt366,
1559                 .init_hwif      = init_hwif_hpt366,
1560                 .init_dma       = init_dma_hpt366,
1561                 .channels       = 2,
1562                 .autodma        = AUTODMA,
1563                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1564                 .bootable       = OFF_BOARD,
1565                 .extra          = 240
1566         },{     /* 1 */
1567                 .name           = "HPT372A",
1568                 .init_setup     = init_setup_hpt372a,
1569                 .init_chipset   = init_chipset_hpt366,
1570                 .init_hwif      = init_hwif_hpt366,
1571                 .init_dma       = init_dma_hpt366,
1572                 .channels       = 2,
1573                 .autodma        = AUTODMA,
1574                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1575                 .bootable       = OFF_BOARD,
1576                 .extra          = 240
1577         },{     /* 2 */
1578                 .name           = "HPT302",
1579                 .init_setup     = init_setup_hpt302,
1580                 .init_chipset   = init_chipset_hpt366,
1581                 .init_hwif      = init_hwif_hpt366,
1582                 .init_dma       = init_dma_hpt366,
1583                 .channels       = 2,
1584                 .autodma        = AUTODMA,
1585                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1586                 .bootable       = OFF_BOARD,
1587                 .extra          = 240
1588         },{     /* 3 */
1589                 .name           = "HPT371",
1590                 .init_setup     = init_setup_hpt371,
1591                 .init_chipset   = init_chipset_hpt366,
1592                 .init_hwif      = init_hwif_hpt366,
1593                 .init_dma       = init_dma_hpt366,
1594                 .channels       = 2,
1595                 .autodma        = AUTODMA,
1596                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1597                 .bootable       = OFF_BOARD,
1598                 .extra          = 240
1599         },{     /* 4 */
1600                 .name           = "HPT374",
1601                 .init_setup     = init_setup_hpt374,
1602                 .init_chipset   = init_chipset_hpt366,
1603                 .init_hwif      = init_hwif_hpt366,
1604                 .init_dma       = init_dma_hpt366,
1605                 .channels       = 2,    /* 4 */
1606                 .autodma        = AUTODMA,
1607                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1608                 .bootable       = OFF_BOARD,
1609                 .extra          = 240
1610         },{     /* 5 */
1611                 .name           = "HPT372N",
1612                 .init_setup     = init_setup_hpt372n,
1613                 .init_chipset   = init_chipset_hpt366,
1614                 .init_hwif      = init_hwif_hpt366,
1615                 .init_dma       = init_dma_hpt366,
1616                 .channels       = 2,    /* 4 */
1617                 .autodma        = AUTODMA,
1618                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1619                 .bootable       = OFF_BOARD,
1620                 .extra          = 240
1621         }
1622 };
1623
1624 /**
1625  *      hpt366_init_one -       called when an HPT366 is found
1626  *      @dev: the hpt366 device
1627  *      @id: the matching pci id
1628  *
1629  *      Called when the PCI registration layer (or the IDE initialization)
1630  *      finds a device matching our IDE device tables.
1631  *
1632  *      NOTE: since we'll have to modify some fields of the ide_pci_device_t
1633  *      structure depending on the chip's revision, we'd better pass a local
1634  *      copy down the call chain...
1635  */
1636 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1637 {
1638         ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1639
1640         return d.init_setup(dev, &d);
1641 }
1642
1643 static struct pci_device_id hpt366_pci_tbl[] = {
1644         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1645         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1646         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1647         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1648         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1649         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1650         { 0, },
1651 };
1652 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1653
1654 static struct pci_driver driver = {
1655         .name           = "HPT366_IDE",
1656         .id_table       = hpt366_pci_tbl,
1657         .probe          = hpt366_init_one,
1658 };
1659
1660 static int __init hpt366_ide_init(void)
1661 {
1662         return ide_pci_register_driver(&driver);
1663 }
1664
1665 module_init(hpt366_ide_init);
1666
1667 MODULE_AUTHOR("Andre Hedrick");
1668 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1669 MODULE_LICENSE("GPL");