drivers/ide/mips/au1xxx-ide.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
   4  *
   5  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
   6  *
   7  * This program is free software; you can redistribute it and/or modify it under
   8  * the terms of the GNU General Public License as published by the Free Software
   9  * Foundation; either version 2 of the License, or (at your option) any later
  10  * version.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  14  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
  15  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  16  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  17  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  18  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  19  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  21  * POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program; if not, write to the Free Software Foundation, Inc.,
  25  * 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  28  *       Interface and Linux Device Driver" Application Note.
  29  */
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/delay.h>
  34 #include <linux/platform_device.h>
  35
  36 #include <linux/init.h>
  37 #include <linux/ide.h>
  38 #include <linux/sysdev.h>
  39
  40 #include <linux/dma-mapping.h>
  41
  42 #include "ide-timing.h"
  43
  44 #include <asm/io.h>
  45 #include <asm/mach-au1x00/au1xxx.h>
  46 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  47
  48 #include <asm/mach-au1x00/au1xxx_ide.h>
  49
  50 #define DRV_NAME        "au1200-ide"
  51 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
  52
  53 /* enable the burstmode in the dbdma */
  54 #define IDE_AU1XXX_BURSTMODE    1
  55
  56 static _auide_hwif auide_hwif;
  57 static int dbdma_init_done;
  58
  59 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
  60
  61 void auide_insw(unsigned long port, void *addr, u32 count)
  62 {
  63         _auide_hwif *ahwif = &auide_hwif;
  64         chan_tab_t *ctp;
  65         au1x_ddma_desc_t *dp;
  66
  67         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
  68                            DDMA_FLAGS_NOIE)) {
  69                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
  70                 return;
  71         }
  72         ctp = *((chan_tab_t **)ahwif->rx_chan);
  73         dp = ctp->cur_ptr;
  74         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  75                 ;
  76         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  77 }
  78
  79 void auide_outsw(unsigned long port, void *addr, u32 count)
  80 {
  81         _auide_hwif *ahwif = &auide_hwif;
  82         chan_tab_t *ctp;
  83         au1x_ddma_desc_t *dp;
  84
  85         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
  86                              count << 1, DDMA_FLAGS_NOIE)) {
  87                 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
  88                 return;
  89         }
  90         ctp = *((chan_tab_t **)ahwif->tx_chan);
  91         dp = ctp->cur_ptr;
  92         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  93                 ;
  94         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  95 }
  96
  97 #endif
  98
  99 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 100 {
 101         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 102
 103         /* set pio mode! */
 104         switch(pio) {
 105         case 0:
 106                 mem_sttime = SBC_IDE_TIMING(PIO0);
 107
 108                 /* set configuration for RCS2# */
 109                 mem_stcfg |= TS_MASK;
 110                 mem_stcfg &= ~TCSOE_MASK;
 111                 mem_stcfg &= ~TOECS_MASK;
 112                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
 113                 break;
 114
 115         case 1:
 116                 mem_sttime = SBC_IDE_TIMING(PIO1);
 117
 118                 /* set configuration for RCS2# */
 119                 mem_stcfg |= TS_MASK;
 120                 mem_stcfg &= ~TCSOE_MASK;
 121                 mem_stcfg &= ~TOECS_MASK;
 122                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
 123                 break;
 124
 125         case 2:
 126                 mem_sttime = SBC_IDE_TIMING(PIO2);
 127
 128                 /* set configuration for RCS2# */
 129                 mem_stcfg &= ~TS_MASK;
 130                 mem_stcfg &= ~TCSOE_MASK;
 131                 mem_stcfg &= ~TOECS_MASK;
 132                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
 133                 break;
 134
 135         case 3:
 136                 mem_sttime = SBC_IDE_TIMING(PIO3);
 137
 138                 /* set configuration for RCS2# */
 139                 mem_stcfg &= ~TS_MASK;
 140                 mem_stcfg &= ~TCSOE_MASK;
 141                 mem_stcfg &= ~TOECS_MASK;
 142                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
 143
 144                 break;
 145
 146         case 4:
 147                 mem_sttime = SBC_IDE_TIMING(PIO4);
 148
 149                 /* set configuration for RCS2# */
 150                 mem_stcfg &= ~TS_MASK;
 151                 mem_stcfg &= ~TCSOE_MASK;
 152                 mem_stcfg &= ~TOECS_MASK;
 153                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
 154                 break;
 155         }
 156
 157         au_writel(mem_sttime,MEM_STTIME2);
 158         au_writel(mem_stcfg,MEM_STCFG2);
 159 }
 160
 161 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
 162 {
 163         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 164
 165         switch(speed) {
 166 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 167         case XFER_MW_DMA_2:
 168                 mem_sttime = SBC_IDE_TIMING(MDMA2);
 169
 170                 /* set configuration for RCS2# */
 171                 mem_stcfg &= ~TS_MASK;
 172                 mem_stcfg &= ~TCSOE_MASK;
 173                 mem_stcfg &= ~TOECS_MASK;
 174                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
 175
 176                 break;
 177         case XFER_MW_DMA_1:
 178                 mem_sttime = SBC_IDE_TIMING(MDMA1);
 179
 180                 /* set configuration for RCS2# */
 181                 mem_stcfg &= ~TS_MASK;
 182                 mem_stcfg &= ~TCSOE_MASK;
 183                 mem_stcfg &= ~TOECS_MASK;
 184                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
 185
 186                 break;
 187         case XFER_MW_DMA_0:
 188                 mem_sttime = SBC_IDE_TIMING(MDMA0);
 189
 190                 /* set configuration for RCS2# */
 191                 mem_stcfg |= TS_MASK;
 192                 mem_stcfg &= ~TCSOE_MASK;
 193                 mem_stcfg &= ~TOECS_MASK;
 194                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
 195
 196                 break;
 197 #endif
 198         }
 199
 200         au_writel(mem_sttime,MEM_STTIME2);
 201         au_writel(mem_stcfg,MEM_STCFG2);
 202 }
 203
 204 /*
 205  * Multi-Word DMA + DbDMA functions
 206  */
 207
 208 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 209 static int auide_build_dmatable(ide_drive_t *drive)
 210 {
 211         int i, iswrite, count = 0;
 212         ide_hwif_t *hwif = HWIF(drive);
 213
 214         struct request *rq = HWGROUP(drive)->rq;
 215
 216         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
 217         struct scatterlist *sg;
 218
 219         iswrite = (rq_data_dir(rq) == WRITE);
 220         /* Save for interrupt context */
 221         ahwif->drive = drive;
 222
 223         hwif->sg_nents = i = ide_build_sglist(drive, rq);
 224
 225         if (!i)
 226                 return 0;
 227
 228         /* fill the descriptors */
 229         sg = hwif->sg_table;
 230         while (i && sg_dma_len(sg)) {
 231                 u32 cur_addr;
 232                 u32 cur_len;
 233
 234                 cur_addr = sg_dma_address(sg);
 235                 cur_len = sg_dma_len(sg);
 236
 237                 while (cur_len) {
 238                         u32 flags = DDMA_FLAGS_NOIE;
 239                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
 240
 241                         if (++count >= PRD_ENTRIES) {
 242                                 printk(KERN_WARNING "%s: DMA table too small\n",
 243                                        drive->name);
 244                                 goto use_pio_instead;
 245                         }
 246
 247                         /* Lets enable intr for the last descriptor only */
 248                         if (1==i)
 249                                 flags = DDMA_FLAGS_IE;
 250                         else
 251                                 flags = DDMA_FLAGS_NOIE;
 252
 253                         if (iswrite) {
 254                                 if(!put_source_flags(ahwif->tx_chan,
 255                                                      (void*) sg_virt(sg),
 256                                                      tc, flags)) {
 257                                         printk(KERN_ERR "%s failed %d\n",
 258                                                __FUNCTION__, __LINE__);
 259                                 }
 260                         } else
 261                         {
 262                                 if(!put_dest_flags(ahwif->rx_chan,
 263                                                    (void*) sg_virt(sg),
 264                                                    tc, flags)) {
 265                                         printk(KERN_ERR "%s failed %d\n",
 266                                                __FUNCTION__, __LINE__);
 267                                 }
 268                         }
 269
 270                         cur_addr += tc;
 271                         cur_len -= tc;
 272                 }
 273                 sg = sg_next(sg);
 274                 i--;
 275         }
 276
 277         if (count)
 278                 return 1;
 279
 280  use_pio_instead:
 281         ide_destroy_dmatable(drive);
 282
 283         return 0; /* revert to PIO for this request */
 284 }
 285
 286 static int auide_dma_end(ide_drive_t *drive)
 287 {
 288         ide_hwif_t *hwif = HWIF(drive);
 289
 290         if (hwif->sg_nents) {
 291                 ide_destroy_dmatable(drive);
 292                 hwif->sg_nents = 0;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static void auide_dma_start(ide_drive_t *drive )
 299 {
 300 }
 301
 302
 303 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
 304 {
 305         /* issue cmd to drive */
 306         ide_execute_command(drive, command, &ide_dma_intr,
 307                             (2*WAIT_CMD), NULL);
 308 }
 309
 310 static int auide_dma_setup(ide_drive_t *drive)
 311 {
 312         struct request *rq = HWGROUP(drive)->rq;
 313
 314         if (!auide_build_dmatable(drive)) {
 315                 ide_map_sg(drive, rq);
 316                 return 1;
 317         }
 318
 319         drive->waiting_for_dma = 1;
 320         return 0;
 321 }
 322
 323 static u8 auide_mdma_filter(ide_drive_t *drive)
 324 {
 325         /*
 326          * FIXME: ->white_list and ->black_list are based on completely bogus
 327          * ->ide_dma_check implementation which didn't set neither the host
 328          * controller timings nor the device for the desired transfer mode.
 329          *
 330          * They should be either removed or 0x00 MWDMA mask should be
 331          * returned for devices on the ->black_list.
 332          */
 333
 334         if (dbdma_init_done == 0) {
 335                 auide_hwif.white_list = ide_in_drive_list(drive->id,
 336                                                           dma_white_list);
 337                 auide_hwif.black_list = ide_in_drive_list(drive->id,
 338                                                           dma_black_list);
 339                 auide_hwif.drive = drive;
 340                 auide_ddma_init(&auide_hwif);
 341                 dbdma_init_done = 1;
 342         }
 343
 344         /* Is the drive in our DMA black list? */
 345         if (auide_hwif.black_list)
 346                 printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
 347                                     drive->name, drive->id->model);
 348
 349         return drive->hwif->mwdma_mask;
 350 }
 351
 352 static int auide_dma_test_irq(ide_drive_t *drive)
 353 {
 354         if (drive->waiting_for_dma == 0)
 355                 printk(KERN_WARNING "%s: ide_dma_test_irq \
 356                                      called while not waiting\n", drive->name);
 357
 358         /* If dbdma didn't execute the STOP command yet, the
 359          * active bit is still set
 360          */
 361         drive->waiting_for_dma++;
 362         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
 363                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
 364                                      complete\n", drive->name);
 365                 return 1;
 366         }
 367         udelay(10);
 368         return 0;
 369 }
 370
 371 static void auide_dma_host_set(ide_drive_t *drive, int on)
 372 {
 373 }
 374
 375 static void auide_dma_lost_irq(ide_drive_t *drive)
 376 {
 377         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 378 }
 379
 380 static void auide_ddma_tx_callback(int irq, void *param)
 381 {
 382         _auide_hwif *ahwif = (_auide_hwif*)param;
 383         ahwif->drive->waiting_for_dma = 0;
 384 }
 385
 386 static void auide_ddma_rx_callback(int irq, void *param)
 387 {
 388         _auide_hwif *ahwif = (_auide_hwif*)param;
 389         ahwif->drive->waiting_for_dma = 0;
 390 }
 391
 392 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 393
 394 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
 395 {
 396         dev->dev_id          = dev_id;
 397         dev->dev_physaddr    = (u32)AU1XXX_ATA_PHYS_ADDR;
 398         dev->dev_intlevel    = 0;
 399         dev->dev_intpolarity = 0;
 400         dev->dev_tsize       = tsize;
 401         dev->dev_devwidth    = devwidth;
 402         dev->dev_flags       = flags;
 403 }
 404
 405 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 406
 407 static void auide_dma_timeout(ide_drive_t *drive)
 408 {
 409         ide_hwif_t *hwif = HWIF(drive);
 410
 411         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 412
 413         if (hwif->ide_dma_test_irq(drive))
 414                 return;
 415
 416         hwif->ide_dma_end(drive);
 417 }
 418
 419
 420 static int auide_ddma_init(_auide_hwif *auide) {
 421
 422         dbdev_tab_t source_dev_tab, target_dev_tab;
 423         u32 dev_id, tsize, devwidth, flags;
 424         ide_hwif_t *hwif = auide->hwif;
 425
 426         dev_id   = AU1XXX_ATA_DDMA_REQ;
 427
 428         if (auide->white_list || auide->black_list) {
 429                 tsize    = 8;
 430                 devwidth = 32;
 431         }
 432         else {
 433                 tsize    = 1;
 434                 devwidth = 16;
 435
 436                 printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
 437                 printk(KERN_ERR "            please read 'Documentation/mips/AU1xxx_IDE.README'");
 438         }
 439
 440 #ifdef IDE_AU1XXX_BURSTMODE
 441         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 442 #else
 443         flags = DEV_FLAGS_SYNC;
 444 #endif
 445
 446         /* setup dev_tab for tx channel */
 447         auide_init_dbdma_dev( &source_dev_tab,
 448                               dev_id,
 449                               tsize, devwidth, DEV_FLAGS_OUT | flags);
 450         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 451
 452         auide_init_dbdma_dev( &source_dev_tab,
 453                               dev_id,
 454                               tsize, devwidth, DEV_FLAGS_IN | flags);
 455         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 456
 457         /* We also need to add a target device for the DMA */
 458         auide_init_dbdma_dev( &target_dev_tab,
 459                               (u32)DSCR_CMD0_ALWAYS,
 460                               tsize, devwidth, DEV_FLAGS_ANYUSE);
 461         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
 462
 463         /* Get a channel for TX */
 464         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
 465                                                  auide->tx_dev_id,
 466                                                  auide_ddma_tx_callback,
 467                                                  (void*)auide);
 468
 469         /* Get a channel for RX */
 470         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 471                                                  auide->target_dev_id,
 472                                                  auide_ddma_rx_callback,
 473                                                  (void*)auide);
 474
 475         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 476                                                              NUM_DESCRIPTORS);
 477         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 478                                                              NUM_DESCRIPTORS);
 479
 480         hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev,
 481                                                 PRD_ENTRIES * PRD_BYTES,        /* 1 Page */
 482                                                 &hwif->dmatable_dma, GFP_KERNEL);
 483
 484         au1xxx_dbdma_start( auide->tx_chan );
 485         au1xxx_dbdma_start( auide->rx_chan );
 486
 487         return 0;
 488 }
 489 #else
 490
 491 static int auide_ddma_init( _auide_hwif *auide )
 492 {
 493         dbdev_tab_t source_dev_tab;
 494         int flags;
 495
 496 #ifdef IDE_AU1XXX_BURSTMODE
 497         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 498 #else
 499         flags = DEV_FLAGS_SYNC;
 500 #endif
 501
 502         /* setup dev_tab for tx channel */
 503         auide_init_dbdma_dev( &source_dev_tab,
 504                               (u32)DSCR_CMD0_ALWAYS,
 505                               8, 32, DEV_FLAGS_OUT | flags);
 506         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 507
 508         auide_init_dbdma_dev( &source_dev_tab,
 509                               (u32)DSCR_CMD0_ALWAYS,
 510                               8, 32, DEV_FLAGS_IN | flags);
 511         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 512
 513         /* Get a channel for TX */
 514         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
 515                                                  auide->tx_dev_id,
 516                                                  NULL,
 517                                                  (void*)auide);
 518
 519         /* Get a channel for RX */
 520         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 521                                                  DSCR_CMD0_ALWAYS,
 522                                                  NULL,
 523                                                  (void*)auide);
 524
 525         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 526                                                              NUM_DESCRIPTORS);
 527         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 528                                                              NUM_DESCRIPTORS);
 529
 530         au1xxx_dbdma_start( auide->tx_chan );
 531         au1xxx_dbdma_start( auide->rx_chan );
 532
 533         return 0;
 534 }
 535 #endif
 536
 537 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
 538 {
 539         int i;
 540         unsigned long *ata_regs = hw->io_ports;
 541
 542         /* FIXME? */
 543         for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
 544                 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
 545         }
 546
 547         /* set the Alternative Status register */
 548         *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
 549 }
 550
 551 static const struct ide_port_info au1xxx_port_info = {
 552         .host_flags             = IDE_HFLAG_POST_SET_MODE |
 553                                   IDE_HFLAG_NO_DMA | /* no SFF-style DMA */
 554                                   IDE_HFLAG_NO_IO_32BIT |
 555                                   IDE_HFLAG_UNMASK_IRQS,
 556         .pio_mask               = ATA_PIO4,
 557 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 558         .mwdma_mask             = ATA_MWDMA2,
 559 #endif
 560 };
 561
 562 static int au_ide_probe(struct device *dev)
 563 {
 564         struct platform_device *pdev = to_platform_device(dev);
 565         _auide_hwif *ahwif = &auide_hwif;
 566         ide_hwif_t *hwif;
 567         struct resource *res;
 568         int ret = 0;
 569         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 570         hw_regs_t hw;
 571
 572 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 573         char *mode = "MWDMA2";
 574 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
 575         char *mode = "PIO+DDMA(offload)";
 576 #endif
 577
 578         memset(&auide_hwif, 0, sizeof(_auide_hwif));
 579         ahwif->irq = platform_get_irq(pdev, 0);
 580
 581         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 582
 583         if (res == NULL) {
 584                 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
 585                 ret = -ENODEV;
 586                 goto out;
 587         }
 588         if (ahwif->irq < 0) {
 589                 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
 590                 ret = -ENODEV;
 591                 goto out;
 592         }
 593
 594         if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
 595                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
 596                 ret =  -EBUSY;
 597                 goto out;
 598         }
 599
 600         ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
 601         if (ahwif->regbase == 0) {
 602                 ret = -ENOMEM;
 603                 goto out;
 604         }
 605
 606         /* FIXME:  This might possibly break PCMCIA IDE devices */
 607
 608         hwif                            = &ide_hwifs[pdev->id];
 609
 610         memset(&hw, 0, sizeof(hw));
 611         auide_setup_ports(&hw, ahwif);
 612         hw.irq = ahwif->irq;
 613         hw.dev = dev;
 614         hw.chipset = ide_au1xxx;
 615
 616         ide_init_port_hw(hwif, &hw);
 617
 618         hwif->dev = dev;
 619
 620         /* hold should be on in all cases */
 621         hwif->hold                      = 1;
 622
 623         hwif->mmio  = 1;
 624
 625         /* If the user has selected DDMA assisted copies,
 626            then set up a few local I/O function entry points
 627         */
 628
 629 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 630         hwif->INSW                      = auide_insw;
 631         hwif->OUTSW                     = auide_outsw;
 632 #endif
 633
 634         hwif->set_pio_mode              = &au1xxx_set_pio_mode;
 635         hwif->set_dma_mode              = &auide_set_dma_mode;
 636
 637 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 638         hwif->dma_timeout               = &auide_dma_timeout;
 639
 640         hwif->mdma_filter               = &auide_mdma_filter;
 641
 642         hwif->dma_host_set              = &auide_dma_host_set;
 643         hwif->dma_exec_cmd              = &auide_dma_exec_cmd;
 644         hwif->dma_start                 = &auide_dma_start;
 645         hwif->ide_dma_end               = &auide_dma_end;
 646         hwif->dma_setup                 = &auide_dma_setup;
 647         hwif->ide_dma_test_irq          = &auide_dma_test_irq;
 648         hwif->dma_lost_irq              = &auide_dma_lost_irq;
 649 #endif
 650         hwif->select_data               = 0;    /* no chipset-specific code */
 651         hwif->config_data               = 0;    /* no chipset-specific code */
 652
 653         auide_hwif.hwif                 = hwif;
 654         hwif->hwif_data                 = &auide_hwif;
 655
 656 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 657         auide_ddma_init(&auide_hwif);
 658         dbdma_init_done = 1;
 659 #endif
 660
 661         idx[0] = hwif->index;
 662
 663         ide_device_add(idx, &au1xxx_port_info);
 664
 665         dev_set_drvdata(dev, hwif);
 666
 667         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
 668
 669  out:
 670         return ret;
 671 }
 672
 673 static int au_ide_remove(struct device *dev)
 674 {
 675         struct platform_device *pdev = to_platform_device(dev);
 676         struct resource *res;
 677         ide_hwif_t *hwif = dev_get_drvdata(dev);
 678         _auide_hwif *ahwif = &auide_hwif;
 679
 680         ide_unregister(hwif->index, 0, 0);
 681
 682         iounmap((void *)ahwif->regbase);
 683
 684         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 685         release_mem_region(res->start, res->end - res->start);
 686
 687         return 0;
 688 }
 689
 690 static struct device_driver au1200_ide_driver = {
 691         .name           = "au1200-ide",
 692         .bus            = &platform_bus_type,
 693         .probe          = au_ide_probe,
 694         .remove         = au_ide_remove,
 695 };
 696
 697 static int __init au_ide_init(void)
 698 {
 699         return driver_register(&au1200_ide_driver);
 700 }
 701
 702 static void __exit au_ide_exit(void)
 703 {
 704         driver_unregister(&au1200_ide_driver);
 705 }
 706
 707 MODULE_LICENSE("GPL");
 708 MODULE_DESCRIPTION("AU1200 IDE driver");
 709
 710 module_init(au_ide_init);
 711 module_exit(au_ide_exit);