drivers/i2c/busses/i2c-stm32f7.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for STMicroelectronics STM32F7 I2C controller
   4  *
   5  * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
   6  * reference manual.
   7  * Please see below a link to the documentation:
   8  * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
   9  *
  10  * Copyright (C) M'boumba Cedric Madianga 2017
  11  * Copyright (C) STMicroelectronics 2017
  12  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
  13  *
  14  * This driver is based on i2c-stm32f4.c
  15  *
  16  */
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/module.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pinctrl/consumer.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/regmap.h>
  34 #include <linux/reset.h>
  35 #include <linux/slab.h>
  36
  37 #include "i2c-stm32.h"
  38
  39 /* STM32F7 I2C registers */
  40 #define STM32F7_I2C_CR1                         0x00
  41 #define STM32F7_I2C_CR2                         0x04
  42 #define STM32F7_I2C_OAR1                        0x08
  43 #define STM32F7_I2C_OAR2                        0x0C
  44 #define STM32F7_I2C_PECR                        0x20
  45 #define STM32F7_I2C_TIMINGR                     0x10
  46 #define STM32F7_I2C_ISR                         0x18
  47 #define STM32F7_I2C_ICR                         0x1C
  48 #define STM32F7_I2C_RXDR                        0x24
  49 #define STM32F7_I2C_TXDR                        0x28
  50
  51 /* STM32F7 I2C control 1 */
  52 #define STM32F7_I2C_CR1_PECEN                   BIT(23)
  53 #define STM32F7_I2C_CR1_SBC                     BIT(16)
  54 #define STM32F7_I2C_CR1_RXDMAEN                 BIT(15)
  55 #define STM32F7_I2C_CR1_TXDMAEN                 BIT(14)
  56 #define STM32F7_I2C_CR1_ANFOFF                  BIT(12)
  57 #define STM32F7_I2C_CR1_ERRIE                   BIT(7)
  58 #define STM32F7_I2C_CR1_TCIE                    BIT(6)
  59 #define STM32F7_I2C_CR1_STOPIE                  BIT(5)
  60 #define STM32F7_I2C_CR1_NACKIE                  BIT(4)
  61 #define STM32F7_I2C_CR1_ADDRIE                  BIT(3)
  62 #define STM32F7_I2C_CR1_RXIE                    BIT(2)
  63 #define STM32F7_I2C_CR1_TXIE                    BIT(1)
  64 #define STM32F7_I2C_CR1_PE                      BIT(0)
  65 #define STM32F7_I2C_ALL_IRQ_MASK                (STM32F7_I2C_CR1_ERRIE \
  66                                                 | STM32F7_I2C_CR1_TCIE \
  67                                                 | STM32F7_I2C_CR1_STOPIE \
  68                                                 | STM32F7_I2C_CR1_NACKIE \
  69                                                 | STM32F7_I2C_CR1_RXIE \
  70                                                 | STM32F7_I2C_CR1_TXIE)
  71 #define STM32F7_I2C_XFER_IRQ_MASK               (STM32F7_I2C_CR1_TCIE \
  72                                                 | STM32F7_I2C_CR1_STOPIE \
  73                                                 | STM32F7_I2C_CR1_NACKIE \
  74                                                 | STM32F7_I2C_CR1_RXIE \
  75                                                 | STM32F7_I2C_CR1_TXIE)
  76
  77 /* STM32F7 I2C control 2 */
  78 #define STM32F7_I2C_CR2_PECBYTE                 BIT(26)
  79 #define STM32F7_I2C_CR2_RELOAD                  BIT(24)
  80 #define STM32F7_I2C_CR2_NBYTES_MASK             GENMASK(23, 16)
  81 #define STM32F7_I2C_CR2_NBYTES(n)               (((n) & 0xff) << 16)
  82 #define STM32F7_I2C_CR2_NACK                    BIT(15)
  83 #define STM32F7_I2C_CR2_STOP                    BIT(14)
  84 #define STM32F7_I2C_CR2_START                   BIT(13)
  85 #define STM32F7_I2C_CR2_HEAD10R                 BIT(12)
  86 #define STM32F7_I2C_CR2_ADD10                   BIT(11)
  87 #define STM32F7_I2C_CR2_RD_WRN                  BIT(10)
  88 #define STM32F7_I2C_CR2_SADD10_MASK             GENMASK(9, 0)
  89 #define STM32F7_I2C_CR2_SADD10(n)               (((n) & \
  90                                                 STM32F7_I2C_CR2_SADD10_MASK))
  91 #define STM32F7_I2C_CR2_SADD7_MASK              GENMASK(7, 1)
  92 #define STM32F7_I2C_CR2_SADD7(n)                (((n) & 0x7f) << 1)
  93
  94 /* STM32F7 I2C Own Address 1 */
  95 #define STM32F7_I2C_OAR1_OA1EN                  BIT(15)
  96 #define STM32F7_I2C_OAR1_OA1MODE                BIT(10)
  97 #define STM32F7_I2C_OAR1_OA1_10_MASK            GENMASK(9, 0)
  98 #define STM32F7_I2C_OAR1_OA1_10(n)              (((n) & \
  99                                                 STM32F7_I2C_OAR1_OA1_10_MASK))
 100 #define STM32F7_I2C_OAR1_OA1_7_MASK             GENMASK(7, 1)
 101 #define STM32F7_I2C_OAR1_OA1_7(n)               (((n) & 0x7f) << 1)
 102 #define STM32F7_I2C_OAR1_MASK                   (STM32F7_I2C_OAR1_OA1_7_MASK \
 103                                                 | STM32F7_I2C_OAR1_OA1_10_MASK \
 104                                                 | STM32F7_I2C_OAR1_OA1EN \
 105                                                 | STM32F7_I2C_OAR1_OA1MODE)
 106
 107 /* STM32F7 I2C Own Address 2 */
 108 #define STM32F7_I2C_OAR2_OA2EN                  BIT(15)
 109 #define STM32F7_I2C_OAR2_OA2MSK_MASK            GENMASK(10, 8)
 110 #define STM32F7_I2C_OAR2_OA2MSK(n)              (((n) & 0x7) << 8)
 111 #define STM32F7_I2C_OAR2_OA2_7_MASK             GENMASK(7, 1)
 112 #define STM32F7_I2C_OAR2_OA2_7(n)               (((n) & 0x7f) << 1)
 113 #define STM32F7_I2C_OAR2_MASK                   (STM32F7_I2C_OAR2_OA2MSK_MASK \
 114                                                 | STM32F7_I2C_OAR2_OA2_7_MASK \
 115                                                 | STM32F7_I2C_OAR2_OA2EN)
 116
 117 /* STM32F7 I2C Interrupt Status */
 118 #define STM32F7_I2C_ISR_ADDCODE_MASK            GENMASK(23, 17)
 119 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
 120                                 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
 121 #define STM32F7_I2C_ISR_DIR                     BIT(16)
 122 #define STM32F7_I2C_ISR_BUSY                    BIT(15)
 123 #define STM32F7_I2C_ISR_PECERR                  BIT(11)
 124 #define STM32F7_I2C_ISR_ARLO                    BIT(9)
 125 #define STM32F7_I2C_ISR_BERR                    BIT(8)
 126 #define STM32F7_I2C_ISR_TCR                     BIT(7)
 127 #define STM32F7_I2C_ISR_TC                      BIT(6)
 128 #define STM32F7_I2C_ISR_STOPF                   BIT(5)
 129 #define STM32F7_I2C_ISR_NACKF                   BIT(4)
 130 #define STM32F7_I2C_ISR_ADDR                    BIT(3)
 131 #define STM32F7_I2C_ISR_RXNE                    BIT(2)
 132 #define STM32F7_I2C_ISR_TXIS                    BIT(1)
 133 #define STM32F7_I2C_ISR_TXE                     BIT(0)
 134
 135 /* STM32F7 I2C Interrupt Clear */
 136 #define STM32F7_I2C_ICR_PECCF                   BIT(11)
 137 #define STM32F7_I2C_ICR_ARLOCF                  BIT(9)
 138 #define STM32F7_I2C_ICR_BERRCF                  BIT(8)
 139 #define STM32F7_I2C_ICR_STOPCF                  BIT(5)
 140 #define STM32F7_I2C_ICR_NACKCF                  BIT(4)
 141 #define STM32F7_I2C_ICR_ADDRCF                  BIT(3)
 142
 143 /* STM32F7 I2C Timing */
 144 #define STM32F7_I2C_TIMINGR_PRESC(n)            (((n) & 0xf) << 28)
 145 #define STM32F7_I2C_TIMINGR_SCLDEL(n)           (((n) & 0xf) << 20)
 146 #define STM32F7_I2C_TIMINGR_SDADEL(n)           (((n) & 0xf) << 16)
 147 #define STM32F7_I2C_TIMINGR_SCLH(n)             (((n) & 0xff) << 8)
 148 #define STM32F7_I2C_TIMINGR_SCLL(n)             ((n) & 0xff)
 149
 150 #define STM32F7_I2C_MAX_LEN                     0xff
 151 #define STM32F7_I2C_DMA_LEN_MIN                 0x16
 152 #define STM32F7_I2C_MAX_SLAVE                   0x2
 153
 154 #define STM32F7_I2C_DNF_DEFAULT                 0
 155 #define STM32F7_I2C_DNF_MAX                     16
 156
 157 #define STM32F7_I2C_ANALOG_FILTER_ENABLE        1
 158 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN     50      /* ns */
 159 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX     260     /* ns */
 160
 161 #define STM32F7_I2C_RISE_TIME_DEFAULT           25      /* ns */
 162 #define STM32F7_I2C_FALL_TIME_DEFAULT           10      /* ns */
 163
 164 #define STM32F7_PRESC_MAX                       BIT(4)
 165 #define STM32F7_SCLDEL_MAX                      BIT(4)
 166 #define STM32F7_SDADEL_MAX                      BIT(4)
 167 #define STM32F7_SCLH_MAX                        BIT(8)
 168 #define STM32F7_SCLL_MAX                        BIT(8)
 169
 170 #define STM32F7_AUTOSUSPEND_DELAY               (HZ / 100)
 171
 172 /**
 173  * struct stm32f7_i2c_spec - private i2c specification timing
 174  * @rate: I2C bus speed (Hz)
 175  * @rate_min: 80% of I2C bus speed (Hz)
 176  * @rate_max: 100% of I2C bus speed (Hz)
 177  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 178  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 179  * @hddat_min: Min data hold time (ns)
 180  * @vddat_max: Max data valid time (ns)
 181  * @sudat_min: Min data setup time (ns)
 182  * @l_min: Min low period of the SCL clock (ns)
 183  * @h_min: Min high period of the SCL clock (ns)
 184  */
 185 struct stm32f7_i2c_spec {
 186         u32 rate;
 187         u32 rate_min;
 188         u32 rate_max;
 189         u32 fall_max;
 190         u32 rise_max;
 191         u32 hddat_min;
 192         u32 vddat_max;
 193         u32 sudat_min;
 194         u32 l_min;
 195         u32 h_min;
 196 };
 197
 198 /**
 199  * struct stm32f7_i2c_setup - private I2C timing setup parameters
 200  * @speed: I2C speed mode (standard, Fast Plus)
 201  * @speed_freq: I2C speed frequency  (Hz)
 202  * @clock_src: I2C clock source frequency (Hz)
 203  * @rise_time: Rise time (ns)
 204  * @fall_time: Fall time (ns)
 205  * @dnf: Digital filter coefficient (0-16)
 206  * @analog_filter: Analog filter delay (On/Off)
 207  */
 208 struct stm32f7_i2c_setup {
 209         enum stm32_i2c_speed speed;
 210         u32 speed_freq;
 211         u32 clock_src;
 212         u32 rise_time;
 213         u32 fall_time;
 214         u8 dnf;
 215         bool analog_filter;
 216 };
 217
 218 /**
 219  * struct stm32f7_i2c_timings - private I2C output parameters
 220  * @node: List entry
 221  * @presc: Prescaler value
 222  * @scldel: Data setup time
 223  * @sdadel: Data hold time
 224  * @sclh: SCL high period (master mode)
 225  * @scll: SCL low period (master mode)
 226  */
 227 struct stm32f7_i2c_timings {
 228         struct list_head node;
 229         u8 presc;
 230         u8 scldel;
 231         u8 sdadel;
 232         u8 sclh;
 233         u8 scll;
 234 };
 235
 236 /**
 237  * struct stm32f7_i2c_msg - client specific data
 238  * @addr: 8-bit or 10-bit slave addr, including r/w bit
 239  * @count: number of bytes to be transferred
 240  * @buf: data buffer
 241  * @result: result of the transfer
 242  * @stop: last I2C msg to be sent, i.e. STOP to be generated
 243  * @smbus: boolean to know if the I2C IP is used in SMBus mode
 244  * @size: type of SMBus protocol
 245  * @read_write: direction of SMBus protocol
 246  * SMBus block read and SMBus block write - block read process call protocols
 247  * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
 248  * contain a maximum of 32 bytes of data + byte command + byte count + PEC
 249  * This buffer has to be 32-bit aligned to be compliant with memory address
 250  * register in DMA mode.
 251  */
 252 struct stm32f7_i2c_msg {
 253         u16 addr;
 254         u32 count;
 255         u8 *buf;
 256         int result;
 257         bool stop;
 258         bool smbus;
 259         int size;
 260         char read_write;
 261         u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
 262 };
 263
 264 /**
 265  * struct stm32f7_i2c_dev - private data of the controller
 266  * @adap: I2C adapter for this controller
 267  * @dev: device for this controller
 268  * @base: virtual memory area
 269  * @complete: completion of I2C message
 270  * @clk: hw i2c clock
 271  * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
 272  * @msg: Pointer to data to be written
 273  * @msg_num: number of I2C messages to be executed
 274  * @msg_id: message identifiant
 275  * @f7_msg: customized i2c msg for driver usage
 276  * @setup: I2C timing input setup
 277  * @timing: I2C computed timings
 278  * @slave: list of slave devices registered on the I2C bus
 279  * @slave_running: slave device currently used
 280  * @slave_dir: transfer direction for the current slave device
 281  * @master_mode: boolean to know in which mode the I2C is running (master or
 282  * slave)
 283  * @dma: dma data
 284  * @use_dma: boolean to know if dma is used in the current transfer
 285  * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
 286  */
 287 struct stm32f7_i2c_dev {
 288         struct i2c_adapter adap;
 289         struct device *dev;
 290         void __iomem *base;
 291         struct completion complete;
 292         struct clk *clk;
 293         int speed;
 294         struct i2c_msg *msg;
 295         unsigned int msg_num;
 296         unsigned int msg_id;
 297         struct stm32f7_i2c_msg f7_msg;
 298         struct stm32f7_i2c_setup setup;
 299         struct stm32f7_i2c_timings timing;
 300         struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
 301         struct i2c_client *slave_running;
 302         u32 slave_dir;
 303         bool master_mode;
 304         struct stm32_i2c_dma *dma;
 305         bool use_dma;
 306         struct regmap *regmap;
 307 };
 308
 309 /**
 310  * All these values are coming from I2C Specification, Version 6.0, 4th of
 311  * April 2014.
 312  *
 313  * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
 314  * and Fast-mode Plus I2C-bus devices
 315  */
 316 static struct stm32f7_i2c_spec i2c_specs[] = {
 317         [STM32_I2C_SPEED_STANDARD] = {
 318                 .rate = 100000,
 319                 .rate_min = 80000,
 320                 .rate_max = 100000,
 321                 .fall_max = 300,
 322                 .rise_max = 1000,
 323                 .hddat_min = 0,
 324                 .vddat_max = 3450,
 325                 .sudat_min = 250,
 326                 .l_min = 4700,
 327                 .h_min = 4000,
 328         },
 329         [STM32_I2C_SPEED_FAST] = {
 330                 .rate = 400000,
 331                 .rate_min = 320000,
 332                 .rate_max = 400000,
 333                 .fall_max = 300,
 334                 .rise_max = 300,
 335                 .hddat_min = 0,
 336                 .vddat_max = 900,
 337                 .sudat_min = 100,
 338                 .l_min = 1300,
 339                 .h_min = 600,
 340         },
 341         [STM32_I2C_SPEED_FAST_PLUS] = {
 342                 .rate = 1000000,
 343                 .rate_min = 800000,
 344                 .rate_max = 1000000,
 345                 .fall_max = 100,
 346                 .rise_max = 120,
 347                 .hddat_min = 0,
 348                 .vddat_max = 450,
 349                 .sudat_min = 50,
 350                 .l_min = 500,
 351                 .h_min = 260,
 352         },
 353 };
 354
 355 static const struct stm32f7_i2c_setup stm32f7_setup = {
 356         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 357         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 358         .dnf = STM32F7_I2C_DNF_DEFAULT,
 359         .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
 360 };
 361
 362 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
 363 {
 364         writel_relaxed(readl_relaxed(reg) | mask, reg);
 365 }
 366
 367 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
 368 {
 369         writel_relaxed(readl_relaxed(reg) & ~mask, reg);
 370 }
 371
 372 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
 373 {
 374         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
 375 }
 376
 377 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
 378                                       struct stm32f7_i2c_setup *setup,
 379                                       struct stm32f7_i2c_timings *output)
 380 {
 381         u32 p_prev = STM32F7_PRESC_MAX;
 382         u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 383                                        setup->clock_src);
 384         u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 385                                        setup->speed_freq);
 386         u32 clk_error_prev = i2cbus;
 387         u32 tsync;
 388         u32 af_delay_min, af_delay_max;
 389         u32 dnf_delay;
 390         u32 clk_min, clk_max;
 391         int sdadel_min, sdadel_max;
 392         int scldel_min;
 393         struct stm32f7_i2c_timings *v, *_v, *s;
 394         struct list_head solutions;
 395         u16 p, l, a, h;
 396         int ret = 0;
 397
 398         if (setup->speed >= STM32_I2C_SPEED_END) {
 399                 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
 400                         setup->speed, STM32_I2C_SPEED_END - 1);
 401                 return -EINVAL;
 402         }
 403
 404         if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
 405             (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
 406                 dev_err(i2c_dev->dev,
 407                         "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 408                         setup->rise_time, i2c_specs[setup->speed].rise_max,
 409                         setup->fall_time, i2c_specs[setup->speed].fall_max);
 410                 return -EINVAL;
 411         }
 412
 413         if (setup->dnf > STM32F7_I2C_DNF_MAX) {
 414                 dev_err(i2c_dev->dev,
 415                         "DNF out of bound %d/%d\n",
 416                         setup->dnf, STM32F7_I2C_DNF_MAX);
 417                 return -EINVAL;
 418         }
 419
 420         if (setup->speed_freq > i2c_specs[setup->speed].rate) {
 421                 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
 422                         setup->speed_freq, i2c_specs[setup->speed].rate);
 423                 return -EINVAL;
 424         }
 425
 426         /*  Analog and Digital Filters */
 427         af_delay_min =
 428                 (setup->analog_filter ?
 429                  STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
 430         af_delay_max =
 431                 (setup->analog_filter ?
 432                  STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
 433         dnf_delay = setup->dnf * i2cclk;
 434
 435         sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
 436                 af_delay_min - (setup->dnf + 3) * i2cclk;
 437
 438         sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
 439                 af_delay_max - (setup->dnf + 4) * i2cclk;
 440
 441         scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
 442
 443         if (sdadel_min < 0)
 444                 sdadel_min = 0;
 445         if (sdadel_max < 0)
 446                 sdadel_max = 0;
 447
 448         dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 449                 sdadel_min, sdadel_max, scldel_min);
 450
 451         INIT_LIST_HEAD(&solutions);
 452         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 453         for (p = 0; p < STM32F7_PRESC_MAX; p++) {
 454                 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
 455                         u32 scldel = (l + 1) * (p + 1) * i2cclk;
 456
 457                         if (scldel < scldel_min)
 458                                 continue;
 459
 460                         for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
 461                                 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
 462
 463                                 if (((sdadel >= sdadel_min) &&
 464                                      (sdadel <= sdadel_max)) &&
 465                                     (p != p_prev)) {
 466                                         v = kmalloc(sizeof(*v), GFP_KERNEL);
 467                                         if (!v) {
 468                                                 ret = -ENOMEM;
 469                                                 goto exit;
 470                                         }
 471
 472                                         v->presc = p;
 473                                         v->scldel = l;
 474                                         v->sdadel = a;
 475                                         p_prev = p;
 476
 477                                         list_add_tail(&v->node,
 478                                                       &solutions);
 479                                 }
 480                         }
 481                 }
 482         }
 483
 484         if (list_empty(&solutions)) {
 485                 dev_err(i2c_dev->dev, "no Prescaler solution\n");
 486                 ret = -EPERM;
 487                 goto exit;
 488         }
 489
 490         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 491         s = NULL;
 492         clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
 493         clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
 494
 495         /*
 496          * Among Prescaler possibilities discovered above figures out SCL Low
 497          * and High Period. Provided:
 498          * - SCL Low Period has to be higher than SCL Clock Low Period
 499          *   defined by I2C Specification. I2C Clock has to be lower than
 500          *   (SCL Low Period - Analog/Digital filters) / 4.
 501          * - SCL High Period has to be lower than SCL Clock High Period
 502          *   defined by I2C Specification
 503          * - I2C Clock has to be lower than SCL High Period
 504          */
 505         list_for_each_entry(v, &solutions, node) {
 506                 u32 prescaler = (v->presc + 1) * i2cclk;
 507
 508                 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
 509                         u32 tscl_l = (l + 1) * prescaler + tsync;
 510
 511                         if ((tscl_l < i2c_specs[setup->speed].l_min) ||
 512                             (i2cclk >=
 513                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 514                                 continue;
 515                         }
 516
 517                         for (h = 0; h < STM32F7_SCLH_MAX; h++) {
 518                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 519                                 u32 tscl = tscl_l + tscl_h +
 520                                         setup->rise_time + setup->fall_time;
 521
 522                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 523                                     (tscl_h >= i2c_specs[setup->speed].h_min) &&
 524                                     (i2cclk < tscl_h)) {
 525                                         int clk_error = tscl - i2cbus;
 526
 527                                         if (clk_error < 0)
 528                                                 clk_error = -clk_error;
 529
 530                                         if (clk_error < clk_error_prev) {
 531                                                 clk_error_prev = clk_error;
 532                                                 v->scll = l;
 533                                                 v->sclh = h;
 534                                                 s = v;
 535                                         }
 536                                 }
 537                         }
 538                 }
 539         }
 540
 541         if (!s) {
 542                 dev_err(i2c_dev->dev, "no solution at all\n");
 543                 ret = -EPERM;
 544                 goto exit;
 545         }
 546
 547         output->presc = s->presc;
 548         output->scldel = s->scldel;
 549         output->sdadel = s->sdadel;
 550         output->scll = s->scll;
 551         output->sclh = s->sclh;
 552
 553         dev_dbg(i2c_dev->dev,
 554                 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 555                 output->presc,
 556                 output->scldel, output->sdadel,
 557                 output->scll, output->sclh);
 558
 559 exit:
 560         /* Release list and memory */
 561         list_for_each_entry_safe(v, _v, &solutions, node) {
 562                 list_del(&v->node);
 563                 kfree(v);
 564         }
 565
 566         return ret;
 567 }
 568
 569 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
 570                                     struct stm32f7_i2c_setup *setup)
 571 {
 572         int ret = 0;
 573
 574         setup->speed = i2c_dev->speed;
 575         setup->speed_freq = i2c_specs[setup->speed].rate;
 576         setup->clock_src = clk_get_rate(i2c_dev->clk);
 577
 578         if (!setup->clock_src) {
 579                 dev_err(i2c_dev->dev, "clock rate is 0\n");
 580                 return -EINVAL;
 581         }
 582
 583         do {
 584                 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
 585                                                  &i2c_dev->timing);
 586                 if (ret) {
 587                         dev_err(i2c_dev->dev,
 588                                 "failed to compute I2C timings.\n");
 589                         if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
 590                                 i2c_dev->speed--;
 591                                 setup->speed = i2c_dev->speed;
 592                                 setup->speed_freq =
 593                                         i2c_specs[setup->speed].rate;
 594                                 dev_warn(i2c_dev->dev,
 595                                          "downgrade I2C Speed Freq to (%i)\n",
 596                                          i2c_specs[setup->speed].rate);
 597                         } else {
 598                                 break;
 599                         }
 600                 }
 601         } while (ret);
 602
 603         if (ret) {
 604                 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
 605                 return ret;
 606         }
 607
 608         dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
 609                 setup->speed, setup->speed_freq, setup->clock_src);
 610         dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
 611                 setup->rise_time, setup->fall_time);
 612         dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
 613                 (setup->analog_filter ? "On" : "Off"), setup->dnf);
 614
 615         return 0;
 616 }
 617
 618 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
 619 {
 620         void __iomem *base = i2c_dev->base;
 621         u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
 622
 623         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
 624 }
 625
 626 static void stm32f7_i2c_dma_callback(void *arg)
 627 {
 628         struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
 629         struct stm32_i2c_dma *dma = i2c_dev->dma;
 630         struct device *dev = dma->chan_using->device->dev;
 631
 632         stm32f7_i2c_disable_dma_req(i2c_dev);
 633         dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
 634         complete(&dma->dma_complete);
 635 }
 636
 637 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
 638 {
 639         struct stm32f7_i2c_timings *t = &i2c_dev->timing;
 640         u32 timing = 0;
 641
 642         /* Timing settings */
 643         timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
 644         timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
 645         timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
 646         timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
 647         timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
 648         writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
 649
 650         /* Enable I2C */
 651         if (i2c_dev->setup.analog_filter)
 652                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 653                                      STM32F7_I2C_CR1_ANFOFF);
 654         else
 655                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 656                                      STM32F7_I2C_CR1_ANFOFF);
 657         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 658                              STM32F7_I2C_CR1_PE);
 659 }
 660
 661 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
 662 {
 663         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 664         void __iomem *base = i2c_dev->base;
 665
 666         if (f7_msg->count) {
 667                 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
 668                 f7_msg->count--;
 669         }
 670 }
 671
 672 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
 673 {
 674         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 675         void __iomem *base = i2c_dev->base;
 676
 677         if (f7_msg->count) {
 678                 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
 679                 f7_msg->count--;
 680         } else {
 681                 /* Flush RX buffer has no data is expected */
 682                 readb_relaxed(base + STM32F7_I2C_RXDR);
 683         }
 684 }
 685
 686 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
 687 {
 688         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 689         u32 cr2;
 690
 691         if (i2c_dev->use_dma)
 692                 f7_msg->count -= STM32F7_I2C_MAX_LEN;
 693
 694         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 695
 696         cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
 697         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 698                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 699         } else {
 700                 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
 701                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 702         }
 703
 704         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 705 }
 706
 707 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
 708 {
 709         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 710         u32 cr2;
 711         u8 *val;
 712
 713         /*
 714          * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
 715          * data received inform us how many data will follow.
 716          */
 717         stm32f7_i2c_read_rx_data(i2c_dev);
 718
 719         /*
 720          * Update NBYTES with the value read to continue the transfer
 721          */
 722         val = f7_msg->buf - sizeof(u8);
 723         f7_msg->count = *val;
 724         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 725         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 726         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 727         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 728 }
 729
 730 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
 731 {
 732         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 733
 734         dev_info(i2c_dev->dev, "Trying to recover bus\n");
 735
 736         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 737                              STM32F7_I2C_CR1_PE);
 738
 739         stm32f7_i2c_hw_config(i2c_dev);
 740
 741         return 0;
 742 }
 743
 744 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
 745 {
 746         u32 status;
 747         int ret;
 748
 749         ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
 750                                          status,
 751                                          !(status & STM32F7_I2C_ISR_BUSY),
 752                                          10, 1000);
 753         if (!ret)
 754                 return 0;
 755
 756         dev_info(i2c_dev->dev, "bus busy\n");
 757
 758         ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
 759         if (ret) {
 760                 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
 761                 return ret;
 762         }
 763
 764         return -EBUSY;
 765 }
 766
 767 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 768                                  struct i2c_msg *msg)
 769 {
 770         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 771         void __iomem *base = i2c_dev->base;
 772         u32 cr1, cr2;
 773         int ret;
 774
 775         f7_msg->addr = msg->addr;
 776         f7_msg->buf = msg->buf;
 777         f7_msg->count = msg->len;
 778         f7_msg->result = 0;
 779         f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
 780
 781         reinit_completion(&i2c_dev->complete);
 782
 783         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 784         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 785
 786         /* Set transfer direction */
 787         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 788         if (msg->flags & I2C_M_RD)
 789                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 790
 791         /* Set slave address */
 792         cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
 793         if (msg->flags & I2C_M_TEN) {
 794                 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
 795                 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
 796                 cr2 |= STM32F7_I2C_CR2_ADD10;
 797         } else {
 798                 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
 799                 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 800         }
 801
 802         /* Set nb bytes to transfer and reload if needed */
 803         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 804         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 805                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 806                 cr2 |= STM32F7_I2C_CR2_RELOAD;
 807         } else {
 808                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 809         }
 810
 811         /* Enable NACK, STOP, error and transfer complete interrupts */
 812         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 813                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 814
 815         /* Clear DMA req and TX/RX interrupt */
 816         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 817                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 818
 819         /* Configure DMA or enable RX/TX interrupt */
 820         i2c_dev->use_dma = false;
 821         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
 822                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 823                                               msg->flags & I2C_M_RD,
 824                                               f7_msg->count, f7_msg->buf,
 825                                               stm32f7_i2c_dma_callback,
 826                                               i2c_dev);
 827                 if (!ret)
 828                         i2c_dev->use_dma = true;
 829                 else
 830                         dev_warn(i2c_dev->dev, "can't use DMA\n");
 831         }
 832
 833         if (!i2c_dev->use_dma) {
 834                 if (msg->flags & I2C_M_RD)
 835                         cr1 |= STM32F7_I2C_CR1_RXIE;
 836                 else
 837                         cr1 |= STM32F7_I2C_CR1_TXIE;
 838         } else {
 839                 if (msg->flags & I2C_M_RD)
 840                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
 841                 else
 842                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
 843         }
 844
 845         /* Configure Start/Repeated Start */
 846         cr2 |= STM32F7_I2C_CR2_START;
 847
 848         i2c_dev->master_mode = true;
 849
 850         /* Write configurations registers */
 851         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
 852         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
 853 }
 854
 855 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 856                                       unsigned short flags, u8 command,
 857                                       union i2c_smbus_data *data)
 858 {
 859         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 860         struct device *dev = i2c_dev->dev;
 861         void __iomem *base = i2c_dev->base;
 862         u32 cr1, cr2;
 863         int i, ret;
 864
 865         f7_msg->result = 0;
 866         reinit_completion(&i2c_dev->complete);
 867
 868         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 869         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 870
 871         /* Set transfer direction */
 872         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 873         if (f7_msg->read_write)
 874                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 875
 876         /* Set slave address */
 877         cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
 878         cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 879
 880         f7_msg->smbus_buf[0] = command;
 881         switch (f7_msg->size) {
 882         case I2C_SMBUS_QUICK:
 883                 f7_msg->stop = true;
 884                 f7_msg->count = 0;
 885                 break;
 886         case I2C_SMBUS_BYTE:
 887                 f7_msg->stop = true;
 888                 f7_msg->count = 1;
 889                 break;
 890         case I2C_SMBUS_BYTE_DATA:
 891                 if (f7_msg->read_write) {
 892                         f7_msg->stop = false;
 893                         f7_msg->count = 1;
 894                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 895                 } else {
 896                         f7_msg->stop = true;
 897                         f7_msg->count = 2;
 898                         f7_msg->smbus_buf[1] = data->byte;
 899                 }
 900                 break;
 901         case I2C_SMBUS_WORD_DATA:
 902                 if (f7_msg->read_write) {
 903                         f7_msg->stop = false;
 904                         f7_msg->count = 1;
 905                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 906                 } else {
 907                         f7_msg->stop = true;
 908                         f7_msg->count = 3;
 909                         f7_msg->smbus_buf[1] = data->word & 0xff;
 910                         f7_msg->smbus_buf[2] = data->word >> 8;
 911                 }
 912                 break;
 913         case I2C_SMBUS_BLOCK_DATA:
 914                 if (f7_msg->read_write) {
 915                         f7_msg->stop = false;
 916                         f7_msg->count = 1;
 917                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 918                 } else {
 919                         f7_msg->stop = true;
 920                         if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
 921                             !data->block[0]) {
 922                                 dev_err(dev, "Invalid block write size %d\n",
 923                                         data->block[0]);
 924                                 return -EINVAL;
 925                         }
 926                         f7_msg->count = data->block[0] + 2;
 927                         for (i = 1; i < f7_msg->count; i++)
 928                                 f7_msg->smbus_buf[i] = data->block[i - 1];
 929                 }
 930                 break;
 931         case I2C_SMBUS_PROC_CALL:
 932                 f7_msg->stop = false;
 933                 f7_msg->count = 3;
 934                 f7_msg->smbus_buf[1] = data->word & 0xff;
 935                 f7_msg->smbus_buf[2] = data->word >> 8;
 936                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 937                 f7_msg->read_write = I2C_SMBUS_READ;
 938                 break;
 939         case I2C_SMBUS_BLOCK_PROC_CALL:
 940                 f7_msg->stop = false;
 941                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
 942                         dev_err(dev, "Invalid block write size %d\n",
 943                                 data->block[0]);
 944                         return -EINVAL;
 945                 }
 946                 f7_msg->count = data->block[0] + 2;
 947                 for (i = 1; i < f7_msg->count; i++)
 948                         f7_msg->smbus_buf[i] = data->block[i - 1];
 949                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 950                 f7_msg->read_write = I2C_SMBUS_READ;
 951                 break;
 952         default:
 953                 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
 954                 return -EOPNOTSUPP;
 955         }
 956
 957         f7_msg->buf = f7_msg->smbus_buf;
 958
 959         /* Configure PEC */
 960         if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
 961                 cr1 |= STM32F7_I2C_CR1_PECEN;
 962                 cr2 |= STM32F7_I2C_CR2_PECBYTE;
 963                 if (!f7_msg->read_write)
 964                         f7_msg->count++;
 965         } else {
 966                 cr1 &= ~STM32F7_I2C_CR1_PECEN;
 967                 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
 968         }
 969
 970         /* Set number of bytes to be transferred */
 971         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 972         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 973
 974         /* Enable NACK, STOP, error and transfer complete interrupts */
 975         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 976                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 977
 978         /* Clear DMA req and TX/RX interrupt */
 979         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 980                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 981
 982         /* Configure DMA or enable RX/TX interrupt */
 983         i2c_dev->use_dma = false;
 984         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
 985                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 986                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
 987                                               f7_msg->count, f7_msg->buf,
 988                                               stm32f7_i2c_dma_callback,
 989                                               i2c_dev);
 990                 if (!ret)
 991                         i2c_dev->use_dma = true;
 992                 else
 993                         dev_warn(i2c_dev->dev, "can't use DMA\n");
 994         }
 995
 996         if (!i2c_dev->use_dma) {
 997                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
 998                         cr1 |= STM32F7_I2C_CR1_RXIE;
 999                 else
1000                         cr1 |= STM32F7_I2C_CR1_TXIE;
1001         } else {
1002                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1003                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1004                 else
1005                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1006         }
1007
1008         /* Set Start bit */
1009         cr2 |= STM32F7_I2C_CR2_START;
1010
1011         i2c_dev->master_mode = true;
1012
1013         /* Write configurations registers */
1014         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1015         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1016
1017         return 0;
1018 }
1019
1020 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1021 {
1022         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1023         void __iomem *base = i2c_dev->base;
1024         u32 cr1, cr2;
1025         int ret;
1026
1027         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1028         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1029
1030         /* Set transfer direction */
1031         cr2 |= STM32F7_I2C_CR2_RD_WRN;
1032
1033         switch (f7_msg->size) {
1034         case I2C_SMBUS_BYTE_DATA:
1035                 f7_msg->count = 1;
1036                 break;
1037         case I2C_SMBUS_WORD_DATA:
1038         case I2C_SMBUS_PROC_CALL:
1039                 f7_msg->count = 2;
1040                 break;
1041         case I2C_SMBUS_BLOCK_DATA:
1042         case I2C_SMBUS_BLOCK_PROC_CALL:
1043                 f7_msg->count = 1;
1044                 cr2 |= STM32F7_I2C_CR2_RELOAD;
1045                 break;
1046         }
1047
1048         f7_msg->buf = f7_msg->smbus_buf;
1049         f7_msg->stop = true;
1050
1051         /* Add one byte for PEC if needed */
1052         if (cr1 & STM32F7_I2C_CR1_PECEN)
1053                 f7_msg->count++;
1054
1055         /* Set number of bytes to be transferred */
1056         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1057         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1058
1059         /*
1060          * Configure RX/TX interrupt:
1061          */
1062         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1063         cr1 |= STM32F7_I2C_CR1_RXIE;
1064
1065         /*
1066          * Configure DMA or enable RX/TX interrupt:
1067          * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1068          * dma as we don't know in advance how many data will be received
1069          */
1070         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1071                  STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1072
1073         i2c_dev->use_dma = false;
1074         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1075             f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1076             f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1077                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1078                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1079                                               f7_msg->count, f7_msg->buf,
1080                                               stm32f7_i2c_dma_callback,
1081                                               i2c_dev);
1082
1083                 if (!ret)
1084                         i2c_dev->use_dma = true;
1085                 else
1086                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1087         }
1088
1089         if (!i2c_dev->use_dma)
1090                 cr1 |= STM32F7_I2C_CR1_RXIE;
1091         else
1092                 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1093
1094         /* Configure Repeated Start */
1095         cr2 |= STM32F7_I2C_CR2_START;
1096
1097         /* Write configurations registers */
1098         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1099         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1100 }
1101
1102 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1103 {
1104         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1105         u8 count, internal_pec, received_pec;
1106
1107         internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1108
1109         switch (f7_msg->size) {
1110         case I2C_SMBUS_BYTE:
1111         case I2C_SMBUS_BYTE_DATA:
1112                 received_pec = f7_msg->smbus_buf[1];
1113                 break;
1114         case I2C_SMBUS_WORD_DATA:
1115         case I2C_SMBUS_PROC_CALL:
1116                 received_pec = f7_msg->smbus_buf[2];
1117                 break;
1118         case I2C_SMBUS_BLOCK_DATA:
1119         case I2C_SMBUS_BLOCK_PROC_CALL:
1120                 count = f7_msg->smbus_buf[0];
1121                 received_pec = f7_msg->smbus_buf[count];
1122                 break;
1123         default:
1124                 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1125                 return -EINVAL;
1126         }
1127
1128         if (internal_pec != received_pec) {
1129                 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1130                         internal_pec, received_pec);
1131                 return -EBADMSG;
1132         }
1133
1134         return 0;
1135 }
1136
1137 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1138 {
1139         u32 addr;
1140
1141         if (!slave)
1142                 return false;
1143
1144         if (slave->flags & I2C_CLIENT_TEN) {
1145                 /*
1146                  * For 10-bit addr, addcode = 11110XY with
1147                  * X = Bit 9 of slave address
1148                  * Y = Bit 8 of slave address
1149                  */
1150                 addr = slave->addr >> 8;
1151                 addr |= 0x78;
1152                 if (addr == addcode)
1153                         return true;
1154         } else {
1155                 addr = slave->addr & 0x7f;
1156                 if (addr == addcode)
1157                         return true;
1158         }
1159
1160         return false;
1161 }
1162
1163 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1164 {
1165         struct i2c_client *slave = i2c_dev->slave_running;
1166         void __iomem *base = i2c_dev->base;
1167         u32 mask;
1168         u8 value = 0;
1169
1170         if (i2c_dev->slave_dir) {
1171                 /* Notify i2c slave that new read transfer is starting */
1172                 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1173
1174                 /*
1175                  * Disable slave TX config in case of I2C combined message
1176                  * (I2C Write followed by I2C Read)
1177                  */
1178                 mask = STM32F7_I2C_CR2_RELOAD;
1179                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1180                 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1181                        STM32F7_I2C_CR1_TCIE;
1182                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1183
1184                 /* Enable TX empty, STOP, NACK interrupts */
1185                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1186                         STM32F7_I2C_CR1_TXIE;
1187                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1188
1189         } else {
1190                 /* Notify i2c slave that new write transfer is starting */
1191                 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1192
1193                 /* Set reload mode to be able to ACK/NACK each received byte */
1194                 mask = STM32F7_I2C_CR2_RELOAD;
1195                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1196
1197                 /*
1198                  * Set STOP, NACK, RX empty and transfer complete interrupts.*
1199                  * Set Slave Byte Control to be able to ACK/NACK each data
1200                  * byte received
1201                  */
1202                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1203                         STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1204                         STM32F7_I2C_CR1_TCIE;
1205                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1206         }
1207 }
1208
1209 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1210 {
1211         void __iomem *base = i2c_dev->base;
1212         u32 isr, addcode, dir, mask;
1213         int i;
1214
1215         isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1216         addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1217         dir = isr & STM32F7_I2C_ISR_DIR;
1218
1219         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1220                 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1221                         i2c_dev->slave_running = i2c_dev->slave[i];
1222                         i2c_dev->slave_dir = dir;
1223
1224                         /* Start I2C slave processing */
1225                         stm32f7_i2c_slave_start(i2c_dev);
1226
1227                         /* Clear ADDR flag */
1228                         mask = STM32F7_I2C_ICR_ADDRCF;
1229                         writel_relaxed(mask, base + STM32F7_I2C_ICR);
1230                         break;
1231                 }
1232         }
1233 }
1234
1235 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1236                                     struct i2c_client *slave, int *id)
1237 {
1238         int i;
1239
1240         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1241                 if (i2c_dev->slave[i] == slave) {
1242                         *id = i;
1243                         return 0;
1244                 }
1245         }
1246
1247         dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1248
1249         return -ENODEV;
1250 }
1251
1252 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1253                                          struct i2c_client *slave, int *id)
1254 {
1255         struct device *dev = i2c_dev->dev;
1256         int i;
1257
1258         /*
1259          * slave[0] supports 7-bit and 10-bit slave address
1260          * slave[1] supports 7-bit slave address only
1261          */
1262         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1263                 if (i == 1 && (slave->flags & I2C_CLIENT_PEC))
1264                         continue;
1265                 if (!i2c_dev->slave[i]) {
1266                         *id = i;
1267                         return 0;
1268                 }
1269         }
1270
1271         dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1272
1273         return -EINVAL;
1274 }
1275
1276 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1277 {
1278         int i;
1279
1280         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1281                 if (i2c_dev->slave[i])
1282                         return true;
1283         }
1284
1285         return false;
1286 }
1287
1288 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1289 {
1290         int i, busy;
1291
1292         busy = 0;
1293         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1294                 if (i2c_dev->slave[i])
1295                         busy++;
1296         }
1297
1298         return i == busy;
1299 }
1300
1301 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1302 {
1303         void __iomem *base = i2c_dev->base;
1304         u32 cr2, status, mask;
1305         u8 val;
1306         int ret;
1307
1308         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1309
1310         /* Slave transmitter mode */
1311         if (status & STM32F7_I2C_ISR_TXIS) {
1312                 i2c_slave_event(i2c_dev->slave_running,
1313                                 I2C_SLAVE_READ_PROCESSED,
1314                                 &val);
1315
1316                 /* Write data byte */
1317                 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1318         }
1319
1320         /* Transfer Complete Reload for Slave receiver mode */
1321         if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1322                 /*
1323                  * Read data byte then set NBYTES to receive next byte or NACK
1324                  * the current received byte
1325                  */
1326                 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1327                 ret = i2c_slave_event(i2c_dev->slave_running,
1328                                       I2C_SLAVE_WRITE_RECEIVED,
1329                                       &val);
1330                 if (!ret) {
1331                         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1332                         cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1333                         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1334                 } else {
1335                         mask = STM32F7_I2C_CR2_NACK;
1336                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1337                 }
1338         }
1339
1340         /* NACK received */
1341         if (status & STM32F7_I2C_ISR_NACKF) {
1342                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1343                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1344         }
1345
1346         /* STOP received */
1347         if (status & STM32F7_I2C_ISR_STOPF) {
1348                 /* Disable interrupts */
1349                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1350
1351                 if (i2c_dev->slave_dir) {
1352                         /*
1353                          * Flush TX buffer in order to not used the byte in
1354                          * TXDR for the next transfer
1355                          */
1356                         mask = STM32F7_I2C_ISR_TXE;
1357                         stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1358                 }
1359
1360                 /* Clear STOP flag */
1361                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1362
1363                 /* Notify i2c slave that a STOP flag has been detected */
1364                 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1365
1366                 i2c_dev->slave_running = NULL;
1367         }
1368
1369         /* Address match received */
1370         if (status & STM32F7_I2C_ISR_ADDR)
1371                 stm32f7_i2c_slave_addr(i2c_dev);
1372
1373         return IRQ_HANDLED;
1374 }
1375
1376 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1377 {
1378         struct stm32f7_i2c_dev *i2c_dev = data;
1379         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1380         void __iomem *base = i2c_dev->base;
1381         u32 status, mask;
1382         int ret = IRQ_HANDLED;
1383
1384         /* Check if the interrupt if for a slave device */
1385         if (!i2c_dev->master_mode) {
1386                 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1387                 return ret;
1388         }
1389
1390         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1391
1392         /* Tx empty */
1393         if (status & STM32F7_I2C_ISR_TXIS)
1394                 stm32f7_i2c_write_tx_data(i2c_dev);
1395
1396         /* RX not empty */
1397         if (status & STM32F7_I2C_ISR_RXNE)
1398                 stm32f7_i2c_read_rx_data(i2c_dev);
1399
1400         /* NACK received */
1401         if (status & STM32F7_I2C_ISR_NACKF) {
1402                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1403                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1404                 f7_msg->result = -ENXIO;
1405         }
1406
1407         /* STOP detection flag */
1408         if (status & STM32F7_I2C_ISR_STOPF) {
1409                 /* Disable interrupts */
1410                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1411                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1412                 else
1413                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1414                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1415
1416                 /* Clear STOP flag */
1417                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1418
1419                 if (i2c_dev->use_dma) {
1420                         ret = IRQ_WAKE_THREAD;
1421                 } else {
1422                         i2c_dev->master_mode = false;
1423                         complete(&i2c_dev->complete);
1424                 }
1425         }
1426
1427         /* Transfer complete */
1428         if (status & STM32F7_I2C_ISR_TC) {
1429                 if (f7_msg->stop) {
1430                         mask = STM32F7_I2C_CR2_STOP;
1431                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1432                 } else if (i2c_dev->use_dma) {
1433                         ret = IRQ_WAKE_THREAD;
1434                 } else if (f7_msg->smbus) {
1435                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1436                 } else {
1437                         i2c_dev->msg_id++;
1438                         i2c_dev->msg++;
1439                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1440                 }
1441         }
1442
1443         if (status & STM32F7_I2C_ISR_TCR) {
1444                 if (f7_msg->smbus)
1445                         stm32f7_i2c_smbus_reload(i2c_dev);
1446                 else
1447                         stm32f7_i2c_reload(i2c_dev);
1448         }
1449
1450         return ret;
1451 }
1452
1453 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1454 {
1455         struct stm32f7_i2c_dev *i2c_dev = data;
1456         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1457         struct stm32_i2c_dma *dma = i2c_dev->dma;
1458         u32 status;
1459         int ret;
1460
1461         /*
1462          * Wait for dma transfer completion before sending next message or
1463          * notity the end of xfer to the client
1464          */
1465         ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1466         if (!ret) {
1467                 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1468                 stm32f7_i2c_disable_dma_req(i2c_dev);
1469                 dmaengine_terminate_all(dma->chan_using);
1470                 f7_msg->result = -ETIMEDOUT;
1471         }
1472
1473         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1474
1475         if (status & STM32F7_I2C_ISR_TC) {
1476                 if (f7_msg->smbus) {
1477                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1478                 } else {
1479                         i2c_dev->msg_id++;
1480                         i2c_dev->msg++;
1481                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1482                 }
1483         } else {
1484                 i2c_dev->master_mode = false;
1485                 complete(&i2c_dev->complete);
1486         }
1487
1488         return IRQ_HANDLED;
1489 }
1490
1491 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1492 {
1493         struct stm32f7_i2c_dev *i2c_dev = data;
1494         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1495         void __iomem *base = i2c_dev->base;
1496         struct device *dev = i2c_dev->dev;
1497         struct stm32_i2c_dma *dma = i2c_dev->dma;
1498         u32 mask, status;
1499
1500         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1501
1502         /* Bus error */
1503         if (status & STM32F7_I2C_ISR_BERR) {
1504                 dev_err(dev, "<%s>: Bus error\n", __func__);
1505                 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1506                 stm32f7_i2c_release_bus(&i2c_dev->adap);
1507                 f7_msg->result = -EIO;
1508         }
1509
1510         /* Arbitration loss */
1511         if (status & STM32F7_I2C_ISR_ARLO) {
1512                 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1513                 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1514                 f7_msg->result = -EAGAIN;
1515         }
1516
1517         if (status & STM32F7_I2C_ISR_PECERR) {
1518                 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1519                 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1520                 f7_msg->result = -EINVAL;
1521         }
1522
1523         /* Disable interrupts */
1524         if (stm32f7_i2c_is_slave_registered(i2c_dev))
1525                 mask = STM32F7_I2C_XFER_IRQ_MASK;
1526         else
1527                 mask = STM32F7_I2C_ALL_IRQ_MASK;
1528         stm32f7_i2c_disable_irq(i2c_dev, mask);
1529
1530         /* Disable dma */
1531         if (i2c_dev->use_dma) {
1532                 stm32f7_i2c_disable_dma_req(i2c_dev);
1533                 dmaengine_terminate_all(dma->chan_using);
1534         }
1535
1536         i2c_dev->master_mode = false;
1537         complete(&i2c_dev->complete);
1538
1539         return IRQ_HANDLED;
1540 }
1541
1542 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1543                             struct i2c_msg msgs[], int num)
1544 {
1545         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1546         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1547         struct stm32_i2c_dma *dma = i2c_dev->dma;
1548         unsigned long time_left;
1549         int ret;
1550
1551         i2c_dev->msg = msgs;
1552         i2c_dev->msg_num = num;
1553         i2c_dev->msg_id = 0;
1554         f7_msg->smbus = false;
1555
1556         ret = pm_runtime_get_sync(i2c_dev->dev);
1557         if (ret < 0)
1558                 return ret;
1559
1560         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1561         if (ret)
1562                 goto pm_free;
1563
1564         stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1565
1566         time_left = wait_for_completion_timeout(&i2c_dev->complete,
1567                                                 i2c_dev->adap.timeout);
1568         ret = f7_msg->result;
1569
1570         if (!time_left) {
1571                 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1572                         i2c_dev->msg->addr);
1573                 if (i2c_dev->use_dma)
1574                         dmaengine_terminate_all(dma->chan_using);
1575                 ret = -ETIMEDOUT;
1576         }
1577
1578 pm_free:
1579         pm_runtime_mark_last_busy(i2c_dev->dev);
1580         pm_runtime_put_autosuspend(i2c_dev->dev);
1581
1582         return (ret < 0) ? ret : num;
1583 }
1584
1585 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1586                                   unsigned short flags, char read_write,
1587                                   u8 command, int size,
1588                                   union i2c_smbus_data *data)
1589 {
1590         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1591         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1592         struct stm32_i2c_dma *dma = i2c_dev->dma;
1593         struct device *dev = i2c_dev->dev;
1594         unsigned long timeout;
1595         int i, ret;
1596
1597         f7_msg->addr = addr;
1598         f7_msg->size = size;
1599         f7_msg->read_write = read_write;
1600         f7_msg->smbus = true;
1601
1602         ret = pm_runtime_get_sync(dev);
1603         if (ret < 0)
1604                 return ret;
1605
1606         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1607         if (ret)
1608                 goto pm_free;
1609
1610         ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1611         if (ret)
1612                 goto pm_free;
1613
1614         timeout = wait_for_completion_timeout(&i2c_dev->complete,
1615                                               i2c_dev->adap.timeout);
1616         ret = f7_msg->result;
1617         if (ret)
1618                 goto pm_free;
1619
1620         if (!timeout) {
1621                 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1622                 if (i2c_dev->use_dma)
1623                         dmaengine_terminate_all(dma->chan_using);
1624                 ret = -ETIMEDOUT;
1625                 goto pm_free;
1626         }
1627
1628         /* Check PEC */
1629         if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1630                 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1631                 if (ret)
1632                         goto pm_free;
1633         }
1634
1635         if (read_write && size != I2C_SMBUS_QUICK) {
1636                 switch (size) {
1637                 case I2C_SMBUS_BYTE:
1638                 case I2C_SMBUS_BYTE_DATA:
1639                         data->byte = f7_msg->smbus_buf[0];
1640                 break;
1641                 case I2C_SMBUS_WORD_DATA:
1642                 case I2C_SMBUS_PROC_CALL:
1643                         data->word = f7_msg->smbus_buf[0] |
1644                                 (f7_msg->smbus_buf[1] << 8);
1645                 break;
1646                 case I2C_SMBUS_BLOCK_DATA:
1647                 case I2C_SMBUS_BLOCK_PROC_CALL:
1648                 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1649                         data->block[i] = f7_msg->smbus_buf[i];
1650                 break;
1651                 default:
1652                         dev_err(dev, "Unsupported smbus transaction\n");
1653                         ret = -EINVAL;
1654                 }
1655         }
1656
1657 pm_free:
1658         pm_runtime_mark_last_busy(dev);
1659         pm_runtime_put_autosuspend(dev);
1660         return ret;
1661 }
1662
1663 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1664 {
1665         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1666         void __iomem *base = i2c_dev->base;
1667         struct device *dev = i2c_dev->dev;
1668         u32 oar1, oar2, mask;
1669         int id, ret;
1670
1671         if (slave->flags & I2C_CLIENT_PEC) {
1672                 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1673                 return -EINVAL;
1674         }
1675
1676         if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1677                 dev_err(dev, "Too much slave registered\n");
1678                 return -EBUSY;
1679         }
1680
1681         ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1682         if (ret)
1683                 return ret;
1684
1685         ret = pm_runtime_get_sync(dev);
1686         if (ret < 0)
1687                 return ret;
1688
1689         if (id == 0) {
1690                 /* Configure Own Address 1 */
1691                 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1692                 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1693                 if (slave->flags & I2C_CLIENT_TEN) {
1694                         oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1695                         oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1696                 } else {
1697                         oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1698                 }
1699                 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1700                 i2c_dev->slave[id] = slave;
1701                 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1702         } else if (id == 1) {
1703                 /* Configure Own Address 2 */
1704                 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1705                 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1706                 if (slave->flags & I2C_CLIENT_TEN) {
1707                         ret = -EOPNOTSUPP;
1708                         goto pm_free;
1709                 }
1710
1711                 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1712                 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1713                 i2c_dev->slave[id] = slave;
1714                 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1715         } else {
1716                 ret = -ENODEV;
1717                 goto pm_free;
1718         }
1719
1720         /* Enable ACK */
1721         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1722
1723         /* Enable Address match interrupt, error interrupt and enable I2C  */
1724         mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1725                 STM32F7_I2C_CR1_PE;
1726         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1727
1728         ret = 0;
1729 pm_free:
1730         pm_runtime_mark_last_busy(dev);
1731         pm_runtime_put_autosuspend(dev);
1732
1733         return ret;
1734 }
1735
1736 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1737 {
1738         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1739         void __iomem *base = i2c_dev->base;
1740         u32 mask;
1741         int id, ret;
1742
1743         ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1744         if (ret)
1745                 return ret;
1746
1747         WARN_ON(!i2c_dev->slave[id]);
1748
1749         ret = pm_runtime_get_sync(i2c_dev->dev);
1750         if (ret < 0)
1751                 return ret;
1752
1753         if (id == 0) {
1754                 mask = STM32F7_I2C_OAR1_OA1EN;
1755                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1756         } else {
1757                 mask = STM32F7_I2C_OAR2_OA2EN;
1758                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1759         }
1760
1761         i2c_dev->slave[id] = NULL;
1762
1763         if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1764                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1765
1766         pm_runtime_mark_last_busy(i2c_dev->dev);
1767         pm_runtime_put_autosuspend(i2c_dev->dev);
1768
1769         return 0;
1770 }
1771
1772 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1773                                           struct stm32f7_i2c_dev *i2c_dev)
1774 {
1775         struct device_node *np = pdev->dev.of_node;
1776         int ret;
1777         u32 reg, mask;
1778
1779         i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1780         if (IS_ERR(i2c_dev->regmap)) {
1781                 /* Optional */
1782                 return 0;
1783         }
1784
1785         ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, &reg);
1786         if (ret)
1787                 return ret;
1788
1789         ret = of_property_read_u32_index(np, "st,syscfg-fmp", 2, &mask);
1790         if (ret)
1791                 return ret;
1792
1793         return regmap_update_bits(i2c_dev->regmap, reg, mask, mask);
1794 }
1795
1796 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1797 {
1798         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1799                 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1800                 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1801                 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1802                 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC;
1803 }
1804
1805 static struct i2c_algorithm stm32f7_i2c_algo = {
1806         .master_xfer = stm32f7_i2c_xfer,
1807         .smbus_xfer = stm32f7_i2c_smbus_xfer,
1808         .functionality = stm32f7_i2c_func,
1809         .reg_slave = stm32f7_i2c_reg_slave,
1810         .unreg_slave = stm32f7_i2c_unreg_slave,
1811 };
1812
1813 static int stm32f7_i2c_probe(struct platform_device *pdev)
1814 {
1815         struct device_node *np = pdev->dev.of_node;
1816         struct stm32f7_i2c_dev *i2c_dev;
1817         const struct stm32f7_i2c_setup *setup;
1818         struct resource *res;
1819         u32 irq_error, irq_event, clk_rate, rise_time, fall_time;
1820         struct i2c_adapter *adap;
1821         struct reset_control *rst;
1822         dma_addr_t phy_addr;
1823         int ret;
1824
1825         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1826         if (!i2c_dev)
1827                 return -ENOMEM;
1828
1829         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1830         i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1831         if (IS_ERR(i2c_dev->base))
1832                 return PTR_ERR(i2c_dev->base);
1833         phy_addr = (dma_addr_t)res->start;
1834
1835         irq_event = irq_of_parse_and_map(np, 0);
1836         if (!irq_event) {
1837                 dev_err(&pdev->dev, "IRQ event missing or invalid\n");
1838                 return -EINVAL;
1839         }
1840
1841         irq_error = irq_of_parse_and_map(np, 1);
1842         if (!irq_error) {
1843                 dev_err(&pdev->dev, "IRQ error missing or invalid\n");
1844                 return -EINVAL;
1845         }
1846
1847         i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1848         if (IS_ERR(i2c_dev->clk)) {
1849                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1850                 return PTR_ERR(i2c_dev->clk);
1851         }
1852
1853         ret = clk_prepare_enable(i2c_dev->clk);
1854         if (ret) {
1855                 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
1856                 return ret;
1857         }
1858
1859         i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1860         ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1861                                        &clk_rate);
1862         if (!ret && clk_rate >= 1000000) {
1863                 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
1864                 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
1865                 if (ret)
1866                         goto clk_free;
1867         } else if (!ret && clk_rate >= 400000) {
1868                 i2c_dev->speed = STM32_I2C_SPEED_FAST;
1869         } else if (!ret && clk_rate >= 100000) {
1870                 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1871         }
1872
1873         rst = devm_reset_control_get(&pdev->dev, NULL);
1874         if (IS_ERR(rst)) {
1875                 dev_err(&pdev->dev, "Error: Missing controller reset\n");
1876                 ret = PTR_ERR(rst);
1877                 goto clk_free;
1878         }
1879         reset_control_assert(rst);
1880         udelay(2);
1881         reset_control_deassert(rst);
1882
1883         i2c_dev->dev = &pdev->dev;
1884
1885         ret = devm_request_threaded_irq(&pdev->dev, irq_event,
1886                                         stm32f7_i2c_isr_event,
1887                                         stm32f7_i2c_isr_event_thread,
1888                                         IRQF_ONESHOT,
1889                                         pdev->name, i2c_dev);
1890         if (ret) {
1891                 dev_err(&pdev->dev, "Failed to request irq event %i\n",
1892                         irq_event);
1893                 goto clk_free;
1894         }
1895
1896         ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
1897                                pdev->name, i2c_dev);
1898         if (ret) {
1899                 dev_err(&pdev->dev, "Failed to request irq error %i\n",
1900                         irq_error);
1901                 goto clk_free;
1902         }
1903
1904         setup = of_device_get_match_data(&pdev->dev);
1905         if (!setup) {
1906                 dev_err(&pdev->dev, "Can't get device data\n");
1907                 ret = -ENODEV;
1908                 goto clk_free;
1909         }
1910         i2c_dev->setup = *setup;
1911
1912         ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
1913                                        &rise_time);
1914         if (!ret)
1915                 i2c_dev->setup.rise_time = rise_time;
1916
1917         ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
1918                                        &fall_time);
1919         if (!ret)
1920                 i2c_dev->setup.fall_time = fall_time;
1921
1922         ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
1923         if (ret)
1924                 goto clk_free;
1925
1926         adap = &i2c_dev->adap;
1927         i2c_set_adapdata(adap, i2c_dev);
1928         snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
1929                  &res->start);
1930         adap->owner = THIS_MODULE;
1931         adap->timeout = 2 * HZ;
1932         adap->retries = 3;
1933         adap->algo = &stm32f7_i2c_algo;
1934         adap->dev.parent = &pdev->dev;
1935         adap->dev.of_node = pdev->dev.of_node;
1936
1937         init_completion(&i2c_dev->complete);
1938
1939         /* Init DMA config if supported */
1940         i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
1941                                              STM32F7_I2C_TXDR,
1942                                              STM32F7_I2C_RXDR);
1943
1944         platform_set_drvdata(pdev, i2c_dev);
1945
1946         pm_runtime_set_autosuspend_delay(i2c_dev->dev,
1947                                          STM32F7_AUTOSUSPEND_DELAY);
1948         pm_runtime_use_autosuspend(i2c_dev->dev);
1949         pm_runtime_set_active(i2c_dev->dev);
1950         pm_runtime_enable(i2c_dev->dev);
1951
1952         pm_runtime_get_noresume(&pdev->dev);
1953
1954         stm32f7_i2c_hw_config(i2c_dev);
1955
1956         ret = i2c_add_adapter(adap);
1957         if (ret)
1958                 goto pm_disable;
1959
1960         dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
1961
1962         pm_runtime_mark_last_busy(i2c_dev->dev);
1963         pm_runtime_put_autosuspend(i2c_dev->dev);
1964
1965         return 0;
1966
1967 pm_disable:
1968         pm_runtime_put_noidle(i2c_dev->dev);
1969         pm_runtime_disable(i2c_dev->dev);
1970         pm_runtime_set_suspended(i2c_dev->dev);
1971         pm_runtime_dont_use_autosuspend(i2c_dev->dev);
1972
1973 clk_free:
1974         clk_disable_unprepare(i2c_dev->clk);
1975
1976         return ret;
1977 }
1978
1979 static int stm32f7_i2c_remove(struct platform_device *pdev)
1980 {
1981         struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1982
1983         if (i2c_dev->dma) {
1984                 stm32_i2c_dma_free(i2c_dev->dma);
1985                 i2c_dev->dma = NULL;
1986         }
1987
1988         i2c_del_adapter(&i2c_dev->adap);
1989         pm_runtime_get_sync(i2c_dev->dev);
1990
1991         clk_disable_unprepare(i2c_dev->clk);
1992
1993         pm_runtime_put_noidle(i2c_dev->dev);
1994         pm_runtime_disable(i2c_dev->dev);
1995         pm_runtime_set_suspended(i2c_dev->dev);
1996         pm_runtime_dont_use_autosuspend(i2c_dev->dev);
1997
1998         return 0;
1999 }
2000
2001 #ifdef CONFIG_PM
2002 static int stm32f7_i2c_runtime_suspend(struct device *dev)
2003 {
2004         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2005
2006         if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2007                 clk_disable_unprepare(i2c_dev->clk);
2008
2009         return 0;
2010 }
2011
2012 static int stm32f7_i2c_runtime_resume(struct device *dev)
2013 {
2014         struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2015         int ret;
2016
2017         if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2018                 ret = clk_prepare_enable(i2c_dev->clk);
2019                 if (ret) {
2020                         dev_err(dev, "failed to prepare_enable clock\n");
2021                         return ret;
2022                 }
2023         }
2024
2025         return 0;
2026 }
2027 #endif
2028
2029 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2030         SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2031                            stm32f7_i2c_runtime_resume, NULL)
2032 };
2033
2034 static const struct of_device_id stm32f7_i2c_match[] = {
2035         { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2036         {},
2037 };
2038 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2039
2040 static struct platform_driver stm32f7_i2c_driver = {
2041         .driver = {
2042                 .name = "stm32f7-i2c",
2043                 .of_match_table = stm32f7_i2c_match,
2044                 .pm = &stm32f7_i2c_pm_ops,
2045         },
2046         .probe = stm32f7_i2c_probe,
2047         .remove = stm32f7_i2c_remove,
2048 };
2049
2050 module_platform_driver(stm32f7_i2c_driver);
2051
2052 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2053 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2054 MODULE_LICENSE("GPL v2");