drivers/i2c/busses/i2c-sprd.c

   1 /*
   2  * Copyright (C) 2017 Spreadtrum Communications Inc.
   3  *
   4  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/i2c.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #define I2C_CTL                 0x00
  21 #define I2C_ADDR_CFG            0x04
  22 #define I2C_COUNT               0x08
  23 #define I2C_RX                  0x0c
  24 #define I2C_TX                  0x10
  25 #define I2C_STATUS              0x14
  26 #define I2C_HSMODE_CFG          0x18
  27 #define I2C_VERSION             0x1c
  28 #define ADDR_DVD0               0x20
  29 #define ADDR_DVD1               0x24
  30 #define ADDR_STA0_DVD           0x28
  31 #define ADDR_RST                0x2c
  32
  33 /* I2C_CTL */
  34 #define STP_EN                  BIT(20)
  35 #define FIFO_AF_LVL_MASK        GENMASK(19, 16)
  36 #define FIFO_AF_LVL             16
  37 #define FIFO_AE_LVL_MASK        GENMASK(15, 12)
  38 #define FIFO_AE_LVL             12
  39 #define I2C_DMA_EN              BIT(11)
  40 #define FULL_INTEN              BIT(10)
  41 #define EMPTY_INTEN             BIT(9)
  42 #define I2C_DVD_OPT             BIT(8)
  43 #define I2C_OUT_OPT             BIT(7)
  44 #define I2C_TRIM_OPT            BIT(6)
  45 #define I2C_HS_MODE             BIT(4)
  46 #define I2C_MODE                BIT(3)
  47 #define I2C_EN                  BIT(2)
  48 #define I2C_INT_EN              BIT(1)
  49 #define I2C_START               BIT(0)
  50
  51 /* I2C_STATUS */
  52 #define SDA_IN                  BIT(21)
  53 #define SCL_IN                  BIT(20)
  54 #define FIFO_FULL               BIT(4)
  55 #define FIFO_EMPTY              BIT(3)
  56 #define I2C_INT                 BIT(2)
  57 #define I2C_RX_ACK              BIT(1)
  58 #define I2C_BUSY                BIT(0)
  59
  60 /* ADDR_RST */
  61 #define I2C_RST                 BIT(0)
  62
  63 #define I2C_FIFO_DEEP           12
  64 #define I2C_FIFO_FULL_THLD      15
  65 #define I2C_FIFO_EMPTY_THLD     4
  66 #define I2C_DATA_STEP           8
  67 #define I2C_ADDR_DVD0_CALC(high, low)   \
  68         ((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
  69 #define I2C_ADDR_DVD1_CALC(high, low)   \
  70         (((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
  71
  72 /* timeout (ms) for pm runtime autosuspend */
  73 #define SPRD_I2C_PM_TIMEOUT     1000
  74
  75 /* SPRD i2c data structure */
  76 struct sprd_i2c {
  77         struct i2c_adapter adap;
  78         struct device *dev;
  79         void __iomem *base;
  80         struct i2c_msg *msg;
  81         struct clk *clk;
  82         u32 src_clk;
  83         u32 bus_freq;
  84         struct completion complete;
  85         u8 *buf;
  86         u32 count;
  87         int irq;
  88         int err;
  89 };
  90
  91 static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
  92 {
  93         writel(count, i2c_dev->base + I2C_COUNT);
  94 }
  95
  96 static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop)
  97 {
  98         u32 tmp = readl(i2c_dev->base + I2C_CTL);
  99
 100         if (stop)
 101                 writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
 102         else
 103                 writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
 104 }
 105
 106 static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev)
 107 {
 108         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 109
 110         writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
 111 }
 112
 113 static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev)
 114 {
 115         u32 tmp = readl(i2c_dev->base + I2C_STATUS);
 116
 117         writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
 118 }
 119
 120 static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev)
 121 {
 122         u32 tmp = readl(i2c_dev->base + I2C_STATUS);
 123
 124         writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
 125 }
 126
 127 static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev)
 128 {
 129         writel(I2C_RST, i2c_dev->base + ADDR_RST);
 130 }
 131
 132 static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m)
 133 {
 134         writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
 135 }
 136
 137 static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
 138 {
 139         u32 i;
 140
 141         for (i = 0; i < len; i++)
 142                 writeb(buf[i], i2c_dev->base + I2C_TX);
 143 }
 144
 145 static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
 146 {
 147         u32 i;
 148
 149         for (i = 0; i < len; i++)
 150                 buf[i] = readb(i2c_dev->base + I2C_RX);
 151 }
 152
 153 static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld)
 154 {
 155         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 156
 157         tmp &= ~FIFO_AF_LVL_MASK;
 158         tmp |= full_thld << FIFO_AF_LVL;
 159         writel(tmp, i2c_dev->base + I2C_CTL);
 160 };
 161
 162 static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld)
 163 {
 164         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 165
 166         tmp &= ~FIFO_AE_LVL_MASK;
 167         tmp |= empty_thld << FIFO_AE_LVL;
 168         writel(tmp, i2c_dev->base + I2C_CTL);
 169 };
 170
 171 static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable)
 172 {
 173         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 174
 175         if (enable)
 176                 tmp |= FULL_INTEN;
 177         else
 178                 tmp &= ~FULL_INTEN;
 179
 180         writel(tmp, i2c_dev->base + I2C_CTL);
 181 };
 182
 183 static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable)
 184 {
 185         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 186
 187         if (enable)
 188                 tmp |= EMPTY_INTEN;
 189         else
 190                 tmp &= ~EMPTY_INTEN;
 191
 192         writel(tmp, i2c_dev->base + I2C_CTL);
 193 };
 194
 195 static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev)
 196 {
 197         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 198
 199         writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
 200 }
 201
 202 static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw)
 203 {
 204         u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE;
 205
 206         writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
 207 }
 208
 209 static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev)
 210 {
 211         u32 i2c_count = i2c_dev->count;
 212         u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP;
 213         struct i2c_msg *msg = i2c_dev->msg;
 214
 215         if (msg->flags & I2C_M_RD) {
 216                 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD);
 217                 i2c_dev->count -= I2C_FIFO_FULL_THLD;
 218                 i2c_dev->buf += I2C_FIFO_FULL_THLD;
 219
 220                 /*
 221                  * If the read data count is larger than rx fifo full threshold,
 222                  * we should enable the rx fifo full interrupt to read data
 223                  * again.
 224                  */
 225                 if (i2c_dev->count >= I2C_FIFO_FULL_THLD)
 226                         sprd_i2c_set_fifo_full_int(i2c_dev, 1);
 227         } else {
 228                 sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran);
 229                 i2c_dev->buf += need_tran;
 230                 i2c_dev->count -= need_tran;
 231
 232                 /*
 233                  * If the write data count is arger than tx fifo depth which
 234                  * means we can not write all data in one time, then we should
 235                  * enable the tx fifo empty interrupt to write again.
 236                  */
 237                 if (i2c_count > I2C_FIFO_DEEP)
 238                         sprd_i2c_set_fifo_empty_int(i2c_dev, 1);
 239         }
 240 }
 241
 242 static int sprd_i2c_handle_msg(struct i2c_adapter *i2c_adap,
 243                                struct i2c_msg *msg, bool is_last_msg)
 244 {
 245         struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
 246
 247         i2c_dev->msg = msg;
 248         i2c_dev->buf = msg->buf;
 249         i2c_dev->count = msg->len;
 250
 251         reinit_completion(&i2c_dev->complete);
 252         sprd_i2c_reset_fifo(i2c_dev);
 253         sprd_i2c_set_devaddr(i2c_dev, msg);
 254         sprd_i2c_set_count(i2c_dev, msg->len);
 255
 256         if (msg->flags & I2C_M_RD) {
 257                 sprd_i2c_opt_mode(i2c_dev, 1);
 258                 sprd_i2c_send_stop(i2c_dev, 1);
 259         } else {
 260                 sprd_i2c_opt_mode(i2c_dev, 0);
 261                 sprd_i2c_send_stop(i2c_dev, !!is_last_msg);
 262         }
 263
 264         /*
 265          * We should enable rx fifo full interrupt to get data when receiving
 266          * full data.
 267          */
 268         if (msg->flags & I2C_M_RD)
 269                 sprd_i2c_set_fifo_full_int(i2c_dev, 1);
 270         else
 271                 sprd_i2c_data_transfer(i2c_dev);
 272
 273         sprd_i2c_opt_start(i2c_dev);
 274
 275         wait_for_completion(&i2c_dev->complete);
 276
 277         return i2c_dev->err;
 278 }
 279
 280 static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap,
 281                                 struct i2c_msg *msgs, int num)
 282 {
 283         struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
 284         int im, ret;
 285
 286         ret = pm_runtime_get_sync(i2c_dev->dev);
 287         if (ret < 0)
 288                 return ret;
 289
 290         for (im = 0; im < num - 1; im++) {
 291                 ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im], 0);
 292                 if (ret)
 293                         goto err_msg;
 294         }
 295
 296         ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im++], 1);
 297
 298 err_msg:
 299         pm_runtime_mark_last_busy(i2c_dev->dev);
 300         pm_runtime_put_autosuspend(i2c_dev->dev);
 301
 302         return ret < 0 ? ret : im;
 303 }
 304
 305 static u32 sprd_i2c_func(struct i2c_adapter *adap)
 306 {
 307         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 308 }
 309
 310 static const struct i2c_algorithm sprd_i2c_algo = {
 311         .master_xfer = sprd_i2c_master_xfer,
 312         .functionality = sprd_i2c_func,
 313 };
 314
 315 static void sprd_i2c_set_clk(struct sprd_i2c *i2c_dev, u32 freq)
 316 {
 317         u32 apb_clk = i2c_dev->src_clk;
 318         /*
 319          * From I2C databook, the prescale calculation formula:
 320          * prescale = freq_i2c / (4 * freq_scl) - 1;
 321          */
 322         u32 i2c_dvd = apb_clk / (4 * freq) - 1;
 323         /*
 324          * From I2C databook, the high period of SCL clock is recommended as
 325          * 40% (2/5), and the low period of SCL clock is recommended as 60%
 326          * (3/5), then the formula should be:
 327          * high = (prescale * 2 * 2) / 5
 328          * low = (prescale * 2 * 3) / 5
 329          */
 330         u32 high = ((i2c_dvd << 1) * 2) / 5;
 331         u32 low = ((i2c_dvd << 1) * 3) / 5;
 332         u32 div0 = I2C_ADDR_DVD0_CALC(high, low);
 333         u32 div1 = I2C_ADDR_DVD1_CALC(high, low);
 334
 335         writel(div0, i2c_dev->base + ADDR_DVD0);
 336         writel(div1, i2c_dev->base + ADDR_DVD1);
 337
 338         /* Start hold timing = hold time(us) * source clock */
 339         if (freq == 400000)
 340                 writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD);
 341         else if (freq == 100000)
 342                 writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD);
 343 }
 344
 345 static void sprd_i2c_enable(struct sprd_i2c *i2c_dev)
 346 {
 347         u32 tmp = I2C_DVD_OPT;
 348
 349         writel(tmp, i2c_dev->base + I2C_CTL);
 350
 351         sprd_i2c_set_full_thld(i2c_dev, I2C_FIFO_FULL_THLD);
 352         sprd_i2c_set_empty_thld(i2c_dev, I2C_FIFO_EMPTY_THLD);
 353
 354         sprd_i2c_set_clk(i2c_dev, i2c_dev->bus_freq);
 355         sprd_i2c_reset_fifo(i2c_dev);
 356         sprd_i2c_clear_irq(i2c_dev);
 357
 358         tmp = readl(i2c_dev->base + I2C_CTL);
 359         writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL);
 360 }
 361
 362 static irqreturn_t sprd_i2c_isr_thread(int irq, void *dev_id)
 363 {
 364         struct sprd_i2c *i2c_dev = dev_id;
 365         struct i2c_msg *msg = i2c_dev->msg;
 366         bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
 367         u32 i2c_count = readl(i2c_dev->base + I2C_COUNT);
 368         u32 i2c_tran;
 369
 370         if (msg->flags & I2C_M_RD)
 371                 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
 372         else
 373                 i2c_tran = i2c_count;
 374
 375         /*
 376          * If we got one ACK from slave when writing data, and we did not
 377          * finish this transmission (i2c_tran is not zero), then we should
 378          * continue to write data.
 379          *
 380          * For reading data, ack is always true, if i2c_tran is not 0 which
 381          * means we still need to contine to read data from slave.
 382          */
 383         if (i2c_tran && ack) {
 384                 sprd_i2c_data_transfer(i2c_dev);
 385                 return IRQ_HANDLED;
 386         }
 387
 388         i2c_dev->err = 0;
 389
 390         /*
 391          * If we did not get one ACK from slave when writing data, we should
 392          * return -EIO to notify users.
 393          */
 394         if (!ack)
 395                 i2c_dev->err = -EIO;
 396         else if (msg->flags & I2C_M_RD && i2c_dev->count)
 397                 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, i2c_dev->count);
 398
 399         /* Transmission is done and clear ack and start operation */
 400         sprd_i2c_clear_ack(i2c_dev);
 401         sprd_i2c_clear_start(i2c_dev);
 402         complete(&i2c_dev->complete);
 403
 404         return IRQ_HANDLED;
 405 }
 406
 407 static irqreturn_t sprd_i2c_isr(int irq, void *dev_id)
 408 {
 409         struct sprd_i2c *i2c_dev = dev_id;
 410         struct i2c_msg *msg = i2c_dev->msg;
 411         u32 i2c_count = readl(i2c_dev->base + I2C_COUNT);
 412         bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
 413         u32 i2c_tran;
 414
 415         if (msg->flags & I2C_M_RD)
 416                 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
 417         else
 418                 i2c_tran = i2c_count;
 419
 420         /*
 421          * If we did not get one ACK from slave when writing data, then we
 422          * should finish this transmission since we got some errors.
 423          *
 424          * When writing data, if i2c_tran == 0 which means we have writen
 425          * done all data, then we can finish this transmission.
 426          *
 427          * When reading data, if conut < rx fifo full threshold, which
 428          * means we can read all data in one time, then we can finish this
 429          * transmission too.
 430          */
 431         if (!i2c_tran || !ack) {
 432                 sprd_i2c_clear_start(i2c_dev);
 433                 sprd_i2c_clear_irq(i2c_dev);
 434         }
 435
 436         sprd_i2c_set_fifo_empty_int(i2c_dev, 0);
 437         sprd_i2c_set_fifo_full_int(i2c_dev, 0);
 438
 439         return IRQ_WAKE_THREAD;
 440 }
 441
 442 static int sprd_i2c_clk_init(struct sprd_i2c *i2c_dev)
 443 {
 444         struct clk *clk_i2c, *clk_parent;
 445
 446         clk_i2c = devm_clk_get(i2c_dev->dev, "i2c");
 447         if (IS_ERR(clk_i2c)) {
 448                 dev_warn(i2c_dev->dev, "i2c%d can't get the i2c clock\n",
 449                          i2c_dev->adap.nr);
 450                 clk_i2c = NULL;
 451         }
 452
 453         clk_parent = devm_clk_get(i2c_dev->dev, "source");
 454         if (IS_ERR(clk_parent)) {
 455                 dev_warn(i2c_dev->dev, "i2c%d can't get the source clock\n",
 456                          i2c_dev->adap.nr);
 457                 clk_parent = NULL;
 458         }
 459
 460         if (clk_set_parent(clk_i2c, clk_parent))
 461                 i2c_dev->src_clk = clk_get_rate(clk_i2c);
 462         else
 463                 i2c_dev->src_clk = 26000000;
 464
 465         dev_dbg(i2c_dev->dev, "i2c%d set source clock is %d\n",
 466                 i2c_dev->adap.nr, i2c_dev->src_clk);
 467
 468         i2c_dev->clk = devm_clk_get(i2c_dev->dev, "enable");
 469         if (IS_ERR(i2c_dev->clk)) {
 470                 dev_warn(i2c_dev->dev, "i2c%d can't get the enable clock\n",
 471                          i2c_dev->adap.nr);
 472                 i2c_dev->clk = NULL;
 473         }
 474
 475         return 0;
 476 }
 477
 478 static int sprd_i2c_probe(struct platform_device *pdev)
 479 {
 480         struct device *dev = &pdev->dev;
 481         struct sprd_i2c *i2c_dev;
 482         struct resource *res;
 483         u32 prop;
 484         int ret;
 485
 486         pdev->id = of_alias_get_id(dev->of_node, "i2c");
 487
 488         i2c_dev = devm_kzalloc(dev, sizeof(struct sprd_i2c), GFP_KERNEL);
 489         if (!i2c_dev)
 490                 return -ENOMEM;
 491
 492         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 493         i2c_dev->base = devm_ioremap_resource(dev, res);
 494         if (IS_ERR(i2c_dev->base))
 495                 return PTR_ERR(i2c_dev->base);
 496
 497         i2c_dev->irq = platform_get_irq(pdev, 0);
 498         if (i2c_dev->irq < 0) {
 499                 dev_err(&pdev->dev, "failed to get irq resource\n");
 500                 return i2c_dev->irq;
 501         }
 502
 503         i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
 504         init_completion(&i2c_dev->complete);
 505         snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
 506                  "%s", "sprd-i2c");
 507
 508         i2c_dev->bus_freq = 100000;
 509         i2c_dev->adap.owner = THIS_MODULE;
 510         i2c_dev->dev = dev;
 511         i2c_dev->adap.retries = 3;
 512         i2c_dev->adap.algo = &sprd_i2c_algo;
 513         i2c_dev->adap.algo_data = i2c_dev;
 514         i2c_dev->adap.dev.parent = dev;
 515         i2c_dev->adap.nr = pdev->id;
 516         i2c_dev->adap.dev.of_node = dev->of_node;
 517
 518         if (!of_property_read_u32(dev->of_node, "clock-frequency", &prop))
 519                 i2c_dev->bus_freq = prop;
 520
 521         /* We only support 100k and 400k now, otherwise will return error. */
 522         if (i2c_dev->bus_freq != 100000 && i2c_dev->bus_freq != 400000)
 523                 return -EINVAL;
 524
 525         sprd_i2c_clk_init(i2c_dev);
 526         platform_set_drvdata(pdev, i2c_dev);
 527
 528         ret = clk_prepare_enable(i2c_dev->clk);
 529         if (ret)
 530                 return ret;
 531
 532         sprd_i2c_enable(i2c_dev);
 533
 534         pm_runtime_set_autosuspend_delay(i2c_dev->dev, SPRD_I2C_PM_TIMEOUT);
 535         pm_runtime_use_autosuspend(i2c_dev->dev);
 536         pm_runtime_set_active(i2c_dev->dev);
 537         pm_runtime_enable(i2c_dev->dev);
 538
 539         ret = pm_runtime_get_sync(i2c_dev->dev);
 540         if (ret < 0)
 541                 goto err_rpm_put;
 542
 543         ret = devm_request_threaded_irq(dev, i2c_dev->irq,
 544                 sprd_i2c_isr, sprd_i2c_isr_thread,
 545                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
 546                 pdev->name, i2c_dev);
 547         if (ret) {
 548                 dev_err(&pdev->dev, "failed to request irq %d\n", i2c_dev->irq);
 549                 goto err_rpm_put;
 550         }
 551
 552         ret = i2c_add_numbered_adapter(&i2c_dev->adap);
 553         if (ret) {
 554                 dev_err(&pdev->dev, "add adapter failed\n");
 555                 goto err_rpm_put;
 556         }
 557
 558         pm_runtime_mark_last_busy(i2c_dev->dev);
 559         pm_runtime_put_autosuspend(i2c_dev->dev);
 560         return 0;
 561
 562 err_rpm_put:
 563         pm_runtime_put_noidle(i2c_dev->dev);
 564         pm_runtime_disable(i2c_dev->dev);
 565         clk_disable_unprepare(i2c_dev->clk);
 566         return ret;
 567 }
 568
 569 static int sprd_i2c_remove(struct platform_device *pdev)
 570 {
 571         struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev);
 572         int ret;
 573
 574         ret = pm_runtime_get_sync(i2c_dev->dev);
 575         if (ret < 0)
 576                 return ret;
 577
 578         i2c_del_adapter(&i2c_dev->adap);
 579         clk_disable_unprepare(i2c_dev->clk);
 580
 581         pm_runtime_put_noidle(i2c_dev->dev);
 582         pm_runtime_disable(i2c_dev->dev);
 583
 584         return 0;
 585 }
 586
 587 static int __maybe_unused sprd_i2c_suspend_noirq(struct device *pdev)
 588 {
 589         return pm_runtime_force_suspend(pdev);
 590 }
 591
 592 static int __maybe_unused sprd_i2c_resume_noirq(struct device *pdev)
 593 {
 594         return pm_runtime_force_resume(pdev);
 595 }
 596
 597 static int __maybe_unused sprd_i2c_runtime_suspend(struct device *pdev)
 598 {
 599         struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
 600
 601         clk_disable_unprepare(i2c_dev->clk);
 602
 603         return 0;
 604 }
 605
 606 static int __maybe_unused sprd_i2c_runtime_resume(struct device *pdev)
 607 {
 608         struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
 609         int ret;
 610
 611         ret = clk_prepare_enable(i2c_dev->clk);
 612         if (ret)
 613                 return ret;
 614
 615         sprd_i2c_enable(i2c_dev);
 616
 617         return 0;
 618 }
 619
 620 static const struct dev_pm_ops sprd_i2c_pm_ops = {
 621         SET_RUNTIME_PM_OPS(sprd_i2c_runtime_suspend,
 622                            sprd_i2c_runtime_resume, NULL)
 623
 624         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sprd_i2c_suspend_noirq,
 625                                       sprd_i2c_resume_noirq)
 626 };
 627
 628 static const struct of_device_id sprd_i2c_of_match[] = {
 629         { .compatible = "sprd,sc9860-i2c", },
 630         {},
 631 };
 632
 633 static struct platform_driver sprd_i2c_driver = {
 634         .probe = sprd_i2c_probe,
 635         .remove = sprd_i2c_remove,
 636         .driver = {
 637                    .name = "sprd-i2c",
 638                    .of_match_table = sprd_i2c_of_match,
 639                    .pm = &sprd_i2c_pm_ops,
 640         },
 641 };
 642
 643 static int sprd_i2c_init(void)
 644 {
 645         return platform_driver_register(&sprd_i2c_driver);
 646 }
 647 arch_initcall_sync(sprd_i2c_init);