drivers/i2c/busses/i2c-sprd.c

   1 /*
   2  * Copyright (C) 2017 Spreadtrum Communications Inc.
   3  *
   4  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/i2c.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #define I2C_CTL                 0x00
  21 #define I2C_ADDR_CFG            0x04
  22 #define I2C_COUNT               0x08
  23 #define I2C_RX                  0x0c
  24 #define I2C_TX                  0x10
  25 #define I2C_STATUS              0x14
  26 #define I2C_HSMODE_CFG          0x18
  27 #define I2C_VERSION             0x1c
  28 #define ADDR_DVD0               0x20
  29 #define ADDR_DVD1               0x24
  30 #define ADDR_STA0_DVD           0x28
  31 #define ADDR_RST                0x2c
  32
  33 /* I2C_CTL */
  34 #define STP_EN                  BIT(20)
  35 #define FIFO_AF_LVL_MASK        GENMASK(19, 16)
  36 #define FIFO_AF_LVL             16
  37 #define FIFO_AE_LVL_MASK        GENMASK(15, 12)
  38 #define FIFO_AE_LVL             12
  39 #define I2C_DMA_EN              BIT(11)
  40 #define FULL_INTEN              BIT(10)
  41 #define EMPTY_INTEN             BIT(9)
  42 #define I2C_DVD_OPT             BIT(8)
  43 #define I2C_OUT_OPT             BIT(7)
  44 #define I2C_TRIM_OPT            BIT(6)
  45 #define I2C_HS_MODE             BIT(4)
  46 #define I2C_MODE                BIT(3)
  47 #define I2C_EN                  BIT(2)
  48 #define I2C_INT_EN              BIT(1)
  49 #define I2C_START               BIT(0)
  50
  51 /* I2C_STATUS */
  52 #define SDA_IN                  BIT(21)
  53 #define SCL_IN                  BIT(20)
  54 #define FIFO_FULL               BIT(4)
  55 #define FIFO_EMPTY              BIT(3)
  56 #define I2C_INT                 BIT(2)
  57 #define I2C_RX_ACK              BIT(1)
  58 #define I2C_BUSY                BIT(0)
  59
  60 /* ADDR_RST */
  61 #define I2C_RST                 BIT(0)
  62
  63 #define I2C_FIFO_DEEP           12
  64 #define I2C_FIFO_FULL_THLD      15
  65 #define I2C_FIFO_EMPTY_THLD     4
  66 #define I2C_DATA_STEP           8
  67 #define I2C_ADDR_DVD0_CALC(high, low)   \
  68         ((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
  69 #define I2C_ADDR_DVD1_CALC(high, low)   \
  70         (((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
  71
  72 /* timeout (ms) for pm runtime autosuspend */
  73 #define SPRD_I2C_PM_TIMEOUT     1000
  74
  75 /* SPRD i2c data structure */
  76 struct sprd_i2c {
  77         struct i2c_adapter adap;
  78         struct device *dev;
  79         void __iomem *base;
  80         struct i2c_msg *msg;
  81         struct clk *clk;
  82         u32 src_clk;
  83         u32 bus_freq;
  84         struct completion complete;
  85         u8 *buf;
  86         u32 count;
  87         int irq;
  88         int err;
  89         bool is_suspended;
  90 };
  91
  92 static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
  93 {
  94         writel(count, i2c_dev->base + I2C_COUNT);
  95 }
  96
  97 static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop)
  98 {
  99         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 100
 101         if (stop)
 102                 writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
 103         else
 104                 writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
 105 }
 106
 107 static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev)
 108 {
 109         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 110
 111         writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
 112 }
 113
 114 static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev)
 115 {
 116         u32 tmp = readl(i2c_dev->base + I2C_STATUS);
 117
 118         writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
 119 }
 120
 121 static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev)
 122 {
 123         u32 tmp = readl(i2c_dev->base + I2C_STATUS);
 124
 125         writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
 126 }
 127
 128 static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev)
 129 {
 130         writel(I2C_RST, i2c_dev->base + ADDR_RST);
 131 }
 132
 133 static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m)
 134 {
 135         writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
 136 }
 137
 138 static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
 139 {
 140         u32 i;
 141
 142         for (i = 0; i < len; i++)
 143                 writeb(buf[i], i2c_dev->base + I2C_TX);
 144 }
 145
 146 static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
 147 {
 148         u32 i;
 149
 150         for (i = 0; i < len; i++)
 151                 buf[i] = readb(i2c_dev->base + I2C_RX);
 152 }
 153
 154 static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld)
 155 {
 156         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 157
 158         tmp &= ~FIFO_AF_LVL_MASK;
 159         tmp |= full_thld << FIFO_AF_LVL;
 160         writel(tmp, i2c_dev->base + I2C_CTL);
 161 };
 162
 163 static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld)
 164 {
 165         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 166
 167         tmp &= ~FIFO_AE_LVL_MASK;
 168         tmp |= empty_thld << FIFO_AE_LVL;
 169         writel(tmp, i2c_dev->base + I2C_CTL);
 170 };
 171
 172 static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable)
 173 {
 174         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 175
 176         if (enable)
 177                 tmp |= FULL_INTEN;
 178         else
 179                 tmp &= ~FULL_INTEN;
 180
 181         writel(tmp, i2c_dev->base + I2C_CTL);
 182 };
 183
 184 static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable)
 185 {
 186         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 187
 188         if (enable)
 189                 tmp |= EMPTY_INTEN;
 190         else
 191                 tmp &= ~EMPTY_INTEN;
 192
 193         writel(tmp, i2c_dev->base + I2C_CTL);
 194 };
 195
 196 static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev)
 197 {
 198         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 199
 200         writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
 201 }
 202
 203 static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw)
 204 {
 205         u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE;
 206
 207         writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
 208 }
 209
 210 static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev)
 211 {
 212         u32 i2c_count = i2c_dev->count;
 213         u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP;
 214         struct i2c_msg *msg = i2c_dev->msg;
 215
 216         if (msg->flags & I2C_M_RD) {
 217                 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD);
 218                 i2c_dev->count -= I2C_FIFO_FULL_THLD;
 219                 i2c_dev->buf += I2C_FIFO_FULL_THLD;
 220
 221                 /*
 222                  * If the read data count is larger than rx fifo full threshold,
 223                  * we should enable the rx fifo full interrupt to read data
 224                  * again.
 225                  */
 226                 if (i2c_dev->count >= I2C_FIFO_FULL_THLD)
 227                         sprd_i2c_set_fifo_full_int(i2c_dev, 1);
 228         } else {
 229                 sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran);
 230                 i2c_dev->buf += need_tran;
 231                 i2c_dev->count -= need_tran;
 232
 233                 /*
 234                  * If the write data count is arger than tx fifo depth which
 235                  * means we can not write all data in one time, then we should
 236                  * enable the tx fifo empty interrupt to write again.
 237                  */
 238                 if (i2c_count > I2C_FIFO_DEEP)
 239                         sprd_i2c_set_fifo_empty_int(i2c_dev, 1);
 240         }
 241 }
 242
 243 static int sprd_i2c_handle_msg(struct i2c_adapter *i2c_adap,
 244                                struct i2c_msg *msg, bool is_last_msg)
 245 {
 246         struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
 247
 248         i2c_dev->msg = msg;
 249         i2c_dev->buf = msg->buf;
 250         i2c_dev->count = msg->len;
 251
 252         reinit_completion(&i2c_dev->complete);
 253         sprd_i2c_reset_fifo(i2c_dev);
 254         sprd_i2c_set_devaddr(i2c_dev, msg);
 255         sprd_i2c_set_count(i2c_dev, msg->len);
 256
 257         if (msg->flags & I2C_M_RD) {
 258                 sprd_i2c_opt_mode(i2c_dev, 1);
 259                 sprd_i2c_send_stop(i2c_dev, 1);
 260         } else {
 261                 sprd_i2c_opt_mode(i2c_dev, 0);
 262                 sprd_i2c_send_stop(i2c_dev, !!is_last_msg);
 263         }
 264
 265         /*
 266          * We should enable rx fifo full interrupt to get data when receiving
 267          * full data.
 268          */
 269         if (msg->flags & I2C_M_RD)
 270                 sprd_i2c_set_fifo_full_int(i2c_dev, 1);
 271         else
 272                 sprd_i2c_data_transfer(i2c_dev);
 273
 274         sprd_i2c_opt_start(i2c_dev);
 275
 276         wait_for_completion(&i2c_dev->complete);
 277
 278         return i2c_dev->err;
 279 }
 280
 281 static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap,
 282                                 struct i2c_msg *msgs, int num)
 283 {
 284         struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
 285         int im, ret;
 286
 287         if (i2c_dev->is_suspended)
 288                 return -EBUSY;
 289
 290         ret = pm_runtime_get_sync(i2c_dev->dev);
 291         if (ret < 0)
 292                 return ret;
 293
 294         for (im = 0; im < num - 1; im++) {
 295                 ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im], 0);
 296                 if (ret)
 297                         goto err_msg;
 298         }
 299
 300         ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im++], 1);
 301
 302 err_msg:
 303         pm_runtime_mark_last_busy(i2c_dev->dev);
 304         pm_runtime_put_autosuspend(i2c_dev->dev);
 305
 306         return ret < 0 ? ret : im;
 307 }
 308
 309 static u32 sprd_i2c_func(struct i2c_adapter *adap)
 310 {
 311         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 312 }
 313
 314 static const struct i2c_algorithm sprd_i2c_algo = {
 315         .master_xfer = sprd_i2c_master_xfer,
 316         .functionality = sprd_i2c_func,
 317 };
 318
 319 static void sprd_i2c_set_clk(struct sprd_i2c *i2c_dev, u32 freq)
 320 {
 321         u32 apb_clk = i2c_dev->src_clk;
 322         /*
 323          * From I2C databook, the prescale calculation formula:
 324          * prescale = freq_i2c / (4 * freq_scl) - 1;
 325          */
 326         u32 i2c_dvd = apb_clk / (4 * freq) - 1;
 327         /*
 328          * From I2C databook, the high period of SCL clock is recommended as
 329          * 40% (2/5), and the low period of SCL clock is recommended as 60%
 330          * (3/5), then the formula should be:
 331          * high = (prescale * 2 * 2) / 5
 332          * low = (prescale * 2 * 3) / 5
 333          */
 334         u32 high = ((i2c_dvd << 1) * 2) / 5;
 335         u32 low = ((i2c_dvd << 1) * 3) / 5;
 336         u32 div0 = I2C_ADDR_DVD0_CALC(high, low);
 337         u32 div1 = I2C_ADDR_DVD1_CALC(high, low);
 338
 339         writel(div0, i2c_dev->base + ADDR_DVD0);
 340         writel(div1, i2c_dev->base + ADDR_DVD1);
 341
 342         /* Start hold timing = hold time(us) * source clock */
 343         if (freq == 400000)
 344                 writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD);
 345         else if (freq == 100000)
 346                 writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD);
 347 }
 348
 349 static void sprd_i2c_enable(struct sprd_i2c *i2c_dev)
 350 {
 351         u32 tmp = I2C_DVD_OPT;
 352
 353         writel(tmp, i2c_dev->base + I2C_CTL);
 354
 355         sprd_i2c_set_full_thld(i2c_dev, I2C_FIFO_FULL_THLD);
 356         sprd_i2c_set_empty_thld(i2c_dev, I2C_FIFO_EMPTY_THLD);
 357
 358         sprd_i2c_set_clk(i2c_dev, i2c_dev->bus_freq);
 359         sprd_i2c_reset_fifo(i2c_dev);
 360         sprd_i2c_clear_irq(i2c_dev);
 361
 362         tmp = readl(i2c_dev->base + I2C_CTL);
 363         writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL);
 364 }
 365
 366 static irqreturn_t sprd_i2c_isr_thread(int irq, void *dev_id)
 367 {
 368         struct sprd_i2c *i2c_dev = dev_id;
 369         struct i2c_msg *msg = i2c_dev->msg;
 370         bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
 371         u32 i2c_count = readl(i2c_dev->base + I2C_COUNT);
 372         u32 i2c_tran;
 373
 374         if (msg->flags & I2C_M_RD)
 375                 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
 376         else
 377                 i2c_tran = i2c_count;
 378
 379         /*
 380          * If we got one ACK from slave when writing data, and we did not
 381          * finish this transmission (i2c_tran is not zero), then we should
 382          * continue to write data.
 383          *
 384          * For reading data, ack is always true, if i2c_tran is not 0 which
 385          * means we still need to contine to read data from slave.
 386          */
 387         if (i2c_tran && ack) {
 388                 sprd_i2c_data_transfer(i2c_dev);
 389                 return IRQ_HANDLED;
 390         }
 391
 392         i2c_dev->err = 0;
 393
 394         /*
 395          * If we did not get one ACK from slave when writing data, we should
 396          * return -EIO to notify users.
 397          */
 398         if (!ack)
 399                 i2c_dev->err = -EIO;
 400         else if (msg->flags & I2C_M_RD && i2c_dev->count)
 401                 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, i2c_dev->count);
 402
 403         /* Transmission is done and clear ack and start operation */
 404         sprd_i2c_clear_ack(i2c_dev);
 405         sprd_i2c_clear_start(i2c_dev);
 406         complete(&i2c_dev->complete);
 407
 408         return IRQ_HANDLED;
 409 }
 410
 411 static irqreturn_t sprd_i2c_isr(int irq, void *dev_id)
 412 {
 413         struct sprd_i2c *i2c_dev = dev_id;
 414         struct i2c_msg *msg = i2c_dev->msg;
 415         u32 i2c_count = readl(i2c_dev->base + I2C_COUNT);
 416         bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
 417         u32 i2c_tran;
 418
 419         if (msg->flags & I2C_M_RD)
 420                 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
 421         else
 422                 i2c_tran = i2c_count;
 423
 424         /*
 425          * If we did not get one ACK from slave when writing data, then we
 426          * should finish this transmission since we got some errors.
 427          *
 428          * When writing data, if i2c_tran == 0 which means we have writen
 429          * done all data, then we can finish this transmission.
 430          *
 431          * When reading data, if conut < rx fifo full threshold, which
 432          * means we can read all data in one time, then we can finish this
 433          * transmission too.
 434          */
 435         if (!i2c_tran || !ack) {
 436                 sprd_i2c_clear_start(i2c_dev);
 437                 sprd_i2c_clear_irq(i2c_dev);
 438         }
 439
 440         sprd_i2c_set_fifo_empty_int(i2c_dev, 0);
 441         sprd_i2c_set_fifo_full_int(i2c_dev, 0);
 442
 443         return IRQ_WAKE_THREAD;
 444 }
 445
 446 static int sprd_i2c_clk_init(struct sprd_i2c *i2c_dev)
 447 {
 448         struct clk *clk_i2c, *clk_parent;
 449
 450         clk_i2c = devm_clk_get(i2c_dev->dev, "i2c");
 451         if (IS_ERR(clk_i2c)) {
 452                 dev_warn(i2c_dev->dev, "i2c%d can't get the i2c clock\n",
 453                          i2c_dev->adap.nr);
 454                 clk_i2c = NULL;
 455         }
 456
 457         clk_parent = devm_clk_get(i2c_dev->dev, "source");
 458         if (IS_ERR(clk_parent)) {
 459                 dev_warn(i2c_dev->dev, "i2c%d can't get the source clock\n",
 460                          i2c_dev->adap.nr);
 461                 clk_parent = NULL;
 462         }
 463
 464         if (clk_set_parent(clk_i2c, clk_parent))
 465                 i2c_dev->src_clk = clk_get_rate(clk_i2c);
 466         else
 467                 i2c_dev->src_clk = 26000000;
 468
 469         dev_dbg(i2c_dev->dev, "i2c%d set source clock is %d\n",
 470                 i2c_dev->adap.nr, i2c_dev->src_clk);
 471
 472         i2c_dev->clk = devm_clk_get(i2c_dev->dev, "enable");
 473         if (IS_ERR(i2c_dev->clk)) {
 474                 dev_warn(i2c_dev->dev, "i2c%d can't get the enable clock\n",
 475                          i2c_dev->adap.nr);
 476                 i2c_dev->clk = NULL;
 477         }
 478
 479         return 0;
 480 }
 481
 482 static int sprd_i2c_probe(struct platform_device *pdev)
 483 {
 484         struct device *dev = &pdev->dev;
 485         struct sprd_i2c *i2c_dev;
 486         struct resource *res;
 487         u32 prop;
 488         int ret;
 489
 490         pdev->id = of_alias_get_id(dev->of_node, "i2c");
 491
 492         i2c_dev = devm_kzalloc(dev, sizeof(struct sprd_i2c), GFP_KERNEL);
 493         if (!i2c_dev)
 494                 return -ENOMEM;
 495
 496         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 497         i2c_dev->base = devm_ioremap_resource(dev, res);
 498         if (IS_ERR(i2c_dev->base))
 499                 return PTR_ERR(i2c_dev->base);
 500
 501         i2c_dev->irq = platform_get_irq(pdev, 0);
 502         if (i2c_dev->irq < 0) {
 503                 dev_err(&pdev->dev, "failed to get irq resource\n");
 504                 return i2c_dev->irq;
 505         }
 506
 507         i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
 508         init_completion(&i2c_dev->complete);
 509         snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
 510                  "%s", "sprd-i2c");
 511
 512         i2c_dev->bus_freq = 100000;
 513         i2c_dev->adap.owner = THIS_MODULE;
 514         i2c_dev->dev = dev;
 515         i2c_dev->adap.retries = 3;
 516         i2c_dev->adap.algo = &sprd_i2c_algo;
 517         i2c_dev->adap.algo_data = i2c_dev;
 518         i2c_dev->adap.dev.parent = dev;
 519         i2c_dev->adap.nr = pdev->id;
 520         i2c_dev->adap.dev.of_node = dev->of_node;
 521
 522         if (!of_property_read_u32(dev->of_node, "clock-frequency", &prop))
 523                 i2c_dev->bus_freq = prop;
 524
 525         /* We only support 100k and 400k now, otherwise will return error. */
 526         if (i2c_dev->bus_freq != 100000 && i2c_dev->bus_freq != 400000)
 527                 return -EINVAL;
 528
 529         sprd_i2c_clk_init(i2c_dev);
 530         platform_set_drvdata(pdev, i2c_dev);
 531
 532         ret = clk_prepare_enable(i2c_dev->clk);
 533         if (ret)
 534                 return ret;
 535
 536         sprd_i2c_enable(i2c_dev);
 537
 538         pm_runtime_set_autosuspend_delay(i2c_dev->dev, SPRD_I2C_PM_TIMEOUT);
 539         pm_runtime_use_autosuspend(i2c_dev->dev);
 540         pm_runtime_set_active(i2c_dev->dev);
 541         pm_runtime_enable(i2c_dev->dev);
 542
 543         ret = pm_runtime_get_sync(i2c_dev->dev);
 544         if (ret < 0)
 545                 goto err_rpm_put;
 546
 547         ret = devm_request_threaded_irq(dev, i2c_dev->irq,
 548                 sprd_i2c_isr, sprd_i2c_isr_thread,
 549                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
 550                 pdev->name, i2c_dev);
 551         if (ret) {
 552                 dev_err(&pdev->dev, "failed to request irq %d\n", i2c_dev->irq);
 553                 goto err_rpm_put;
 554         }
 555
 556         ret = i2c_add_numbered_adapter(&i2c_dev->adap);
 557         if (ret) {
 558                 dev_err(&pdev->dev, "add adapter failed\n");
 559                 goto err_rpm_put;
 560         }
 561
 562         pm_runtime_mark_last_busy(i2c_dev->dev);
 563         pm_runtime_put_autosuspend(i2c_dev->dev);
 564         return 0;
 565
 566 err_rpm_put:
 567         pm_runtime_put_noidle(i2c_dev->dev);
 568         pm_runtime_disable(i2c_dev->dev);
 569         clk_disable_unprepare(i2c_dev->clk);
 570         return ret;
 571 }
 572
 573 static int sprd_i2c_remove(struct platform_device *pdev)
 574 {
 575         struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev);
 576         int ret;
 577
 578         ret = pm_runtime_get_sync(i2c_dev->dev);
 579         if (ret < 0)
 580                 return ret;
 581
 582         i2c_del_adapter(&i2c_dev->adap);
 583         clk_disable_unprepare(i2c_dev->clk);
 584
 585         pm_runtime_put_noidle(i2c_dev->dev);
 586         pm_runtime_disable(i2c_dev->dev);
 587
 588         return 0;
 589 }
 590
 591 static int __maybe_unused sprd_i2c_suspend_noirq(struct device *pdev)
 592 {
 593         struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
 594
 595         i2c_lock_adapter(&i2c_dev->adap);
 596         i2c_dev->is_suspended = true;
 597         i2c_unlock_adapter(&i2c_dev->adap);
 598
 599         return pm_runtime_force_suspend(pdev);
 600 }
 601
 602 static int __maybe_unused sprd_i2c_resume_noirq(struct device *pdev)
 603 {
 604         struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
 605
 606         i2c_lock_adapter(&i2c_dev->adap);
 607         i2c_dev->is_suspended = false;
 608         i2c_unlock_adapter(&i2c_dev->adap);
 609
 610         return pm_runtime_force_resume(pdev);
 611 }
 612
 613 static int __maybe_unused sprd_i2c_runtime_suspend(struct device *pdev)
 614 {
 615         struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
 616
 617         clk_disable_unprepare(i2c_dev->clk);
 618
 619         return 0;
 620 }
 621
 622 static int __maybe_unused sprd_i2c_runtime_resume(struct device *pdev)
 623 {
 624         struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
 625         int ret;
 626
 627         ret = clk_prepare_enable(i2c_dev->clk);
 628         if (ret)
 629                 return ret;
 630
 631         sprd_i2c_enable(i2c_dev);
 632
 633         return 0;
 634 }
 635
 636 static const struct dev_pm_ops sprd_i2c_pm_ops = {
 637         SET_RUNTIME_PM_OPS(sprd_i2c_runtime_suspend,
 638                            sprd_i2c_runtime_resume, NULL)
 639
 640         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sprd_i2c_suspend_noirq,
 641                                       sprd_i2c_resume_noirq)
 642 };
 643
 644 static const struct of_device_id sprd_i2c_of_match[] = {
 645         { .compatible = "sprd,sc9860-i2c", },
 646         {},
 647 };
 648
 649 static struct platform_driver sprd_i2c_driver = {
 650         .probe = sprd_i2c_probe,
 651         .remove = sprd_i2c_remove,
 652         .driver = {
 653                    .name = "sprd-i2c",
 654                    .of_match_table = sprd_i2c_of_match,
 655                    .pm = &sprd_i2c_pm_ops,
 656         },
 657 };
 658
 659 static int sprd_i2c_init(void)
 660 {
 661         return platform_driver_register(&sprd_i2c_driver);
 662 }
 663 arch_initcall_sync(sprd_i2c_init);