drivers/i2c/busses/i2c-sirf.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * I2C bus driver for CSR SiRFprimaII
   4  *
   5  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   6  */
   7
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/slab.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/i2c.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17
  18 #define SIRFSOC_I2C_CLK_CTRL            0x00
  19 #define SIRFSOC_I2C_STATUS              0x0C
  20 #define SIRFSOC_I2C_CTRL                0x10
  21 #define SIRFSOC_I2C_IO_CTRL             0x14
  22 #define SIRFSOC_I2C_SDA_DELAY           0x18
  23 #define SIRFSOC_I2C_CMD_START           0x1C
  24 #define SIRFSOC_I2C_CMD_BUF             0x30
  25 #define SIRFSOC_I2C_DATA_BUF            0x80
  26
  27 #define SIRFSOC_I2C_CMD_BUF_MAX         16
  28 #define SIRFSOC_I2C_DATA_BUF_MAX        16
  29
  30 #define SIRFSOC_I2C_CMD(x)              (SIRFSOC_I2C_CMD_BUF + (x)*0x04)
  31 #define SIRFSOC_I2C_DATA_MASK(x)        (0xFF<<(((x)&3)*8))
  32 #define SIRFSOC_I2C_DATA_SHIFT(x)       (((x)&3)*8)
  33
  34 #define SIRFSOC_I2C_DIV_MASK            (0xFFFF)
  35
  36 /* I2C status flags */
  37 #define SIRFSOC_I2C_STAT_BUSY           BIT(0)
  38 #define SIRFSOC_I2C_STAT_TIP            BIT(1)
  39 #define SIRFSOC_I2C_STAT_NACK           BIT(2)
  40 #define SIRFSOC_I2C_STAT_TR_INT         BIT(4)
  41 #define SIRFSOC_I2C_STAT_STOP           BIT(6)
  42 #define SIRFSOC_I2C_STAT_CMD_DONE       BIT(8)
  43 #define SIRFSOC_I2C_STAT_ERR            BIT(9)
  44 #define SIRFSOC_I2C_CMD_INDEX           (0x1F<<16)
  45
  46 /* I2C control flags */
  47 #define SIRFSOC_I2C_RESET               BIT(0)
  48 #define SIRFSOC_I2C_CORE_EN             BIT(1)
  49 #define SIRFSOC_I2C_MASTER_MODE         BIT(2)
  50 #define SIRFSOC_I2C_CMD_DONE_EN         BIT(11)
  51 #define SIRFSOC_I2C_ERR_INT_EN          BIT(12)
  52
  53 #define SIRFSOC_I2C_SDA_DELAY_MASK      (0xFF)
  54 #define SIRFSOC_I2C_SCLF_FILTER         (3<<8)
  55
  56 #define SIRFSOC_I2C_START_CMD           BIT(0)
  57
  58 #define SIRFSOC_I2C_CMD_RP(x)           ((x)&0x7)
  59 #define SIRFSOC_I2C_NACK                BIT(3)
  60 #define SIRFSOC_I2C_WRITE               BIT(4)
  61 #define SIRFSOC_I2C_READ                BIT(5)
  62 #define SIRFSOC_I2C_STOP                BIT(6)
  63 #define SIRFSOC_I2C_START               BIT(7)
  64
  65 #define SIRFSOC_I2C_DEFAULT_SPEED 100000
  66 #define SIRFSOC_I2C_ERR_NOACK      1
  67 #define SIRFSOC_I2C_ERR_TIMEOUT    2
  68
  69 struct sirfsoc_i2c {
  70         void __iomem *base;
  71         struct clk *clk;
  72         u32 cmd_ptr;            /* Current position in CMD buffer */
  73         u8 *buf;                /* Buffer passed by user */
  74         u32 msg_len;            /* Message length */
  75         u32 finished_len;       /* number of bytes read/written */
  76         u32 read_cmd_len;       /* number of read cmd sent */
  77         int msg_read;           /* 1 indicates a read message */
  78         int err_status;         /* 1 indicates an error on bus */
  79
  80         u32 sda_delay;          /* For suspend/resume */
  81         u32 clk_div;
  82         int last;               /* Last message in transfer, STOP cmd can be sent */
  83
  84         struct completion done; /* indicates completion of message transfer */
  85         struct i2c_adapter adapter;
  86 };
  87
  88 static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
  89 {
  90         u32 data = 0;
  91         int i;
  92
  93         for (i = 0; i < siic->read_cmd_len; i++) {
  94                 if (!(i & 0x3))
  95                         data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
  96                 siic->buf[siic->finished_len++] =
  97                         (u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
  98                                 SIRFSOC_I2C_DATA_SHIFT(i));
  99         }
 100 }
 101
 102 static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
 103 {
 104         u32 regval;
 105         int i = 0;
 106
 107         if (siic->msg_read) {
 108                 while (((siic->finished_len + i) < siic->msg_len)
 109                                 && (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
 110                         regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
 111                         if (((siic->finished_len + i) ==
 112                                         (siic->msg_len - 1)) && siic->last)
 113                                 regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
 114                         writel(regval,
 115                                 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 116                         i++;
 117                 }
 118
 119                 siic->read_cmd_len = i;
 120         } else {
 121                 while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
 122                                 && (siic->finished_len < siic->msg_len)) {
 123                         regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
 124                         if ((siic->finished_len == (siic->msg_len - 1))
 125                                 && siic->last)
 126                                 regval |= SIRFSOC_I2C_STOP;
 127                         writel(regval,
 128                                 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 129                         writel(siic->buf[siic->finished_len++],
 130                                 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 131                 }
 132         }
 133         siic->cmd_ptr = 0;
 134
 135         /* Trigger the transfer */
 136         writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
 137 }
 138
 139 static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
 140 {
 141         struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id;
 142         u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
 143
 144         if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
 145                 /* Error conditions */
 146                 siic->err_status = SIRFSOC_I2C_ERR_NOACK;
 147                 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
 148
 149                 if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
 150                         dev_dbg(&siic->adapter.dev, "ACK not received\n");
 151                 else
 152                         dev_err(&siic->adapter.dev, "I2C error\n");
 153
 154                 /*
 155                  * Due to hardware ANOMALY, we need to reset I2C earlier after
 156                  * we get NOACK while accessing non-existing clients, otherwise
 157                  * we will get errors even we access existing clients later
 158                  */
 159                 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
 160                                 siic->base + SIRFSOC_I2C_CTRL);
 161                 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
 162                         cpu_relax();
 163
 164                 complete(&siic->done);
 165         } else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
 166                 /* CMD buffer execution complete */
 167                 if (siic->msg_read)
 168                         i2c_sirfsoc_read_data(siic);
 169                 if (siic->finished_len == siic->msg_len)
 170                         complete(&siic->done);
 171                 else /* Fill a new CMD buffer for left data */
 172                         i2c_sirfsoc_queue_cmd(siic);
 173
 174                 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
 175         }
 176
 177         return IRQ_HANDLED;
 178 }
 179
 180 static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
 181         struct i2c_msg *msg)
 182 {
 183         unsigned char addr;
 184         u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE;
 185
 186         /* no data and last message -> add STOP */
 187         if (siic->last && (msg->len == 0))
 188                 regval |= SIRFSOC_I2C_STOP;
 189
 190         writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 191
 192         addr = i2c_8bit_addr_from_msg(msg);
 193
 194         /* Reverse direction bit */
 195         if (msg->flags & I2C_M_REV_DIR_ADDR)
 196                 addr ^= 1;
 197
 198         writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 199 }
 200
 201 static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg)
 202 {
 203         u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
 204         /* timeout waiting for the xfer to finish or fail */
 205         int timeout = msecs_to_jiffies((msg->len + 1) * 50);
 206
 207         i2c_sirfsoc_set_address(siic, msg);
 208
 209         writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN,
 210                 siic->base + SIRFSOC_I2C_CTRL);
 211         i2c_sirfsoc_queue_cmd(siic);
 212
 213         if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
 214                 siic->err_status = SIRFSOC_I2C_ERR_TIMEOUT;
 215                 dev_err(&siic->adapter.dev, "Transfer timeout\n");
 216         }
 217
 218         writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN),
 219                 siic->base + SIRFSOC_I2C_CTRL);
 220         writel(0, siic->base + SIRFSOC_I2C_CMD_START);
 221
 222         /* i2c control doesn't response, reset it */
 223         if (siic->err_status == SIRFSOC_I2C_ERR_TIMEOUT) {
 224                 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
 225                         siic->base + SIRFSOC_I2C_CTRL);
 226                 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
 227                         cpu_relax();
 228         }
 229         return siic->err_status ? -EAGAIN : 0;
 230 }
 231
 232 static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
 233 {
 234         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 235 }
 236
 237 static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 238         int num)
 239 {
 240         struct sirfsoc_i2c *siic = adap->algo_data;
 241         int i, ret;
 242
 243         clk_enable(siic->clk);
 244
 245         for (i = 0; i < num; i++) {
 246                 siic->buf = msgs[i].buf;
 247                 siic->msg_len = msgs[i].len;
 248                 siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
 249                 siic->err_status = 0;
 250                 siic->cmd_ptr = 0;
 251                 siic->finished_len = 0;
 252                 siic->last = (i == (num - 1));
 253
 254                 ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
 255                 if (ret) {
 256                         clk_disable(siic->clk);
 257                         return ret;
 258                 }
 259         }
 260
 261         clk_disable(siic->clk);
 262         return num;
 263 }
 264
 265 /* I2C algorithms associated with this master controller driver */
 266 static const struct i2c_algorithm i2c_sirfsoc_algo = {
 267         .master_xfer = i2c_sirfsoc_xfer,
 268         .functionality = i2c_sirfsoc_func,
 269 };
 270
 271 static int i2c_sirfsoc_probe(struct platform_device *pdev)
 272 {
 273         struct sirfsoc_i2c *siic;
 274         struct i2c_adapter *adap;
 275         struct resource *mem_res;
 276         struct clk *clk;
 277         int bitrate;
 278         int ctrl_speed;
 279         int irq;
 280
 281         int err;
 282         u32 regval;
 283
 284         clk = clk_get(&pdev->dev, NULL);
 285         if (IS_ERR(clk)) {
 286                 err = PTR_ERR(clk);
 287                 dev_err(&pdev->dev, "Clock get failed\n");
 288                 goto err_get_clk;
 289         }
 290
 291         err = clk_prepare(clk);
 292         if (err) {
 293                 dev_err(&pdev->dev, "Clock prepare failed\n");
 294                 goto err_clk_prep;
 295         }
 296
 297         err = clk_enable(clk);
 298         if (err) {
 299                 dev_err(&pdev->dev, "Clock enable failed\n");
 300                 goto err_clk_en;
 301         }
 302
 303         ctrl_speed = clk_get_rate(clk);
 304
 305         siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
 306         if (!siic) {
 307                 err = -ENOMEM;
 308                 goto out;
 309         }
 310         adap = &siic->adapter;
 311         adap->class = I2C_CLASS_DEPRECATED;
 312
 313         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 314         siic->base = devm_ioremap_resource(&pdev->dev, mem_res);
 315         if (IS_ERR(siic->base)) {
 316                 err = PTR_ERR(siic->base);
 317                 goto out;
 318         }
 319
 320         irq = platform_get_irq(pdev, 0);
 321         if (irq < 0) {
 322                 err = irq;
 323                 goto out;
 324         }
 325         err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
 326                 dev_name(&pdev->dev), siic);
 327         if (err)
 328                 goto out;
 329
 330         adap->algo = &i2c_sirfsoc_algo;
 331         adap->algo_data = siic;
 332         adap->retries = 3;
 333
 334         adap->dev.of_node = pdev->dev.of_node;
 335         adap->dev.parent = &pdev->dev;
 336         adap->nr = pdev->id;
 337
 338         strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));
 339
 340         platform_set_drvdata(pdev, adap);
 341         init_completion(&siic->done);
 342
 343         /* Controller initialisation */
 344
 345         writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
 346         while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
 347                 cpu_relax();
 348         writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
 349                 siic->base + SIRFSOC_I2C_CTRL);
 350
 351         siic->clk = clk;
 352
 353         err = of_property_read_u32(pdev->dev.of_node,
 354                 "clock-frequency", &bitrate);
 355         if (err < 0)
 356                 bitrate = SIRFSOC_I2C_DEFAULT_SPEED;
 357
 358         /*
 359          * Due to some hardware design issues, we need to tune the formula.
 360          * Since i2c is open drain interface that allows the slave to
 361          * stall the transaction by holding the SCL line at '0', the RTL
 362          * implementation is waiting for SCL feedback from the pin after
 363          * setting it to High-Z ('1'). This wait adds to the high-time
 364          * interval counter few cycles of the input synchronization
 365          * (depending on the SCL_FILTER_REG field), and also the time it
 366          * takes for the board pull-up resistor to rise the SCL line.
 367          * For slow SCL settings these additions are negligible,
 368          * but they start to affect the speed when clock is set to faster
 369          * frequencies.
 370          * Through the actual tests, use the different user_div value(which
 371          * in the divider formula 'Fio / (Fi2c * user_div)') to adapt
 372          * the different ranges of i2c bus clock frequency, to make the SCL
 373          * more accurate.
 374          */
 375         if (bitrate <= 30000)
 376                 regval = ctrl_speed / (bitrate * 5);
 377         else if (bitrate > 30000 && bitrate <= 280000)
 378                 regval = (2 * ctrl_speed) / (bitrate * 11);
 379         else
 380                 regval = ctrl_speed / (bitrate * 6);
 381
 382         writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
 383         if (regval > 0xFF)
 384                 writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
 385         else
 386                 writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);
 387
 388         err = i2c_add_numbered_adapter(adap);
 389         if (err < 0)
 390                 goto out;
 391
 392         clk_disable(clk);
 393
 394         dev_info(&pdev->dev, " I2C adapter ready to operate\n");
 395
 396         return 0;
 397
 398 out:
 399         clk_disable(clk);
 400 err_clk_en:
 401         clk_unprepare(clk);
 402 err_clk_prep:
 403         clk_put(clk);
 404 err_get_clk:
 405         return err;
 406 }
 407
 408 static int i2c_sirfsoc_remove(struct platform_device *pdev)
 409 {
 410         struct i2c_adapter *adapter = platform_get_drvdata(pdev);
 411         struct sirfsoc_i2c *siic = adapter->algo_data;
 412
 413         writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
 414         i2c_del_adapter(adapter);
 415         clk_unprepare(siic->clk);
 416         clk_put(siic->clk);
 417         return 0;
 418 }
 419
 420 #ifdef CONFIG_PM
 421 static int i2c_sirfsoc_suspend(struct device *dev)
 422 {
 423         struct i2c_adapter *adapter = dev_get_drvdata(dev);
 424         struct sirfsoc_i2c *siic = adapter->algo_data;
 425
 426         clk_enable(siic->clk);
 427         siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
 428         siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
 429         clk_disable(siic->clk);
 430         return 0;
 431 }
 432
 433 static int i2c_sirfsoc_resume(struct device *dev)
 434 {
 435         struct i2c_adapter *adapter = dev_get_drvdata(dev);
 436         struct sirfsoc_i2c *siic = adapter->algo_data;
 437
 438         clk_enable(siic->clk);
 439         writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
 440         while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
 441                 cpu_relax();
 442         writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
 443                 siic->base + SIRFSOC_I2C_CTRL);
 444         writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
 445         writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
 446         clk_disable(siic->clk);
 447         return 0;
 448 }
 449
 450 static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
 451         .suspend = i2c_sirfsoc_suspend,
 452         .resume = i2c_sirfsoc_resume,
 453 };
 454 #endif
 455
 456 static const struct of_device_id sirfsoc_i2c_of_match[] = {
 457         { .compatible = "sirf,prima2-i2c", },
 458         {},
 459 };
 460 MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);
 461
 462 static struct platform_driver i2c_sirfsoc_driver = {
 463         .driver = {
 464                 .name = "sirfsoc_i2c",
 465 #ifdef CONFIG_PM
 466                 .pm = &i2c_sirfsoc_pm_ops,
 467 #endif
 468                 .of_match_table = sirfsoc_i2c_of_match,
 469         },
 470         .probe = i2c_sirfsoc_probe,
 471         .remove = i2c_sirfsoc_remove,
 472 };
 473 module_platform_driver(i2c_sirfsoc_driver);
 474
 475 MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
 476 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
 477         "Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
 478 MODULE_LICENSE("GPL v2");