drivers/i2c/busses/i2c-s3c2410.c

   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005,2009 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17 */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21
  22 #include <linux/i2c.h>
  23 #include <linux/init.h>
  24 #include <linux/time.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/err.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/clk.h>
  32 #include <linux/cpufreq.h>
  33 #include <linux/slab.h>
  34 #include <linux/io.h>
  35 #include <linux/of.h>
  36 #include <linux/of_gpio.h>
  37 #include <linux/pinctrl/consumer.h>
  38 #include <linux/mfd/syscon.h>
  39 #include <linux/regmap.h>
  40
  41 #include <asm/irq.h>
  42
  43 #include <linux/platform_data/i2c-s3c2410.h>
  44
  45 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
  46
  47 #define S3C2410_IICCON                  0x00
  48 #define S3C2410_IICSTAT                 0x04
  49 #define S3C2410_IICADD                  0x08
  50 #define S3C2410_IICDS                   0x0C
  51 #define S3C2440_IICLC                   0x10
  52
  53 #define S3C2410_IICCON_ACKEN            (1 << 7)
  54 #define S3C2410_IICCON_TXDIV_16         (0 << 6)
  55 #define S3C2410_IICCON_TXDIV_512        (1 << 6)
  56 #define S3C2410_IICCON_IRQEN            (1 << 5)
  57 #define S3C2410_IICCON_IRQPEND          (1 << 4)
  58 #define S3C2410_IICCON_SCALE(x)         ((x) & 0xf)
  59 #define S3C2410_IICCON_SCALEMASK        (0xf)
  60
  61 #define S3C2410_IICSTAT_MASTER_RX       (2 << 6)
  62 #define S3C2410_IICSTAT_MASTER_TX       (3 << 6)
  63 #define S3C2410_IICSTAT_SLAVE_RX        (0 << 6)
  64 #define S3C2410_IICSTAT_SLAVE_TX        (1 << 6)
  65 #define S3C2410_IICSTAT_MODEMASK        (3 << 6)
  66
  67 #define S3C2410_IICSTAT_START           (1 << 5)
  68 #define S3C2410_IICSTAT_BUSBUSY         (1 << 5)
  69 #define S3C2410_IICSTAT_TXRXEN          (1 << 4)
  70 #define S3C2410_IICSTAT_ARBITR          (1 << 3)
  71 #define S3C2410_IICSTAT_ASSLAVE         (1 << 2)
  72 #define S3C2410_IICSTAT_ADDR0           (1 << 1)
  73 #define S3C2410_IICSTAT_LASTBIT         (1 << 0)
  74
  75 #define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
  76 #define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
  77 #define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
  78 #define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
  79 #define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
  80
  81 #define S3C2410_IICLC_FILTER_ON         (1 << 2)
  82
  83 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
  84 #define QUIRK_S3C2440           (1 << 0)
  85 #define QUIRK_HDMIPHY           (1 << 1)
  86 #define QUIRK_NO_GPIO           (1 << 2)
  87 #define QUIRK_POLL              (1 << 3)
  88
  89 /* Max time to wait for bus to become idle after a xfer (in us) */
  90 #define S3C2410_IDLE_TIMEOUT    5000
  91
  92 /* Exynos5 Sysreg offset */
  93 #define EXYNOS5_SYS_I2C_CFG     0x0234
  94
  95 /* i2c controller state */
  96 enum s3c24xx_i2c_state {
  97         STATE_IDLE,
  98         STATE_START,
  99         STATE_READ,
 100         STATE_WRITE,
 101         STATE_STOP
 102 };
 103
 104 struct s3c24xx_i2c {
 105         wait_queue_head_t       wait;
 106         kernel_ulong_t          quirks;
 107
 108         struct i2c_msg          *msg;
 109         unsigned int            msg_num;
 110         unsigned int            msg_idx;
 111         unsigned int            msg_ptr;
 112
 113         unsigned int            tx_setup;
 114         unsigned int            irq;
 115
 116         enum s3c24xx_i2c_state  state;
 117         unsigned long           clkrate;
 118
 119         void __iomem            *regs;
 120         struct clk              *clk;
 121         struct device           *dev;
 122         struct i2c_adapter      adap;
 123
 124         struct s3c2410_platform_i2c     *pdata;
 125         int                     gpios[2];
 126         struct pinctrl          *pctrl;
 127 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 128         struct notifier_block   freq_transition;
 129 #endif
 130         struct regmap           *sysreg;
 131         unsigned int            sys_i2c_cfg;
 132 };
 133
 134 static const struct platform_device_id s3c24xx_driver_ids[] = {
 135         {
 136                 .name           = "s3c2410-i2c",
 137                 .driver_data    = 0,
 138         }, {
 139                 .name           = "s3c2440-i2c",
 140                 .driver_data    = QUIRK_S3C2440,
 141         }, {
 142                 .name           = "s3c2440-hdmiphy-i2c",
 143                 .driver_data    = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
 144         }, { },
 145 };
 146 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 147
 148 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
 149
 150 #ifdef CONFIG_OF
 151 static const struct of_device_id s3c24xx_i2c_match[] = {
 152         { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
 153         { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
 154         { .compatible = "samsung,s3c2440-hdmiphy-i2c",
 155           .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
 156         { .compatible = "samsung,exynos5-sata-phy-i2c",
 157           .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
 158         {},
 159 };
 160 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
 161 #endif
 162
 163 /*
 164  * Get controller type either from device tree or platform device variant.
 165  */
 166 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
 167 {
 168         if (pdev->dev.of_node) {
 169                 const struct of_device_id *match;
 170
 171                 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
 172                 return (kernel_ulong_t)match->data;
 173         }
 174
 175         return platform_get_device_id(pdev)->driver_data;
 176 }
 177
 178 /*
 179  * Complete the message and wake up the caller, using the given return code,
 180  * or zero to mean ok.
 181  */
 182 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 183 {
 184         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 185
 186         i2c->msg_ptr = 0;
 187         i2c->msg = NULL;
 188         i2c->msg_idx++;
 189         i2c->msg_num = 0;
 190         if (ret)
 191                 i2c->msg_idx = ret;
 192
 193         if (!(i2c->quirks & QUIRK_POLL))
 194                 wake_up(&i2c->wait);
 195 }
 196
 197 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 198 {
 199         unsigned long tmp;
 200
 201         tmp = readl(i2c->regs + S3C2410_IICCON);
 202         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 203 }
 204
 205 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 206 {
 207         unsigned long tmp;
 208
 209         tmp = readl(i2c->regs + S3C2410_IICCON);
 210         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 211 }
 212
 213 /* irq enable/disable functions */
 214 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 215 {
 216         unsigned long tmp;
 217
 218         tmp = readl(i2c->regs + S3C2410_IICCON);
 219         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 220 }
 221
 222 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 223 {
 224         unsigned long tmp;
 225
 226         tmp = readl(i2c->regs + S3C2410_IICCON);
 227         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 228 }
 229
 230 static bool is_ack(struct s3c24xx_i2c *i2c)
 231 {
 232         int tries;
 233
 234         for (tries = 50; tries; --tries) {
 235                 if (readl(i2c->regs + S3C2410_IICCON)
 236                         & S3C2410_IICCON_IRQPEND) {
 237                         if (!(readl(i2c->regs + S3C2410_IICSTAT)
 238                                 & S3C2410_IICSTAT_LASTBIT))
 239                                 return true;
 240                 }
 241                 usleep_range(1000, 2000);
 242         }
 243         dev_err(i2c->dev, "ack was not received\n");
 244         return false;
 245 }
 246
 247 /*
 248  * put the start of a message onto the bus
 249  */
 250 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 251                                       struct i2c_msg *msg)
 252 {
 253         unsigned int addr = (msg->addr & 0x7f) << 1;
 254         unsigned long stat;
 255         unsigned long iiccon;
 256
 257         stat = 0;
 258         stat |=  S3C2410_IICSTAT_TXRXEN;
 259
 260         if (msg->flags & I2C_M_RD) {
 261                 stat |= S3C2410_IICSTAT_MASTER_RX;
 262                 addr |= 1;
 263         } else
 264                 stat |= S3C2410_IICSTAT_MASTER_TX;
 265
 266         if (msg->flags & I2C_M_REV_DIR_ADDR)
 267                 addr ^= 1;
 268
 269         /* todo - check for whether ack wanted or not */
 270         s3c24xx_i2c_enable_ack(i2c);
 271
 272         iiccon = readl(i2c->regs + S3C2410_IICCON);
 273         writel(stat, i2c->regs + S3C2410_IICSTAT);
 274
 275         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 276         writeb(addr, i2c->regs + S3C2410_IICDS);
 277
 278         /*
 279          * delay here to ensure the data byte has gotten onto the bus
 280          * before the transaction is started
 281          */
 282         ndelay(i2c->tx_setup);
 283
 284         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 285         writel(iiccon, i2c->regs + S3C2410_IICCON);
 286
 287         stat |= S3C2410_IICSTAT_START;
 288         writel(stat, i2c->regs + S3C2410_IICSTAT);
 289
 290         if (i2c->quirks & QUIRK_POLL) {
 291                 while ((i2c->msg_num != 0) && is_ack(i2c)) {
 292                         i2c_s3c_irq_nextbyte(i2c, stat);
 293                         stat = readl(i2c->regs + S3C2410_IICSTAT);
 294
 295                         if (stat & S3C2410_IICSTAT_ARBITR)
 296                                 dev_err(i2c->dev, "deal with arbitration loss\n");
 297                 }
 298         }
 299 }
 300
 301 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 302 {
 303         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 304
 305         dev_dbg(i2c->dev, "STOP\n");
 306
 307         /*
 308          * The datasheet says that the STOP sequence should be:
 309          *  1) I2CSTAT.5 = 0    - Clear BUSY (or 'generate STOP')
 310          *  2) I2CCON.4 = 0     - Clear IRQPEND
 311          *  3) Wait until the stop condition takes effect.
 312          *  4*) I2CSTAT.4 = 0   - Clear TXRXEN
 313          *
 314          * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
 315          *
 316          * However, after much experimentation, it appears that:
 317          * a) normal buses automatically clear BUSY and transition from
 318          *    Master->Slave when they complete generating a STOP condition.
 319          *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
 320          *    after starting the STOP generation here.
 321          * b) HDMIPHY bus does neither, so there is no way to do step 3.
 322          *    There is no indication when this bus has finished generating
 323          *    STOP.
 324          *
 325          * In fact, we have found that as soon as the IRQPEND bit is cleared in
 326          * step 2, the HDMIPHY bus generates the STOP condition, and then
 327          * immediately starts transferring another data byte, even though the
 328          * bus is supposedly stopped.  This is presumably because the bus is
 329          * still in "Master" mode, and its BUSY bit is still set.
 330          *
 331          * To avoid these extra post-STOP transactions on HDMI phy devices, we
 332          * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
 333          * instead of first generating a proper STOP condition.  This should
 334          * float SDA & SCK terminating the transfer.  Subsequent transfers
 335          *  start with a proper START condition, and proceed normally.
 336          *
 337          * The HDMIPHY bus is an internal bus that always has exactly two
 338          * devices, the host as Master and the HDMIPHY device as the slave.
 339          * Skipping the STOP condition has been tested on this bus and works.
 340          */
 341         if (i2c->quirks & QUIRK_HDMIPHY) {
 342                 /* Stop driving the I2C pins */
 343                 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
 344         } else {
 345                 /* stop the transfer */
 346                 iicstat &= ~S3C2410_IICSTAT_START;
 347         }
 348         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 349
 350         i2c->state = STATE_STOP;
 351
 352         s3c24xx_i2c_master_complete(i2c, ret);
 353         s3c24xx_i2c_disable_irq(i2c);
 354 }
 355
 356 /*
 357  * helper functions to determine the current state in the set of
 358  * messages we are sending
 359  */
 360
 361 /*
 362  * returns TRUE if the current message is the last in the set
 363  */
 364 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 365 {
 366         return i2c->msg_idx >= (i2c->msg_num - 1);
 367 }
 368
 369 /*
 370  * returns TRUE if we this is the last byte in the current message
 371  */
 372 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 373 {
 374         /*
 375          * msg->len is always 1 for the first byte of smbus block read.
 376          * Actual length will be read from slave. More bytes will be
 377          * read according to the length then.
 378          */
 379         if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 380                 return 0;
 381
 382         return i2c->msg_ptr == i2c->msg->len-1;
 383 }
 384
 385 /*
 386  * returns TRUE if we reached the end of the current message
 387  */
 388 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 389 {
 390         return i2c->msg_ptr >= i2c->msg->len;
 391 }
 392
 393 /*
 394  * process an interrupt and work out what to do
 395  */
 396 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 397 {
 398         unsigned long tmp;
 399         unsigned char byte;
 400         int ret = 0;
 401
 402         switch (i2c->state) {
 403
 404         case STATE_IDLE:
 405                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 406                 goto out;
 407
 408         case STATE_STOP:
 409                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 410                 s3c24xx_i2c_disable_irq(i2c);
 411                 goto out_ack;
 412
 413         case STATE_START:
 414                 /*
 415                  * last thing we did was send a start condition on the
 416                  * bus, or started a new i2c message
 417                  */
 418                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 419                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 420                         /* ack was not received... */
 421                         dev_dbg(i2c->dev, "ack was not received\n");
 422                         s3c24xx_i2c_stop(i2c, -ENXIO);
 423                         goto out_ack;
 424                 }
 425
 426                 if (i2c->msg->flags & I2C_M_RD)
 427                         i2c->state = STATE_READ;
 428                 else
 429                         i2c->state = STATE_WRITE;
 430
 431                 /*
 432                  * Terminate the transfer if there is nothing to do
 433                  * as this is used by the i2c probe to find devices.
 434                  */
 435                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 436                         s3c24xx_i2c_stop(i2c, 0);
 437                         goto out_ack;
 438                 }
 439
 440                 if (i2c->state == STATE_READ)
 441                         goto prepare_read;
 442
 443                 /*
 444                  * fall through to the write state, as we will need to
 445                  * send a byte as well
 446                  */
 447
 448         case STATE_WRITE:
 449                 /*
 450                  * we are writing data to the device... check for the
 451                  * end of the message, and if so, work out what to do
 452                  */
 453                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 454                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 455                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 456
 457                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 458                                 goto out_ack;
 459                         }
 460                 }
 461
 462  retry_write:
 463
 464                 if (!is_msgend(i2c)) {
 465                         byte = i2c->msg->buf[i2c->msg_ptr++];
 466                         writeb(byte, i2c->regs + S3C2410_IICDS);
 467
 468                         /*
 469                          * delay after writing the byte to allow the
 470                          * data setup time on the bus, as writing the
 471                          * data to the register causes the first bit
 472                          * to appear on SDA, and SCL will change as
 473                          * soon as the interrupt is acknowledged
 474                          */
 475                         ndelay(i2c->tx_setup);
 476
 477                 } else if (!is_lastmsg(i2c)) {
 478                         /* we need to go to the next i2c message */
 479
 480                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 481
 482                         i2c->msg_ptr = 0;
 483                         i2c->msg_idx++;
 484                         i2c->msg++;
 485
 486                         /* check to see if we need to do another message */
 487                         if (i2c->msg->flags & I2C_M_NOSTART) {
 488
 489                                 if (i2c->msg->flags & I2C_M_RD) {
 490                                         /*
 491                                          * cannot do this, the controller
 492                                          * forces us to send a new START
 493                                          * when we change direction
 494                                          */
 495                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 496                                 }
 497
 498                                 goto retry_write;
 499                         } else {
 500                                 /* send the new start */
 501                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 502                                 i2c->state = STATE_START;
 503                         }
 504
 505                 } else {
 506                         /* send stop */
 507                         s3c24xx_i2c_stop(i2c, 0);
 508                 }
 509                 break;
 510
 511         case STATE_READ:
 512                 /*
 513                  * we have a byte of data in the data register, do
 514                  * something with it, and then work out whether we are
 515                  * going to do any more read/write
 516                  */
 517                 byte = readb(i2c->regs + S3C2410_IICDS);
 518                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 519
 520                 /* Add actual length to read for smbus block read */
 521                 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 522                         i2c->msg->len += byte;
 523  prepare_read:
 524                 if (is_msglast(i2c)) {
 525                         /* last byte of buffer */
 526
 527                         if (is_lastmsg(i2c))
 528                                 s3c24xx_i2c_disable_ack(i2c);
 529
 530                 } else if (is_msgend(i2c)) {
 531                         /*
 532                          * ok, we've read the entire buffer, see if there
 533                          * is anything else we need to do
 534                          */
 535                         if (is_lastmsg(i2c)) {
 536                                 /* last message, send stop and complete */
 537                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 538
 539                                 s3c24xx_i2c_stop(i2c, 0);
 540                         } else {
 541                                 /* go to the next transfer */
 542                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 543
 544                                 i2c->msg_ptr = 0;
 545                                 i2c->msg_idx++;
 546                                 i2c->msg++;
 547                         }
 548                 }
 549
 550                 break;
 551         }
 552
 553         /* acknowlegde the IRQ and get back on with the work */
 554
 555  out_ack:
 556         tmp = readl(i2c->regs + S3C2410_IICCON);
 557         tmp &= ~S3C2410_IICCON_IRQPEND;
 558         writel(tmp, i2c->regs + S3C2410_IICCON);
 559  out:
 560         return ret;
 561 }
 562
 563 /*
 564  * top level IRQ servicing routine
 565  */
 566 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 567 {
 568         struct s3c24xx_i2c *i2c = dev_id;
 569         unsigned long status;
 570         unsigned long tmp;
 571
 572         status = readl(i2c->regs + S3C2410_IICSTAT);
 573
 574         if (status & S3C2410_IICSTAT_ARBITR) {
 575                 /* deal with arbitration loss */
 576                 dev_err(i2c->dev, "deal with arbitration loss\n");
 577         }
 578
 579         if (i2c->state == STATE_IDLE) {
 580                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 581
 582                 tmp = readl(i2c->regs + S3C2410_IICCON);
 583                 tmp &= ~S3C2410_IICCON_IRQPEND;
 584                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 585                 goto out;
 586         }
 587
 588         /*
 589          * pretty much this leaves us with the fact that we've
 590          * transmitted or received whatever byte we last sent
 591          */
 592         i2c_s3c_irq_nextbyte(i2c, status);
 593
 594  out:
 595         return IRQ_HANDLED;
 596 }
 597
 598 /*
 599  * Disable the bus so that we won't get any interrupts from now on, or try
 600  * to drive any lines. This is the default state when we don't have
 601  * anything to send/receive.
 602  *
 603  * If there is an event on the bus, or we have a pre-existing event at
 604  * kernel boot time, we may not notice the event and the I2C controller
 605  * will lock the bus with the I2C clock line low indefinitely.
 606  */
 607 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
 608 {
 609         unsigned long tmp;
 610
 611         /* Stop driving the I2C pins */
 612         tmp = readl(i2c->regs + S3C2410_IICSTAT);
 613         tmp &= ~S3C2410_IICSTAT_TXRXEN;
 614         writel(tmp, i2c->regs + S3C2410_IICSTAT);
 615
 616         /* We don't expect any interrupts now, and don't want send acks */
 617         tmp = readl(i2c->regs + S3C2410_IICCON);
 618         tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
 619                 S3C2410_IICCON_ACKEN);
 620         writel(tmp, i2c->regs + S3C2410_IICCON);
 621 }
 622
 623
 624 /*
 625  * get the i2c bus for a master transaction
 626  */
 627 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 628 {
 629         unsigned long iicstat;
 630         int timeout = 400;
 631
 632         while (timeout-- > 0) {
 633                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 634
 635                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 636                         return 0;
 637
 638                 msleep(1);
 639         }
 640
 641         return -ETIMEDOUT;
 642 }
 643
 644 /*
 645  * wait for the i2c bus to become idle.
 646  */
 647 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
 648 {
 649         unsigned long iicstat;
 650         ktime_t start, now;
 651         unsigned long delay;
 652         int spins;
 653
 654         /* ensure the stop has been through the bus */
 655
 656         dev_dbg(i2c->dev, "waiting for bus idle\n");
 657
 658         start = now = ktime_get();
 659
 660         /*
 661          * Most of the time, the bus is already idle within a few usec of the
 662          * end of a transaction.  However, really slow i2c devices can stretch
 663          * the clock, delaying STOP generation.
 664          *
 665          * On slower SoCs this typically happens within a very small number of
 666          * instructions so busy wait briefly to avoid scheduling overhead.
 667          */
 668         spins = 3;
 669         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 670         while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
 671                 cpu_relax();
 672                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 673         }
 674
 675         /*
 676          * If we do get an appreciable delay as a compromise between idle
 677          * detection latency for the normal, fast case, and system load in the
 678          * slow device case, use an exponential back off in the polling loop,
 679          * up to 1/10th of the total timeout, then continue to poll at a
 680          * constant rate up to the timeout.
 681          */
 682         delay = 1;
 683         while ((iicstat & S3C2410_IICSTAT_START) &&
 684                ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
 685                 usleep_range(delay, 2 * delay);
 686                 if (delay < S3C2410_IDLE_TIMEOUT / 10)
 687                         delay <<= 1;
 688                 now = ktime_get();
 689                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 690         }
 691
 692         if (iicstat & S3C2410_IICSTAT_START)
 693                 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
 694 }
 695
 696 /*
 697  * this starts an i2c transfer
 698  */
 699 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 700                               struct i2c_msg *msgs, int num)
 701 {
 702         unsigned long timeout;
 703         int ret;
 704
 705         ret = s3c24xx_i2c_set_master(i2c);
 706         if (ret != 0) {
 707                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 708                 ret = -EAGAIN;
 709                 goto out;
 710         }
 711
 712         i2c->msg     = msgs;
 713         i2c->msg_num = num;
 714         i2c->msg_ptr = 0;
 715         i2c->msg_idx = 0;
 716         i2c->state   = STATE_START;
 717
 718         s3c24xx_i2c_enable_irq(i2c);
 719         s3c24xx_i2c_message_start(i2c, msgs);
 720
 721         if (i2c->quirks & QUIRK_POLL) {
 722                 ret = i2c->msg_idx;
 723
 724                 if (ret != num)
 725                         dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 726
 727                 goto out;
 728         }
 729
 730         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 731
 732         ret = i2c->msg_idx;
 733
 734         /*
 735          * Having these next two as dev_err() makes life very
 736          * noisy when doing an i2cdetect
 737          */
 738         if (timeout == 0)
 739                 dev_dbg(i2c->dev, "timeout\n");
 740         else if (ret != num)
 741                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 742
 743         /* For QUIRK_HDMIPHY, bus is already disabled */
 744         if (i2c->quirks & QUIRK_HDMIPHY)
 745                 goto out;
 746
 747         s3c24xx_i2c_wait_idle(i2c);
 748
 749         s3c24xx_i2c_disable_bus(i2c);
 750
 751  out:
 752         i2c->state = STATE_IDLE;
 753
 754         return ret;
 755 }
 756
 757 /*
 758  * first port of call from the i2c bus code when an message needs
 759  * transferring across the i2c bus.
 760  */
 761 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 762                         struct i2c_msg *msgs, int num)
 763 {
 764         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 765         int retry;
 766         int ret;
 767
 768         ret = clk_enable(i2c->clk);
 769         if (ret)
 770                 return ret;
 771
 772         for (retry = 0; retry < adap->retries; retry++) {
 773
 774                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 775
 776                 if (ret != -EAGAIN) {
 777                         clk_disable(i2c->clk);
 778                         return ret;
 779                 }
 780
 781                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 782
 783                 udelay(100);
 784         }
 785
 786         clk_disable(i2c->clk);
 787         return -EREMOTEIO;
 788 }
 789
 790 /* declare our i2c functionality */
 791 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 792 {
 793         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
 794                 I2C_FUNC_PROTOCOL_MANGLING;
 795 }
 796
 797 /* i2c bus registration info */
 798 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 799         .master_xfer            = s3c24xx_i2c_xfer,
 800         .functionality          = s3c24xx_i2c_func,
 801 };
 802
 803 /*
 804  * return the divisor settings for a given frequency
 805  */
 806 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 807                                    unsigned int *div1, unsigned int *divs)
 808 {
 809         unsigned int calc_divs = clkin / wanted;
 810         unsigned int calc_div1;
 811
 812         if (calc_divs > (16*16))
 813                 calc_div1 = 512;
 814         else
 815                 calc_div1 = 16;
 816
 817         calc_divs += calc_div1-1;
 818         calc_divs /= calc_div1;
 819
 820         if (calc_divs == 0)
 821                 calc_divs = 1;
 822         if (calc_divs > 17)
 823                 calc_divs = 17;
 824
 825         *divs = calc_divs;
 826         *div1 = calc_div1;
 827
 828         return clkin / (calc_divs * calc_div1);
 829 }
 830
 831 /*
 832  * work out a divisor for the user requested frequency setting,
 833  * either by the requested frequency, or scanning the acceptable
 834  * range of frequencies until something is found
 835  */
 836 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 837 {
 838         struct s3c2410_platform_i2c *pdata = i2c->pdata;
 839         unsigned long clkin = clk_get_rate(i2c->clk);
 840         unsigned int divs, div1;
 841         unsigned long target_frequency;
 842         u32 iiccon;
 843         int freq;
 844
 845         i2c->clkrate = clkin;
 846         clkin /= 1000;          /* clkin now in KHz */
 847
 848         dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
 849
 850         target_frequency = pdata->frequency ? pdata->frequency : 100000;
 851
 852         target_frequency /= 1000; /* Target frequency now in KHz */
 853
 854         freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
 855
 856         if (freq > target_frequency) {
 857                 dev_err(i2c->dev,
 858                         "Unable to achieve desired frequency %luKHz."   \
 859                         " Lowest achievable %dKHz\n", target_frequency, freq);
 860                 return -EINVAL;
 861         }
 862
 863         *got = freq;
 864
 865         iiccon = readl(i2c->regs + S3C2410_IICCON);
 866         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 867         iiccon |= (divs-1);
 868
 869         if (div1 == 512)
 870                 iiccon |= S3C2410_IICCON_TXDIV_512;
 871
 872         if (i2c->quirks & QUIRK_POLL)
 873                 iiccon |= S3C2410_IICCON_SCALE(2);
 874
 875         writel(iiccon, i2c->regs + S3C2410_IICCON);
 876
 877         if (i2c->quirks & QUIRK_S3C2440) {
 878                 unsigned long sda_delay;
 879
 880                 if (pdata->sda_delay) {
 881                         sda_delay = clkin * pdata->sda_delay;
 882                         sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
 883                         sda_delay = DIV_ROUND_UP(sda_delay, 5);
 884                         if (sda_delay > 3)
 885                                 sda_delay = 3;
 886                         sda_delay |= S3C2410_IICLC_FILTER_ON;
 887                 } else
 888                         sda_delay = 0;
 889
 890                 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
 891                 writel(sda_delay, i2c->regs + S3C2440_IICLC);
 892         }
 893
 894         return 0;
 895 }
 896
 897 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 898
 899 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 900
 901 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 902                                           unsigned long val, void *data)
 903 {
 904         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 905         unsigned int got;
 906         int delta_f;
 907         int ret;
 908
 909         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 910
 911         /* if we're post-change and the input clock has slowed down
 912          * or at pre-change and the clock is about to speed up, then
 913          * adjust our clock rate. <0 is slow, >0 speedup.
 914          */
 915
 916         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 917             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 918                 i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
 919                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 920                 i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
 921
 922                 if (ret < 0)
 923                         dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
 924                 else
 925                         dev_info(i2c->dev, "setting freq %d\n", got);
 926         }
 927
 928         return 0;
 929 }
 930
 931 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 932 {
 933         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 934
 935         return cpufreq_register_notifier(&i2c->freq_transition,
 936                                          CPUFREQ_TRANSITION_NOTIFIER);
 937 }
 938
 939 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 940 {
 941         cpufreq_unregister_notifier(&i2c->freq_transition,
 942                                     CPUFREQ_TRANSITION_NOTIFIER);
 943 }
 944
 945 #else
 946 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 947 {
 948         return 0;
 949 }
 950
 951 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 952 {
 953 }
 954 #endif
 955
 956 #ifdef CONFIG_OF
 957 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 958 {
 959         int idx, gpio, ret;
 960
 961         if (i2c->quirks & QUIRK_NO_GPIO)
 962                 return 0;
 963
 964         for (idx = 0; idx < 2; idx++) {
 965                 gpio = of_get_gpio(i2c->dev->of_node, idx);
 966                 if (!gpio_is_valid(gpio)) {
 967                         dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
 968                         goto free_gpio;
 969                 }
 970                 i2c->gpios[idx] = gpio;
 971
 972                 ret = gpio_request(gpio, "i2c-bus");
 973                 if (ret) {
 974                         dev_err(i2c->dev, "gpio [%d] request failed (%d)\n",
 975                                 gpio, ret);
 976                         goto free_gpio;
 977                 }
 978         }
 979         return 0;
 980
 981 free_gpio:
 982         while (--idx >= 0)
 983                 gpio_free(i2c->gpios[idx]);
 984         return -EINVAL;
 985 }
 986
 987 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
 988 {
 989         unsigned int idx;
 990
 991         if (i2c->quirks & QUIRK_NO_GPIO)
 992                 return;
 993
 994         for (idx = 0; idx < 2; idx++)
 995                 gpio_free(i2c->gpios[idx]);
 996 }
 997 #else
 998 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 999 {
1000         return 0;
1001 }
1002
1003 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
1004 {
1005 }
1006 #endif
1007
1008 /*
1009  * initialise the controller, set the IO lines and frequency
1010  */
1011 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
1012 {
1013         struct s3c2410_platform_i2c *pdata;
1014         unsigned int freq;
1015
1016         /* get the plafrom data */
1017
1018         pdata = i2c->pdata;
1019
1020         /* write slave address */
1021
1022         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
1023
1024         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
1025
1026         writel(0, i2c->regs + S3C2410_IICCON);
1027         writel(0, i2c->regs + S3C2410_IICSTAT);
1028
1029         /* we need to work out the divisors for the clock... */
1030
1031         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
1032                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
1033                 return -EINVAL;
1034         }
1035
1036         /* todo - check that the i2c lines aren't being dragged anywhere */
1037
1038         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1039         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1040                 readl(i2c->regs + S3C2410_IICCON));
1041
1042         return 0;
1043 }
1044
1045 #ifdef CONFIG_OF
1046 /*
1047  * Parse the device tree node and retreive the platform data.
1048  */
1049 static void
1050 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1051 {
1052         struct s3c2410_platform_i2c *pdata = i2c->pdata;
1053         int id;
1054
1055         if (!np)
1056                 return;
1057
1058         pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1059         of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1060         of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1061         of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1062                                 (u32 *)&pdata->frequency);
1063         /*
1064          * Exynos5's legacy i2c controller and new high speed i2c
1065          * controller have muxed interrupt sources. By default the
1066          * interrupts for 4-channel HS-I2C controller are enabled.
1067          * If nodes for first four channels of legacy i2c controller
1068          * are available then re-configure the interrupts via the
1069          * system register.
1070          */
1071         id = of_alias_get_id(np, "i2c");
1072         i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1073                         "samsung,sysreg-phandle");
1074         if (IS_ERR(i2c->sysreg))
1075                 return;
1076
1077         regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1078 }
1079 #else
1080 static void
1081 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
1082 #endif
1083
1084 static int s3c24xx_i2c_probe(struct platform_device *pdev)
1085 {
1086         struct s3c24xx_i2c *i2c;
1087         struct s3c2410_platform_i2c *pdata = NULL;
1088         struct resource *res;
1089         int ret;
1090
1091         if (!pdev->dev.of_node) {
1092                 pdata = dev_get_platdata(&pdev->dev);
1093                 if (!pdata) {
1094                         dev_err(&pdev->dev, "no platform data\n");
1095                         return -EINVAL;
1096                 }
1097         }
1098
1099         i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1100         if (!i2c)
1101                 return -ENOMEM;
1102
1103         i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1104         if (!i2c->pdata)
1105                 return -ENOMEM;
1106
1107         i2c->quirks = s3c24xx_get_device_quirks(pdev);
1108         i2c->sysreg = ERR_PTR(-ENOENT);
1109         if (pdata)
1110                 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1111         else
1112                 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1113
1114         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1115         i2c->adap.owner = THIS_MODULE;
1116         i2c->adap.algo = &s3c24xx_i2c_algorithm;
1117         i2c->adap.retries = 2;
1118         i2c->adap.class = I2C_CLASS_DEPRECATED;
1119         i2c->tx_setup = 50;
1120
1121         init_waitqueue_head(&i2c->wait);
1122
1123         /* find the clock and enable it */
1124         i2c->dev = &pdev->dev;
1125         i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1126         if (IS_ERR(i2c->clk)) {
1127                 dev_err(&pdev->dev, "cannot get clock\n");
1128                 return -ENOENT;
1129         }
1130
1131         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1132
1133         /* map the registers */
1134         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1135         i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1136
1137         if (IS_ERR(i2c->regs))
1138                 return PTR_ERR(i2c->regs);
1139
1140         dev_dbg(&pdev->dev, "registers %p (%p)\n",
1141                 i2c->regs, res);
1142
1143         /* setup info block for the i2c core */
1144         i2c->adap.algo_data = i2c;
1145         i2c->adap.dev.parent = &pdev->dev;
1146         i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1147
1148         /* inititalise the i2c gpio lines */
1149         if (i2c->pdata->cfg_gpio)
1150                 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1151         else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1152                 return -EINVAL;
1153
1154         /* initialise the i2c controller */
1155         ret = clk_prepare_enable(i2c->clk);
1156         if (ret) {
1157                 dev_err(&pdev->dev, "I2C clock enable failed\n");
1158                 return ret;
1159         }
1160
1161         ret = s3c24xx_i2c_init(i2c);
1162         clk_disable(i2c->clk);
1163         if (ret != 0) {
1164                 dev_err(&pdev->dev, "I2C controller init failed\n");
1165                 clk_unprepare(i2c->clk);
1166                 return ret;
1167         }
1168
1169         /*
1170          * find the IRQ for this unit (note, this relies on the init call to
1171          * ensure no current IRQs pending
1172          */
1173         if (!(i2c->quirks & QUIRK_POLL)) {
1174                 i2c->irq = ret = platform_get_irq(pdev, 0);
1175                 if (ret <= 0) {
1176                         dev_err(&pdev->dev, "cannot find IRQ\n");
1177                         clk_unprepare(i2c->clk);
1178                         return ret;
1179                 }
1180
1181                 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1182                                        0, dev_name(&pdev->dev), i2c);
1183                 if (ret != 0) {
1184                         dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1185                         clk_unprepare(i2c->clk);
1186                         return ret;
1187                 }
1188         }
1189
1190         ret = s3c24xx_i2c_register_cpufreq(i2c);
1191         if (ret < 0) {
1192                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1193                 clk_unprepare(i2c->clk);
1194                 return ret;
1195         }
1196
1197         /*
1198          * Note, previous versions of the driver used i2c_add_adapter()
1199          * to add the bus at any number. We now pass the bus number via
1200          * the platform data, so if unset it will now default to always
1201          * being bus 0.
1202          */
1203         i2c->adap.nr = i2c->pdata->bus_num;
1204         i2c->adap.dev.of_node = pdev->dev.of_node;
1205
1206         platform_set_drvdata(pdev, i2c);
1207
1208         pm_runtime_enable(&pdev->dev);
1209
1210         ret = i2c_add_numbered_adapter(&i2c->adap);
1211         if (ret < 0) {
1212                 pm_runtime_disable(&pdev->dev);
1213                 s3c24xx_i2c_deregister_cpufreq(i2c);
1214                 clk_unprepare(i2c->clk);
1215                 return ret;
1216         }
1217
1218         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1219         return 0;
1220 }
1221
1222 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1223 {
1224         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1225
1226         clk_unprepare(i2c->clk);
1227
1228         pm_runtime_disable(&pdev->dev);
1229
1230         s3c24xx_i2c_deregister_cpufreq(i2c);
1231
1232         i2c_del_adapter(&i2c->adap);
1233
1234         if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1235                 s3c24xx_i2c_dt_gpio_free(i2c);
1236
1237         return 0;
1238 }
1239
1240 #ifdef CONFIG_PM_SLEEP
1241 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1242 {
1243         struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1244
1245         i2c_mark_adapter_suspended(&i2c->adap);
1246
1247         if (!IS_ERR(i2c->sysreg))
1248                 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1249
1250         return 0;
1251 }
1252
1253 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1254 {
1255         struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1256         int ret;
1257
1258         if (!IS_ERR(i2c->sysreg))
1259                 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1260
1261         ret = clk_enable(i2c->clk);
1262         if (ret)
1263                 return ret;
1264         s3c24xx_i2c_init(i2c);
1265         clk_disable(i2c->clk);
1266         i2c_mark_adapter_resumed(&i2c->adap);
1267
1268         return 0;
1269 }
1270 #endif
1271
1272 #ifdef CONFIG_PM
1273 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1274         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1275                                       s3c24xx_i2c_resume_noirq)
1276 };
1277
1278 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1279 #else
1280 #define S3C24XX_DEV_PM_OPS NULL
1281 #endif
1282
1283 static struct platform_driver s3c24xx_i2c_driver = {
1284         .probe          = s3c24xx_i2c_probe,
1285         .remove         = s3c24xx_i2c_remove,
1286         .id_table       = s3c24xx_driver_ids,
1287         .driver         = {
1288                 .name   = "s3c-i2c",
1289                 .pm     = S3C24XX_DEV_PM_OPS,
1290                 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1291         },
1292 };
1293
1294 static int __init i2c_adap_s3c_init(void)
1295 {
1296         return platform_driver_register(&s3c24xx_i2c_driver);
1297 }
1298 subsys_initcall(i2c_adap_s3c_init);
1299
1300 static void __exit i2c_adap_s3c_exit(void)
1301 {
1302         platform_driver_unregister(&s3c24xx_i2c_driver);
1303 }
1304 module_exit(i2c_adap_s3c_exit);
1305
1306 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1307 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1308 MODULE_LICENSE("GPL");