treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
[sfrench/cifs-2.6.git] / drivers / i2c / busses / i2c-s3c2410.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3  *
4  * Copyright (C) 2004,2005,2009 Simtec Electronics
5  *      Ben Dooks <ben@simtec.co.uk>
6  *
7  * S3C2410 I2C Controller
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/time.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/clk.h>
23 #include <linux/cpufreq.h>
24 #include <linux/slab.h>
25 #include <linux/io.h>
26 #include <linux/of.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
31
32 #include <asm/irq.h>
33
34 #include <linux/platform_data/i2c-s3c2410.h>
35
36 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
37
38 #define S3C2410_IICCON                  0x00
39 #define S3C2410_IICSTAT                 0x04
40 #define S3C2410_IICADD                  0x08
41 #define S3C2410_IICDS                   0x0C
42 #define S3C2440_IICLC                   0x10
43
44 #define S3C2410_IICCON_ACKEN            (1 << 7)
45 #define S3C2410_IICCON_TXDIV_16         (0 << 6)
46 #define S3C2410_IICCON_TXDIV_512        (1 << 6)
47 #define S3C2410_IICCON_IRQEN            (1 << 5)
48 #define S3C2410_IICCON_IRQPEND          (1 << 4)
49 #define S3C2410_IICCON_SCALE(x)         ((x) & 0xf)
50 #define S3C2410_IICCON_SCALEMASK        (0xf)
51
52 #define S3C2410_IICSTAT_MASTER_RX       (2 << 6)
53 #define S3C2410_IICSTAT_MASTER_TX       (3 << 6)
54 #define S3C2410_IICSTAT_SLAVE_RX        (0 << 6)
55 #define S3C2410_IICSTAT_SLAVE_TX        (1 << 6)
56 #define S3C2410_IICSTAT_MODEMASK        (3 << 6)
57
58 #define S3C2410_IICSTAT_START           (1 << 5)
59 #define S3C2410_IICSTAT_BUSBUSY         (1 << 5)
60 #define S3C2410_IICSTAT_TXRXEN          (1 << 4)
61 #define S3C2410_IICSTAT_ARBITR          (1 << 3)
62 #define S3C2410_IICSTAT_ASSLAVE         (1 << 2)
63 #define S3C2410_IICSTAT_ADDR0           (1 << 1)
64 #define S3C2410_IICSTAT_LASTBIT         (1 << 0)
65
66 #define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
67 #define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
68 #define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
69 #define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
70 #define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
71
72 #define S3C2410_IICLC_FILTER_ON         (1 << 2)
73
74 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
75 #define QUIRK_S3C2440           (1 << 0)
76 #define QUIRK_HDMIPHY           (1 << 1)
77 #define QUIRK_NO_GPIO           (1 << 2)
78 #define QUIRK_POLL              (1 << 3)
79
80 /* Max time to wait for bus to become idle after a xfer (in us) */
81 #define S3C2410_IDLE_TIMEOUT    5000
82
83 /* Exynos5 Sysreg offset */
84 #define EXYNOS5_SYS_I2C_CFG     0x0234
85
86 /* i2c controller state */
87 enum s3c24xx_i2c_state {
88         STATE_IDLE,
89         STATE_START,
90         STATE_READ,
91         STATE_WRITE,
92         STATE_STOP
93 };
94
95 struct s3c24xx_i2c {
96         wait_queue_head_t       wait;
97         kernel_ulong_t          quirks;
98
99         struct i2c_msg          *msg;
100         unsigned int            msg_num;
101         unsigned int            msg_idx;
102         unsigned int            msg_ptr;
103
104         unsigned int            tx_setup;
105         unsigned int            irq;
106
107         enum s3c24xx_i2c_state  state;
108         unsigned long           clkrate;
109
110         void __iomem            *regs;
111         struct clk              *clk;
112         struct device           *dev;
113         struct i2c_adapter      adap;
114
115         struct s3c2410_platform_i2c     *pdata;
116         int                     gpios[2];
117         struct pinctrl          *pctrl;
118 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
119         struct notifier_block   freq_transition;
120 #endif
121         struct regmap           *sysreg;
122         unsigned int            sys_i2c_cfg;
123 };
124
125 static const struct platform_device_id s3c24xx_driver_ids[] = {
126         {
127                 .name           = "s3c2410-i2c",
128                 .driver_data    = 0,
129         }, {
130                 .name           = "s3c2440-i2c",
131                 .driver_data    = QUIRK_S3C2440,
132         }, {
133                 .name           = "s3c2440-hdmiphy-i2c",
134                 .driver_data    = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
135         }, { },
136 };
137 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
138
139 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
140
141 #ifdef CONFIG_OF
142 static const struct of_device_id s3c24xx_i2c_match[] = {
143         { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
144         { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
145         { .compatible = "samsung,s3c2440-hdmiphy-i2c",
146           .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
147         { .compatible = "samsung,exynos5-sata-phy-i2c",
148           .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
149         {},
150 };
151 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
152 #endif
153
154 /*
155  * Get controller type either from device tree or platform device variant.
156  */
157 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
158 {
159         if (pdev->dev.of_node) {
160                 const struct of_device_id *match;
161
162                 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
163                 return (kernel_ulong_t)match->data;
164         }
165
166         return platform_get_device_id(pdev)->driver_data;
167 }
168
169 /*
170  * Complete the message and wake up the caller, using the given return code,
171  * or zero to mean ok.
172  */
173 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
174 {
175         dev_dbg(i2c->dev, "master_complete %d\n", ret);
176
177         i2c->msg_ptr = 0;
178         i2c->msg = NULL;
179         i2c->msg_idx++;
180         i2c->msg_num = 0;
181         if (ret)
182                 i2c->msg_idx = ret;
183
184         if (!(i2c->quirks & QUIRK_POLL))
185                 wake_up(&i2c->wait);
186 }
187
188 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
189 {
190         unsigned long tmp;
191
192         tmp = readl(i2c->regs + S3C2410_IICCON);
193         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
194 }
195
196 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
197 {
198         unsigned long tmp;
199
200         tmp = readl(i2c->regs + S3C2410_IICCON);
201         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
202 }
203
204 /* irq enable/disable functions */
205 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
206 {
207         unsigned long tmp;
208
209         tmp = readl(i2c->regs + S3C2410_IICCON);
210         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
211 }
212
213 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
214 {
215         unsigned long tmp;
216
217         tmp = readl(i2c->regs + S3C2410_IICCON);
218         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
219 }
220
221 static bool is_ack(struct s3c24xx_i2c *i2c)
222 {
223         int tries;
224
225         for (tries = 50; tries; --tries) {
226                 if (readl(i2c->regs + S3C2410_IICCON)
227                         & S3C2410_IICCON_IRQPEND) {
228                         if (!(readl(i2c->regs + S3C2410_IICSTAT)
229                                 & S3C2410_IICSTAT_LASTBIT))
230                                 return true;
231                 }
232                 usleep_range(1000, 2000);
233         }
234         dev_err(i2c->dev, "ack was not received\n");
235         return false;
236 }
237
238 /*
239  * put the start of a message onto the bus
240  */
241 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
242                                       struct i2c_msg *msg)
243 {
244         unsigned int addr = (msg->addr & 0x7f) << 1;
245         unsigned long stat;
246         unsigned long iiccon;
247
248         stat = 0;
249         stat |=  S3C2410_IICSTAT_TXRXEN;
250
251         if (msg->flags & I2C_M_RD) {
252                 stat |= S3C2410_IICSTAT_MASTER_RX;
253                 addr |= 1;
254         } else
255                 stat |= S3C2410_IICSTAT_MASTER_TX;
256
257         if (msg->flags & I2C_M_REV_DIR_ADDR)
258                 addr ^= 1;
259
260         /* todo - check for whether ack wanted or not */
261         s3c24xx_i2c_enable_ack(i2c);
262
263         iiccon = readl(i2c->regs + S3C2410_IICCON);
264         writel(stat, i2c->regs + S3C2410_IICSTAT);
265
266         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
267         writeb(addr, i2c->regs + S3C2410_IICDS);
268
269         /*
270          * delay here to ensure the data byte has gotten onto the bus
271          * before the transaction is started
272          */
273         ndelay(i2c->tx_setup);
274
275         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
276         writel(iiccon, i2c->regs + S3C2410_IICCON);
277
278         stat |= S3C2410_IICSTAT_START;
279         writel(stat, i2c->regs + S3C2410_IICSTAT);
280
281         if (i2c->quirks & QUIRK_POLL) {
282                 while ((i2c->msg_num != 0) && is_ack(i2c)) {
283                         i2c_s3c_irq_nextbyte(i2c, stat);
284                         stat = readl(i2c->regs + S3C2410_IICSTAT);
285
286                         if (stat & S3C2410_IICSTAT_ARBITR)
287                                 dev_err(i2c->dev, "deal with arbitration loss\n");
288                 }
289         }
290 }
291
292 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
293 {
294         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
295
296         dev_dbg(i2c->dev, "STOP\n");
297
298         /*
299          * The datasheet says that the STOP sequence should be:
300          *  1) I2CSTAT.5 = 0    - Clear BUSY (or 'generate STOP')
301          *  2) I2CCON.4 = 0     - Clear IRQPEND
302          *  3) Wait until the stop condition takes effect.
303          *  4*) I2CSTAT.4 = 0   - Clear TXRXEN
304          *
305          * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
306          *
307          * However, after much experimentation, it appears that:
308          * a) normal buses automatically clear BUSY and transition from
309          *    Master->Slave when they complete generating a STOP condition.
310          *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
311          *    after starting the STOP generation here.
312          * b) HDMIPHY bus does neither, so there is no way to do step 3.
313          *    There is no indication when this bus has finished generating
314          *    STOP.
315          *
316          * In fact, we have found that as soon as the IRQPEND bit is cleared in
317          * step 2, the HDMIPHY bus generates the STOP condition, and then
318          * immediately starts transferring another data byte, even though the
319          * bus is supposedly stopped.  This is presumably because the bus is
320          * still in "Master" mode, and its BUSY bit is still set.
321          *
322          * To avoid these extra post-STOP transactions on HDMI phy devices, we
323          * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
324          * instead of first generating a proper STOP condition.  This should
325          * float SDA & SCK terminating the transfer.  Subsequent transfers
326          *  start with a proper START condition, and proceed normally.
327          *
328          * The HDMIPHY bus is an internal bus that always has exactly two
329          * devices, the host as Master and the HDMIPHY device as the slave.
330          * Skipping the STOP condition has been tested on this bus and works.
331          */
332         if (i2c->quirks & QUIRK_HDMIPHY) {
333                 /* Stop driving the I2C pins */
334                 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
335         } else {
336                 /* stop the transfer */
337                 iicstat &= ~S3C2410_IICSTAT_START;
338         }
339         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
340
341         i2c->state = STATE_STOP;
342
343         s3c24xx_i2c_master_complete(i2c, ret);
344         s3c24xx_i2c_disable_irq(i2c);
345 }
346
347 /*
348  * helper functions to determine the current state in the set of
349  * messages we are sending
350  */
351
352 /*
353  * returns TRUE if the current message is the last in the set
354  */
355 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
356 {
357         return i2c->msg_idx >= (i2c->msg_num - 1);
358 }
359
360 /*
361  * returns TRUE if we this is the last byte in the current message
362  */
363 static inline int is_msglast(struct s3c24xx_i2c *i2c)
364 {
365         /*
366          * msg->len is always 1 for the first byte of smbus block read.
367          * Actual length will be read from slave. More bytes will be
368          * read according to the length then.
369          */
370         if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
371                 return 0;
372
373         return i2c->msg_ptr == i2c->msg->len-1;
374 }
375
376 /*
377  * returns TRUE if we reached the end of the current message
378  */
379 static inline int is_msgend(struct s3c24xx_i2c *i2c)
380 {
381         return i2c->msg_ptr >= i2c->msg->len;
382 }
383
384 /*
385  * process an interrupt and work out what to do
386  */
387 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
388 {
389         unsigned long tmp;
390         unsigned char byte;
391         int ret = 0;
392
393         switch (i2c->state) {
394
395         case STATE_IDLE:
396                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
397                 goto out;
398
399         case STATE_STOP:
400                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
401                 s3c24xx_i2c_disable_irq(i2c);
402                 goto out_ack;
403
404         case STATE_START:
405                 /*
406                  * last thing we did was send a start condition on the
407                  * bus, or started a new i2c message
408                  */
409                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
410                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
411                         /* ack was not received... */
412                         dev_dbg(i2c->dev, "ack was not received\n");
413                         s3c24xx_i2c_stop(i2c, -ENXIO);
414                         goto out_ack;
415                 }
416
417                 if (i2c->msg->flags & I2C_M_RD)
418                         i2c->state = STATE_READ;
419                 else
420                         i2c->state = STATE_WRITE;
421
422                 /*
423                  * Terminate the transfer if there is nothing to do
424                  * as this is used by the i2c probe to find devices.
425                  */
426                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
427                         s3c24xx_i2c_stop(i2c, 0);
428                         goto out_ack;
429                 }
430
431                 if (i2c->state == STATE_READ)
432                         goto prepare_read;
433
434                 /*
435                  * fall through to the write state, as we will need to
436                  * send a byte as well
437                  */
438
439         case STATE_WRITE:
440                 /*
441                  * we are writing data to the device... check for the
442                  * end of the message, and if so, work out what to do
443                  */
444                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
445                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
446                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
447
448                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
449                                 goto out_ack;
450                         }
451                 }
452
453  retry_write:
454
455                 if (!is_msgend(i2c)) {
456                         byte = i2c->msg->buf[i2c->msg_ptr++];
457                         writeb(byte, i2c->regs + S3C2410_IICDS);
458
459                         /*
460                          * delay after writing the byte to allow the
461                          * data setup time on the bus, as writing the
462                          * data to the register causes the first bit
463                          * to appear on SDA, and SCL will change as
464                          * soon as the interrupt is acknowledged
465                          */
466                         ndelay(i2c->tx_setup);
467
468                 } else if (!is_lastmsg(i2c)) {
469                         /* we need to go to the next i2c message */
470
471                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
472
473                         i2c->msg_ptr = 0;
474                         i2c->msg_idx++;
475                         i2c->msg++;
476
477                         /* check to see if we need to do another message */
478                         if (i2c->msg->flags & I2C_M_NOSTART) {
479
480                                 if (i2c->msg->flags & I2C_M_RD) {
481                                         /*
482                                          * cannot do this, the controller
483                                          * forces us to send a new START
484                                          * when we change direction
485                                          */
486                                         s3c24xx_i2c_stop(i2c, -EINVAL);
487                                 }
488
489                                 goto retry_write;
490                         } else {
491                                 /* send the new start */
492                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
493                                 i2c->state = STATE_START;
494                         }
495
496                 } else {
497                         /* send stop */
498                         s3c24xx_i2c_stop(i2c, 0);
499                 }
500                 break;
501
502         case STATE_READ:
503                 /*
504                  * we have a byte of data in the data register, do
505                  * something with it, and then work out whether we are
506                  * going to do any more read/write
507                  */
508                 byte = readb(i2c->regs + S3C2410_IICDS);
509                 i2c->msg->buf[i2c->msg_ptr++] = byte;
510
511                 /* Add actual length to read for smbus block read */
512                 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
513                         i2c->msg->len += byte;
514  prepare_read:
515                 if (is_msglast(i2c)) {
516                         /* last byte of buffer */
517
518                         if (is_lastmsg(i2c))
519                                 s3c24xx_i2c_disable_ack(i2c);
520
521                 } else if (is_msgend(i2c)) {
522                         /*
523                          * ok, we've read the entire buffer, see if there
524                          * is anything else we need to do
525                          */
526                         if (is_lastmsg(i2c)) {
527                                 /* last message, send stop and complete */
528                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
529
530                                 s3c24xx_i2c_stop(i2c, 0);
531                         } else {
532                                 /* go to the next transfer */
533                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
534
535                                 i2c->msg_ptr = 0;
536                                 i2c->msg_idx++;
537                                 i2c->msg++;
538                         }
539                 }
540
541                 break;
542         }
543
544         /* acknowlegde the IRQ and get back on with the work */
545
546  out_ack:
547         tmp = readl(i2c->regs + S3C2410_IICCON);
548         tmp &= ~S3C2410_IICCON_IRQPEND;
549         writel(tmp, i2c->regs + S3C2410_IICCON);
550  out:
551         return ret;
552 }
553
554 /*
555  * top level IRQ servicing routine
556  */
557 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
558 {
559         struct s3c24xx_i2c *i2c = dev_id;
560         unsigned long status;
561         unsigned long tmp;
562
563         status = readl(i2c->regs + S3C2410_IICSTAT);
564
565         if (status & S3C2410_IICSTAT_ARBITR) {
566                 /* deal with arbitration loss */
567                 dev_err(i2c->dev, "deal with arbitration loss\n");
568         }
569
570         if (i2c->state == STATE_IDLE) {
571                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
572
573                 tmp = readl(i2c->regs + S3C2410_IICCON);
574                 tmp &= ~S3C2410_IICCON_IRQPEND;
575                 writel(tmp, i2c->regs +  S3C2410_IICCON);
576                 goto out;
577         }
578
579         /*
580          * pretty much this leaves us with the fact that we've
581          * transmitted or received whatever byte we last sent
582          */
583         i2c_s3c_irq_nextbyte(i2c, status);
584
585  out:
586         return IRQ_HANDLED;
587 }
588
589 /*
590  * Disable the bus so that we won't get any interrupts from now on, or try
591  * to drive any lines. This is the default state when we don't have
592  * anything to send/receive.
593  *
594  * If there is an event on the bus, or we have a pre-existing event at
595  * kernel boot time, we may not notice the event and the I2C controller
596  * will lock the bus with the I2C clock line low indefinitely.
597  */
598 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
599 {
600         unsigned long tmp;
601
602         /* Stop driving the I2C pins */
603         tmp = readl(i2c->regs + S3C2410_IICSTAT);
604         tmp &= ~S3C2410_IICSTAT_TXRXEN;
605         writel(tmp, i2c->regs + S3C2410_IICSTAT);
606
607         /* We don't expect any interrupts now, and don't want send acks */
608         tmp = readl(i2c->regs + S3C2410_IICCON);
609         tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
610                 S3C2410_IICCON_ACKEN);
611         writel(tmp, i2c->regs + S3C2410_IICCON);
612 }
613
614
615 /*
616  * get the i2c bus for a master transaction
617  */
618 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
619 {
620         unsigned long iicstat;
621         int timeout = 400;
622
623         while (timeout-- > 0) {
624                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
625
626                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
627                         return 0;
628
629                 msleep(1);
630         }
631
632         return -ETIMEDOUT;
633 }
634
635 /*
636  * wait for the i2c bus to become idle.
637  */
638 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
639 {
640         unsigned long iicstat;
641         ktime_t start, now;
642         unsigned long delay;
643         int spins;
644
645         /* ensure the stop has been through the bus */
646
647         dev_dbg(i2c->dev, "waiting for bus idle\n");
648
649         start = now = ktime_get();
650
651         /*
652          * Most of the time, the bus is already idle within a few usec of the
653          * end of a transaction.  However, really slow i2c devices can stretch
654          * the clock, delaying STOP generation.
655          *
656          * On slower SoCs this typically happens within a very small number of
657          * instructions so busy wait briefly to avoid scheduling overhead.
658          */
659         spins = 3;
660         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
661         while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
662                 cpu_relax();
663                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
664         }
665
666         /*
667          * If we do get an appreciable delay as a compromise between idle
668          * detection latency for the normal, fast case, and system load in the
669          * slow device case, use an exponential back off in the polling loop,
670          * up to 1/10th of the total timeout, then continue to poll at a
671          * constant rate up to the timeout.
672          */
673         delay = 1;
674         while ((iicstat & S3C2410_IICSTAT_START) &&
675                ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
676                 usleep_range(delay, 2 * delay);
677                 if (delay < S3C2410_IDLE_TIMEOUT / 10)
678                         delay <<= 1;
679                 now = ktime_get();
680                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
681         }
682
683         if (iicstat & S3C2410_IICSTAT_START)
684                 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
685 }
686
687 /*
688  * this starts an i2c transfer
689  */
690 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
691                               struct i2c_msg *msgs, int num)
692 {
693         unsigned long timeout;
694         int ret;
695
696         ret = s3c24xx_i2c_set_master(i2c);
697         if (ret != 0) {
698                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
699                 ret = -EAGAIN;
700                 goto out;
701         }
702
703         i2c->msg     = msgs;
704         i2c->msg_num = num;
705         i2c->msg_ptr = 0;
706         i2c->msg_idx = 0;
707         i2c->state   = STATE_START;
708
709         s3c24xx_i2c_enable_irq(i2c);
710         s3c24xx_i2c_message_start(i2c, msgs);
711
712         if (i2c->quirks & QUIRK_POLL) {
713                 ret = i2c->msg_idx;
714
715                 if (ret != num)
716                         dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
717
718                 goto out;
719         }
720
721         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
722
723         ret = i2c->msg_idx;
724
725         /*
726          * Having these next two as dev_err() makes life very
727          * noisy when doing an i2cdetect
728          */
729         if (timeout == 0)
730                 dev_dbg(i2c->dev, "timeout\n");
731         else if (ret != num)
732                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
733
734         /* For QUIRK_HDMIPHY, bus is already disabled */
735         if (i2c->quirks & QUIRK_HDMIPHY)
736                 goto out;
737
738         s3c24xx_i2c_wait_idle(i2c);
739
740         s3c24xx_i2c_disable_bus(i2c);
741
742  out:
743         i2c->state = STATE_IDLE;
744
745         return ret;
746 }
747
748 /*
749  * first port of call from the i2c bus code when an message needs
750  * transferring across the i2c bus.
751  */
752 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
753                         struct i2c_msg *msgs, int num)
754 {
755         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
756         int retry;
757         int ret;
758
759         ret = clk_enable(i2c->clk);
760         if (ret)
761                 return ret;
762
763         for (retry = 0; retry < adap->retries; retry++) {
764
765                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
766
767                 if (ret != -EAGAIN) {
768                         clk_disable(i2c->clk);
769                         return ret;
770                 }
771
772                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
773
774                 udelay(100);
775         }
776
777         clk_disable(i2c->clk);
778         return -EREMOTEIO;
779 }
780
781 /* declare our i2c functionality */
782 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
783 {
784         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
785                 I2C_FUNC_PROTOCOL_MANGLING;
786 }
787
788 /* i2c bus registration info */
789 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
790         .master_xfer            = s3c24xx_i2c_xfer,
791         .functionality          = s3c24xx_i2c_func,
792 };
793
794 /*
795  * return the divisor settings for a given frequency
796  */
797 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
798                                    unsigned int *div1, unsigned int *divs)
799 {
800         unsigned int calc_divs = clkin / wanted;
801         unsigned int calc_div1;
802
803         if (calc_divs > (16*16))
804                 calc_div1 = 512;
805         else
806                 calc_div1 = 16;
807
808         calc_divs += calc_div1-1;
809         calc_divs /= calc_div1;
810
811         if (calc_divs == 0)
812                 calc_divs = 1;
813         if (calc_divs > 17)
814                 calc_divs = 17;
815
816         *divs = calc_divs;
817         *div1 = calc_div1;
818
819         return clkin / (calc_divs * calc_div1);
820 }
821
822 /*
823  * work out a divisor for the user requested frequency setting,
824  * either by the requested frequency, or scanning the acceptable
825  * range of frequencies until something is found
826  */
827 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
828 {
829         struct s3c2410_platform_i2c *pdata = i2c->pdata;
830         unsigned long clkin = clk_get_rate(i2c->clk);
831         unsigned int divs, div1;
832         unsigned long target_frequency;
833         u32 iiccon;
834         int freq;
835
836         i2c->clkrate = clkin;
837         clkin /= 1000;          /* clkin now in KHz */
838
839         dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
840
841         target_frequency = pdata->frequency ? pdata->frequency : 100000;
842
843         target_frequency /= 1000; /* Target frequency now in KHz */
844
845         freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
846
847         if (freq > target_frequency) {
848                 dev_err(i2c->dev,
849                         "Unable to achieve desired frequency %luKHz."   \
850                         " Lowest achievable %dKHz\n", target_frequency, freq);
851                 return -EINVAL;
852         }
853
854         *got = freq;
855
856         iiccon = readl(i2c->regs + S3C2410_IICCON);
857         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
858         iiccon |= (divs-1);
859
860         if (div1 == 512)
861                 iiccon |= S3C2410_IICCON_TXDIV_512;
862
863         if (i2c->quirks & QUIRK_POLL)
864                 iiccon |= S3C2410_IICCON_SCALE(2);
865
866         writel(iiccon, i2c->regs + S3C2410_IICCON);
867
868         if (i2c->quirks & QUIRK_S3C2440) {
869                 unsigned long sda_delay;
870
871                 if (pdata->sda_delay) {
872                         sda_delay = clkin * pdata->sda_delay;
873                         sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
874                         sda_delay = DIV_ROUND_UP(sda_delay, 5);
875                         if (sda_delay > 3)
876                                 sda_delay = 3;
877                         sda_delay |= S3C2410_IICLC_FILTER_ON;
878                 } else
879                         sda_delay = 0;
880
881                 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
882                 writel(sda_delay, i2c->regs + S3C2440_IICLC);
883         }
884
885         return 0;
886 }
887
888 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
889
890 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
891
892 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
893                                           unsigned long val, void *data)
894 {
895         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
896         unsigned int got;
897         int delta_f;
898         int ret;
899
900         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
901
902         /* if we're post-change and the input clock has slowed down
903          * or at pre-change and the clock is about to speed up, then
904          * adjust our clock rate. <0 is slow, >0 speedup.
905          */
906
907         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
908             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
909                 i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
910                 ret = s3c24xx_i2c_clockrate(i2c, &got);
911                 i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
912
913                 if (ret < 0)
914                         dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
915                 else
916                         dev_info(i2c->dev, "setting freq %d\n", got);
917         }
918
919         return 0;
920 }
921
922 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
923 {
924         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
925
926         return cpufreq_register_notifier(&i2c->freq_transition,
927                                          CPUFREQ_TRANSITION_NOTIFIER);
928 }
929
930 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
931 {
932         cpufreq_unregister_notifier(&i2c->freq_transition,
933                                     CPUFREQ_TRANSITION_NOTIFIER);
934 }
935
936 #else
937 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
938 {
939         return 0;
940 }
941
942 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
943 {
944 }
945 #endif
946
947 #ifdef CONFIG_OF
948 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
949 {
950         int idx, gpio, ret;
951
952         if (i2c->quirks & QUIRK_NO_GPIO)
953                 return 0;
954
955         for (idx = 0; idx < 2; idx++) {
956                 gpio = of_get_gpio(i2c->dev->of_node, idx);
957                 if (!gpio_is_valid(gpio)) {
958                         dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
959                         goto free_gpio;
960                 }
961                 i2c->gpios[idx] = gpio;
962
963                 ret = gpio_request(gpio, "i2c-bus");
964                 if (ret) {
965                         dev_err(i2c->dev, "gpio [%d] request failed (%d)\n",
966                                 gpio, ret);
967                         goto free_gpio;
968                 }
969         }
970         return 0;
971
972 free_gpio:
973         while (--idx >= 0)
974                 gpio_free(i2c->gpios[idx]);
975         return -EINVAL;
976 }
977
978 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
979 {
980         unsigned int idx;
981
982         if (i2c->quirks & QUIRK_NO_GPIO)
983                 return;
984
985         for (idx = 0; idx < 2; idx++)
986                 gpio_free(i2c->gpios[idx]);
987 }
988 #else
989 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
990 {
991         return 0;
992 }
993
994 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
995 {
996 }
997 #endif
998
999 /*
1000  * initialise the controller, set the IO lines and frequency
1001  */
1002 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
1003 {
1004         struct s3c2410_platform_i2c *pdata;
1005         unsigned int freq;
1006
1007         /* get the plafrom data */
1008
1009         pdata = i2c->pdata;
1010
1011         /* write slave address */
1012
1013         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
1014
1015         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
1016
1017         writel(0, i2c->regs + S3C2410_IICCON);
1018         writel(0, i2c->regs + S3C2410_IICSTAT);
1019
1020         /* we need to work out the divisors for the clock... */
1021
1022         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
1023                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
1024                 return -EINVAL;
1025         }
1026
1027         /* todo - check that the i2c lines aren't being dragged anywhere */
1028
1029         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1030         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1031                 readl(i2c->regs + S3C2410_IICCON));
1032
1033         return 0;
1034 }
1035
1036 #ifdef CONFIG_OF
1037 /*
1038  * Parse the device tree node and retreive the platform data.
1039  */
1040 static void
1041 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1042 {
1043         struct s3c2410_platform_i2c *pdata = i2c->pdata;
1044         int id;
1045
1046         if (!np)
1047                 return;
1048
1049         pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1050         of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1051         of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1052         of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1053                                 (u32 *)&pdata->frequency);
1054         /*
1055          * Exynos5's legacy i2c controller and new high speed i2c
1056          * controller have muxed interrupt sources. By default the
1057          * interrupts for 4-channel HS-I2C controller are enabled.
1058          * If nodes for first four channels of legacy i2c controller
1059          * are available then re-configure the interrupts via the
1060          * system register.
1061          */
1062         id = of_alias_get_id(np, "i2c");
1063         i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1064                         "samsung,sysreg-phandle");
1065         if (IS_ERR(i2c->sysreg))
1066                 return;
1067
1068         regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1069 }
1070 #else
1071 static void
1072 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
1073 #endif
1074
1075 static int s3c24xx_i2c_probe(struct platform_device *pdev)
1076 {
1077         struct s3c24xx_i2c *i2c;
1078         struct s3c2410_platform_i2c *pdata = NULL;
1079         struct resource *res;
1080         int ret;
1081
1082         if (!pdev->dev.of_node) {
1083                 pdata = dev_get_platdata(&pdev->dev);
1084                 if (!pdata) {
1085                         dev_err(&pdev->dev, "no platform data\n");
1086                         return -EINVAL;
1087                 }
1088         }
1089
1090         i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1091         if (!i2c)
1092                 return -ENOMEM;
1093
1094         i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1095         if (!i2c->pdata)
1096                 return -ENOMEM;
1097
1098         i2c->quirks = s3c24xx_get_device_quirks(pdev);
1099         i2c->sysreg = ERR_PTR(-ENOENT);
1100         if (pdata)
1101                 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1102         else
1103                 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1104
1105         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1106         i2c->adap.owner = THIS_MODULE;
1107         i2c->adap.algo = &s3c24xx_i2c_algorithm;
1108         i2c->adap.retries = 2;
1109         i2c->adap.class = I2C_CLASS_DEPRECATED;
1110         i2c->tx_setup = 50;
1111
1112         init_waitqueue_head(&i2c->wait);
1113
1114         /* find the clock and enable it */
1115         i2c->dev = &pdev->dev;
1116         i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1117         if (IS_ERR(i2c->clk)) {
1118                 dev_err(&pdev->dev, "cannot get clock\n");
1119                 return -ENOENT;
1120         }
1121
1122         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1123
1124         /* map the registers */
1125         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1126         i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1127
1128         if (IS_ERR(i2c->regs))
1129                 return PTR_ERR(i2c->regs);
1130
1131         dev_dbg(&pdev->dev, "registers %p (%p)\n",
1132                 i2c->regs, res);
1133
1134         /* setup info block for the i2c core */
1135         i2c->adap.algo_data = i2c;
1136         i2c->adap.dev.parent = &pdev->dev;
1137         i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1138
1139         /* inititalise the i2c gpio lines */
1140         if (i2c->pdata->cfg_gpio)
1141                 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1142         else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1143                 return -EINVAL;
1144
1145         /* initialise the i2c controller */
1146         ret = clk_prepare_enable(i2c->clk);
1147         if (ret) {
1148                 dev_err(&pdev->dev, "I2C clock enable failed\n");
1149                 return ret;
1150         }
1151
1152         ret = s3c24xx_i2c_init(i2c);
1153         clk_disable(i2c->clk);
1154         if (ret != 0) {
1155                 dev_err(&pdev->dev, "I2C controller init failed\n");
1156                 clk_unprepare(i2c->clk);
1157                 return ret;
1158         }
1159
1160         /*
1161          * find the IRQ for this unit (note, this relies on the init call to
1162          * ensure no current IRQs pending
1163          */
1164         if (!(i2c->quirks & QUIRK_POLL)) {
1165                 i2c->irq = ret = platform_get_irq(pdev, 0);
1166                 if (ret <= 0) {
1167                         dev_err(&pdev->dev, "cannot find IRQ\n");
1168                         clk_unprepare(i2c->clk);
1169                         return ret;
1170                 }
1171
1172                 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1173                                        0, dev_name(&pdev->dev), i2c);
1174                 if (ret != 0) {
1175                         dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1176                         clk_unprepare(i2c->clk);
1177                         return ret;
1178                 }
1179         }
1180
1181         ret = s3c24xx_i2c_register_cpufreq(i2c);
1182         if (ret < 0) {
1183                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1184                 clk_unprepare(i2c->clk);
1185                 return ret;
1186         }
1187
1188         /*
1189          * Note, previous versions of the driver used i2c_add_adapter()
1190          * to add the bus at any number. We now pass the bus number via
1191          * the platform data, so if unset it will now default to always
1192          * being bus 0.
1193          */
1194         i2c->adap.nr = i2c->pdata->bus_num;
1195         i2c->adap.dev.of_node = pdev->dev.of_node;
1196
1197         platform_set_drvdata(pdev, i2c);
1198
1199         pm_runtime_enable(&pdev->dev);
1200
1201         ret = i2c_add_numbered_adapter(&i2c->adap);
1202         if (ret < 0) {
1203                 pm_runtime_disable(&pdev->dev);
1204                 s3c24xx_i2c_deregister_cpufreq(i2c);
1205                 clk_unprepare(i2c->clk);
1206                 return ret;
1207         }
1208
1209         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1210         return 0;
1211 }
1212
1213 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1214 {
1215         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1216
1217         clk_unprepare(i2c->clk);
1218
1219         pm_runtime_disable(&pdev->dev);
1220
1221         s3c24xx_i2c_deregister_cpufreq(i2c);
1222
1223         i2c_del_adapter(&i2c->adap);
1224
1225         if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1226                 s3c24xx_i2c_dt_gpio_free(i2c);
1227
1228         return 0;
1229 }
1230
1231 #ifdef CONFIG_PM_SLEEP
1232 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1233 {
1234         struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1235
1236         i2c_mark_adapter_suspended(&i2c->adap);
1237
1238         if (!IS_ERR(i2c->sysreg))
1239                 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1240
1241         return 0;
1242 }
1243
1244 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1245 {
1246         struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1247         int ret;
1248
1249         if (!IS_ERR(i2c->sysreg))
1250                 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1251
1252         ret = clk_enable(i2c->clk);
1253         if (ret)
1254                 return ret;
1255         s3c24xx_i2c_init(i2c);
1256         clk_disable(i2c->clk);
1257         i2c_mark_adapter_resumed(&i2c->adap);
1258
1259         return 0;
1260 }
1261 #endif
1262
1263 #ifdef CONFIG_PM
1264 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1265         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1266                                       s3c24xx_i2c_resume_noirq)
1267 };
1268
1269 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1270 #else
1271 #define S3C24XX_DEV_PM_OPS NULL
1272 #endif
1273
1274 static struct platform_driver s3c24xx_i2c_driver = {
1275         .probe          = s3c24xx_i2c_probe,
1276         .remove         = s3c24xx_i2c_remove,
1277         .id_table       = s3c24xx_driver_ids,
1278         .driver         = {
1279                 .name   = "s3c-i2c",
1280                 .pm     = S3C24XX_DEV_PM_OPS,
1281                 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1282         },
1283 };
1284
1285 static int __init i2c_adap_s3c_init(void)
1286 {
1287         return platform_driver_register(&s3c24xx_i2c_driver);
1288 }
1289 subsys_initcall(i2c_adap_s3c_init);
1290
1291 static void __exit i2c_adap_s3c_exit(void)
1292 {
1293         platform_driver_unregister(&s3c24xx_i2c_driver);
1294 }
1295 module_exit(i2c_adap_s3c_exit);
1296
1297 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1298 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1299 MODULE_LICENSE("GPL");