drivers/i2c/busses/i2c-pxa.c

   1 /*
   2  *  i2c_adap_pxa.c
   3  *
   4  *  I2C adapter for the PXA I2C bus access.
   5  *
   6  *  Copyright (C) 2002 Intrinsyc Software Inc.
   7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  History:
  14  *    Apr 2002: Initial version [CS]
  15  *    Jun 2002: Properly seperated algo/adap [FB]
  16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  20  *    Feb 2005: Rework slave mode handling [RMK]
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/i2c-id.h>
  26 #include <linux/init.h>
  27 #include <linux/time.h>
  28 #include <linux/sched.h>
  29 #include <linux/delay.h>
  30 #include <linux/errno.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/i2c-pxa.h>
  33 #include <linux/platform_device.h>
  34
  35 #include <asm/hardware.h>
  36 #include <asm/irq.h>
  37 #include <asm/arch/i2c.h>
  38 #include <asm/arch/pxa-regs.h>
  39
  40 struct pxa_i2c {
  41         spinlock_t              lock;
  42         wait_queue_head_t       wait;
  43         struct i2c_msg          *msg;
  44         unsigned int            msg_num;
  45         unsigned int            msg_idx;
  46         unsigned int            msg_ptr;
  47         unsigned int            slave_addr;
  48
  49         struct i2c_adapter      adap;
  50 #ifdef CONFIG_I2C_PXA_SLAVE
  51         struct i2c_slave_client *slave;
  52 #endif
  53
  54         unsigned int            irqlogidx;
  55         u32                     isrlog[32];
  56         u32                     icrlog[32];
  57 };
  58
  59 /*
  60  * I2C Slave mode address
  61  */
  62 #define I2C_PXA_SLAVE_ADDR      0x1
  63
  64 #ifdef DEBUG
  65
  66 struct bits {
  67         u32     mask;
  68         const char *set;
  69         const char *unset;
  70 };
  71 #define BIT(m, s, u)    { .mask = m, .set = s, .unset = u }
  72
  73 static inline void
  74 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
  75 {
  76         printk("%s %08x: ", prefix, val);
  77         while (num--) {
  78                 const char *str = val & bits->mask ? bits->set : bits->unset;
  79                 if (str)
  80                         printk("%s ", str);
  81                 bits++;
  82         }
  83 }
  84
  85 static const struct bits isr_bits[] = {
  86         BIT(ISR_RWM,    "RX",           "TX"),
  87         BIT(ISR_ACKNAK, "NAK",          "ACK"),
  88         BIT(ISR_UB,     "Bsy",          "Rdy"),
  89         BIT(ISR_IBB,    "BusBsy",       "BusRdy"),
  90         BIT(ISR_SSD,    "SlaveStop",    NULL),
  91         BIT(ISR_ALD,    "ALD",          NULL),
  92         BIT(ISR_ITE,    "TxEmpty",      NULL),
  93         BIT(ISR_IRF,    "RxFull",       NULL),
  94         BIT(ISR_GCAD,   "GenCall",      NULL),
  95         BIT(ISR_SAD,    "SlaveAddr",    NULL),
  96         BIT(ISR_BED,    "BusErr",       NULL),
  97 };
  98
  99 static void decode_ISR(unsigned int val)
 100 {
 101         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 102         printk("\n");
 103 }
 104
 105 static const struct bits icr_bits[] = {
 106         BIT(ICR_START,  "START",        NULL),
 107         BIT(ICR_STOP,   "STOP",         NULL),
 108         BIT(ICR_ACKNAK, "ACKNAK",       NULL),
 109         BIT(ICR_TB,     "TB",           NULL),
 110         BIT(ICR_MA,     "MA",           NULL),
 111         BIT(ICR_SCLE,   "SCLE",         "scle"),
 112         BIT(ICR_IUE,    "IUE",          "iue"),
 113         BIT(ICR_GCD,    "GCD",          NULL),
 114         BIT(ICR_ITEIE,  "ITEIE",        NULL),
 115         BIT(ICR_IRFIE,  "IRFIE",        NULL),
 116         BIT(ICR_BEIE,   "BEIE",         NULL),
 117         BIT(ICR_SSDIE,  "SSDIE",        NULL),
 118         BIT(ICR_ALDIE,  "ALDIE",        NULL),
 119         BIT(ICR_SADIE,  "SADIE",        NULL),
 120         BIT(ICR_UR,     "UR",           "ur"),
 121 };
 122
 123 static void decode_ICR(unsigned int val)
 124 {
 125         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 126         printk("\n");
 127 }
 128
 129 static unsigned int i2c_debug = DEBUG;
 130
 131 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 132 {
 133         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR);
 134 }
 135
 136 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
 137 #else
 138 #define i2c_debug       0
 139
 140 #define show_state(i2c) do { } while (0)
 141 #define decode_ISR(val) do { } while (0)
 142 #define decode_ICR(val) do { } while (0)
 143 #endif
 144
 145 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
 146
 147 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 148
 149 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 150 {
 151         unsigned int i;
 152         printk("i2c: error: %s\n", why);
 153         printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
 154                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 155         printk("i2c: ICR: %08x ISR: %08x\n"
 156                "i2c: log: ", ICR, ISR);
 157         for (i = 0; i < i2c->irqlogidx; i++)
 158                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
 159         printk("\n");
 160 }
 161
 162 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 163 {
 164         return !(ICR & ICR_SCLE);
 165 }
 166
 167 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 168 {
 169         unsigned long timeout = jiffies + HZ/4;
 170
 171         if (i2c_pxa_is_slavemode(i2c)) {
 172                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 173                 return;
 174         }
 175
 176         while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) {
 177                 unsigned long icr = ICR;
 178
 179                 icr &= ~ICR_START;
 180                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 181
 182                 ICR = icr;
 183
 184                 show_state(i2c);
 185
 186                 msleep(1);
 187         }
 188
 189         ICR &= ~(ICR_MA | ICR_START | ICR_STOP);
 190 }
 191
 192 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 193 {
 194         int timeout = DEF_TIMEOUT;
 195
 196         while (timeout-- && ISR & (ISR_IBB | ISR_UB)) {
 197                 if ((ISR & ISR_SAD) != 0)
 198                         timeout += 4;
 199
 200                 msleep(2);
 201                 show_state(i2c);
 202         }
 203
 204         if (timeout <= 0)
 205                 show_state(i2c);
 206
 207         return timeout <= 0 ? I2C_RETRY : 0;
 208 }
 209
 210 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 211 {
 212         unsigned long timeout = jiffies + HZ*4;
 213
 214         while (time_before(jiffies, timeout)) {
 215                 if (i2c_debug > 1)
 216                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 217                                 __func__, (long)jiffies, ISR, ICR, IBMR);
 218
 219                 if (ISR & ISR_SAD) {
 220                         if (i2c_debug > 0)
 221                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 222                         goto out;
 223                 }
 224
 225                 /* wait for unit and bus being not busy, and we also do a
 226                  * quick check of the i2c lines themselves to ensure they've
 227                  * gone high...
 228                  */
 229                 if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) {
 230                         if (i2c_debug > 0)
 231                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 232                         return 1;
 233                 }
 234
 235                 msleep(1);
 236         }
 237
 238         if (i2c_debug > 0)
 239                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 240  out:
 241         return 0;
 242 }
 243
 244 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 245 {
 246         if (i2c_debug)
 247                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 248
 249         if ((ISR & (ISR_UB | ISR_IBB)) != 0) {
 250                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 251                 if (!i2c_pxa_wait_master(i2c)) {
 252                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 253                         return I2C_RETRY;
 254                 }
 255         }
 256
 257         ICR |= ICR_SCLE;
 258         return 0;
 259 }
 260
 261 #ifdef CONFIG_I2C_PXA_SLAVE
 262 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 263 {
 264         unsigned long timeout = jiffies + HZ*1;
 265
 266         /* wait for stop */
 267
 268         show_state(i2c);
 269
 270         while (time_before(jiffies, timeout)) {
 271                 if (i2c_debug > 1)
 272                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 273                                 __func__, (long)jiffies, ISR, ICR, IBMR);
 274
 275                 if ((ISR & (ISR_UB|ISR_IBB)) == 0 ||
 276                     (ISR & ISR_SAD) != 0 ||
 277                     (ICR & ICR_SCLE) == 0) {
 278                         if (i2c_debug > 1)
 279                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 280                         return 1;
 281                 }
 282
 283                 msleep(1);
 284         }
 285
 286         if (i2c_debug > 0)
 287                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 288         return 0;
 289 }
 290
 291 /*
 292  * clear the hold on the bus, and take of anything else
 293  * that has been configured
 294  */
 295 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 296 {
 297         show_state(i2c);
 298
 299         if (errcode < 0) {
 300                 udelay(100);   /* simple delay */
 301         } else {
 302                 /* we need to wait for the stop condition to end */
 303
 304                 /* if we where in stop, then clear... */
 305                 if (ICR & ICR_STOP) {
 306                         udelay(100);
 307                         ICR &= ~ICR_STOP;
 308                 }
 309
 310                 if (!i2c_pxa_wait_slave(i2c)) {
 311                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 312                                 __func__);
 313                         return;
 314                 }
 315         }
 316
 317         ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA);
 318         ICR &= ~ICR_SCLE;
 319
 320         if (i2c_debug) {
 321                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", ICR, ISR);
 322                 decode_ICR(ICR);
 323         }
 324 }
 325 #else
 326 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 327 #endif
 328
 329 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 330 {
 331         pr_debug("Resetting I2C Controller Unit\n");
 332
 333         /* abort any transfer currently under way */
 334         i2c_pxa_abort(i2c);
 335
 336         /* reset according to 9.8 */
 337         ICR = ICR_UR;
 338         ISR = I2C_ISR_INIT;
 339         ICR &= ~ICR_UR;
 340
 341         ISAR = i2c->slave_addr;
 342
 343         /* set control register values */
 344         ICR = I2C_ICR_INIT;
 345
 346 #ifdef CONFIG_I2C_PXA_SLAVE
 347         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 348         ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE;
 349 #endif
 350
 351         i2c_pxa_set_slave(i2c, 0);
 352
 353         /* enable unit */
 354         ICR |= ICR_IUE;
 355         udelay(100);
 356 }
 357
 358
 359 #ifdef CONFIG_I2C_PXA_SLAVE
 360 /*
 361  * I2C EEPROM emulation.
 362  */
 363 static struct i2c_eeprom_emu eeprom = {
 364         .size = I2C_EEPROM_EMU_SIZE,
 365         .watch = LIST_HEAD_INIT(eeprom.watch),
 366 };
 367
 368 struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void)
 369 {
 370         return &eeprom;
 371 }
 372
 373 int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *emu, void *data,
 374                               unsigned int addr, unsigned int size,
 375                               struct i2c_eeprom_emu_watcher *watcher)
 376 {
 377         struct i2c_eeprom_emu_watch *watch;
 378         unsigned long flags;
 379
 380         if (addr + size > emu->size)
 381                 return -EINVAL;
 382
 383         watch = kmalloc(sizeof(struct i2c_eeprom_emu_watch), GFP_KERNEL);
 384         if (watch) {
 385                 watch->start = addr;
 386                 watch->end = addr + size - 1;
 387                 watch->ops = watcher;
 388                 watch->data = data;
 389
 390                 local_irq_save(flags);
 391                 list_add(&watch->node, &emu->watch);
 392                 local_irq_restore(flags);
 393         }
 394
 395         return watch ? 0 : -ENOMEM;
 396 }
 397
 398 void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *emu, void *data,
 399                                struct i2c_eeprom_emu_watcher *watcher)
 400 {
 401         struct i2c_eeprom_emu_watch *watch, *n;
 402         unsigned long flags;
 403
 404         list_for_each_entry_safe(watch, n, &emu->watch, node) {
 405                 if (watch->ops == watcher && watch->data == data) {
 406                         local_irq_save(flags);
 407                         list_del(&watch->node);
 408                         local_irq_restore(flags);
 409                         kfree(watch);
 410                 }
 411         }
 412 }
 413
 414 static void i2c_eeprom_emu_event(void *ptr, i2c_slave_event_t event)
 415 {
 416         struct i2c_eeprom_emu *emu = ptr;
 417
 418         eedbg(3, "i2c_eeprom_emu_event: %d\n", event);
 419
 420         switch (event) {
 421         case I2C_SLAVE_EVENT_START_WRITE:
 422                 emu->seen_start = 1;
 423                 eedbg(2, "i2c_eeprom: write initiated\n");
 424                 break;
 425
 426         case I2C_SLAVE_EVENT_START_READ:
 427                 emu->seen_start = 0;
 428                 eedbg(2, "i2c_eeprom: read initiated\n");
 429                 break;
 430
 431         case I2C_SLAVE_EVENT_STOP:
 432                 emu->seen_start = 0;
 433                 eedbg(2, "i2c_eeprom: received stop\n");
 434                 break;
 435
 436         default:
 437                 eedbg(0, "i2c_eeprom: unhandled event\n");
 438                 break;
 439         }
 440 }
 441
 442 static int i2c_eeprom_emu_read(void *ptr)
 443 {
 444         struct i2c_eeprom_emu *emu = ptr;
 445         int ret;
 446
 447         ret = emu->bytes[emu->ptr];
 448         emu->ptr = (emu->ptr + 1) % emu->size;
 449
 450         return ret;
 451 }
 452
 453 static void i2c_eeprom_emu_write(void *ptr, unsigned int val)
 454 {
 455         struct i2c_eeprom_emu *emu = ptr;
 456         struct i2c_eeprom_emu_watch *watch;
 457
 458         if (emu->seen_start != 0) {
 459                 eedbg(2, "i2c_eeprom_emu_write: setting ptr %02x\n", val);
 460                 emu->ptr = val;
 461                 emu->seen_start = 0;
 462                 return;
 463         }
 464
 465         emu->bytes[emu->ptr] = val;
 466
 467         eedbg(1, "i2c_eeprom_emu_write: ptr=0x%02x, val=0x%02x\n",
 468               emu->ptr, val);
 469
 470         list_for_each_entry(watch, &emu->watch, node) {
 471                 if (!watch->ops || !watch->ops->write)
 472                         continue;
 473                 if (watch->start <= emu->ptr && watch->end >= emu->ptr)
 474                         watch->ops->write(watch->data, emu->ptr, val);
 475         }
 476
 477         emu->ptr = (emu->ptr + 1) % emu->size;
 478 }
 479
 480 struct i2c_slave_client eeprom_client = {
 481         .data   = &eeprom,
 482         .event  = i2c_eeprom_emu_event,
 483         .read   = i2c_eeprom_emu_read,
 484         .write  = i2c_eeprom_emu_write
 485 };
 486
 487 /*
 488  * PXA I2C Slave mode
 489  */
 490
 491 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 492 {
 493         if (isr & ISR_BED) {
 494                 /* what should we do here? */
 495         } else {
 496                 int ret = 0;
 497
 498                 if (i2c->slave != NULL)
 499                         ret = i2c->slave->read(i2c->slave->data);
 500
 501                 IDBR = ret;
 502                 ICR |= ICR_TB;   /* allow next byte */
 503         }
 504 }
 505
 506 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 507 {
 508         unsigned int byte = IDBR;
 509
 510         if (i2c->slave != NULL)
 511                 i2c->slave->write(i2c->slave->data, byte);
 512
 513         ICR |= ICR_TB;
 514 }
 515
 516 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 517 {
 518         int timeout;
 519
 520         if (i2c_debug > 0)
 521                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 522                        (isr & ISR_RWM) ? 'r' : 't');
 523
 524         if (i2c->slave != NULL)
 525                 i2c->slave->event(i2c->slave->data,
 526                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
 527
 528         /*
 529          * slave could interrupt in the middle of us generating a
 530          * start condition... if this happens, we'd better back off
 531          * and stop holding the poor thing up
 532          */
 533         ICR &= ~(ICR_START|ICR_STOP);
 534         ICR |= ICR_TB;
 535
 536         timeout = 0x10000;
 537
 538         while (1) {
 539                 if ((IBMR & 2) == 2)
 540                         break;
 541
 542                 timeout--;
 543
 544                 if (timeout <= 0) {
 545                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 546                         break;
 547                 }
 548         }
 549
 550         ICR &= ~ICR_SCLE;
 551 }
 552
 553 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 554 {
 555         if (i2c_debug > 2)
 556                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 557
 558         if (i2c->slave != NULL)
 559                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
 560
 561         if (i2c_debug > 2)
 562                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 563
 564         /*
 565          * If we have a master-mode message waiting,
 566          * kick it off now that the slave has completed.
 567          */
 568         if (i2c->msg)
 569                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 570 }
 571 #else
 572 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 573 {
 574         if (isr & ISR_BED) {
 575                 /* what should we do here? */
 576         } else {
 577                 IDBR = 0;
 578                 ICR |= ICR_TB;
 579         }
 580 }
 581
 582 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 583 {
 584         ICR |= ICR_TB | ICR_ACKNAK;
 585 }
 586
 587 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 588 {
 589         int timeout;
 590
 591         /*
 592          * slave could interrupt in the middle of us generating a
 593          * start condition... if this happens, we'd better back off
 594          * and stop holding the poor thing up
 595          */
 596         ICR &= ~(ICR_START|ICR_STOP);
 597         ICR |= ICR_TB | ICR_ACKNAK;
 598
 599         timeout = 0x10000;
 600
 601         while (1) {
 602                 if ((IBMR & 2) == 2)
 603                         break;
 604
 605                 timeout--;
 606
 607                 if (timeout <= 0) {
 608                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 609                         break;
 610                 }
 611         }
 612
 613         ICR &= ~ICR_SCLE;
 614 }
 615
 616 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 617 {
 618         if (i2c->msg)
 619                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 620 }
 621 #endif
 622
 623 /*
 624  * PXA I2C Master mode
 625  */
 626
 627 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
 628 {
 629         unsigned int addr = (msg->addr & 0x7f) << 1;
 630
 631         if (msg->flags & I2C_M_RD)
 632                 addr |= 1;
 633
 634         return addr;
 635 }
 636
 637 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 638 {
 639         u32 icr;
 640
 641         /*
 642          * Step 1: target slave address into IDBR
 643          */
 644         IDBR = i2c_pxa_addr_byte(i2c->msg);
 645
 646         /*
 647          * Step 2: initiate the write.
 648          */
 649         icr = ICR & ~(ICR_STOP | ICR_ALDIE);
 650         ICR = icr | ICR_START | ICR_TB;
 651 }
 652
 653 /*
 654  * We are protected by the adapter bus mutex.
 655  */
 656 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
 657 {
 658         long timeout;
 659         int ret;
 660
 661         /*
 662          * Wait for the bus to become free.
 663          */
 664         ret = i2c_pxa_wait_bus_not_busy(i2c);
 665         if (ret) {
 666                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
 667                 goto out;
 668         }
 669
 670         /*
 671          * Set master mode.
 672          */
 673         ret = i2c_pxa_set_master(i2c);
 674         if (ret) {
 675                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
 676                 goto out;
 677         }
 678
 679         spin_lock_irq(&i2c->lock);
 680
 681         i2c->msg = msg;
 682         i2c->msg_num = num;
 683         i2c->msg_idx = 0;
 684         i2c->msg_ptr = 0;
 685         i2c->irqlogidx = 0;
 686
 687         i2c_pxa_start_message(i2c);
 688
 689         spin_unlock_irq(&i2c->lock);
 690
 691         /*
 692          * The rest of the processing occurs in the interrupt handler.
 693          */
 694         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 695
 696         /*
 697          * We place the return code in i2c->msg_idx.
 698          */
 699         ret = i2c->msg_idx;
 700
 701         if (timeout == 0)
 702                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 703
 704  out:
 705         return ret;
 706 }
 707
 708 /*
 709  * i2c_pxa_master_complete - complete the message and wake up.
 710  */
 711 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 712 {
 713         i2c->msg_ptr = 0;
 714         i2c->msg = NULL;
 715         i2c->msg_idx ++;
 716         i2c->msg_num = 0;
 717         if (ret)
 718                 i2c->msg_idx = ret;
 719         wake_up(&i2c->wait);
 720 }
 721
 722 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 723 {
 724         u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 725
 726  again:
 727         /*
 728          * If ISR_ALD is set, we lost arbitration.
 729          */
 730         if (isr & ISR_ALD) {
 731                 /*
 732                  * Do we need to do anything here?  The PXA docs
 733                  * are vague about what happens.
 734                  */
 735                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 736
 737                 /*
 738                  * We ignore this error.  We seem to see spurious ALDs
 739                  * for seemingly no reason.  If we handle them as I think
 740                  * they should, we end up causing an I2C error, which
 741                  * is painful for some systems.
 742                  */
 743                 return; /* ignore */
 744         }
 745
 746         if (isr & ISR_BED) {
 747                 int ret = BUS_ERROR;
 748
 749                 /*
 750                  * I2C bus error - either the device NAK'd us, or
 751                  * something more serious happened.  If we were NAK'd
 752                  * on the initial address phase, we can retry.
 753                  */
 754                 if (isr & ISR_ACKNAK) {
 755                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 756                                 ret = I2C_RETRY;
 757                         else
 758                                 ret = XFER_NAKED;
 759                 }
 760                 i2c_pxa_master_complete(i2c, ret);
 761         } else if (isr & ISR_RWM) {
 762                 /*
 763                  * Read mode.  We have just sent the address byte, and
 764                  * now we must initiate the transfer.
 765                  */
 766                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 767                     i2c->msg_idx == i2c->msg_num - 1)
 768                         icr |= ICR_STOP | ICR_ACKNAK;
 769
 770                 icr |= ICR_ALDIE | ICR_TB;
 771         } else if (i2c->msg_ptr < i2c->msg->len) {
 772                 /*
 773                  * Write mode.  Write the next data byte.
 774                  */
 775                 IDBR = i2c->msg->buf[i2c->msg_ptr++];
 776
 777                 icr |= ICR_ALDIE | ICR_TB;
 778
 779                 /*
 780                  * If this is the last byte of the last message, send
 781                  * a STOP.
 782                  */
 783                 if (i2c->msg_ptr == i2c->msg->len &&
 784                     i2c->msg_idx == i2c->msg_num - 1)
 785                         icr |= ICR_STOP;
 786         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 787                 /*
 788                  * Next segment of the message.
 789                  */
 790                 i2c->msg_ptr = 0;
 791                 i2c->msg_idx ++;
 792                 i2c->msg++;
 793
 794                 /*
 795                  * If we aren't doing a repeated start and address,
 796                  * go back and try to send the next byte.  Note that
 797                  * we do not support switching the R/W direction here.
 798                  */
 799                 if (i2c->msg->flags & I2C_M_NOSTART)
 800                         goto again;
 801
 802                 /*
 803                  * Write the next address.
 804                  */
 805                 IDBR = i2c_pxa_addr_byte(i2c->msg);
 806
 807                 /*
 808                  * And trigger a repeated start, and send the byte.
 809                  */
 810                 icr &= ~ICR_ALDIE;
 811                 icr |= ICR_START | ICR_TB;
 812         } else {
 813                 if (i2c->msg->len == 0) {
 814                         /*
 815                          * Device probes have a message length of zero
 816                          * and need the bus to be reset before it can
 817                          * be used again.
 818                          */
 819                         i2c_pxa_reset(i2c);
 820                 }
 821                 i2c_pxa_master_complete(i2c, 0);
 822         }
 823
 824         i2c->icrlog[i2c->irqlogidx-1] = icr;
 825
 826         ICR = icr;
 827         show_state(i2c);
 828 }
 829
 830 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 831 {
 832         u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 833
 834         /*
 835          * Read the byte.
 836          */
 837         i2c->msg->buf[i2c->msg_ptr++] = IDBR;
 838
 839         if (i2c->msg_ptr < i2c->msg->len) {
 840                 /*
 841                  * If this is the last byte of the last
 842                  * message, send a STOP.
 843                  */
 844                 if (i2c->msg_ptr == i2c->msg->len - 1)
 845                         icr |= ICR_STOP | ICR_ACKNAK;
 846
 847                 icr |= ICR_ALDIE | ICR_TB;
 848         } else {
 849                 i2c_pxa_master_complete(i2c, 0);
 850         }
 851
 852         i2c->icrlog[i2c->irqlogidx-1] = icr;
 853
 854         ICR = icr;
 855 }
 856
 857 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
 858 {
 859         struct pxa_i2c *i2c = dev_id;
 860         u32 isr = ISR;
 861
 862         if (i2c_debug > 2 && 0) {
 863                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 864                         __func__, isr, ICR, IBMR);
 865                 decode_ISR(isr);
 866         }
 867
 868         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
 869                 i2c->isrlog[i2c->irqlogidx++] = isr;
 870
 871         show_state(i2c);
 872
 873         /*
 874          * Always clear all pending IRQs.
 875          */
 876         ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED);
 877
 878         if (isr & ISR_SAD)
 879                 i2c_pxa_slave_start(i2c, isr);
 880         if (isr & ISR_SSD)
 881                 i2c_pxa_slave_stop(i2c);
 882
 883         if (i2c_pxa_is_slavemode(i2c)) {
 884                 if (isr & ISR_ITE)
 885                         i2c_pxa_slave_txempty(i2c, isr);
 886                 if (isr & ISR_IRF)
 887                         i2c_pxa_slave_rxfull(i2c, isr);
 888         } else if (i2c->msg) {
 889                 if (isr & ISR_ITE)
 890                         i2c_pxa_irq_txempty(i2c, isr);
 891                 if (isr & ISR_IRF)
 892                         i2c_pxa_irq_rxfull(i2c, isr);
 893         } else {
 894                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
 895         }
 896
 897         return IRQ_HANDLED;
 898 }
 899
 900
 901 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 902 {
 903         struct pxa_i2c *i2c = adap->algo_data;
 904         int ret, i;
 905
 906         /* If the I2C controller is disabled we need to reset it (probably due
 907            to a suspend/resume destroying state). We do this here as we can then
 908            avoid worrying about resuming the controller before its users. */
 909         if (!(ICR & ICR_IUE))
 910                 i2c_pxa_reset(i2c);
 911
 912         for (i = adap->retries; i >= 0; i--) {
 913                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
 914                 if (ret != I2C_RETRY)
 915                         goto out;
 916
 917                 if (i2c_debug)
 918                         dev_dbg(&adap->dev, "Retrying transmission\n");
 919                 udelay(100);
 920         }
 921         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 922         ret = -EREMOTEIO;
 923  out:
 924         i2c_pxa_set_slave(i2c, ret);
 925         return ret;
 926 }
 927
 928 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
 929 {
 930         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 931 }
 932
 933 static const struct i2c_algorithm i2c_pxa_algorithm = {
 934         .master_xfer    = i2c_pxa_xfer,
 935         .functionality  = i2c_pxa_functionality,
 936 };
 937
 938 static struct pxa_i2c i2c_pxa = {
 939         .lock   = SPIN_LOCK_UNLOCKED,
 940         .wait   = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),
 941         .adap   = {
 942                 .owner          = THIS_MODULE,
 943                 .algo           = &i2c_pxa_algorithm,
 944                 .name           = "pxa2xx-i2c",
 945                 .retries        = 5,
 946         },
 947 };
 948
 949 static int i2c_pxa_probe(struct platform_device *dev)
 950 {
 951         struct pxa_i2c *i2c = &i2c_pxa;
 952 #ifdef CONFIG_I2C_PXA_SLAVE
 953         struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
 954 #endif
 955         int ret;
 956
 957 #ifdef CONFIG_PXA27x
 958         pxa_gpio_mode(GPIO117_I2CSCL_MD);
 959         pxa_gpio_mode(GPIO118_I2CSDA_MD);
 960         udelay(100);
 961 #endif
 962
 963         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
 964
 965 #ifdef CONFIG_I2C_PXA_SLAVE
 966         i2c->slave = &eeprom_client;
 967         if (plat) {
 968                 i2c->slave_addr = plat->slave_addr;
 969                 if (plat->slave)
 970                         i2c->slave = plat->slave;
 971         }
 972 #endif
 973
 974         pxa_set_cken(CKEN14_I2C, 1);
 975         ret = request_irq(IRQ_I2C, i2c_pxa_handler, IRQF_DISABLED,
 976                           "pxa2xx-i2c", i2c);
 977         if (ret)
 978                 goto out;
 979
 980         i2c_pxa_reset(i2c);
 981
 982         i2c->adap.algo_data = i2c;
 983         i2c->adap.dev.parent = &dev->dev;
 984
 985         ret = i2c_add_adapter(&i2c->adap);
 986         if (ret < 0) {
 987                 printk(KERN_INFO "I2C: Failed to add bus\n");
 988                 goto err_irq;
 989         }
 990
 991         platform_set_drvdata(dev, i2c);
 992
 993 #ifdef CONFIG_I2C_PXA_SLAVE
 994         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
 995                i2c->adap.dev.bus_id, i2c->slave_addr);
 996 #else
 997         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
 998                i2c->adap.dev.bus_id);
 999 #endif
1000         return 0;
1001
1002  err_irq:
1003         free_irq(IRQ_I2C, i2c);
1004  out:
1005         return ret;
1006 }
1007
1008 static int i2c_pxa_remove(struct platform_device *dev)
1009 {
1010         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1011
1012         platform_set_drvdata(dev, NULL);
1013
1014         i2c_del_adapter(&i2c->adap);
1015         free_irq(IRQ_I2C, i2c);
1016         pxa_set_cken(CKEN14_I2C, 0);
1017
1018         return 0;
1019 }
1020
1021 static struct platform_driver i2c_pxa_driver = {
1022         .probe          = i2c_pxa_probe,
1023         .remove         = i2c_pxa_remove,
1024         .driver         = {
1025                 .name   = "pxa2xx-i2c",
1026         },
1027 };
1028
1029 static int __init i2c_adap_pxa_init(void)
1030 {
1031         return platform_driver_register(&i2c_pxa_driver);
1032 }
1033
1034 static void i2c_adap_pxa_exit(void)
1035 {
1036         return platform_driver_unregister(&i2c_pxa_driver);
1037 }
1038
1039 MODULE_LICENSE("GPL");
1040
1041 module_init(i2c_adap_pxa_init);
1042 module_exit(i2c_adap_pxa_exit);