Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
[sfrench/cifs-2.6.git] / drivers / i2c / busses / i2c-pxa.c
1 /*
2  *  i2c_adap_pxa.c
3  *
4  *  I2C adapter for the PXA I2C bus access.
5  *
6  *  Copyright (C) 2002 Intrinsyc Software Inc.
7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8  *
9  *  This program is free software; you can redistribute it and/or modify
10  *  it under the terms of the GNU General Public License version 2 as
11  *  published by the Free Software Foundation.
12  *
13  *  History:
14  *    Apr 2002: Initial version [CS]
15  *    Jun 2002: Properly seperated algo/adap [FB]
16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20  *    Feb 2005: Rework slave mode handling [RMK]
21  */
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
34
35 #include <asm/hardware.h>
36 #include <asm/irq.h>
37 #include <asm/io.h>
38 #include <asm/arch/i2c.h>
39 #include <asm/arch/pxa-regs.h>
40
41 struct pxa_i2c {
42         spinlock_t              lock;
43         wait_queue_head_t       wait;
44         struct i2c_msg          *msg;
45         unsigned int            msg_num;
46         unsigned int            msg_idx;
47         unsigned int            msg_ptr;
48         unsigned int            slave_addr;
49
50         struct i2c_adapter      adap;
51 #ifdef CONFIG_I2C_PXA_SLAVE
52         struct i2c_slave_client *slave;
53 #endif
54
55         unsigned int            irqlogidx;
56         u32                     isrlog[32];
57         u32                     icrlog[32];
58
59         void __iomem            *reg_base;
60
61         unsigned long           iobase;
62         unsigned long           iosize;
63
64         int                     irq;
65 };
66
67 #define _IBMR(i2c)      ((i2c)->reg_base + 0)
68 #define _IDBR(i2c)      ((i2c)->reg_base + 8)
69 #define _ICR(i2c)       ((i2c)->reg_base + 0x10)
70 #define _ISR(i2c)       ((i2c)->reg_base + 0x18)
71 #define _ISAR(i2c)      ((i2c)->reg_base + 0x20)
72
73 /*
74  * I2C Slave mode address
75  */
76 #define I2C_PXA_SLAVE_ADDR      0x1
77
78 #ifdef DEBUG
79
80 struct bits {
81         u32     mask;
82         const char *set;
83         const char *unset;
84 };
85 #define BIT(m, s, u)    { .mask = m, .set = s, .unset = u }
86
87 static inline void
88 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
89 {
90         printk("%s %08x: ", prefix, val);
91         while (num--) {
92                 const char *str = val & bits->mask ? bits->set : bits->unset;
93                 if (str)
94                         printk("%s ", str);
95                 bits++;
96         }
97 }
98
99 static const struct bits isr_bits[] = {
100         BIT(ISR_RWM,    "RX",           "TX"),
101         BIT(ISR_ACKNAK, "NAK",          "ACK"),
102         BIT(ISR_UB,     "Bsy",          "Rdy"),
103         BIT(ISR_IBB,    "BusBsy",       "BusRdy"),
104         BIT(ISR_SSD,    "SlaveStop",    NULL),
105         BIT(ISR_ALD,    "ALD",          NULL),
106         BIT(ISR_ITE,    "TxEmpty",      NULL),
107         BIT(ISR_IRF,    "RxFull",       NULL),
108         BIT(ISR_GCAD,   "GenCall",      NULL),
109         BIT(ISR_SAD,    "SlaveAddr",    NULL),
110         BIT(ISR_BED,    "BusErr",       NULL),
111 };
112
113 static void decode_ISR(unsigned int val)
114 {
115         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
116         printk("\n");
117 }
118
119 static const struct bits icr_bits[] = {
120         BIT(ICR_START,  "START",        NULL),
121         BIT(ICR_STOP,   "STOP",         NULL),
122         BIT(ICR_ACKNAK, "ACKNAK",       NULL),
123         BIT(ICR_TB,     "TB",           NULL),
124         BIT(ICR_MA,     "MA",           NULL),
125         BIT(ICR_SCLE,   "SCLE",         "scle"),
126         BIT(ICR_IUE,    "IUE",          "iue"),
127         BIT(ICR_GCD,    "GCD",          NULL),
128         BIT(ICR_ITEIE,  "ITEIE",        NULL),
129         BIT(ICR_IRFIE,  "IRFIE",        NULL),
130         BIT(ICR_BEIE,   "BEIE",         NULL),
131         BIT(ICR_SSDIE,  "SSDIE",        NULL),
132         BIT(ICR_ALDIE,  "ALDIE",        NULL),
133         BIT(ICR_SADIE,  "SADIE",        NULL),
134         BIT(ICR_UR,     "UR",           "ur"),
135 };
136
137 static void decode_ICR(unsigned int val)
138 {
139         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
140         printk("\n");
141 }
142
143 static unsigned int i2c_debug = DEBUG;
144
145 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
146 {
147         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
148                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
149 }
150
151 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
152 #else
153 #define i2c_debug       0
154
155 #define show_state(i2c) do { } while (0)
156 #define decode_ISR(val) do { } while (0)
157 #define decode_ICR(val) do { } while (0)
158 #endif
159
160 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
161
162 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
163
164 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
165 {
166         unsigned int i;
167         printk("i2c: error: %s\n", why);
168         printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
169                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
170         printk("i2c: ICR: %08x ISR: %08x\n"
171                "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c)));
172         for (i = 0; i < i2c->irqlogidx; i++)
173                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
174         printk("\n");
175 }
176
177 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
178 {
179         return !(readl(_ICR(i2c)) & ICR_SCLE);
180 }
181
182 static void i2c_pxa_abort(struct pxa_i2c *i2c)
183 {
184         unsigned long timeout = jiffies + HZ/4;
185
186         if (i2c_pxa_is_slavemode(i2c)) {
187                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
188                 return;
189         }
190
191         while (time_before(jiffies, timeout) && (readl(_IBMR(i2c)) & 0x1) == 0) {
192                 unsigned long icr = readl(_ICR(i2c));
193
194                 icr &= ~ICR_START;
195                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
196
197                 writel(icr, _ICR(i2c));
198
199                 show_state(i2c);
200
201                 msleep(1);
202         }
203
204         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
205                _ICR(i2c));
206 }
207
208 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
209 {
210         int timeout = DEF_TIMEOUT;
211
212         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
213                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
214                         timeout += 4;
215
216                 msleep(2);
217                 show_state(i2c);
218         }
219
220         if (timeout <= 0)
221                 show_state(i2c);
222
223         return timeout <= 0 ? I2C_RETRY : 0;
224 }
225
226 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
227 {
228         unsigned long timeout = jiffies + HZ*4;
229
230         while (time_before(jiffies, timeout)) {
231                 if (i2c_debug > 1)
232                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
233                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
234
235                 if (readl(_ISR(i2c)) & ISR_SAD) {
236                         if (i2c_debug > 0)
237                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
238                         goto out;
239                 }
240
241                 /* wait for unit and bus being not busy, and we also do a
242                  * quick check of the i2c lines themselves to ensure they've
243                  * gone high...
244                  */
245                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
246                         if (i2c_debug > 0)
247                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
248                         return 1;
249                 }
250
251                 msleep(1);
252         }
253
254         if (i2c_debug > 0)
255                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
256  out:
257         return 0;
258 }
259
260 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
261 {
262         if (i2c_debug)
263                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
264
265         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
266                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
267                 if (!i2c_pxa_wait_master(i2c)) {
268                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
269                         return I2C_RETRY;
270                 }
271         }
272
273         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
274         return 0;
275 }
276
277 #ifdef CONFIG_I2C_PXA_SLAVE
278 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
279 {
280         unsigned long timeout = jiffies + HZ*1;
281
282         /* wait for stop */
283
284         show_state(i2c);
285
286         while (time_before(jiffies, timeout)) {
287                 if (i2c_debug > 1)
288                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
289                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
290
291                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
292                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
293                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
294                         if (i2c_debug > 1)
295                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
296                         return 1;
297                 }
298
299                 msleep(1);
300         }
301
302         if (i2c_debug > 0)
303                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
304         return 0;
305 }
306
307 /*
308  * clear the hold on the bus, and take of anything else
309  * that has been configured
310  */
311 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
312 {
313         show_state(i2c);
314
315         if (errcode < 0) {
316                 udelay(100);   /* simple delay */
317         } else {
318                 /* we need to wait for the stop condition to end */
319
320                 /* if we where in stop, then clear... */
321                 if (readl(_ICR(i2c)) & ICR_STOP) {
322                         udelay(100);
323                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
324                 }
325
326                 if (!i2c_pxa_wait_slave(i2c)) {
327                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
328                                 __func__);
329                         return;
330                 }
331         }
332
333         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
334         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
335
336         if (i2c_debug) {
337                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
338                 decode_ICR(readl(_ICR(i2c)));
339         }
340 }
341 #else
342 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
343 #endif
344
345 static void i2c_pxa_reset(struct pxa_i2c *i2c)
346 {
347         pr_debug("Resetting I2C Controller Unit\n");
348
349         /* abort any transfer currently under way */
350         i2c_pxa_abort(i2c);
351
352         /* reset according to 9.8 */
353         writel(ICR_UR, _ICR(i2c));
354         writel(I2C_ISR_INIT, _ISR(i2c));
355         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
356
357         writel(i2c->slave_addr, _ISAR(i2c));
358
359         /* set control register values */
360         writel(I2C_ICR_INIT, _ICR(i2c));
361
362 #ifdef CONFIG_I2C_PXA_SLAVE
363         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
364         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
365 #endif
366
367         i2c_pxa_set_slave(i2c, 0);
368
369         /* enable unit */
370         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
371         udelay(100);
372 }
373
374
375 #ifdef CONFIG_I2C_PXA_SLAVE
376 /*
377  * PXA I2C Slave mode
378  */
379
380 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
381 {
382         if (isr & ISR_BED) {
383                 /* what should we do here? */
384         } else {
385                 int ret = 0;
386
387                 if (i2c->slave != NULL)
388                         ret = i2c->slave->read(i2c->slave->data);
389
390                 writel(ret, _IDBR(i2c));
391                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
392         }
393 }
394
395 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
396 {
397         unsigned int byte = readl(_IDBR(i2c));
398
399         if (i2c->slave != NULL)
400                 i2c->slave->write(i2c->slave->data, byte);
401
402         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
403 }
404
405 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
406 {
407         int timeout;
408
409         if (i2c_debug > 0)
410                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
411                        (isr & ISR_RWM) ? 'r' : 't');
412
413         if (i2c->slave != NULL)
414                 i2c->slave->event(i2c->slave->data,
415                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
416
417         /*
418          * slave could interrupt in the middle of us generating a
419          * start condition... if this happens, we'd better back off
420          * and stop holding the poor thing up
421          */
422         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
423         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
424
425         timeout = 0x10000;
426
427         while (1) {
428                 if ((readl(_IBMR(i2c)) & 2) == 2)
429                         break;
430
431                 timeout--;
432
433                 if (timeout <= 0) {
434                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
435                         break;
436                 }
437         }
438
439         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
440 }
441
442 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
443 {
444         if (i2c_debug > 2)
445                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
446
447         if (i2c->slave != NULL)
448                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
449
450         if (i2c_debug > 2)
451                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
452
453         /*
454          * If we have a master-mode message waiting,
455          * kick it off now that the slave has completed.
456          */
457         if (i2c->msg)
458                 i2c_pxa_master_complete(i2c, I2C_RETRY);
459 }
460 #else
461 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
462 {
463         if (isr & ISR_BED) {
464                 /* what should we do here? */
465         } else {
466                 writel(0, _IDBR(i2c));
467                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
468         }
469 }
470
471 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
472 {
473         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
474 }
475
476 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
477 {
478         int timeout;
479
480         /*
481          * slave could interrupt in the middle of us generating a
482          * start condition... if this happens, we'd better back off
483          * and stop holding the poor thing up
484          */
485         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
486         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
487
488         timeout = 0x10000;
489
490         while (1) {
491                 if ((readl(_IBMR(i2c)) & 2) == 2)
492                         break;
493
494                 timeout--;
495
496                 if (timeout <= 0) {
497                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
498                         break;
499                 }
500         }
501
502         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
503 }
504
505 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
506 {
507         if (i2c->msg)
508                 i2c_pxa_master_complete(i2c, I2C_RETRY);
509 }
510 #endif
511
512 /*
513  * PXA I2C Master mode
514  */
515
516 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
517 {
518         unsigned int addr = (msg->addr & 0x7f) << 1;
519
520         if (msg->flags & I2C_M_RD)
521                 addr |= 1;
522
523         return addr;
524 }
525
526 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
527 {
528         u32 icr;
529
530         /*
531          * Step 1: target slave address into IDBR
532          */
533         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
534
535         /*
536          * Step 2: initiate the write.
537          */
538         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
539         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
540 }
541
542 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
543 {
544         u32 icr;
545
546         /*
547          * Clear the STOP and ACK flags
548          */
549         icr = readl(_ICR(i2c));
550         icr &= ~(ICR_STOP | ICR_ACKNAK);
551         writel(icr, _IRC(i2c));
552 }
553
554 /*
555  * We are protected by the adapter bus mutex.
556  */
557 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
558 {
559         long timeout;
560         int ret;
561
562         /*
563          * Wait for the bus to become free.
564          */
565         ret = i2c_pxa_wait_bus_not_busy(i2c);
566         if (ret) {
567                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
568                 goto out;
569         }
570
571         /*
572          * Set master mode.
573          */
574         ret = i2c_pxa_set_master(i2c);
575         if (ret) {
576                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
577                 goto out;
578         }
579
580         spin_lock_irq(&i2c->lock);
581
582         i2c->msg = msg;
583         i2c->msg_num = num;
584         i2c->msg_idx = 0;
585         i2c->msg_ptr = 0;
586         i2c->irqlogidx = 0;
587
588         i2c_pxa_start_message(i2c);
589
590         spin_unlock_irq(&i2c->lock);
591
592         /*
593          * The rest of the processing occurs in the interrupt handler.
594          */
595         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
596         i2c_pxa_stop_message(i2c);
597
598         /*
599          * We place the return code in i2c->msg_idx.
600          */
601         ret = i2c->msg_idx;
602
603         if (timeout == 0)
604                 i2c_pxa_scream_blue_murder(i2c, "timeout");
605
606  out:
607         return ret;
608 }
609
610 /*
611  * i2c_pxa_master_complete - complete the message and wake up.
612  */
613 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
614 {
615         i2c->msg_ptr = 0;
616         i2c->msg = NULL;
617         i2c->msg_idx ++;
618         i2c->msg_num = 0;
619         if (ret)
620                 i2c->msg_idx = ret;
621         wake_up(&i2c->wait);
622 }
623
624 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
625 {
626         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
627
628  again:
629         /*
630          * If ISR_ALD is set, we lost arbitration.
631          */
632         if (isr & ISR_ALD) {
633                 /*
634                  * Do we need to do anything here?  The PXA docs
635                  * are vague about what happens.
636                  */
637                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
638
639                 /*
640                  * We ignore this error.  We seem to see spurious ALDs
641                  * for seemingly no reason.  If we handle them as I think
642                  * they should, we end up causing an I2C error, which
643                  * is painful for some systems.
644                  */
645                 return; /* ignore */
646         }
647
648         if (isr & ISR_BED) {
649                 int ret = BUS_ERROR;
650
651                 /*
652                  * I2C bus error - either the device NAK'd us, or
653                  * something more serious happened.  If we were NAK'd
654                  * on the initial address phase, we can retry.
655                  */
656                 if (isr & ISR_ACKNAK) {
657                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
658                                 ret = I2C_RETRY;
659                         else
660                                 ret = XFER_NAKED;
661                 }
662                 i2c_pxa_master_complete(i2c, ret);
663         } else if (isr & ISR_RWM) {
664                 /*
665                  * Read mode.  We have just sent the address byte, and
666                  * now we must initiate the transfer.
667                  */
668                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
669                     i2c->msg_idx == i2c->msg_num - 1)
670                         icr |= ICR_STOP | ICR_ACKNAK;
671
672                 icr |= ICR_ALDIE | ICR_TB;
673         } else if (i2c->msg_ptr < i2c->msg->len) {
674                 /*
675                  * Write mode.  Write the next data byte.
676                  */
677                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
678
679                 icr |= ICR_ALDIE | ICR_TB;
680
681                 /*
682                  * If this is the last byte of the last message, send
683                  * a STOP.
684                  */
685                 if (i2c->msg_ptr == i2c->msg->len &&
686                     i2c->msg_idx == i2c->msg_num - 1)
687                         icr |= ICR_STOP;
688         } else if (i2c->msg_idx < i2c->msg_num - 1) {
689                 /*
690                  * Next segment of the message.
691                  */
692                 i2c->msg_ptr = 0;
693                 i2c->msg_idx ++;
694                 i2c->msg++;
695
696                 /*
697                  * If we aren't doing a repeated start and address,
698                  * go back and try to send the next byte.  Note that
699                  * we do not support switching the R/W direction here.
700                  */
701                 if (i2c->msg->flags & I2C_M_NOSTART)
702                         goto again;
703
704                 /*
705                  * Write the next address.
706                  */
707                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
708
709                 /*
710                  * And trigger a repeated start, and send the byte.
711                  */
712                 icr &= ~ICR_ALDIE;
713                 icr |= ICR_START | ICR_TB;
714         } else {
715                 if (i2c->msg->len == 0) {
716                         /*
717                          * Device probes have a message length of zero
718                          * and need the bus to be reset before it can
719                          * be used again.
720                          */
721                         i2c_pxa_reset(i2c);
722                 }
723                 i2c_pxa_master_complete(i2c, 0);
724         }
725
726         i2c->icrlog[i2c->irqlogidx-1] = icr;
727
728         writel(icr, _ICR(i2c));
729         show_state(i2c);
730 }
731
732 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
733 {
734         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
735
736         /*
737          * Read the byte.
738          */
739         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
740
741         if (i2c->msg_ptr < i2c->msg->len) {
742                 /*
743                  * If this is the last byte of the last
744                  * message, send a STOP.
745                  */
746                 if (i2c->msg_ptr == i2c->msg->len - 1)
747                         icr |= ICR_STOP | ICR_ACKNAK;
748
749                 icr |= ICR_ALDIE | ICR_TB;
750         } else {
751                 i2c_pxa_master_complete(i2c, 0);
752         }
753
754         i2c->icrlog[i2c->irqlogidx-1] = icr;
755
756         writel(icr, _ICR(i2c));
757 }
758
759 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
760 {
761         struct pxa_i2c *i2c = dev_id;
762         u32 isr = readl(_ISR(i2c));
763
764         if (i2c_debug > 2 && 0) {
765                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
766                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
767                 decode_ISR(isr);
768         }
769
770         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
771                 i2c->isrlog[i2c->irqlogidx++] = isr;
772
773         show_state(i2c);
774
775         /*
776          * Always clear all pending IRQs.
777          */
778         writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
779
780         if (isr & ISR_SAD)
781                 i2c_pxa_slave_start(i2c, isr);
782         if (isr & ISR_SSD)
783                 i2c_pxa_slave_stop(i2c);
784
785         if (i2c_pxa_is_slavemode(i2c)) {
786                 if (isr & ISR_ITE)
787                         i2c_pxa_slave_txempty(i2c, isr);
788                 if (isr & ISR_IRF)
789                         i2c_pxa_slave_rxfull(i2c, isr);
790         } else if (i2c->msg) {
791                 if (isr & ISR_ITE)
792                         i2c_pxa_irq_txempty(i2c, isr);
793                 if (isr & ISR_IRF)
794                         i2c_pxa_irq_rxfull(i2c, isr);
795         } else {
796                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
797         }
798
799         return IRQ_HANDLED;
800 }
801
802
803 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
804 {
805         struct pxa_i2c *i2c = adap->algo_data;
806         int ret, i;
807
808         /* If the I2C controller is disabled we need to reset it (probably due
809            to a suspend/resume destroying state). We do this here as we can then
810            avoid worrying about resuming the controller before its users. */
811         if (!(readl(_ICR(i2c)) & ICR_IUE))
812                 i2c_pxa_reset(i2c);
813
814         for (i = adap->retries; i >= 0; i--) {
815                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
816                 if (ret != I2C_RETRY)
817                         goto out;
818
819                 if (i2c_debug)
820                         dev_dbg(&adap->dev, "Retrying transmission\n");
821                 udelay(100);
822         }
823         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
824         ret = -EREMOTEIO;
825  out:
826         i2c_pxa_set_slave(i2c, ret);
827         return ret;
828 }
829
830 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
831 {
832         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
833 }
834
835 static const struct i2c_algorithm i2c_pxa_algorithm = {
836         .master_xfer    = i2c_pxa_xfer,
837         .functionality  = i2c_pxa_functionality,
838 };
839
840 static struct pxa_i2c i2c_pxa = {
841         .lock   = __SPIN_LOCK_UNLOCKED(i2c_pxa.lock),
842         .adap   = {
843                 .owner          = THIS_MODULE,
844                 .algo           = &i2c_pxa_algorithm,
845                 .name           = "pxa2xx-i2c.0",
846                 .retries        = 5,
847         },
848 };
849
850 #define res_len(r)              ((r)->end - (r)->start + 1)
851 static int i2c_pxa_probe(struct platform_device *dev)
852 {
853         struct pxa_i2c *i2c = &i2c_pxa;
854         struct resource *res;
855         struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
856         int ret;
857         int irq;
858
859         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
860         irq = platform_get_irq(dev, 0);
861         if (res == NULL || irq < 0)
862                 return -ENODEV;
863
864         if (!request_mem_region(res->start, res_len(res), res->name))
865                 return -ENOMEM;
866
867         i2c = kmalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
868         if (!i2c) {
869                 ret = -ENOMEM;
870                 goto emalloc;
871         }
872
873         memcpy(i2c, &i2c_pxa, sizeof(struct pxa_i2c));
874         init_waitqueue_head(&i2c->wait);
875         i2c->adap.name[strlen(i2c->adap.name) - 1] = '0' + dev->id % 10;
876
877         i2c->reg_base = ioremap(res->start, res_len(res));
878         if (!i2c->reg_base) {
879                 ret = -EIO;
880                 goto eremap;
881         }
882
883         i2c->iobase = res->start;
884         i2c->iosize = res_len(res);
885
886         i2c->irq = irq;
887
888         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
889
890 #ifdef CONFIG_I2C_PXA_SLAVE
891         if (plat) {
892                 i2c->slave_addr = plat->slave_addr;
893                 i2c->slave = plat->slave;
894         }
895 #endif
896
897         switch (dev->id) {
898         case 0:
899 #ifdef CONFIG_PXA27x
900                 pxa_gpio_mode(GPIO117_I2CSCL_MD);
901                 pxa_gpio_mode(GPIO118_I2CSDA_MD);
902 #endif
903                 pxa_set_cken(CKEN_I2C, 1);
904                 break;
905 #ifdef CONFIG_PXA27x
906         case 1:
907                 local_irq_disable();
908                 PCFR |= PCFR_PI2CEN;
909                 local_irq_enable();
910                 pxa_set_cken(CKEN_PWRI2C, 1);
911 #endif
912         }
913
914         ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
915                           i2c->adap.name, i2c);
916         if (ret)
917                 goto ereqirq;
918
919
920         i2c_pxa_reset(i2c);
921
922         i2c->adap.algo_data = i2c;
923         i2c->adap.dev.parent = &dev->dev;
924
925         if (plat) {
926                 i2c->adap.class = plat->class;
927         }
928
929         ret = i2c_add_adapter(&i2c->adap);
930         if (ret < 0) {
931                 printk(KERN_INFO "I2C: Failed to add bus\n");
932                 goto eadapt;
933         }
934
935         platform_set_drvdata(dev, i2c);
936
937 #ifdef CONFIG_I2C_PXA_SLAVE
938         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
939                i2c->adap.dev.bus_id, i2c->slave_addr);
940 #else
941         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
942                i2c->adap.dev.bus_id);
943 #endif
944         return 0;
945
946 eadapt:
947         free_irq(irq, i2c);
948 ereqirq:
949         switch (dev->id) {
950         case 0:
951                 pxa_set_cken(CKEN_I2C, 0);
952                 break;
953 #ifdef CONFIG_PXA27x
954         case 1:
955                 pxa_set_cken(CKEN_PWRI2C, 0);
956                 local_irq_disable();
957                 PCFR &= ~PCFR_PI2CEN;
958                 local_irq_enable();
959 #endif
960         }
961 eremap:
962         kfree(i2c);
963 emalloc:
964         release_mem_region(res->start, res_len(res));
965         return ret;
966 }
967
968 static int i2c_pxa_remove(struct platform_device *dev)
969 {
970         struct pxa_i2c *i2c = platform_get_drvdata(dev);
971
972         platform_set_drvdata(dev, NULL);
973
974         i2c_del_adapter(&i2c->adap);
975         free_irq(i2c->irq, i2c);
976         switch (dev->id) {
977         case 0:
978                 pxa_set_cken(CKEN_I2C, 0);
979                 break;
980 #ifdef CONFIG_PXA27x
981         case 1:
982                 pxa_set_cken(CKEN_PWRI2C, 0);
983                 local_irq_disable();
984                 PCFR &= ~PCFR_PI2CEN;
985                 local_irq_enable();
986 #endif
987         }
988         release_mem_region(i2c->iobase, i2c->iosize);
989         kfree(i2c);
990
991         return 0;
992 }
993
994 static struct platform_driver i2c_pxa_driver = {
995         .probe          = i2c_pxa_probe,
996         .remove         = i2c_pxa_remove,
997         .driver         = {
998                 .name   = "pxa2xx-i2c",
999         },
1000 };
1001
1002 static int __init i2c_adap_pxa_init(void)
1003 {
1004         return platform_driver_register(&i2c_pxa_driver);
1005 }
1006
1007 static void i2c_adap_pxa_exit(void)
1008 {
1009         return platform_driver_unregister(&i2c_pxa_driver);
1010 }
1011
1012 MODULE_LICENSE("GPL");
1013
1014 module_init(i2c_adap_pxa_init);
1015 module_exit(i2c_adap_pxa_exit);