i2c/nuc900: add i2c driver support for nuc900
[sfrench/cifs-2.6.git] / drivers / i2c / busses / i2c-pxa.c
1 /*
2  *  i2c_adap_pxa.c
3  *
4  *  I2C adapter for the PXA I2C bus access.
5  *
6  *  Copyright (C) 2002 Intrinsyc Software Inc.
7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8  *
9  *  This program is free software; you can redistribute it and/or modify
10  *  it under the terms of the GNU General Public License version 2 as
11  *  published by the Free Software Foundation.
12  *
13  *  History:
14  *    Apr 2002: Initial version [CS]
15  *    Jun 2002: Properly separated algo/adap [FB]
16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20  *    Feb 2005: Rework slave mode handling [RMK]
21  */
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
36 #include <linux/slab.h>
37 #include <linux/io.h>
38
39 #include <asm/irq.h>
40 #include <plat/i2c.h>
41
42 /*
43  * I2C register offsets will be shifted 0 or 1 bit left, depending on
44  * different SoCs
45  */
46 #define REG_SHIFT_0     (0 << 0)
47 #define REG_SHIFT_1     (1 << 0)
48 #define REG_SHIFT(d)    ((d) & 0x1)
49
50 static const struct platform_device_id i2c_pxa_id_table[] = {
51         { "pxa2xx-i2c",         REG_SHIFT_1 },
52         { "pxa3xx-pwri2c",      REG_SHIFT_0 },
53         { },
54 };
55 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
56
57 /*
58  * I2C registers and bit definitions
59  */
60 #define IBMR            (0x00)
61 #define IDBR            (0x08)
62 #define ICR             (0x10)
63 #define ISR             (0x18)
64 #define ISAR            (0x20)
65
66 #define ICR_START       (1 << 0)           /* start bit */
67 #define ICR_STOP        (1 << 1)           /* stop bit */
68 #define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
69 #define ICR_TB          (1 << 3)           /* transfer byte bit */
70 #define ICR_MA          (1 << 4)           /* master abort */
71 #define ICR_SCLE        (1 << 5)           /* master clock enable */
72 #define ICR_IUE         (1 << 6)           /* unit enable */
73 #define ICR_GCD         (1 << 7)           /* general call disable */
74 #define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
75 #define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
76 #define ICR_BEIE        (1 << 10)          /* enable bus error ints */
77 #define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
78 #define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
79 #define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
80 #define ICR_UR          (1 << 14)          /* unit reset */
81 #define ICR_FM          (1 << 15)          /* fast mode */
82
83 #define ISR_RWM         (1 << 0)           /* read/write mode */
84 #define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
85 #define ISR_UB          (1 << 2)           /* unit busy */
86 #define ISR_IBB         (1 << 3)           /* bus busy */
87 #define ISR_SSD         (1 << 4)           /* slave stop detected */
88 #define ISR_ALD         (1 << 5)           /* arbitration loss detected */
89 #define ISR_ITE         (1 << 6)           /* tx buffer empty */
90 #define ISR_IRF         (1 << 7)           /* rx buffer full */
91 #define ISR_GCAD        (1 << 8)           /* general call address detected */
92 #define ISR_SAD         (1 << 9)           /* slave address detected */
93 #define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
94
95 struct pxa_i2c {
96         spinlock_t              lock;
97         wait_queue_head_t       wait;
98         struct i2c_msg          *msg;
99         unsigned int            msg_num;
100         unsigned int            msg_idx;
101         unsigned int            msg_ptr;
102         unsigned int            slave_addr;
103
104         struct i2c_adapter      adap;
105         struct clk              *clk;
106 #ifdef CONFIG_I2C_PXA_SLAVE
107         struct i2c_slave_client *slave;
108 #endif
109
110         unsigned int            irqlogidx;
111         u32                     isrlog[32];
112         u32                     icrlog[32];
113
114         void __iomem            *reg_base;
115         unsigned int            reg_shift;
116
117         unsigned long           iobase;
118         unsigned long           iosize;
119
120         int                     irq;
121         unsigned int            use_pio :1;
122         unsigned int            fast_mode :1;
123 };
124
125 #define _IBMR(i2c)      ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
126 #define _IDBR(i2c)      ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
127 #define _ICR(i2c)       ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
128 #define _ISR(i2c)       ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
129 #define _ISAR(i2c)      ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
130
131 /*
132  * I2C Slave mode address
133  */
134 #define I2C_PXA_SLAVE_ADDR      0x1
135
136 #ifdef DEBUG
137
138 struct bits {
139         u32     mask;
140         const char *set;
141         const char *unset;
142 };
143 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
144
145 static inline void
146 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
147 {
148         printk("%s %08x: ", prefix, val);
149         while (num--) {
150                 const char *str = val & bits->mask ? bits->set : bits->unset;
151                 if (str)
152                         printk("%s ", str);
153                 bits++;
154         }
155 }
156
157 static const struct bits isr_bits[] = {
158         PXA_BIT(ISR_RWM,        "RX",           "TX"),
159         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
160         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
161         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
162         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
163         PXA_BIT(ISR_ALD,        "ALD",          NULL),
164         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
165         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
166         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
167         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
168         PXA_BIT(ISR_BED,        "BusErr",       NULL),
169 };
170
171 static void decode_ISR(unsigned int val)
172 {
173         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
174         printk("\n");
175 }
176
177 static const struct bits icr_bits[] = {
178         PXA_BIT(ICR_START,  "START",    NULL),
179         PXA_BIT(ICR_STOP,   "STOP",     NULL),
180         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
181         PXA_BIT(ICR_TB,     "TB",       NULL),
182         PXA_BIT(ICR_MA,     "MA",       NULL),
183         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
184         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
185         PXA_BIT(ICR_GCD,    "GCD",      NULL),
186         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
187         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
188         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
189         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
190         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
191         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
192         PXA_BIT(ICR_UR,     "UR",               "ur"),
193 };
194
195 #ifdef CONFIG_I2C_PXA_SLAVE
196 static void decode_ICR(unsigned int val)
197 {
198         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
199         printk("\n");
200 }
201 #endif
202
203 static unsigned int i2c_debug = DEBUG;
204
205 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
206 {
207         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
208                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
209 }
210
211 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
212
213 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
214 {
215         unsigned int i;
216         printk(KERN_ERR "i2c: error: %s\n", why);
217         printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
218                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
219         printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n",
220                readl(_ICR(i2c)), readl(_ISR(i2c)));
221         printk(KERN_DEBUG "i2c: log: ");
222         for (i = 0; i < i2c->irqlogidx; i++)
223                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
224         printk("\n");
225 }
226
227 #else /* ifdef DEBUG */
228
229 #define i2c_debug       0
230
231 #define show_state(i2c) do { } while (0)
232 #define decode_ISR(val) do { } while (0)
233 #define decode_ICR(val) do { } while (0)
234 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
235
236 #endif /* ifdef DEBUG / else */
237
238 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
239 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
240
241 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
242 {
243         return !(readl(_ICR(i2c)) & ICR_SCLE);
244 }
245
246 static void i2c_pxa_abort(struct pxa_i2c *i2c)
247 {
248         int i = 250;
249
250         if (i2c_pxa_is_slavemode(i2c)) {
251                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
252                 return;
253         }
254
255         while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
256                 unsigned long icr = readl(_ICR(i2c));
257
258                 icr &= ~ICR_START;
259                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
260
261                 writel(icr, _ICR(i2c));
262
263                 show_state(i2c);
264
265                 mdelay(1);
266                 i --;
267         }
268
269         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
270                _ICR(i2c));
271 }
272
273 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
274 {
275         int timeout = DEF_TIMEOUT;
276
277         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
278                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
279                         timeout += 4;
280
281                 msleep(2);
282                 show_state(i2c);
283         }
284
285         if (timeout < 0)
286                 show_state(i2c);
287
288         return timeout < 0 ? I2C_RETRY : 0;
289 }
290
291 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
292 {
293         unsigned long timeout = jiffies + HZ*4;
294
295         while (time_before(jiffies, timeout)) {
296                 if (i2c_debug > 1)
297                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
298                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
299
300                 if (readl(_ISR(i2c)) & ISR_SAD) {
301                         if (i2c_debug > 0)
302                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
303                         goto out;
304                 }
305
306                 /* wait for unit and bus being not busy, and we also do a
307                  * quick check of the i2c lines themselves to ensure they've
308                  * gone high...
309                  */
310                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
311                         if (i2c_debug > 0)
312                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
313                         return 1;
314                 }
315
316                 msleep(1);
317         }
318
319         if (i2c_debug > 0)
320                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
321  out:
322         return 0;
323 }
324
325 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
326 {
327         if (i2c_debug)
328                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
329
330         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
331                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
332                 if (!i2c_pxa_wait_master(i2c)) {
333                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
334                         return I2C_RETRY;
335                 }
336         }
337
338         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
339         return 0;
340 }
341
342 #ifdef CONFIG_I2C_PXA_SLAVE
343 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
344 {
345         unsigned long timeout = jiffies + HZ*1;
346
347         /* wait for stop */
348
349         show_state(i2c);
350
351         while (time_before(jiffies, timeout)) {
352                 if (i2c_debug > 1)
353                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
354                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
355
356                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
357                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
358                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
359                         if (i2c_debug > 1)
360                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
361                         return 1;
362                 }
363
364                 msleep(1);
365         }
366
367         if (i2c_debug > 0)
368                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
369         return 0;
370 }
371
372 /*
373  * clear the hold on the bus, and take of anything else
374  * that has been configured
375  */
376 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
377 {
378         show_state(i2c);
379
380         if (errcode < 0) {
381                 udelay(100);   /* simple delay */
382         } else {
383                 /* we need to wait for the stop condition to end */
384
385                 /* if we where in stop, then clear... */
386                 if (readl(_ICR(i2c)) & ICR_STOP) {
387                         udelay(100);
388                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
389                 }
390
391                 if (!i2c_pxa_wait_slave(i2c)) {
392                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
393                                 __func__);
394                         return;
395                 }
396         }
397
398         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
399         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
400
401         if (i2c_debug) {
402                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
403                 decode_ICR(readl(_ICR(i2c)));
404         }
405 }
406 #else
407 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
408 #endif
409
410 static void i2c_pxa_reset(struct pxa_i2c *i2c)
411 {
412         pr_debug("Resetting I2C Controller Unit\n");
413
414         /* abort any transfer currently under way */
415         i2c_pxa_abort(i2c);
416
417         /* reset according to 9.8 */
418         writel(ICR_UR, _ICR(i2c));
419         writel(I2C_ISR_INIT, _ISR(i2c));
420         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
421
422         writel(i2c->slave_addr, _ISAR(i2c));
423
424         /* set control register values */
425         writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
426
427 #ifdef CONFIG_I2C_PXA_SLAVE
428         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
429         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
430 #endif
431
432         i2c_pxa_set_slave(i2c, 0);
433
434         /* enable unit */
435         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
436         udelay(100);
437 }
438
439
440 #ifdef CONFIG_I2C_PXA_SLAVE
441 /*
442  * PXA I2C Slave mode
443  */
444
445 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
446 {
447         if (isr & ISR_BED) {
448                 /* what should we do here? */
449         } else {
450                 int ret = 0;
451
452                 if (i2c->slave != NULL)
453                         ret = i2c->slave->read(i2c->slave->data);
454
455                 writel(ret, _IDBR(i2c));
456                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
457         }
458 }
459
460 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
461 {
462         unsigned int byte = readl(_IDBR(i2c));
463
464         if (i2c->slave != NULL)
465                 i2c->slave->write(i2c->slave->data, byte);
466
467         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
468 }
469
470 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
471 {
472         int timeout;
473
474         if (i2c_debug > 0)
475                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
476                        (isr & ISR_RWM) ? 'r' : 't');
477
478         if (i2c->slave != NULL)
479                 i2c->slave->event(i2c->slave->data,
480                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
481
482         /*
483          * slave could interrupt in the middle of us generating a
484          * start condition... if this happens, we'd better back off
485          * and stop holding the poor thing up
486          */
487         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
488         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
489
490         timeout = 0x10000;
491
492         while (1) {
493                 if ((readl(_IBMR(i2c)) & 2) == 2)
494                         break;
495
496                 timeout--;
497
498                 if (timeout <= 0) {
499                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
500                         break;
501                 }
502         }
503
504         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
505 }
506
507 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
508 {
509         if (i2c_debug > 2)
510                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
511
512         if (i2c->slave != NULL)
513                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
514
515         if (i2c_debug > 2)
516                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
517
518         /*
519          * If we have a master-mode message waiting,
520          * kick it off now that the slave has completed.
521          */
522         if (i2c->msg)
523                 i2c_pxa_master_complete(i2c, I2C_RETRY);
524 }
525 #else
526 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
527 {
528         if (isr & ISR_BED) {
529                 /* what should we do here? */
530         } else {
531                 writel(0, _IDBR(i2c));
532                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
533         }
534 }
535
536 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
537 {
538         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
539 }
540
541 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
542 {
543         int timeout;
544
545         /*
546          * slave could interrupt in the middle of us generating a
547          * start condition... if this happens, we'd better back off
548          * and stop holding the poor thing up
549          */
550         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
551         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
552
553         timeout = 0x10000;
554
555         while (1) {
556                 if ((readl(_IBMR(i2c)) & 2) == 2)
557                         break;
558
559                 timeout--;
560
561                 if (timeout <= 0) {
562                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
563                         break;
564                 }
565         }
566
567         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
568 }
569
570 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
571 {
572         if (i2c->msg)
573                 i2c_pxa_master_complete(i2c, I2C_RETRY);
574 }
575 #endif
576
577 /*
578  * PXA I2C Master mode
579  */
580
581 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
582 {
583         unsigned int addr = (msg->addr & 0x7f) << 1;
584
585         if (msg->flags & I2C_M_RD)
586                 addr |= 1;
587
588         return addr;
589 }
590
591 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
592 {
593         u32 icr;
594
595         /*
596          * Step 1: target slave address into IDBR
597          */
598         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
599
600         /*
601          * Step 2: initiate the write.
602          */
603         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
604         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
605 }
606
607 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
608 {
609         u32 icr;
610
611         /*
612          * Clear the STOP and ACK flags
613          */
614         icr = readl(_ICR(i2c));
615         icr &= ~(ICR_STOP | ICR_ACKNAK);
616         writel(icr, _ICR(i2c));
617 }
618
619 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
620 {
621         /* make timeout the same as for interrupt based functions */
622         long timeout = 2 * DEF_TIMEOUT;
623
624         /*
625          * Wait for the bus to become free.
626          */
627         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
628                 udelay(1000);
629                 show_state(i2c);
630         }
631
632         if (timeout < 0) {
633                 show_state(i2c);
634                 dev_err(&i2c->adap.dev,
635                         "i2c_pxa: timeout waiting for bus free\n");
636                 return I2C_RETRY;
637         }
638
639         /*
640          * Set master mode.
641          */
642         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
643
644         return 0;
645 }
646
647 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
648                                struct i2c_msg *msg, int num)
649 {
650         unsigned long timeout = 500000; /* 5 seconds */
651         int ret = 0;
652
653         ret = i2c_pxa_pio_set_master(i2c);
654         if (ret)
655                 goto out;
656
657         i2c->msg = msg;
658         i2c->msg_num = num;
659         i2c->msg_idx = 0;
660         i2c->msg_ptr = 0;
661         i2c->irqlogidx = 0;
662
663         i2c_pxa_start_message(i2c);
664
665         while (i2c->msg_num > 0 && --timeout) {
666                 i2c_pxa_handler(0, i2c);
667                 udelay(10);
668         }
669
670         i2c_pxa_stop_message(i2c);
671
672         /*
673          * We place the return code in i2c->msg_idx.
674          */
675         ret = i2c->msg_idx;
676
677 out:
678         if (timeout == 0)
679                 i2c_pxa_scream_blue_murder(i2c, "timeout");
680
681         return ret;
682 }
683
684 /*
685  * We are protected by the adapter bus mutex.
686  */
687 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
688 {
689         long timeout;
690         int ret;
691
692         /*
693          * Wait for the bus to become free.
694          */
695         ret = i2c_pxa_wait_bus_not_busy(i2c);
696         if (ret) {
697                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
698                 goto out;
699         }
700
701         /*
702          * Set master mode.
703          */
704         ret = i2c_pxa_set_master(i2c);
705         if (ret) {
706                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
707                 goto out;
708         }
709
710         spin_lock_irq(&i2c->lock);
711
712         i2c->msg = msg;
713         i2c->msg_num = num;
714         i2c->msg_idx = 0;
715         i2c->msg_ptr = 0;
716         i2c->irqlogidx = 0;
717
718         i2c_pxa_start_message(i2c);
719
720         spin_unlock_irq(&i2c->lock);
721
722         /*
723          * The rest of the processing occurs in the interrupt handler.
724          */
725         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
726         i2c_pxa_stop_message(i2c);
727
728         /*
729          * We place the return code in i2c->msg_idx.
730          */
731         ret = i2c->msg_idx;
732
733         if (timeout == 0)
734                 i2c_pxa_scream_blue_murder(i2c, "timeout");
735
736  out:
737         return ret;
738 }
739
740 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
741                             struct i2c_msg msgs[], int num)
742 {
743         struct pxa_i2c *i2c = adap->algo_data;
744         int ret, i;
745
746         /* If the I2C controller is disabled we need to reset it
747           (probably due to a suspend/resume destroying state). We do
748           this here as we can then avoid worrying about resuming the
749           controller before its users. */
750         if (!(readl(_ICR(i2c)) & ICR_IUE))
751                 i2c_pxa_reset(i2c);
752
753         for (i = adap->retries; i >= 0; i--) {
754                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
755                 if (ret != I2C_RETRY)
756                         goto out;
757
758                 if (i2c_debug)
759                         dev_dbg(&adap->dev, "Retrying transmission\n");
760                 udelay(100);
761         }
762         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
763         ret = -EREMOTEIO;
764  out:
765         i2c_pxa_set_slave(i2c, ret);
766         return ret;
767 }
768
769 /*
770  * i2c_pxa_master_complete - complete the message and wake up.
771  */
772 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
773 {
774         i2c->msg_ptr = 0;
775         i2c->msg = NULL;
776         i2c->msg_idx ++;
777         i2c->msg_num = 0;
778         if (ret)
779                 i2c->msg_idx = ret;
780         if (!i2c->use_pio)
781                 wake_up(&i2c->wait);
782 }
783
784 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
785 {
786         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
787
788  again:
789         /*
790          * If ISR_ALD is set, we lost arbitration.
791          */
792         if (isr & ISR_ALD) {
793                 /*
794                  * Do we need to do anything here?  The PXA docs
795                  * are vague about what happens.
796                  */
797                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
798
799                 /*
800                  * We ignore this error.  We seem to see spurious ALDs
801                  * for seemingly no reason.  If we handle them as I think
802                  * they should, we end up causing an I2C error, which
803                  * is painful for some systems.
804                  */
805                 return; /* ignore */
806         }
807
808         if (isr & ISR_BED) {
809                 int ret = BUS_ERROR;
810
811                 /*
812                  * I2C bus error - either the device NAK'd us, or
813                  * something more serious happened.  If we were NAK'd
814                  * on the initial address phase, we can retry.
815                  */
816                 if (isr & ISR_ACKNAK) {
817                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
818                                 ret = I2C_RETRY;
819                         else
820                                 ret = XFER_NAKED;
821                 }
822                 i2c_pxa_master_complete(i2c, ret);
823         } else if (isr & ISR_RWM) {
824                 /*
825                  * Read mode.  We have just sent the address byte, and
826                  * now we must initiate the transfer.
827                  */
828                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
829                     i2c->msg_idx == i2c->msg_num - 1)
830                         icr |= ICR_STOP | ICR_ACKNAK;
831
832                 icr |= ICR_ALDIE | ICR_TB;
833         } else if (i2c->msg_ptr < i2c->msg->len) {
834                 /*
835                  * Write mode.  Write the next data byte.
836                  */
837                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
838
839                 icr |= ICR_ALDIE | ICR_TB;
840
841                 /*
842                  * If this is the last byte of the last message, send
843                  * a STOP.
844                  */
845                 if (i2c->msg_ptr == i2c->msg->len &&
846                     i2c->msg_idx == i2c->msg_num - 1)
847                         icr |= ICR_STOP;
848         } else if (i2c->msg_idx < i2c->msg_num - 1) {
849                 /*
850                  * Next segment of the message.
851                  */
852                 i2c->msg_ptr = 0;
853                 i2c->msg_idx ++;
854                 i2c->msg++;
855
856                 /*
857                  * If we aren't doing a repeated start and address,
858                  * go back and try to send the next byte.  Note that
859                  * we do not support switching the R/W direction here.
860                  */
861                 if (i2c->msg->flags & I2C_M_NOSTART)
862                         goto again;
863
864                 /*
865                  * Write the next address.
866                  */
867                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
868
869                 /*
870                  * And trigger a repeated start, and send the byte.
871                  */
872                 icr &= ~ICR_ALDIE;
873                 icr |= ICR_START | ICR_TB;
874         } else {
875                 if (i2c->msg->len == 0) {
876                         /*
877                          * Device probes have a message length of zero
878                          * and need the bus to be reset before it can
879                          * be used again.
880                          */
881                         i2c_pxa_reset(i2c);
882                 }
883                 i2c_pxa_master_complete(i2c, 0);
884         }
885
886         i2c->icrlog[i2c->irqlogidx-1] = icr;
887
888         writel(icr, _ICR(i2c));
889         show_state(i2c);
890 }
891
892 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
893 {
894         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
895
896         /*
897          * Read the byte.
898          */
899         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
900
901         if (i2c->msg_ptr < i2c->msg->len) {
902                 /*
903                  * If this is the last byte of the last
904                  * message, send a STOP.
905                  */
906                 if (i2c->msg_ptr == i2c->msg->len - 1)
907                         icr |= ICR_STOP | ICR_ACKNAK;
908
909                 icr |= ICR_ALDIE | ICR_TB;
910         } else {
911                 i2c_pxa_master_complete(i2c, 0);
912         }
913
914         i2c->icrlog[i2c->irqlogidx-1] = icr;
915
916         writel(icr, _ICR(i2c));
917 }
918
919 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
920 {
921         struct pxa_i2c *i2c = dev_id;
922         u32 isr = readl(_ISR(i2c));
923
924         if (i2c_debug > 2 && 0) {
925                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
926                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
927                 decode_ISR(isr);
928         }
929
930         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
931                 i2c->isrlog[i2c->irqlogidx++] = isr;
932
933         show_state(i2c);
934
935         /*
936          * Always clear all pending IRQs.
937          */
938         writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
939
940         if (isr & ISR_SAD)
941                 i2c_pxa_slave_start(i2c, isr);
942         if (isr & ISR_SSD)
943                 i2c_pxa_slave_stop(i2c);
944
945         if (i2c_pxa_is_slavemode(i2c)) {
946                 if (isr & ISR_ITE)
947                         i2c_pxa_slave_txempty(i2c, isr);
948                 if (isr & ISR_IRF)
949                         i2c_pxa_slave_rxfull(i2c, isr);
950         } else if (i2c->msg) {
951                 if (isr & ISR_ITE)
952                         i2c_pxa_irq_txempty(i2c, isr);
953                 if (isr & ISR_IRF)
954                         i2c_pxa_irq_rxfull(i2c, isr);
955         } else {
956                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
957         }
958
959         return IRQ_HANDLED;
960 }
961
962
963 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
964 {
965         struct pxa_i2c *i2c = adap->algo_data;
966         int ret, i;
967
968         for (i = adap->retries; i >= 0; i--) {
969                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
970                 if (ret != I2C_RETRY)
971                         goto out;
972
973                 if (i2c_debug)
974                         dev_dbg(&adap->dev, "Retrying transmission\n");
975                 udelay(100);
976         }
977         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
978         ret = -EREMOTEIO;
979  out:
980         i2c_pxa_set_slave(i2c, ret);
981         return ret;
982 }
983
984 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
985 {
986         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
987 }
988
989 static const struct i2c_algorithm i2c_pxa_algorithm = {
990         .master_xfer    = i2c_pxa_xfer,
991         .functionality  = i2c_pxa_functionality,
992 };
993
994 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
995         .master_xfer    = i2c_pxa_pio_xfer,
996         .functionality  = i2c_pxa_functionality,
997 };
998
999 static int i2c_pxa_probe(struct platform_device *dev)
1000 {
1001         struct pxa_i2c *i2c;
1002         struct resource *res;
1003         struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
1004         struct platform_device_id *id = platform_get_device_id(dev);
1005         int ret;
1006         int irq;
1007
1008         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1009         irq = platform_get_irq(dev, 0);
1010         if (res == NULL || irq < 0)
1011                 return -ENODEV;
1012
1013         if (!request_mem_region(res->start, resource_size(res), res->name))
1014                 return -ENOMEM;
1015
1016         i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
1017         if (!i2c) {
1018                 ret = -ENOMEM;
1019                 goto emalloc;
1020         }
1021
1022         i2c->adap.owner   = THIS_MODULE;
1023         i2c->adap.retries = 5;
1024
1025         spin_lock_init(&i2c->lock);
1026         init_waitqueue_head(&i2c->wait);
1027
1028         /*
1029          * If "dev->id" is negative we consider it as zero.
1030          * The reason to do so is to avoid sysfs names that only make
1031          * sense when there are multiple adapters.
1032          */
1033         i2c->adap.nr = dev->id != -1 ? dev->id : 0;
1034         snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
1035                  i2c->adap.nr);
1036
1037         i2c->clk = clk_get(&dev->dev, NULL);
1038         if (IS_ERR(i2c->clk)) {
1039                 ret = PTR_ERR(i2c->clk);
1040                 goto eclk;
1041         }
1042
1043         i2c->reg_base = ioremap(res->start, resource_size(res));
1044         if (!i2c->reg_base) {
1045                 ret = -EIO;
1046                 goto eremap;
1047         }
1048         i2c->reg_shift = REG_SHIFT(id->driver_data);
1049
1050         i2c->iobase = res->start;
1051         i2c->iosize = resource_size(res);
1052
1053         i2c->irq = irq;
1054
1055         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1056
1057 #ifdef CONFIG_I2C_PXA_SLAVE
1058         if (plat) {
1059                 i2c->slave_addr = plat->slave_addr;
1060                 i2c->slave = plat->slave;
1061         }
1062 #endif
1063
1064         clk_enable(i2c->clk);
1065
1066         if (plat) {
1067                 i2c->adap.class = plat->class;
1068                 i2c->use_pio = plat->use_pio;
1069                 i2c->fast_mode = plat->fast_mode;
1070         }
1071
1072         if (i2c->use_pio) {
1073                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1074         } else {
1075                 i2c->adap.algo = &i2c_pxa_algorithm;
1076                 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1077                                   i2c->adap.name, i2c);
1078                 if (ret)
1079                         goto ereqirq;
1080         }
1081
1082         i2c_pxa_reset(i2c);
1083
1084         i2c->adap.algo_data = i2c;
1085         i2c->adap.dev.parent = &dev->dev;
1086
1087         ret = i2c_add_numbered_adapter(&i2c->adap);
1088         if (ret < 0) {
1089                 printk(KERN_INFO "I2C: Failed to add bus\n");
1090                 goto eadapt;
1091         }
1092
1093         platform_set_drvdata(dev, i2c);
1094
1095 #ifdef CONFIG_I2C_PXA_SLAVE
1096         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1097                dev_name(&i2c->adap.dev), i2c->slave_addr);
1098 #else
1099         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1100                dev_name(&i2c->adap.dev));
1101 #endif
1102         return 0;
1103
1104 eadapt:
1105         if (!i2c->use_pio)
1106                 free_irq(irq, i2c);
1107 ereqirq:
1108         clk_disable(i2c->clk);
1109         iounmap(i2c->reg_base);
1110 eremap:
1111         clk_put(i2c->clk);
1112 eclk:
1113         kfree(i2c);
1114 emalloc:
1115         release_mem_region(res->start, resource_size(res));
1116         return ret;
1117 }
1118
1119 static int __exit i2c_pxa_remove(struct platform_device *dev)
1120 {
1121         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1122
1123         platform_set_drvdata(dev, NULL);
1124
1125         i2c_del_adapter(&i2c->adap);
1126         if (!i2c->use_pio)
1127                 free_irq(i2c->irq, i2c);
1128
1129         clk_disable(i2c->clk);
1130         clk_put(i2c->clk);
1131
1132         iounmap(i2c->reg_base);
1133         release_mem_region(i2c->iobase, i2c->iosize);
1134         kfree(i2c);
1135
1136         return 0;
1137 }
1138
1139 #ifdef CONFIG_PM
1140 static int i2c_pxa_suspend_noirq(struct device *dev)
1141 {
1142         struct platform_device *pdev = to_platform_device(dev);
1143         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1144
1145         clk_disable(i2c->clk);
1146
1147         return 0;
1148 }
1149
1150 static int i2c_pxa_resume_noirq(struct device *dev)
1151 {
1152         struct platform_device *pdev = to_platform_device(dev);
1153         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1154
1155         clk_enable(i2c->clk);
1156         i2c_pxa_reset(i2c);
1157
1158         return 0;
1159 }
1160
1161 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1162         .suspend_noirq = i2c_pxa_suspend_noirq,
1163         .resume_noirq = i2c_pxa_resume_noirq,
1164 };
1165
1166 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1167 #else
1168 #define I2C_PXA_DEV_PM_OPS NULL
1169 #endif
1170
1171 static struct platform_driver i2c_pxa_driver = {
1172         .probe          = i2c_pxa_probe,
1173         .remove         = __exit_p(i2c_pxa_remove),
1174         .driver         = {
1175                 .name   = "pxa2xx-i2c",
1176                 .owner  = THIS_MODULE,
1177                 .pm     = I2C_PXA_DEV_PM_OPS,
1178         },
1179         .id_table       = i2c_pxa_id_table,
1180 };
1181
1182 static int __init i2c_adap_pxa_init(void)
1183 {
1184         return platform_driver_register(&i2c_pxa_driver);
1185 }
1186
1187 static void __exit i2c_adap_pxa_exit(void)
1188 {
1189         platform_driver_unregister(&i2c_pxa_driver);
1190 }
1191
1192 MODULE_LICENSE("GPL");
1193 MODULE_ALIAS("platform:pxa2xx-i2c");
1194
1195 subsys_initcall(i2c_adap_pxa_init);
1196 module_exit(i2c_adap_pxa_exit);