2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
3 Philip Edelbrock <phil@netroedge.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
19 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
20 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
25 Note: we assume there can only be one device, with one or more
27 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
28 For devices supporting multiple ports the i2c_adapter should provide
29 an i2c_algorithm to access them.
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/pci.h>
35 #include <linux/kernel.h>
36 #include <linux/delay.h>
37 #include <linux/stddef.h>
38 #include <linux/ioport.h>
39 #include <linux/i2c.h>
40 #include <linux/slab.h>
41 #include <linux/dmi.h>
42 #include <linux/acpi.h>
46 /* PIIX4 SMBus address offsets */
47 #define SMBHSTSTS (0 + piix4_smba)
48 #define SMBHSLVSTS (1 + piix4_smba)
49 #define SMBHSTCNT (2 + piix4_smba)
50 #define SMBHSTCMD (3 + piix4_smba)
51 #define SMBHSTADD (4 + piix4_smba)
52 #define SMBHSTDAT0 (5 + piix4_smba)
53 #define SMBHSTDAT1 (6 + piix4_smba)
54 #define SMBBLKDAT (7 + piix4_smba)
55 #define SMBSLVCNT (8 + piix4_smba)
56 #define SMBSHDWCMD (9 + piix4_smba)
57 #define SMBSLVEVT (0xA + piix4_smba)
58 #define SMBSLVDAT (0xC + piix4_smba)
60 /* count for request_region */
63 /* PCI Address Constants */
65 #define SMBHSTCFG 0x0D2
67 #define SMBSHDW1 0x0D4
68 #define SMBSHDW2 0x0D5
72 #define MAX_TIMEOUT 500
76 #define PIIX4_QUICK 0x00
77 #define PIIX4_BYTE 0x04
78 #define PIIX4_BYTE_DATA 0x08
79 #define PIIX4_WORD_DATA 0x0C
80 #define PIIX4_BLOCK_DATA 0x14
82 /* Multi-port constants */
83 #define PIIX4_MAX_ADAPTERS 4
86 #define SB800_PIIX4_SMB_IDX 0xcd6
88 #define KERNCZ_IMC_IDX 0x3e
89 #define KERNCZ_IMC_DATA 0x3f
92 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
93 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
94 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
96 #define SB800_PIIX4_PORT_IDX 0x2c
97 #define SB800_PIIX4_PORT_IDX_ALT 0x2e
98 #define SB800_PIIX4_PORT_IDX_SEL 0x2f
99 #define SB800_PIIX4_PORT_IDX_MASK 0x06
100 #define SB800_PIIX4_PORT_IDX_SHIFT 1
102 /* On kerncz, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
103 #define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
104 #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
105 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
107 /* insmod parameters */
109 /* If force is set to anything different from 0, we forcibly enable the
112 module_param (force, int, 0);
113 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
115 /* If force_addr is set to anything different from 0, we forcibly enable
116 the PIIX4 at the given address. VERY DANGEROUS! */
117 static int force_addr;
118 module_param_hw(force_addr, int, ioport, 0);
119 MODULE_PARM_DESC(force_addr,
120 "Forcibly enable the PIIX4 at the given address. "
121 "EXTREMELY DANGEROUS!");
123 static int srvrworks_csb5_delay;
124 static struct pci_driver piix4_driver;
126 static const struct dmi_system_id piix4_dmi_blacklist[] = {
128 .ident = "Sapphire AM2RD790",
130 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
131 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
135 .ident = "DFI Lanparty UT 790FX",
137 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
138 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
144 /* The IBM entry is in a separate table because we only check it
145 on Intel-based systems */
146 static const struct dmi_system_id piix4_dmi_ibm[] = {
149 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
157 static u8 piix4_port_sel_sb800;
158 static u8 piix4_port_mask_sb800;
159 static u8 piix4_port_shift_sb800;
160 static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
161 " port 0", " port 2", " port 3", " port 4"
163 static const char *piix4_aux_port_name_sb800 = " port 1";
165 struct i2c_piix4_adapdata {
171 u8 port; /* Port number, shifted */
174 static int piix4_setup(struct pci_dev *PIIX4_dev,
175 const struct pci_device_id *id)
178 unsigned short piix4_smba;
180 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
181 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
182 srvrworks_csb5_delay = 1;
184 /* On some motherboards, it was reported that accessing the SMBus
185 caused severe hardware problems */
186 if (dmi_check_system(piix4_dmi_blacklist)) {
187 dev_err(&PIIX4_dev->dev,
188 "Accessing the SMBus on this system is unsafe!\n");
192 /* Don't access SMBus on IBM systems which get corrupted eeproms */
193 if (dmi_check_system(piix4_dmi_ibm) &&
194 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
195 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
196 "may corrupt your serial eeprom! Refusing to load "
201 /* Determine the address of the SMBus areas */
203 piix4_smba = force_addr & 0xfff0;
206 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
207 piix4_smba &= 0xfff0;
208 if(piix4_smba == 0) {
209 dev_err(&PIIX4_dev->dev, "SMBus base address "
210 "uninitialized - upgrade BIOS or use "
211 "force_addr=0xaddr\n");
216 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
219 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
220 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
225 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
227 /* If force_addr is set, we program the new address here. Just to make
228 sure, we disable the PIIX4 first. */
230 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
231 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
232 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
233 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
234 "new address %04x!\n", piix4_smba);
235 } else if ((temp & 1) == 0) {
237 /* This should never need to be done, but has been
238 * noted that many Dell machines have the SMBus
239 * interface on the PIIX4 disabled!? NOTE: This assumes
240 * I/O space and other allocations WERE done by the
241 * Bios! Don't complain if your hardware does weird
242 * things after enabling this. :') Check for Bios
243 * updates before resorting to this.
245 pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
247 dev_notice(&PIIX4_dev->dev,
248 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
250 dev_err(&PIIX4_dev->dev,
251 "SMBus Host Controller not enabled!\n");
252 release_region(piix4_smba, SMBIOSIZE);
257 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
258 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
259 else if ((temp & 0x0E) == 0)
260 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
262 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
263 "(or code out of date)!\n");
265 pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
266 dev_info(&PIIX4_dev->dev,
267 "SMBus Host Controller at 0x%x, revision %d\n",
273 static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
274 const struct pci_device_id *id, u8 aux)
276 unsigned short piix4_smba;
277 u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel;
278 u8 i2ccfg, i2ccfg_offset = 0x10;
280 /* SB800 and later SMBus does not support forcing address */
281 if (force || force_addr) {
282 dev_err(&PIIX4_dev->dev, "SMBus does not support "
283 "forcing address!\n");
287 /* Determine the address of the SMBus areas */
288 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
289 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
290 PIIX4_dev->revision >= 0x41) ||
291 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
292 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
293 PIIX4_dev->revision >= 0x49) ||
294 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
295 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
298 smb_en = (aux) ? 0x28 : 0x2c;
300 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) {
301 dev_err(&PIIX4_dev->dev,
302 "SMB base address index region 0x%x already in use.\n",
303 SB800_PIIX4_SMB_IDX);
307 outb_p(smb_en, SB800_PIIX4_SMB_IDX);
308 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
309 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
310 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
312 release_region(SB800_PIIX4_SMB_IDX, 2);
315 smb_en_status = smba_en_lo & 0x10;
316 piix4_smba = smba_en_hi << 8;
320 smb_en_status = smba_en_lo & 0x01;
321 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
324 if (!smb_en_status) {
325 dev_err(&PIIX4_dev->dev,
326 "SMBus Host Controller not enabled!\n");
330 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
333 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
334 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
339 /* Aux SMBus does not support IRQ information */
341 dev_info(&PIIX4_dev->dev,
342 "Auxiliary SMBus Host Controller at 0x%x\n",
347 /* Request the SMBus I2C bus config region */
348 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
349 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
350 "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
351 release_region(piix4_smba, SMBIOSIZE);
354 i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
355 release_region(piix4_smba + i2ccfg_offset, 1);
358 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
360 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
362 dev_info(&PIIX4_dev->dev,
363 "SMBus Host Controller at 0x%x, revision %d\n",
364 piix4_smba, i2ccfg >> 4);
366 /* Find which register is used for port selection */
367 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
368 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
369 switch (PIIX4_dev->device) {
370 case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS:
371 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
372 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
373 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
375 case PCI_DEVICE_ID_AMD_HUDSON2_SMBUS:
377 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
378 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
379 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
383 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2,
384 "sb800_piix4_smb")) {
385 release_region(piix4_smba, SMBIOSIZE);
389 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
390 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
391 piix4_port_sel_sb800 = (port_sel & 0x01) ?
392 SB800_PIIX4_PORT_IDX_ALT :
393 SB800_PIIX4_PORT_IDX;
394 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
395 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
396 release_region(SB800_PIIX4_SMB_IDX, 2);
399 dev_info(&PIIX4_dev->dev,
400 "Using register 0x%02x for SMBus port selection\n",
401 (unsigned int)piix4_port_sel_sb800);
406 static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
407 const struct pci_device_id *id,
408 unsigned short base_reg_addr)
410 /* Set up auxiliary SMBus controllers found on some
411 * AMD chipsets e.g. SP5100 (SB700 derivative) */
413 unsigned short piix4_smba;
415 /* Read address of auxiliary SMBus controller */
416 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
417 if ((piix4_smba & 1) == 0) {
418 dev_dbg(&PIIX4_dev->dev,
419 "Auxiliary SMBus controller not enabled\n");
423 piix4_smba &= 0xfff0;
424 if (piix4_smba == 0) {
425 dev_dbg(&PIIX4_dev->dev,
426 "Auxiliary SMBus base address uninitialized\n");
430 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
433 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
434 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
435 "already in use!\n", piix4_smba);
439 dev_info(&PIIX4_dev->dev,
440 "Auxiliary SMBus Host Controller at 0x%x\n",
446 static int piix4_transaction(struct i2c_adapter *piix4_adapter)
448 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
449 unsigned short piix4_smba = adapdata->smba;
454 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
455 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
456 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
459 /* Make sure the SMBus host is ready to start transmitting */
460 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
461 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
462 "Resetting...\n", temp);
463 outb_p(temp, SMBHSTSTS);
464 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
465 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
468 dev_dbg(&piix4_adapter->dev, "Successful!\n");
472 /* start the transaction by setting bit 6 */
473 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
475 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
476 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
477 usleep_range(2000, 2100);
479 usleep_range(250, 500);
481 while ((++timeout < MAX_TIMEOUT) &&
482 ((temp = inb_p(SMBHSTSTS)) & 0x01))
483 usleep_range(250, 500);
485 /* If the SMBus is still busy, we give up */
486 if (timeout == MAX_TIMEOUT) {
487 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
493 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
498 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
499 "locked until next hard reset. (sorry!)\n");
500 /* Clock stops and slave is stuck in mid-transmission */
505 dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
508 if (inb_p(SMBHSTSTS) != 0x00)
509 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
511 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
512 dev_err(&piix4_adapter->dev, "Failed reset at end of "
513 "transaction (%02x)\n", temp);
515 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
516 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
517 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
522 /* Return negative errno on error. */
523 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
524 unsigned short flags, char read_write,
525 u8 command, int size, union i2c_smbus_data * data)
527 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
528 unsigned short piix4_smba = adapdata->smba;
533 case I2C_SMBUS_QUICK:
534 outb_p((addr << 1) | read_write,
539 outb_p((addr << 1) | read_write,
541 if (read_write == I2C_SMBUS_WRITE)
542 outb_p(command, SMBHSTCMD);
545 case I2C_SMBUS_BYTE_DATA:
546 outb_p((addr << 1) | read_write,
548 outb_p(command, SMBHSTCMD);
549 if (read_write == I2C_SMBUS_WRITE)
550 outb_p(data->byte, SMBHSTDAT0);
551 size = PIIX4_BYTE_DATA;
553 case I2C_SMBUS_WORD_DATA:
554 outb_p((addr << 1) | read_write,
556 outb_p(command, SMBHSTCMD);
557 if (read_write == I2C_SMBUS_WRITE) {
558 outb_p(data->word & 0xff, SMBHSTDAT0);
559 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
561 size = PIIX4_WORD_DATA;
563 case I2C_SMBUS_BLOCK_DATA:
564 outb_p((addr << 1) | read_write,
566 outb_p(command, SMBHSTCMD);
567 if (read_write == I2C_SMBUS_WRITE) {
568 len = data->block[0];
569 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
571 outb_p(len, SMBHSTDAT0);
572 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
573 for (i = 1; i <= len; i++)
574 outb_p(data->block[i], SMBBLKDAT);
576 size = PIIX4_BLOCK_DATA;
579 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
583 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
585 status = piix4_transaction(adap);
589 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
595 case PIIX4_BYTE_DATA:
596 data->byte = inb_p(SMBHSTDAT0);
598 case PIIX4_WORD_DATA:
599 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
601 case PIIX4_BLOCK_DATA:
602 data->block[0] = inb_p(SMBHSTDAT0);
603 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
605 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
606 for (i = 1; i <= data->block[0]; i++)
607 data->block[i] = inb_p(SMBBLKDAT);
613 static uint8_t piix4_imc_read(uint8_t idx)
615 outb_p(idx, KERNCZ_IMC_IDX);
616 return inb_p(KERNCZ_IMC_DATA);
619 static void piix4_imc_write(uint8_t idx, uint8_t value)
621 outb_p(idx, KERNCZ_IMC_IDX);
622 outb_p(value, KERNCZ_IMC_DATA);
625 static int piix4_imc_sleep(void)
627 int timeout = MAX_TIMEOUT;
629 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
632 /* clear response register */
633 piix4_imc_write(0x82, 0x00);
634 /* request ownership flag */
635 piix4_imc_write(0x83, 0xB4);
636 /* kick off IMC Mailbox command 96 */
637 piix4_imc_write(0x80, 0x96);
640 if (piix4_imc_read(0x82) == 0xfa) {
641 release_region(KERNCZ_IMC_IDX, 2);
644 usleep_range(1000, 2000);
647 release_region(KERNCZ_IMC_IDX, 2);
651 static void piix4_imc_wakeup(void)
653 int timeout = MAX_TIMEOUT;
655 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
658 /* clear response register */
659 piix4_imc_write(0x82, 0x00);
660 /* release ownership flag */
661 piix4_imc_write(0x83, 0xB5);
662 /* kick off IMC Mailbox command 96 */
663 piix4_imc_write(0x80, 0x96);
666 if (piix4_imc_read(0x82) == 0xfa)
668 usleep_range(1000, 2000);
671 release_region(KERNCZ_IMC_IDX, 2);
675 * Handles access to multiple SMBus ports on the SB800.
676 * The port is selected by bits 2:1 of the smb_en register (0x2c).
677 * Returns negative errno on error.
679 * Note: The selected port must be returned to the initial selection to avoid
680 * problems on certain systems.
682 static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
683 unsigned short flags, char read_write,
684 u8 command, int size, union i2c_smbus_data *data)
686 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
687 unsigned short piix4_smba = adapdata->smba;
688 int retries = MAX_TIMEOUT;
694 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb"))
697 /* Request the SMBUS semaphore, avoid conflicts with the IMC */
698 smbslvcnt = inb_p(SMBSLVCNT);
700 outb_p(smbslvcnt | 0x10, SMBSLVCNT);
702 /* Check the semaphore status */
703 smbslvcnt = inb_p(SMBSLVCNT);
704 if (smbslvcnt & 0x10)
707 usleep_range(1000, 2000);
709 /* SMBus is still owned by the IMC, we give up */
716 * Notify the IMC (Integrated Micro Controller) if required.
717 * Among other responsibilities, the IMC is in charge of monitoring
718 * the System fans and temperature sensors, and act accordingly.
719 * All this is done through SMBus and can/will collide
720 * with our transactions if they are long (BLOCK_DATA).
721 * Therefore we need to request the ownership flag during those
724 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
727 ret = piix4_imc_sleep();
731 "IMC base address index region 0x%x already in use.\n",
736 "Failed to communicate with the IMC.\n");
742 /* If IMC communication fails do not retry */
745 "Continuing without IMC notification.\n");
746 adapdata->notify_imc = false;
750 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
751 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
753 port = adapdata->port;
754 if ((smba_en_lo & piix4_port_mask_sb800) != port)
755 outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port,
756 SB800_PIIX4_SMB_IDX + 1);
758 retval = piix4_access(adap, addr, flags, read_write,
759 command, size, data);
761 outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1);
763 /* Release the semaphore */
764 outb_p(smbslvcnt | 0x20, SMBSLVCNT);
766 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
770 release_region(SB800_PIIX4_SMB_IDX, 2);
774 static u32 piix4_func(struct i2c_adapter *adapter)
776 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
777 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
778 I2C_FUNC_SMBUS_BLOCK_DATA;
781 static const struct i2c_algorithm smbus_algorithm = {
782 .smbus_xfer = piix4_access,
783 .functionality = piix4_func,
786 static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
787 .smbus_xfer = piix4_access_sb800,
788 .functionality = piix4_func,
791 static const struct pci_device_id piix4_ids[] = {
792 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
793 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
794 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
795 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
796 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
797 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
798 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
799 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
800 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
801 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
802 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
803 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
804 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
805 PCI_DEVICE_ID_SERVERWORKS_CSB5) },
806 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
807 PCI_DEVICE_ID_SERVERWORKS_CSB6) },
808 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
809 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
810 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
811 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
815 MODULE_DEVICE_TABLE (pci, piix4_ids);
817 static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
818 static struct i2c_adapter *piix4_aux_adapter;
820 static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
821 bool sb800_main, u8 port, bool notify_imc,
822 const char *name, struct i2c_adapter **padap)
824 struct i2c_adapter *adap;
825 struct i2c_piix4_adapdata *adapdata;
828 adap = kzalloc(sizeof(*adap), GFP_KERNEL);
830 release_region(smba, SMBIOSIZE);
834 adap->owner = THIS_MODULE;
835 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
836 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
839 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
840 if (adapdata == NULL) {
842 release_region(smba, SMBIOSIZE);
846 adapdata->smba = smba;
847 adapdata->sb800_main = sb800_main;
848 adapdata->port = port << piix4_port_shift_sb800;
849 adapdata->notify_imc = notify_imc;
851 /* set up the sysfs linkage to our parent device */
852 adap->dev.parent = &dev->dev;
854 snprintf(adap->name, sizeof(adap->name),
855 "SMBus PIIX4 adapter%s at %04x", name, smba);
857 i2c_set_adapdata(adap, adapdata);
859 retval = i2c_add_adapter(adap);
863 release_region(smba, SMBIOSIZE);
871 static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
874 struct i2c_piix4_adapdata *adapdata;
878 for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) {
879 retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
880 piix4_main_port_names_sb800[port],
881 &piix4_main_adapters[port]);
890 "Error setting up SB800 adapters. Unregistering!\n");
891 while (--port >= 0) {
892 adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
893 if (adapdata->smba) {
894 i2c_del_adapter(piix4_main_adapters[port]);
896 kfree(piix4_main_adapters[port]);
897 piix4_main_adapters[port] = NULL;
904 static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
907 bool is_sb800 = false;
909 if ((dev->vendor == PCI_VENDOR_ID_ATI &&
910 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
911 dev->revision >= 0x40) ||
912 dev->vendor == PCI_VENDOR_ID_AMD ||
913 dev->vendor == PCI_VENDOR_ID_HYGON) {
914 bool notify_imc = false;
917 if ((dev->vendor == PCI_VENDOR_ID_AMD ||
918 dev->vendor == PCI_VENDOR_ID_HYGON) &&
919 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
923 * Detect if IMC is active or not, this method is
924 * described on coreboot's AMD IMC notes
926 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
932 /* base address location etc changed in SB800 */
933 retval = piix4_setup_sb800(dev, id, 0);
938 * Try to register multiplexed main SMBus adapter,
939 * give up if we can't
941 retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
945 retval = piix4_setup(dev, id);
949 /* Try to register main SMBus adapter, give up if we can't */
950 retval = piix4_add_adapter(dev, retval, false, 0, false, "",
951 &piix4_main_adapters[0]);
956 /* Check for auxiliary SMBus on some AMD chipsets */
959 if (dev->vendor == PCI_VENDOR_ID_ATI &&
960 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
961 if (dev->revision < 0x40) {
962 retval = piix4_setup_aux(dev, id, 0x58);
964 /* SB800 added aux bus too */
965 retval = piix4_setup_sb800(dev, id, 1);
969 if (dev->vendor == PCI_VENDOR_ID_AMD &&
970 dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) {
971 retval = piix4_setup_sb800(dev, id, 1);
975 /* Try to add the aux adapter if it exists,
976 * piix4_add_adapter will clean up if this fails */
977 piix4_add_adapter(dev, retval, false, 0, false,
978 is_sb800 ? piix4_aux_port_name_sb800 : "",
985 static void piix4_adap_remove(struct i2c_adapter *adap)
987 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
989 if (adapdata->smba) {
990 i2c_del_adapter(adap);
991 if (adapdata->port == (0 << piix4_port_shift_sb800))
992 release_region(adapdata->smba, SMBIOSIZE);
998 static void piix4_remove(struct pci_dev *dev)
1000 int port = PIIX4_MAX_ADAPTERS;
1002 while (--port >= 0) {
1003 if (piix4_main_adapters[port]) {
1004 piix4_adap_remove(piix4_main_adapters[port]);
1005 piix4_main_adapters[port] = NULL;
1009 if (piix4_aux_adapter) {
1010 piix4_adap_remove(piix4_aux_adapter);
1011 piix4_aux_adapter = NULL;
1015 static struct pci_driver piix4_driver = {
1016 .name = "piix4_smbus",
1017 .id_table = piix4_ids,
1018 .probe = piix4_probe,
1019 .remove = piix4_remove,
1022 module_pci_driver(piix4_driver);
1024 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
1025 "Philip Edelbrock <phil@netroedge.com>");
1026 MODULE_DESCRIPTION("PIIX4 SMBus driver");
1027 MODULE_LICENSE("GPL");