drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/delay.h>
  29 #include <linux/i2c.h>
  30 #include <linux/err.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/completion.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/clk.h>
  35 #include <linux/io.h>
  36 #include <linux/of.h>
  37 #include <linux/of_device.h>
  38 #include <linux/slab.h>
  39 #include <linux/i2c-omap.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/pinctrl/consumer.h>
  42
  43 /* I2C controller revisions */
  44 #define OMAP_I2C_OMAP1_REV_2            0x20
  45
  46 /* I2C controller revisions present on specific hardware */
  47 #define OMAP_I2C_REV_ON_2430            0x00000036
  48 #define OMAP_I2C_REV_ON_3430_3530       0x0000003C
  49 #define OMAP_I2C_REV_ON_3630            0x00000040
  50 #define OMAP_I2C_REV_ON_4430_PLUS       0x50400002
  51
  52 /* timeout waiting for the controller to respond */
  53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  54
  55 /* timeout for pm runtime autosuspend */
  56 #define OMAP_I2C_PM_TIMEOUT             1000    /* ms */
  57
  58 /* timeout for making decision on bus free status */
  59 #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
  60
  61 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
  62 enum {
  63         OMAP_I2C_REV_REG = 0,
  64         OMAP_I2C_IE_REG,
  65         OMAP_I2C_STAT_REG,
  66         OMAP_I2C_IV_REG,
  67         OMAP_I2C_WE_REG,
  68         OMAP_I2C_SYSS_REG,
  69         OMAP_I2C_BUF_REG,
  70         OMAP_I2C_CNT_REG,
  71         OMAP_I2C_DATA_REG,
  72         OMAP_I2C_SYSC_REG,
  73         OMAP_I2C_CON_REG,
  74         OMAP_I2C_OA_REG,
  75         OMAP_I2C_SA_REG,
  76         OMAP_I2C_PSC_REG,
  77         OMAP_I2C_SCLL_REG,
  78         OMAP_I2C_SCLH_REG,
  79         OMAP_I2C_SYSTEST_REG,
  80         OMAP_I2C_BUFSTAT_REG,
  81         /* only on OMAP4430 */
  82         OMAP_I2C_IP_V2_REVNB_LO,
  83         OMAP_I2C_IP_V2_REVNB_HI,
  84         OMAP_I2C_IP_V2_IRQSTATUS_RAW,
  85         OMAP_I2C_IP_V2_IRQENABLE_SET,
  86         OMAP_I2C_IP_V2_IRQENABLE_CLR,
  87 };
  88
  89 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  90 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  91 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  92 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  93 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  94 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  95 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  96 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  97
  98 /* I2C Status Register (OMAP_I2C_STAT): */
  99 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
 100 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
 101 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
 102 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
 103 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
 104 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
 105 #define OMAP_I2C_STAT_BF        (1 << 8)        /* Bus Free */
 106 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
 107 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
 108 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
 109 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
 110 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
 111
 112 /* I2C WE wakeup enable register */
 113 #define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
 114 #define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
 115 #define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
 116 #define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
 117 #define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
 118 #define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
 119 #define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
 120 #define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
 121 #define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
 122 #define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
 123
 124 #define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
 125                                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
 126                                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
 127                                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
 128                                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
 129
 130 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
 131 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
 132 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
 133 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
 134 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
 135
 136 /* I2C Configuration Register (OMAP_I2C_CON): */
 137 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 138 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 139 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 140 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 141 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 142 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 143 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 144 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 145 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 146 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 147
 148 /* I2C SCL time value when Master */
 149 #define OMAP_I2C_SCLL_HSSCLL    8
 150 #define OMAP_I2C_SCLH_HSSCLH    8
 151
 152 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 153 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 154 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 155 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 156 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 157 /* Functional mode */
 158 #define OMAP_I2C_SYSTEST_SCL_I_FUNC     (1 << 8)        /* SCL line input value */
 159 #define OMAP_I2C_SYSTEST_SCL_O_FUNC     (1 << 7)        /* SCL line output value */
 160 #define OMAP_I2C_SYSTEST_SDA_I_FUNC     (1 << 6)        /* SDA line input value */
 161 #define OMAP_I2C_SYSTEST_SDA_O_FUNC     (1 << 5)        /* SDA line output value */
 162 /* SDA/SCL IO mode */
 163 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 164 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 165 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 166 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 167
 168 /* OCP_SYSSTATUS bit definitions */
 169 #define SYSS_RESETDONE_MASK             (1 << 0)
 170
 171 /* OCP_SYSCONFIG bit definitions */
 172 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
 173 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
 174 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
 175 #define SYSC_SOFTRESET_MASK             (1 << 1)
 176 #define SYSC_AUTOIDLE_MASK              (1 << 0)
 177
 178 #define SYSC_IDLEMODE_SMART             0x2
 179 #define SYSC_CLOCKACTIVITY_FCLK         0x2
 180
 181 /* Errata definitions */
 182 #define I2C_OMAP_ERRATA_I207            (1 << 0)
 183 #define I2C_OMAP_ERRATA_I462            (1 << 1)
 184
 185 #define OMAP_I2C_IP_V2_INTERRUPTS_MASK  0x6FFF
 186
 187 struct omap_i2c_dev {
 188         struct device           *dev;
 189         void __iomem            *base;          /* virtual */
 190         int                     irq;
 191         int                     reg_shift;      /* bit shift for I2C register addresses */
 192         struct completion       cmd_complete;
 193         struct resource         *ioarea;
 194         u32                     latency;        /* maximum mpu wkup latency */
 195         void                    (*set_mpu_wkup_lat)(struct device *dev,
 196                                                     long latency);
 197         u32                     speed;          /* Speed of bus in kHz */
 198         u32                     flags;
 199         u16                     scheme;
 200         u16                     cmd_err;
 201         u8                      *buf;
 202         u8                      *regs;
 203         size_t                  buf_len;
 204         struct i2c_adapter      adapter;
 205         u8                      threshold;
 206         u8                      fifo_size;      /* use as flag and value
 207                                                  * fifo_size==0 implies no fifo
 208                                                  * if set, should be trsh+1
 209                                                  */
 210         u32                     rev;
 211         unsigned                b_hw:1;         /* bad h/w fixes */
 212         unsigned                bb_valid:1;     /* true when BB-bit reflects
 213                                                  * the I2C bus state
 214                                                  */
 215         unsigned                receiver:1;     /* true when we're in receiver mode */
 216         u16                     iestate;        /* Saved interrupt register */
 217         u16                     pscstate;
 218         u16                     scllstate;
 219         u16                     sclhstate;
 220         u16                     syscstate;
 221         u16                     westate;
 222         u16                     errata;
 223 };
 224
 225 static const u8 reg_map_ip_v1[] = {
 226         [OMAP_I2C_REV_REG] = 0x00,
 227         [OMAP_I2C_IE_REG] = 0x01,
 228         [OMAP_I2C_STAT_REG] = 0x02,
 229         [OMAP_I2C_IV_REG] = 0x03,
 230         [OMAP_I2C_WE_REG] = 0x03,
 231         [OMAP_I2C_SYSS_REG] = 0x04,
 232         [OMAP_I2C_BUF_REG] = 0x05,
 233         [OMAP_I2C_CNT_REG] = 0x06,
 234         [OMAP_I2C_DATA_REG] = 0x07,
 235         [OMAP_I2C_SYSC_REG] = 0x08,
 236         [OMAP_I2C_CON_REG] = 0x09,
 237         [OMAP_I2C_OA_REG] = 0x0a,
 238         [OMAP_I2C_SA_REG] = 0x0b,
 239         [OMAP_I2C_PSC_REG] = 0x0c,
 240         [OMAP_I2C_SCLL_REG] = 0x0d,
 241         [OMAP_I2C_SCLH_REG] = 0x0e,
 242         [OMAP_I2C_SYSTEST_REG] = 0x0f,
 243         [OMAP_I2C_BUFSTAT_REG] = 0x10,
 244 };
 245
 246 static const u8 reg_map_ip_v2[] = {
 247         [OMAP_I2C_REV_REG] = 0x04,
 248         [OMAP_I2C_IE_REG] = 0x2c,
 249         [OMAP_I2C_STAT_REG] = 0x28,
 250         [OMAP_I2C_IV_REG] = 0x34,
 251         [OMAP_I2C_WE_REG] = 0x34,
 252         [OMAP_I2C_SYSS_REG] = 0x90,
 253         [OMAP_I2C_BUF_REG] = 0x94,
 254         [OMAP_I2C_CNT_REG] = 0x98,
 255         [OMAP_I2C_DATA_REG] = 0x9c,
 256         [OMAP_I2C_SYSC_REG] = 0x10,
 257         [OMAP_I2C_CON_REG] = 0xa4,
 258         [OMAP_I2C_OA_REG] = 0xa8,
 259         [OMAP_I2C_SA_REG] = 0xac,
 260         [OMAP_I2C_PSC_REG] = 0xb0,
 261         [OMAP_I2C_SCLL_REG] = 0xb4,
 262         [OMAP_I2C_SCLH_REG] = 0xb8,
 263         [OMAP_I2C_SYSTEST_REG] = 0xbC,
 264         [OMAP_I2C_BUFSTAT_REG] = 0xc0,
 265         [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
 266         [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
 267         [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
 268         [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
 269         [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
 270 };
 271
 272 static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
 273                                       int reg, u16 val)
 274 {
 275         writew_relaxed(val, omap->base +
 276                         (omap->regs[reg] << omap->reg_shift));
 277 }
 278
 279 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
 280 {
 281         return readw_relaxed(omap->base +
 282                                 (omap->regs[reg] << omap->reg_shift));
 283 }
 284
 285 static void __omap_i2c_init(struct omap_i2c_dev *omap)
 286 {
 287
 288         omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
 289
 290         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 291         omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
 292
 293         /* SCL low and high time values */
 294         omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
 295         omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
 296         if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
 297                 omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
 298
 299         /* Take the I2C module out of reset: */
 300         omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 301
 302         /*
 303          * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
 304          * bus is busy. It will be changed to 1 on the next IP FCLK clock.
 305          * udelay(1) will be enough to fix that.
 306          */
 307
 308         /*
 309          * Don't write to this register if the IE state is 0 as it can
 310          * cause deadlock.
 311          */
 312         if (omap->iestate)
 313                 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
 314 }
 315
 316 static int omap_i2c_reset(struct omap_i2c_dev *omap)
 317 {
 318         unsigned long timeout;
 319         u16 sysc;
 320
 321         if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
 322                 sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
 323
 324                 /* Disable I2C controller before soft reset */
 325                 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
 326                         omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
 327                                 ~(OMAP_I2C_CON_EN));
 328
 329                 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
 330                 /* For some reason we need to set the EN bit before the
 331                  * reset done bit gets set. */
 332                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 333                 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 334                 while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
 335                          SYSS_RESETDONE_MASK)) {
 336                         if (time_after(jiffies, timeout)) {
 337                                 dev_warn(omap->dev, "timeout waiting "
 338                                                 "for controller reset\n");
 339                                 return -ETIMEDOUT;
 340                         }
 341                         msleep(1);
 342                 }
 343
 344                 /* SYSC register is cleared by the reset; rewrite it */
 345                 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
 346
 347                 if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
 348                         /* Schedule I2C-bus monitoring on the next transfer */
 349                         omap->bb_valid = 0;
 350                 }
 351         }
 352
 353         return 0;
 354 }
 355
 356 static int omap_i2c_init(struct omap_i2c_dev *omap)
 357 {
 358         u16 psc = 0, scll = 0, sclh = 0;
 359         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 360         unsigned long fclk_rate = 12000000;
 361         unsigned long internal_clk = 0;
 362         struct clk *fclk;
 363
 364         if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
 365                 /*
 366                  * Enabling all wakup sources to stop I2C freezing on
 367                  * WFI instruction.
 368                  * REVISIT: Some wkup sources might not be needed.
 369                  */
 370                 omap->westate = OMAP_I2C_WE_ALL;
 371         }
 372
 373         if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
 374                 /*
 375                  * The I2C functional clock is the armxor_ck, so there's
 376                  * no need to get "armxor_ck" separately.  Now, if OMAP2420
 377                  * always returns 12MHz for the functional clock, we can
 378                  * do this bit unconditionally.
 379                  */
 380                 fclk = clk_get(omap->dev, "fck");
 381                 fclk_rate = clk_get_rate(fclk);
 382                 clk_put(fclk);
 383
 384                 /* TRM for 5912 says the I2C clock must be prescaled to be
 385                  * between 7 - 12 MHz. The XOR input clock is typically
 386                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 387                  *
 388                  * XOR MHz      Divider         Prescaler
 389                  * 12           1               0
 390                  * 13           2               1
 391                  * 19.2         2               1
 392                  */
 393                 if (fclk_rate > 12000000)
 394                         psc = fclk_rate / 12000000;
 395         }
 396
 397         if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
 398
 399                 /*
 400                  * HSI2C controller internal clk rate should be 19.2 Mhz for
 401                  * HS and for all modes on 2430. On 34xx we can use lower rate
 402                  * to get longer filter period for better noise suppression.
 403                  * The filter is iclk (fclk for HS) period.
 404                  */
 405                 if (omap->speed > 400 ||
 406                                omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
 407                         internal_clk = 19200;
 408                 else if (omap->speed > 100)
 409                         internal_clk = 9600;
 410                 else
 411                         internal_clk = 4000;
 412                 fclk = clk_get(omap->dev, "fck");
 413                 fclk_rate = clk_get_rate(fclk) / 1000;
 414                 clk_put(fclk);
 415
 416                 /* Compute prescaler divisor */
 417                 psc = fclk_rate / internal_clk;
 418                 psc = psc - 1;
 419
 420                 /* If configured for High Speed */
 421                 if (omap->speed > 400) {
 422                         unsigned long scl;
 423
 424                         /* For first phase of HS mode */
 425                         scl = internal_clk / 400;
 426                         fsscll = scl - (scl / 3) - 7;
 427                         fssclh = (scl / 3) - 5;
 428
 429                         /* For second phase of HS mode */
 430                         scl = fclk_rate / omap->speed;
 431                         hsscll = scl - (scl / 3) - 7;
 432                         hssclh = (scl / 3) - 5;
 433                 } else if (omap->speed > 100) {
 434                         unsigned long scl;
 435
 436                         /* Fast mode */
 437                         scl = internal_clk / omap->speed;
 438                         fsscll = scl - (scl / 3) - 7;
 439                         fssclh = (scl / 3) - 5;
 440                 } else {
 441                         /* Standard mode */
 442                         fsscll = internal_clk / (omap->speed * 2) - 7;
 443                         fssclh = internal_clk / (omap->speed * 2) - 5;
 444                 }
 445                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 446                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 447         } else {
 448                 /* Program desired operating rate */
 449                 fclk_rate /= (psc + 1) * 1000;
 450                 if (psc > 2)
 451                         psc = 2;
 452                 scll = fclk_rate / (omap->speed * 2) - 7 + psc;
 453                 sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
 454         }
 455
 456         omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 457                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 458                         OMAP_I2C_IE_AL)  | ((omap->fifo_size) ?
 459                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
 460
 461         omap->pscstate = psc;
 462         omap->scllstate = scll;
 463         omap->sclhstate = sclh;
 464
 465         if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
 466                 /* Not implemented */
 467                 omap->bb_valid = 1;
 468         }
 469
 470         __omap_i2c_init(omap);
 471
 472         return 0;
 473 }
 474
 475 /*
 476  * Waiting on Bus Busy
 477  */
 478 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
 479 {
 480         unsigned long timeout;
 481
 482         timeout = jiffies + OMAP_I2C_TIMEOUT;
 483         while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 484                 if (time_after(jiffies, timeout))
 485                         return i2c_recover_bus(&omap->adapter);
 486                 msleep(1);
 487         }
 488
 489         return 0;
 490 }
 491
 492 /*
 493  * Wait while BB-bit doesn't reflect the I2C bus state
 494  *
 495  * In a multimaster environment, after IP software reset, BB-bit value doesn't
 496  * correspond to the current bus state. It may happen what BB-bit will be 0,
 497  * while the bus is busy due to another I2C master activity.
 498  * Here are BB-bit values after reset:
 499  *     SDA   SCL   BB   NOTES
 500  *       0     0    0   1, 2
 501  *       1     0    0   1, 2
 502  *       0     1    1
 503  *       1     1    0   3
 504  * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
 505  * combinations on the bus, it set BB-bit to 1.
 506  * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
 507  * it set BB-bit to 0 and BF to 1.
 508  * BB and BF bits correctly tracks the bus state while IP is suspended
 509  * BB bit became valid on the next FCLK clock after CON_EN bit set
 510  *
 511  * NOTES:
 512  * 1. Any transfer started when BB=0 and bus is busy wouldn't be
 513  *    completed by IP and results in controller timeout.
 514  * 2. Any transfer started when BB=0 and SCL=0 results in IP
 515  *    starting to drive SDA low. In that case IP corrupt data
 516  *    on the bus.
 517  * 3. Any transfer started in the middle of another master's transfer
 518  *    results in unpredictable results and data corruption
 519  */
 520 static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
 521 {
 522         unsigned long bus_free_timeout = 0;
 523         unsigned long timeout;
 524         int bus_free = 0;
 525         u16 stat, systest;
 526
 527         if (omap->bb_valid)
 528                 return 0;
 529
 530         timeout = jiffies + OMAP_I2C_TIMEOUT;
 531         while (1) {
 532                 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
 533                 /*
 534                  * We will see BB or BF event in a case IP had detected any
 535                  * activity on the I2C bus. Now IP correctly tracks the bus
 536                  * state. BB-bit value is valid.
 537                  */
 538                 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
 539                         break;
 540
 541                 /*
 542                  * Otherwise, we must look signals on the bus to make
 543                  * the right decision.
 544                  */
 545                 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
 546                 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
 547                     (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
 548                         if (!bus_free) {
 549                                 bus_free_timeout = jiffies +
 550                                         OMAP_I2C_BUS_FREE_TIMEOUT;
 551                                 bus_free = 1;
 552                         }
 553
 554                         /*
 555                          * SDA and SCL lines was high for 10 ms without bus
 556                          * activity detected. The bus is free. Consider
 557                          * BB-bit value is valid.
 558                          */
 559                         if (time_after(jiffies, bus_free_timeout))
 560                                 break;
 561                 } else {
 562                         bus_free = 0;
 563                 }
 564
 565                 if (time_after(jiffies, timeout)) {
 566                         dev_warn(omap->dev, "timeout waiting for bus ready\n");
 567                         return -ETIMEDOUT;
 568                 }
 569
 570                 msleep(1);
 571         }
 572
 573         omap->bb_valid = 1;
 574         return 0;
 575 }
 576
 577 static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
 578 {
 579         u16             buf;
 580
 581         if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
 582                 return;
 583
 584         /*
 585          * Set up notification threshold based on message size. We're doing
 586          * this to try and avoid draining feature as much as possible. Whenever
 587          * we have big messages to transfer (bigger than our total fifo size)
 588          * then we might use draining feature to transfer the remaining bytes.
 589          */
 590
 591         omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
 592
 593         buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
 594
 595         if (is_rx) {
 596                 /* Clear RX Threshold */
 597                 buf &= ~(0x3f << 8);
 598                 buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
 599         } else {
 600                 /* Clear TX Threshold */
 601                 buf &= ~0x3f;
 602                 buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
 603         }
 604
 605         omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
 606
 607         if (omap->rev < OMAP_I2C_REV_ON_3630)
 608                 omap->b_hw = 1; /* Enable hardware fixes */
 609
 610         /* calculate wakeup latency constraint for MPU */
 611         if (omap->set_mpu_wkup_lat != NULL)
 612                 omap->latency = (1000000 * omap->threshold) /
 613                         (1000 * omap->speed / 8);
 614 }
 615
 616 /*
 617  * Low level master read/write transaction.
 618  */
 619 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 620                              struct i2c_msg *msg, int stop)
 621 {
 622         struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
 623         unsigned long timeout;
 624         u16 w;
 625
 626         dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 627                 msg->addr, msg->len, msg->flags, stop);
 628
 629         if (msg->len == 0)
 630                 return -EINVAL;
 631
 632         omap->receiver = !!(msg->flags & I2C_M_RD);
 633         omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
 634
 635         omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
 636
 637         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 638         omap->buf = msg->buf;
 639         omap->buf_len = msg->len;
 640
 641         /* make sure writes to omap->buf_len are ordered */
 642         barrier();
 643
 644         omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
 645
 646         /* Clear the FIFO Buffers */
 647         w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
 648         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 649         omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
 650
 651         reinit_completion(&omap->cmd_complete);
 652         omap->cmd_err = 0;
 653
 654         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 655
 656         /* High speed configuration */
 657         if (omap->speed > 400)
 658                 w |= OMAP_I2C_CON_OPMODE_HS;
 659
 660         if (msg->flags & I2C_M_STOP)
 661                 stop = 1;
 662         if (msg->flags & I2C_M_TEN)
 663                 w |= OMAP_I2C_CON_XA;
 664         if (!(msg->flags & I2C_M_RD))
 665                 w |= OMAP_I2C_CON_TRX;
 666
 667         if (!omap->b_hw && stop)
 668                 w |= OMAP_I2C_CON_STP;
 669         /*
 670          * NOTE: STAT_BB bit could became 1 here if another master occupy
 671          * the bus. IP successfully complete transfer when the bus will be
 672          * free again (BB reset to 0).
 673          */
 674         omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
 675
 676         /*
 677          * Don't write stt and stp together on some hardware.
 678          */
 679         if (omap->b_hw && stop) {
 680                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 681                 u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
 682                 while (con & OMAP_I2C_CON_STT) {
 683                         con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
 684
 685                         /* Let the user know if i2c is in a bad state */
 686                         if (time_after(jiffies, delay)) {
 687                                 dev_err(omap->dev, "controller timed out "
 688                                 "waiting for start condition to finish\n");
 689                                 return -ETIMEDOUT;
 690                         }
 691                         cpu_relax();
 692                 }
 693
 694                 w |= OMAP_I2C_CON_STP;
 695                 w &= ~OMAP_I2C_CON_STT;
 696                 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
 697         }
 698
 699         /*
 700          * REVISIT: We should abort the transfer on signals, but the bus goes
 701          * into arbitration and we're currently unable to recover from it.
 702          */
 703         timeout = wait_for_completion_timeout(&omap->cmd_complete,
 704                                                 OMAP_I2C_TIMEOUT);
 705         if (timeout == 0) {
 706                 dev_err(omap->dev, "controller timed out\n");
 707                 omap_i2c_reset(omap);
 708                 __omap_i2c_init(omap);
 709                 return -ETIMEDOUT;
 710         }
 711
 712         if (likely(!omap->cmd_err))
 713                 return 0;
 714
 715         /* We have an error */
 716         if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
 717                 omap_i2c_reset(omap);
 718                 __omap_i2c_init(omap);
 719                 return -EIO;
 720         }
 721
 722         if (omap->cmd_err & OMAP_I2C_STAT_AL)
 723                 return -EAGAIN;
 724
 725         if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
 726                 if (msg->flags & I2C_M_IGNORE_NAK)
 727                         return 0;
 728
 729                 w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
 730                 w |= OMAP_I2C_CON_STP;
 731                 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
 732                 return -EREMOTEIO;
 733         }
 734         return -EIO;
 735 }
 736
 737
 738 /*
 739  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 740  * to do the work during IRQ processing.
 741  */
 742 static int
 743 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 744 {
 745         struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
 746         int i;
 747         int r;
 748
 749         r = pm_runtime_get_sync(omap->dev);
 750         if (r < 0)
 751                 goto out;
 752
 753         r = omap_i2c_wait_for_bb_valid(omap);
 754         if (r < 0)
 755                 goto out;
 756
 757         r = omap_i2c_wait_for_bb(omap);
 758         if (r < 0)
 759                 goto out;
 760
 761         if (omap->set_mpu_wkup_lat != NULL)
 762                 omap->set_mpu_wkup_lat(omap->dev, omap->latency);
 763
 764         for (i = 0; i < num; i++) {
 765                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 766                 if (r != 0)
 767                         break;
 768         }
 769
 770         if (r == 0)
 771                 r = num;
 772
 773         omap_i2c_wait_for_bb(omap);
 774
 775         if (omap->set_mpu_wkup_lat != NULL)
 776                 omap->set_mpu_wkup_lat(omap->dev, -1);
 777
 778 out:
 779         pm_runtime_mark_last_busy(omap->dev);
 780         pm_runtime_put_autosuspend(omap->dev);
 781         return r;
 782 }
 783
 784 static u32
 785 omap_i2c_func(struct i2c_adapter *adap)
 786 {
 787         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 788                I2C_FUNC_PROTOCOL_MANGLING;
 789 }
 790
 791 static inline void
 792 omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
 793 {
 794         omap->cmd_err |= err;
 795         complete(&omap->cmd_complete);
 796 }
 797
 798 static inline void
 799 omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
 800 {
 801         omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
 802 }
 803
 804 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
 805 {
 806         /*
 807          * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
 808          * Not applicable for OMAP4.
 809          * Under certain rare conditions, RDR could be set again
 810          * when the bus is busy, then ignore the interrupt and
 811          * clear the interrupt.
 812          */
 813         if (stat & OMAP_I2C_STAT_RDR) {
 814                 /* Step 1: If RDR is set, clear it */
 815                 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
 816
 817                 /* Step 2: */
 818                 if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
 819                                                 & OMAP_I2C_STAT_BB)) {
 820
 821                         /* Step 3: */
 822                         if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
 823                                                 & OMAP_I2C_STAT_RDR) {
 824                                 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
 825                                 dev_dbg(omap->dev, "RDR when bus is busy.\n");
 826                         }
 827
 828                 }
 829         }
 830 }
 831
 832 /* rev1 devices are apparently only on some 15xx */
 833 #ifdef CONFIG_ARCH_OMAP15XX
 834
 835 static irqreturn_t
 836 omap_i2c_omap1_isr(int this_irq, void *dev_id)
 837 {
 838         struct omap_i2c_dev *omap = dev_id;
 839         u16 iv, w;
 840
 841         if (pm_runtime_suspended(omap->dev))
 842                 return IRQ_NONE;
 843
 844         iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
 845         switch (iv) {
 846         case 0x00:      /* None */
 847                 break;
 848         case 0x01:      /* Arbitration lost */
 849                 dev_err(omap->dev, "Arbitration lost\n");
 850                 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
 851                 break;
 852         case 0x02:      /* No acknowledgement */
 853                 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
 854                 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 855                 break;
 856         case 0x03:      /* Register access ready */
 857                 omap_i2c_complete_cmd(omap, 0);
 858                 break;
 859         case 0x04:      /* Receive data ready */
 860                 if (omap->buf_len) {
 861                         w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
 862                         *omap->buf++ = w;
 863                         omap->buf_len--;
 864                         if (omap->buf_len) {
 865                                 *omap->buf++ = w >> 8;
 866                                 omap->buf_len--;
 867                         }
 868                 } else
 869                         dev_err(omap->dev, "RRDY IRQ while no data requested\n");
 870                 break;
 871         case 0x05:      /* Transmit data ready */
 872                 if (omap->buf_len) {
 873                         w = *omap->buf++;
 874                         omap->buf_len--;
 875                         if (omap->buf_len) {
 876                                 w |= *omap->buf++ << 8;
 877                                 omap->buf_len--;
 878                         }
 879                         omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
 880                 } else
 881                         dev_err(omap->dev, "XRDY IRQ while no data to send\n");
 882                 break;
 883         default:
 884                 return IRQ_NONE;
 885         }
 886
 887         return IRQ_HANDLED;
 888 }
 889 #else
 890 #define omap_i2c_omap1_isr              NULL
 891 #endif
 892
 893 /*
 894  * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
 895  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
 896  * them from the memory to the I2C interface.
 897  */
 898 static int errata_omap3_i462(struct omap_i2c_dev *omap)
 899 {
 900         unsigned long timeout = 10000;
 901         u16 stat;
 902
 903         do {
 904                 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
 905                 if (stat & OMAP_I2C_STAT_XUDF)
 906                         break;
 907
 908                 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 909                         omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
 910                                                         OMAP_I2C_STAT_XDR));
 911                         if (stat & OMAP_I2C_STAT_NACK) {
 912                                 omap->cmd_err |= OMAP_I2C_STAT_NACK;
 913                                 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
 914                         }
 915
 916                         if (stat & OMAP_I2C_STAT_AL) {
 917                                 dev_err(omap->dev, "Arbitration lost\n");
 918                                 omap->cmd_err |= OMAP_I2C_STAT_AL;
 919                                 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
 920                         }
 921
 922                         return -EIO;
 923                 }
 924
 925                 cpu_relax();
 926         } while (--timeout);
 927
 928         if (!timeout) {
 929                 dev_err(omap->dev, "timeout waiting on XUDF bit\n");
 930                 return 0;
 931         }
 932
 933         return 0;
 934 }
 935
 936 static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
 937                 bool is_rdr)
 938 {
 939         u16             w;
 940
 941         while (num_bytes--) {
 942                 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
 943                 *omap->buf++ = w;
 944                 omap->buf_len--;
 945
 946                 /*
 947                  * Data reg in 2430, omap3 and
 948                  * omap4 is 8 bit wide
 949                  */
 950                 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
 951                         *omap->buf++ = w >> 8;
 952                         omap->buf_len--;
 953                 }
 954         }
 955 }
 956
 957 static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
 958                 bool is_xdr)
 959 {
 960         u16             w;
 961
 962         while (num_bytes--) {
 963                 w = *omap->buf++;
 964                 omap->buf_len--;
 965
 966                 /*
 967                  * Data reg in 2430, omap3 and
 968                  * omap4 is 8 bit wide
 969                  */
 970                 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
 971                         w |= *omap->buf++ << 8;
 972                         omap->buf_len--;
 973                 }
 974
 975                 if (omap->errata & I2C_OMAP_ERRATA_I462) {
 976                         int ret;
 977
 978                         ret = errata_omap3_i462(omap);
 979                         if (ret < 0)
 980                                 return ret;
 981                 }
 982
 983                 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
 984         }
 985
 986         return 0;
 987 }
 988
 989 static irqreturn_t
 990 omap_i2c_isr(int irq, void *dev_id)
 991 {
 992         struct omap_i2c_dev *omap = dev_id;
 993         irqreturn_t ret = IRQ_HANDLED;
 994         u16 mask;
 995         u16 stat;
 996
 997         stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
 998         mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
 999
1000         if (stat & mask)
1001                 ret = IRQ_WAKE_THREAD;
1002
1003         return ret;
1004 }
1005
1006 static irqreturn_t
1007 omap_i2c_isr_thread(int this_irq, void *dev_id)
1008 {
1009         struct omap_i2c_dev *omap = dev_id;
1010         u16 bits;
1011         u16 stat;
1012         int err = 0, count = 0;
1013
1014         do {
1015                 bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1016                 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1017                 stat &= bits;
1018
1019                 /* If we're in receiver mode, ignore XDR/XRDY */
1020                 if (omap->receiver)
1021                         stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
1022                 else
1023                         stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
1024
1025                 if (!stat) {
1026                         /* my work here is done */
1027                         goto out;
1028                 }
1029
1030                 dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
1031                 if (count++ == 100) {
1032                         dev_warn(omap->dev, "Too much work in one IRQ\n");
1033                         break;
1034                 }
1035
1036                 if (stat & OMAP_I2C_STAT_NACK) {
1037                         err |= OMAP_I2C_STAT_NACK;
1038                         omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
1039                 }
1040
1041                 if (stat & OMAP_I2C_STAT_AL) {
1042                         dev_err(omap->dev, "Arbitration lost\n");
1043                         err |= OMAP_I2C_STAT_AL;
1044                         omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
1045                 }
1046
1047                 /*
1048                  * ProDB0017052: Clear ARDY bit twice
1049                  */
1050                 if (stat & OMAP_I2C_STAT_ARDY)
1051                         omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
1052
1053                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
1054                                         OMAP_I2C_STAT_AL)) {
1055                         omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
1056                                                 OMAP_I2C_STAT_RDR |
1057                                                 OMAP_I2C_STAT_XRDY |
1058                                                 OMAP_I2C_STAT_XDR |
1059                                                 OMAP_I2C_STAT_ARDY));
1060                         break;
1061                 }
1062
1063                 if (stat & OMAP_I2C_STAT_RDR) {
1064                         u8 num_bytes = 1;
1065
1066                         if (omap->fifo_size)
1067                                 num_bytes = omap->buf_len;
1068
1069                         if (omap->errata & I2C_OMAP_ERRATA_I207) {
1070                                 i2c_omap_errata_i207(omap, stat);
1071                                 num_bytes = (omap_i2c_read_reg(omap,
1072                                         OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
1073                         }
1074
1075                         omap_i2c_receive_data(omap, num_bytes, true);
1076                         omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
1077                         continue;
1078                 }
1079
1080                 if (stat & OMAP_I2C_STAT_RRDY) {
1081                         u8 num_bytes = 1;
1082
1083                         if (omap->threshold)
1084                                 num_bytes = omap->threshold;
1085
1086                         omap_i2c_receive_data(omap, num_bytes, false);
1087                         omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
1088                         continue;
1089                 }
1090
1091                 if (stat & OMAP_I2C_STAT_XDR) {
1092                         u8 num_bytes = 1;
1093                         int ret;
1094
1095                         if (omap->fifo_size)
1096                                 num_bytes = omap->buf_len;
1097
1098                         ret = omap_i2c_transmit_data(omap, num_bytes, true);
1099                         if (ret < 0)
1100                                 break;
1101
1102                         omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
1103                         continue;
1104                 }
1105
1106                 if (stat & OMAP_I2C_STAT_XRDY) {
1107                         u8 num_bytes = 1;
1108                         int ret;
1109
1110                         if (omap->threshold)
1111                                 num_bytes = omap->threshold;
1112
1113                         ret = omap_i2c_transmit_data(omap, num_bytes, false);
1114                         if (ret < 0)
1115                                 break;
1116
1117                         omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
1118                         continue;
1119                 }
1120
1121                 if (stat & OMAP_I2C_STAT_ROVR) {
1122                         dev_err(omap->dev, "Receive overrun\n");
1123                         err |= OMAP_I2C_STAT_ROVR;
1124                         omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
1125                         break;
1126                 }
1127
1128                 if (stat & OMAP_I2C_STAT_XUDF) {
1129                         dev_err(omap->dev, "Transmit underflow\n");
1130                         err |= OMAP_I2C_STAT_XUDF;
1131                         omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
1132                         break;
1133                 }
1134         } while (stat);
1135
1136         omap_i2c_complete_cmd(omap, err);
1137
1138 out:
1139         return IRQ_HANDLED;
1140 }
1141
1142 static const struct i2c_algorithm omap_i2c_algo = {
1143         .master_xfer    = omap_i2c_xfer,
1144         .functionality  = omap_i2c_func,
1145 };
1146
1147 #ifdef CONFIG_OF
1148 static struct omap_i2c_bus_platform_data omap2420_pdata = {
1149         .rev = OMAP_I2C_IP_VERSION_1,
1150         .flags = OMAP_I2C_FLAG_NO_FIFO |
1151                         OMAP_I2C_FLAG_SIMPLE_CLOCK |
1152                         OMAP_I2C_FLAG_16BIT_DATA_REG |
1153                         OMAP_I2C_FLAG_BUS_SHIFT_2,
1154 };
1155
1156 static struct omap_i2c_bus_platform_data omap2430_pdata = {
1157         .rev = OMAP_I2C_IP_VERSION_1,
1158         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1159                         OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1160 };
1161
1162 static struct omap_i2c_bus_platform_data omap3_pdata = {
1163         .rev = OMAP_I2C_IP_VERSION_1,
1164         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1165 };
1166
1167 static struct omap_i2c_bus_platform_data omap4_pdata = {
1168         .rev = OMAP_I2C_IP_VERSION_2,
1169 };
1170
1171 static const struct of_device_id omap_i2c_of_match[] = {
1172         {
1173                 .compatible = "ti,omap4-i2c",
1174                 .data = &omap4_pdata,
1175         },
1176         {
1177                 .compatible = "ti,omap3-i2c",
1178                 .data = &omap3_pdata,
1179         },
1180         {
1181                 .compatible = "ti,omap2430-i2c",
1182                 .data = &omap2430_pdata,
1183         },
1184         {
1185                 .compatible = "ti,omap2420-i2c",
1186                 .data = &omap2420_pdata,
1187         },
1188         { },
1189 };
1190 MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1191 #endif
1192
1193 #define OMAP_I2C_SCHEME(rev)            ((rev & 0xc000) >> 14)
1194
1195 #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1196 #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1197
1198 #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1199 #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1200 #define OMAP_I2C_SCHEME_0               0
1201 #define OMAP_I2C_SCHEME_1               1
1202
1203 static int omap_i2c_get_scl(struct i2c_adapter *adap)
1204 {
1205         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1206         u32 reg;
1207
1208         reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1209
1210         return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
1211 }
1212
1213 static int omap_i2c_get_sda(struct i2c_adapter *adap)
1214 {
1215         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1216         u32 reg;
1217
1218         reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1219
1220         return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
1221 }
1222
1223 static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
1224 {
1225         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1226         u32 reg;
1227
1228         reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1229         if (val)
1230                 reg |= OMAP_I2C_SYSTEST_SCL_O;
1231         else
1232                 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1233         omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1234 }
1235
1236 static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
1237 {
1238         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1239         u32 reg;
1240
1241         reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1242         /* enable test mode */
1243         reg |= OMAP_I2C_SYSTEST_ST_EN;
1244         /* select SDA/SCL IO mode */
1245         reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;
1246         /* set SCL to high-impedance state (reset value is 0) */
1247         reg |= OMAP_I2C_SYSTEST_SCL_O;
1248         /* set SDA to high-impedance state (reset value is 0) */
1249         reg |= OMAP_I2C_SYSTEST_SDA_O;
1250         omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1251 }
1252
1253 static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
1254 {
1255         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1256         u32 reg;
1257
1258         reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1259         /* restore reset values */
1260         reg &= ~OMAP_I2C_SYSTEST_ST_EN;
1261         reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;
1262         reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1263         reg &= ~OMAP_I2C_SYSTEST_SDA_O;
1264         omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1265 }
1266
1267 static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
1268         .get_scl                = omap_i2c_get_scl,
1269         .get_sda                = omap_i2c_get_sda,
1270         .set_scl                = omap_i2c_set_scl,
1271         .prepare_recovery       = omap_i2c_prepare_recovery,
1272         .unprepare_recovery     = omap_i2c_unprepare_recovery,
1273         .recover_bus            = i2c_generic_scl_recovery,
1274 };
1275
1276 static int
1277 omap_i2c_probe(struct platform_device *pdev)
1278 {
1279         struct omap_i2c_dev     *omap;
1280         struct i2c_adapter      *adap;
1281         struct resource         *mem;
1282         const struct omap_i2c_bus_platform_data *pdata =
1283                 dev_get_platdata(&pdev->dev);
1284         struct device_node      *node = pdev->dev.of_node;
1285         const struct of_device_id *match;
1286         int irq;
1287         int r;
1288         u32 rev;
1289         u16 minor, major;
1290
1291         irq = platform_get_irq(pdev, 0);
1292         if (irq < 0) {
1293                 dev_err(&pdev->dev, "no irq resource?\n");
1294                 return irq;
1295         }
1296
1297         omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1298         if (!omap)
1299                 return -ENOMEM;
1300
1301         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1302         omap->base = devm_ioremap_resource(&pdev->dev, mem);
1303         if (IS_ERR(omap->base))
1304                 return PTR_ERR(omap->base);
1305
1306         match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1307         if (match) {
1308                 u32 freq = 100000; /* default to 100000 Hz */
1309
1310                 pdata = match->data;
1311                 omap->flags = pdata->flags;
1312
1313                 of_property_read_u32(node, "clock-frequency", &freq);
1314                 /* convert DT freq value in Hz into kHz for speed */
1315                 omap->speed = freq / 1000;
1316         } else if (pdata != NULL) {
1317                 omap->speed = pdata->clkrate;
1318                 omap->flags = pdata->flags;
1319                 omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1320         }
1321
1322         omap->dev = &pdev->dev;
1323         omap->irq = irq;
1324
1325         platform_set_drvdata(pdev, omap);
1326         init_completion(&omap->cmd_complete);
1327
1328         omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1329
1330         pm_runtime_enable(omap->dev);
1331         pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
1332         pm_runtime_use_autosuspend(omap->dev);
1333
1334         r = pm_runtime_get_sync(omap->dev);
1335         if (r < 0)
1336                 goto err_free_mem;
1337
1338         /*
1339          * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1340          * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1341          * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1342          * readw_relaxed is done.
1343          */
1344         rev = readw_relaxed(omap->base + 0x04);
1345
1346         omap->scheme = OMAP_I2C_SCHEME(rev);
1347         switch (omap->scheme) {
1348         case OMAP_I2C_SCHEME_0:
1349                 omap->regs = (u8 *)reg_map_ip_v1;
1350                 omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
1351                 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1352                 major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1353                 break;
1354         case OMAP_I2C_SCHEME_1:
1355                 /* FALLTHROUGH */
1356         default:
1357                 omap->regs = (u8 *)reg_map_ip_v2;
1358                 rev = (rev << 16) |
1359                         omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
1360                 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1361                 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1362                 omap->rev = rev;
1363         }
1364
1365         omap->errata = 0;
1366
1367         if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
1368                         omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
1369                 omap->errata |= I2C_OMAP_ERRATA_I207;
1370
1371         if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
1372                 omap->errata |= I2C_OMAP_ERRATA_I462;
1373
1374         if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1375                 u16 s;
1376
1377                 /* Set up the fifo size - Get total size */
1378                 s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1379                 omap->fifo_size = 0x8 << s;
1380
1381                 /*
1382                  * Set up notification threshold as half the total available
1383                  * size. This is to ensure that we can handle the status on int
1384                  * call back latencies.
1385                  */
1386
1387                 omap->fifo_size = (omap->fifo_size / 2);
1388
1389                 if (omap->rev < OMAP_I2C_REV_ON_3630)
1390                         omap->b_hw = 1; /* Enable hardware fixes */
1391
1392                 /* calculate wakeup latency constraint for MPU */
1393                 if (omap->set_mpu_wkup_lat != NULL)
1394                         omap->latency = (1000000 * omap->fifo_size) /
1395                                        (1000 * omap->speed / 8);
1396         }
1397
1398         /* reset ASAP, clearing any IRQs */
1399         omap_i2c_init(omap);
1400
1401         if (omap->rev < OMAP_I2C_OMAP1_REV_2)
1402                 r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
1403                                 IRQF_NO_SUSPEND, pdev->name, omap);
1404         else
1405                 r = devm_request_threaded_irq(&pdev->dev, omap->irq,
1406                                 omap_i2c_isr, omap_i2c_isr_thread,
1407                                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1408                                 pdev->name, omap);
1409
1410         if (r) {
1411                 dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
1412                 goto err_unuse_clocks;
1413         }
1414
1415         adap = &omap->adapter;
1416         i2c_set_adapdata(adap, omap);
1417         adap->owner = THIS_MODULE;
1418         adap->class = I2C_CLASS_DEPRECATED;
1419         strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1420         adap->algo = &omap_i2c_algo;
1421         adap->dev.parent = &pdev->dev;
1422         adap->dev.of_node = pdev->dev.of_node;
1423         adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
1424
1425         /* i2c device drivers may be active on return from add_adapter() */
1426         adap->nr = pdev->id;
1427         r = i2c_add_numbered_adapter(adap);
1428         if (r)
1429                 goto err_unuse_clocks;
1430
1431         dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1432                  major, minor, omap->speed);
1433
1434         pm_runtime_mark_last_busy(omap->dev);
1435         pm_runtime_put_autosuspend(omap->dev);
1436
1437         return 0;
1438
1439 err_unuse_clocks:
1440         omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1441         pm_runtime_dont_use_autosuspend(omap->dev);
1442         pm_runtime_put_sync(omap->dev);
1443         pm_runtime_disable(&pdev->dev);
1444 err_free_mem:
1445
1446         return r;
1447 }
1448
1449 static int omap_i2c_remove(struct platform_device *pdev)
1450 {
1451         struct omap_i2c_dev     *omap = platform_get_drvdata(pdev);
1452         int ret;
1453
1454         i2c_del_adapter(&omap->adapter);
1455         ret = pm_runtime_get_sync(&pdev->dev);
1456         if (ret < 0)
1457                 return ret;
1458
1459         omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1460         pm_runtime_dont_use_autosuspend(&pdev->dev);
1461         pm_runtime_put_sync(&pdev->dev);
1462         pm_runtime_disable(&pdev->dev);
1463         return 0;
1464 }
1465
1466 #ifdef CONFIG_PM
1467 static int omap_i2c_runtime_suspend(struct device *dev)
1468 {
1469         struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1470
1471         omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1472
1473         if (omap->scheme == OMAP_I2C_SCHEME_0)
1474                 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
1475         else
1476                 omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1477                                    OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1478
1479         if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
1480                 omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
1481         } else {
1482                 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
1483
1484                 /* Flush posted write */
1485                 omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1486         }
1487
1488         pinctrl_pm_select_sleep_state(dev);
1489
1490         return 0;
1491 }
1492
1493 static int omap_i2c_runtime_resume(struct device *dev)
1494 {
1495         struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1496
1497         pinctrl_pm_select_default_state(dev);
1498
1499         if (!omap->regs)
1500                 return 0;
1501
1502         __omap_i2c_init(omap);
1503
1504         return 0;
1505 }
1506
1507 static const struct dev_pm_ops omap_i2c_pm_ops = {
1508         SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1509                            omap_i2c_runtime_resume, NULL)
1510 };
1511 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1512 #else
1513 #define OMAP_I2C_PM_OPS NULL
1514 #endif /* CONFIG_PM */
1515
1516 static struct platform_driver omap_i2c_driver = {
1517         .probe          = omap_i2c_probe,
1518         .remove         = omap_i2c_remove,
1519         .driver         = {
1520                 .name   = "omap_i2c",
1521                 .pm     = OMAP_I2C_PM_OPS,
1522                 .of_match_table = of_match_ptr(omap_i2c_of_match),
1523         },
1524 };
1525
1526 /* I2C may be needed to bring up other drivers */
1527 static int __init
1528 omap_i2c_init_driver(void)
1529 {
1530         return platform_driver_register(&omap_i2c_driver);
1531 }
1532 subsys_initcall(omap_i2c_init_driver);
1533
1534 static void __exit omap_i2c_exit_driver(void)
1535 {
1536         platform_driver_unregister(&omap_i2c_driver);
1537 }
1538 module_exit(omap_i2c_exit_driver);
1539
1540 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1541 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1542 MODULE_LICENSE("GPL");
1543 MODULE_ALIAS("platform:omap_i2c");