drivers/i2c/busses/i2c-mxs.c

   1 /*
   2  * Freescale MXS I2C bus driver
   3  *
   4  * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
   5  *
   6  * based on a (non-working) driver which was:
   7  *
   8  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/device.h>
  19 #include <linux/module.h>
  20 #include <linux/i2c.h>
  21 #include <linux/err.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/completion.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/io.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/stmp_device.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/of_i2c.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/dmaengine.h>
  34 #include <linux/fsl/mxs-dma.h>
  35
  36 #define DRIVER_NAME "mxs-i2c"
  37
  38 #define MXS_I2C_CTRL0           (0x00)
  39 #define MXS_I2C_CTRL0_SET       (0x04)
  40
  41 #define MXS_I2C_CTRL0_SFTRST                    0x80000000
  42 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST          0x02000000
  43 #define MXS_I2C_CTRL0_RETAIN_CLOCK              0x00200000
  44 #define MXS_I2C_CTRL0_POST_SEND_STOP            0x00100000
  45 #define MXS_I2C_CTRL0_PRE_SEND_START            0x00080000
  46 #define MXS_I2C_CTRL0_MASTER_MODE               0x00020000
  47 #define MXS_I2C_CTRL0_DIRECTION                 0x00010000
  48 #define MXS_I2C_CTRL0_XFER_COUNT(v)             ((v) & 0x0000FFFF)
  49
  50 #define MXS_I2C_TIMING0         (0x10)
  51 #define MXS_I2C_TIMING1         (0x20)
  52 #define MXS_I2C_TIMING2         (0x30)
  53
  54 #define MXS_I2C_CTRL1           (0x40)
  55 #define MXS_I2C_CTRL1_SET       (0x44)
  56 #define MXS_I2C_CTRL1_CLR       (0x48)
  57
  58 #define MXS_I2C_CTRL1_BUS_FREE_IRQ              0x80
  59 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ     0x40
  60 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ          0x20
  61 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ    0x10
  62 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ            0x08
  63 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ           0x04
  64 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ            0x02
  65 #define MXS_I2C_CTRL1_SLAVE_IRQ                 0x01
  66
  67 #define MXS_I2C_IRQ_MASK        (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
  68                                  MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
  69                                  MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
  70                                  MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
  71                                  MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
  72                                  MXS_I2C_CTRL1_SLAVE_IRQ)
  73
  74
  75 #define MXS_CMD_I2C_SELECT      (MXS_I2C_CTRL0_RETAIN_CLOCK |   \
  76                                  MXS_I2C_CTRL0_PRE_SEND_START | \
  77                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  78                                  MXS_I2C_CTRL0_DIRECTION |      \
  79                                  MXS_I2C_CTRL0_XFER_COUNT(1))
  80
  81 #define MXS_CMD_I2C_WRITE       (MXS_I2C_CTRL0_PRE_SEND_START | \
  82                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  83                                  MXS_I2C_CTRL0_DIRECTION)
  84
  85 #define MXS_CMD_I2C_READ        (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
  86                                  MXS_I2C_CTRL0_MASTER_MODE)
  87
  88 struct mxs_i2c_speed_config {
  89         uint32_t        timing0;
  90         uint32_t        timing1;
  91         uint32_t        timing2;
  92 };
  93
  94 /*
  95  * Timing values for the default 24MHz clock supplied into the i2c block.
  96  *
  97  * The bus can operate at 95kHz or at 400kHz with the following timing
  98  * register configurations. The 100kHz mode isn't present because it's
  99  * values are not stated in the i.MX233/i.MX28 datasheet. The 95kHz mode
 100  * shall be close enough replacement. Therefore when the bus is configured
 101  * for 100kHz operation, 95kHz timing settings are actually loaded.
 102  *
 103  * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
 104  */
 105 static const struct mxs_i2c_speed_config mxs_i2c_95kHz_config = {
 106         .timing0        = 0x00780030,
 107         .timing1        = 0x00800030,
 108         .timing2        = 0x00300030,
 109 };
 110
 111 static const struct mxs_i2c_speed_config mxs_i2c_400kHz_config = {
 112         .timing0        = 0x000f0007,
 113         .timing1        = 0x001f000f,
 114         .timing2        = 0x00300030,
 115 };
 116
 117 /**
 118  * struct mxs_i2c_dev - per device, private MXS-I2C data
 119  *
 120  * @dev: driver model device node
 121  * @regs: IO registers pointer
 122  * @cmd_complete: completion object for transaction wait
 123  * @cmd_err: error code for last transaction
 124  * @adapter: i2c subsystem adapter node
 125  */
 126 struct mxs_i2c_dev {
 127         struct device *dev;
 128         void __iomem *regs;
 129         struct completion cmd_complete;
 130         u32 cmd_err;
 131         struct i2c_adapter adapter;
 132         const struct mxs_i2c_speed_config *speed;
 133
 134         /* DMA support components */
 135         int                             dma_channel;
 136         struct dma_chan                 *dmach;
 137         struct mxs_dma_data             dma_data;
 138         uint32_t                        pio_data[2];
 139         uint32_t                        addr_data;
 140         struct scatterlist              sg_io[2];
 141         bool                            dma_read;
 142 };
 143
 144 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 145 {
 146         stmp_reset_block(i2c->regs);
 147
 148         writel(i2c->speed->timing0, i2c->regs + MXS_I2C_TIMING0);
 149         writel(i2c->speed->timing1, i2c->regs + MXS_I2C_TIMING1);
 150         writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2);
 151
 152         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 153 }
 154
 155 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
 156 {
 157         if (i2c->dma_read) {
 158                 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 159                 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 160         } else {
 161                 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 162         }
 163 }
 164
 165 static void mxs_i2c_dma_irq_callback(void *param)
 166 {
 167         struct mxs_i2c_dev *i2c = param;
 168
 169         complete(&i2c->cmd_complete);
 170         mxs_i2c_dma_finish(i2c);
 171 }
 172
 173 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
 174                         struct i2c_msg *msg, uint32_t flags)
 175 {
 176         struct dma_async_tx_descriptor *desc;
 177         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 178
 179         if (msg->flags & I2C_M_RD) {
 180                 i2c->dma_read = 1;
 181                 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
 182
 183                 /*
 184                  * SELECT command.
 185                  */
 186
 187                 /* Queue the PIO register write transfer. */
 188                 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
 189                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 190                                         (struct scatterlist *)&i2c->pio_data[0],
 191                                         1, DMA_TRANS_NONE, 0);
 192                 if (!desc) {
 193                         dev_err(i2c->dev,
 194                                 "Failed to get PIO reg. write descriptor.\n");
 195                         goto select_init_pio_fail;
 196                 }
 197
 198                 /* Queue the DMA data transfer. */
 199                 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
 200                 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 201                 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
 202                                         DMA_MEM_TO_DEV,
 203                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 204                 if (!desc) {
 205                         dev_err(i2c->dev,
 206                                 "Failed to get DMA data write descriptor.\n");
 207                         goto select_init_dma_fail;
 208                 }
 209
 210                 /*
 211                  * READ command.
 212                  */
 213
 214                 /* Queue the PIO register write transfer. */
 215                 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
 216                                 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
 217                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 218                                         (struct scatterlist *)&i2c->pio_data[1],
 219                                         1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
 220                 if (!desc) {
 221                         dev_err(i2c->dev,
 222                                 "Failed to get PIO reg. write descriptor.\n");
 223                         goto select_init_dma_fail;
 224                 }
 225
 226                 /* Queue the DMA data transfer. */
 227                 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
 228                 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 229                 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
 230                                         DMA_DEV_TO_MEM,
 231                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 232                 if (!desc) {
 233                         dev_err(i2c->dev,
 234                                 "Failed to get DMA data write descriptor.\n");
 235                         goto read_init_dma_fail;
 236                 }
 237         } else {
 238                 i2c->dma_read = 0;
 239                 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
 240
 241                 /*
 242                  * WRITE command.
 243                  */
 244
 245                 /* Queue the PIO register write transfer. */
 246                 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
 247                                 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
 248                 desc = dmaengine_prep_slave_sg(i2c->dmach,
 249                                         (struct scatterlist *)&i2c->pio_data[0],
 250                                         1, DMA_TRANS_NONE, 0);
 251                 if (!desc) {
 252                         dev_err(i2c->dev,
 253                                 "Failed to get PIO reg. write descriptor.\n");
 254                         goto write_init_pio_fail;
 255                 }
 256
 257                 /* Queue the DMA data transfer. */
 258                 sg_init_table(i2c->sg_io, 2);
 259                 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
 260                 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
 261                 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 262                 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
 263                                         DMA_MEM_TO_DEV,
 264                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 265                 if (!desc) {
 266                         dev_err(i2c->dev,
 267                                 "Failed to get DMA data write descriptor.\n");
 268                         goto write_init_dma_fail;
 269                 }
 270         }
 271
 272         /*
 273          * The last descriptor must have this callback,
 274          * to finish the DMA transaction.
 275          */
 276         desc->callback = mxs_i2c_dma_irq_callback;
 277         desc->callback_param = i2c;
 278
 279         /* Start the transfer. */
 280         dmaengine_submit(desc);
 281         dma_async_issue_pending(i2c->dmach);
 282         return 0;
 283
 284 /* Read failpath. */
 285 read_init_dma_fail:
 286         dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 287 select_init_dma_fail:
 288         dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 289 select_init_pio_fail:
 290         return -EINVAL;
 291
 292 /* Write failpath. */
 293 write_init_dma_fail:
 294         dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 295 write_init_pio_fail:
 296         return -EINVAL;
 297 }
 298
 299 /*
 300  * Low level master read/write transaction.
 301  */
 302 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 303                                 int stop)
 304 {
 305         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 306         int ret;
 307         int flags;
 308
 309         flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
 310
 311         dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 312                 msg->addr, msg->len, msg->flags, stop);
 313
 314         if (msg->len == 0)
 315                 return -EINVAL;
 316
 317         init_completion(&i2c->cmd_complete);
 318         i2c->cmd_err = 0;
 319
 320         ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
 321         if (ret)
 322                 return ret;
 323
 324         ret = wait_for_completion_timeout(&i2c->cmd_complete,
 325                                                 msecs_to_jiffies(1000));
 326         if (ret == 0)
 327                 goto timeout;
 328
 329         if (i2c->cmd_err == -ENXIO)
 330                 mxs_i2c_reset(i2c);
 331
 332         dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
 333
 334         return i2c->cmd_err;
 335
 336 timeout:
 337         dev_dbg(i2c->dev, "Timeout!\n");
 338         mxs_i2c_dma_finish(i2c);
 339         mxs_i2c_reset(i2c);
 340         return -ETIMEDOUT;
 341 }
 342
 343 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 344                         int num)
 345 {
 346         int i;
 347         int err;
 348
 349         for (i = 0; i < num; i++) {
 350                 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
 351                 if (err)
 352                         return err;
 353         }
 354
 355         return num;
 356 }
 357
 358 static u32 mxs_i2c_func(struct i2c_adapter *adap)
 359 {
 360         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 361 }
 362
 363 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
 364 {
 365         struct mxs_i2c_dev *i2c = dev_id;
 366         u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
 367
 368         if (!stat)
 369                 return IRQ_NONE;
 370
 371         if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 372                 i2c->cmd_err = -ENXIO;
 373         else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
 374                     MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
 375                     MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
 376                 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
 377                 i2c->cmd_err = -EIO;
 378
 379         writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
 380
 381         return IRQ_HANDLED;
 382 }
 383
 384 static const struct i2c_algorithm mxs_i2c_algo = {
 385         .master_xfer = mxs_i2c_xfer,
 386         .functionality = mxs_i2c_func,
 387 };
 388
 389 static bool mxs_i2c_dma_filter(struct dma_chan *chan, void *param)
 390 {
 391         struct mxs_i2c_dev *i2c = param;
 392
 393         if (!mxs_dma_is_apbx(chan))
 394                 return false;
 395
 396         if (chan->chan_id != i2c->dma_channel)
 397                 return false;
 398
 399         chan->private = &i2c->dma_data;
 400
 401         return true;
 402 }
 403
 404 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
 405 {
 406         uint32_t speed;
 407         struct device *dev = i2c->dev;
 408         struct device_node *node = dev->of_node;
 409         int ret;
 410
 411         /*
 412          * TODO: This is a temporary solution and should be changed
 413          * to use generic DMA binding later when the helpers get in.
 414          */
 415         ret = of_property_read_u32(node, "fsl,i2c-dma-channel",
 416                                    &i2c->dma_channel);
 417         if (ret) {
 418                 dev_err(dev, "Failed to get DMA channel!\n");
 419                 return -ENODEV;
 420         }
 421
 422         ret = of_property_read_u32(node, "clock-frequency", &speed);
 423         if (ret)
 424                 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
 425         else if (speed == 400000)
 426                 i2c->speed = &mxs_i2c_400kHz_config;
 427         else if (speed != 100000)
 428                 dev_warn(dev, "Unsupported I2C speed selected, using 100kHz\n");
 429
 430         return 0;
 431 }
 432
 433 static int __devinit mxs_i2c_probe(struct platform_device *pdev)
 434 {
 435         struct device *dev = &pdev->dev;
 436         struct mxs_i2c_dev *i2c;
 437         struct i2c_adapter *adap;
 438         struct pinctrl *pinctrl;
 439         struct resource *res;
 440         resource_size_t res_size;
 441         int err, irq, dmairq;
 442         dma_cap_mask_t mask;
 443
 444         pinctrl = devm_pinctrl_get_select_default(dev);
 445         if (IS_ERR(pinctrl))
 446                 return PTR_ERR(pinctrl);
 447
 448         i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
 449         if (!i2c)
 450                 return -ENOMEM;
 451
 452         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 453         irq = platform_get_irq(pdev, 0);
 454         dmairq = platform_get_irq(pdev, 1);
 455
 456         if (!res || irq < 0 || dmairq < 0)
 457                 return -ENOENT;
 458
 459         res_size = resource_size(res);
 460         if (!devm_request_mem_region(dev, res->start, res_size, res->name))
 461                 return -EBUSY;
 462
 463         i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
 464         if (!i2c->regs)
 465                 return -EBUSY;
 466
 467         err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
 468         if (err)
 469                 return err;
 470
 471         i2c->dev = dev;
 472         i2c->speed = &mxs_i2c_95kHz_config;
 473
 474         if (dev->of_node) {
 475                 err = mxs_i2c_get_ofdata(i2c);
 476                 if (err)
 477                         return err;
 478         }
 479
 480         /* Setup the DMA */
 481         dma_cap_zero(mask);
 482         dma_cap_set(DMA_SLAVE, mask);
 483         i2c->dma_data.chan_irq = dmairq;
 484         i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c);
 485         if (!i2c->dmach) {
 486                 dev_err(dev, "Failed to request dma\n");
 487                 return -ENODEV;
 488         }
 489
 490         platform_set_drvdata(pdev, i2c);
 491
 492         /* Do reset to enforce correct startup after pinmuxing */
 493         mxs_i2c_reset(i2c);
 494
 495         adap = &i2c->adapter;
 496         strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
 497         adap->owner = THIS_MODULE;
 498         adap->algo = &mxs_i2c_algo;
 499         adap->dev.parent = dev;
 500         adap->nr = pdev->id;
 501         adap->dev.of_node = pdev->dev.of_node;
 502         i2c_set_adapdata(adap, i2c);
 503         err = i2c_add_numbered_adapter(adap);
 504         if (err) {
 505                 dev_err(dev, "Failed to add adapter (%d)\n", err);
 506                 writel(MXS_I2C_CTRL0_SFTRST,
 507                                 i2c->regs + MXS_I2C_CTRL0_SET);
 508                 return err;
 509         }
 510
 511         of_i2c_register_devices(adap);
 512
 513         return 0;
 514 }
 515
 516 static int __devexit mxs_i2c_remove(struct platform_device *pdev)
 517 {
 518         struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
 519         int ret;
 520
 521         ret = i2c_del_adapter(&i2c->adapter);
 522         if (ret)
 523                 return -EBUSY;
 524
 525         if (i2c->dmach)
 526                 dma_release_channel(i2c->dmach);
 527
 528         writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
 529
 530         platform_set_drvdata(pdev, NULL);
 531
 532         return 0;
 533 }
 534
 535 static const struct of_device_id mxs_i2c_dt_ids[] = {
 536         { .compatible = "fsl,imx28-i2c", },
 537         { /* sentinel */ }
 538 };
 539 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
 540
 541 static struct platform_driver mxs_i2c_driver = {
 542         .driver = {
 543                    .name = DRIVER_NAME,
 544                    .owner = THIS_MODULE,
 545                    .of_match_table = mxs_i2c_dt_ids,
 546                    },
 547         .remove = __devexit_p(mxs_i2c_remove),
 548 };
 549
 550 static int __init mxs_i2c_init(void)
 551 {
 552         return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
 553 }
 554 subsys_initcall(mxs_i2c_init);
 555
 556 static void __exit mxs_i2c_exit(void)
 557 {
 558         platform_driver_unregister(&mxs_i2c_driver);
 559 }
 560 module_exit(mxs_i2c_exit);
 561
 562 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
 563 MODULE_DESCRIPTION("MXS I2C Bus Driver");
 564 MODULE_LICENSE("GPL");
 565 MODULE_ALIAS("platform:" DRIVER_NAME);