drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  63  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  64  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  65  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  66  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  67  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  68  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  69  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  70  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  71  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  72  *
  73  * Features supported by this driver:
  74  * Software PEC                         no
  75  * Hardware PEC                         yes
  76  * Block buffer                         yes
  77  * Block process call transaction       no
  78  * I2C block read transaction           yes (doesn't use the block buffer)
  79  * Slave mode                           no
  80  * SMBus Host Notify                    yes
  81  * Interrupt processing                 yes
  82  *
  83  * See the file Documentation/i2c/busses/i2c-i801 for details.
  84  */
  85
  86 #include <linux/interrupt.h>
  87 #include <linux/module.h>
  88 #include <linux/pci.h>
  89 #include <linux/kernel.h>
  90 #include <linux/stddef.h>
  91 #include <linux/delay.h>
  92 #include <linux/ioport.h>
  93 #include <linux/init.h>
  94 #include <linux/i2c.h>
  95 #include <linux/i2c-smbus.h>
  96 #include <linux/acpi.h>
  97 #include <linux/io.h>
  98 #include <linux/dmi.h>
  99 #include <linux/slab.h>
 100 #include <linux/wait.h>
 101 #include <linux/err.h>
 102 #include <linux/platform_device.h>
 103 #include <linux/platform_data/itco_wdt.h>
 104 #include <linux/pm_runtime.h>
 105
 106 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 107 #include <linux/gpio.h>
 108 #include <linux/i2c-mux-gpio.h>
 109 #endif
 110
 111 /* I801 SMBus address offsets */
 112 #define SMBHSTSTS(p)    (0 + (p)->smba)
 113 #define SMBHSTCNT(p)    (2 + (p)->smba)
 114 #define SMBHSTCMD(p)    (3 + (p)->smba)
 115 #define SMBHSTADD(p)    (4 + (p)->smba)
 116 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 117 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 118 #define SMBBLKDAT(p)    (7 + (p)->smba)
 119 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 120 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 121 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 122 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 123 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 124 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 125
 126 /* PCI Address Constants */
 127 #define SMBBAR          4
 128 #define SMBPCICTL       0x004
 129 #define SMBPCISTS       0x006
 130 #define SMBHSTCFG       0x040
 131 #define TCOBASE         0x050
 132 #define TCOCTL          0x054
 133
 134 #define ACPIBASE                0x040
 135 #define ACPIBASE_SMI_OFF        0x030
 136 #define ACPICTRL                0x044
 137 #define ACPICTRL_EN             0x080
 138
 139 #define SBREG_BAR               0x10
 140 #define SBREG_SMBCTRL           0xc6000c
 141
 142 /* Host status bits for SMBPCISTS */
 143 #define SMBPCISTS_INTS          BIT(3)
 144
 145 /* Control bits for SMBPCICTL */
 146 #define SMBPCICTL_INTDIS        BIT(10)
 147
 148 /* Host configuration bits for SMBHSTCFG */
 149 #define SMBHSTCFG_HST_EN        BIT(0)
 150 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 151 #define SMBHSTCFG_I2C_EN        BIT(2)
 152 #define SMBHSTCFG_SPD_WD        BIT(4)
 153
 154 /* TCO configuration bits for TCOCTL */
 155 #define TCOCTL_EN               BIT(8)
 156
 157 /* Auxiliary status register bits, ICH4+ only */
 158 #define SMBAUXSTS_CRCE          BIT(0)
 159 #define SMBAUXSTS_STCO          BIT(1)
 160
 161 /* Auxiliary control register bits, ICH4+ only */
 162 #define SMBAUXCTL_CRC           BIT(0)
 163 #define SMBAUXCTL_E32B          BIT(1)
 164
 165 /* Other settings */
 166 #define MAX_RETRIES             400
 167
 168 /* I801 command constants */
 169 #define I801_QUICK              0x00
 170 #define I801_BYTE               0x04
 171 #define I801_BYTE_DATA          0x08
 172 #define I801_WORD_DATA          0x0C
 173 #define I801_PROC_CALL          0x10    /* unimplemented */
 174 #define I801_BLOCK_DATA         0x14
 175 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 176
 177 /* I801 Host Control register bits */
 178 #define SMBHSTCNT_INTREN        BIT(0)
 179 #define SMBHSTCNT_KILL          BIT(1)
 180 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 181 #define SMBHSTCNT_START         BIT(6)
 182 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 183
 184 /* I801 Hosts Status register bits */
 185 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 186 #define SMBHSTSTS_INUSE_STS     BIT(6)
 187 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 188 #define SMBHSTSTS_FAILED        BIT(4)
 189 #define SMBHSTSTS_BUS_ERR       BIT(3)
 190 #define SMBHSTSTS_DEV_ERR       BIT(2)
 191 #define SMBHSTSTS_INTR          BIT(1)
 192 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 193
 194 /* Host Notify Status register bits */
 195 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 196
 197 /* Host Notify Command register bits */
 198 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 199
 200 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 201                                  SMBHSTSTS_DEV_ERR)
 202
 203 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 204                                  STATUS_ERROR_FLAGS)
 205
 206 /* Older devices have their ID defined in <linux/pci_ids.h> */
 207 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 208 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 209 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 210 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 212 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 216 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 217 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 218 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 219 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 220 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 221 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 222 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 223 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 224 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 225 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 226 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 227 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 228 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 229 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 230 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 231 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 232 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 233 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 234 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 235 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 236 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 237 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 238 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 239
 240 struct i801_mux_config {
 241         char *gpio_chip;
 242         unsigned values[3];
 243         int n_values;
 244         unsigned classes[3];
 245         unsigned gpios[2];              /* Relative to gpio_chip->base */
 246         int n_gpios;
 247 };
 248
 249 struct i801_priv {
 250         struct i2c_adapter adapter;
 251         unsigned long smba;
 252         unsigned char original_hstcfg;
 253         unsigned char original_slvcmd;
 254         struct pci_dev *pci_dev;
 255         unsigned int features;
 256
 257         /* isr processing */
 258         wait_queue_head_t waitq;
 259         u8 status;
 260
 261         /* Command state used by isr for byte-by-byte block transactions */
 262         u8 cmd;
 263         bool is_read;
 264         int count;
 265         int len;
 266         u8 *data;
 267
 268 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 269         const struct i801_mux_config *mux_drvdata;
 270         struct platform_device *mux_pdev;
 271 #endif
 272         struct platform_device *tco_pdev;
 273
 274         /*
 275          * If set to true the host controller registers are reserved for
 276          * ACPI AML use. Protected by acpi_lock.
 277          */
 278         bool acpi_reserved;
 279         struct mutex acpi_lock;
 280 };
 281
 282 #define FEATURE_SMBUS_PEC       BIT(0)
 283 #define FEATURE_BLOCK_BUFFER    BIT(1)
 284 #define FEATURE_BLOCK_PROC      BIT(2)
 285 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 286 #define FEATURE_IRQ             BIT(4)
 287 #define FEATURE_HOST_NOTIFY     BIT(5)
 288 /* Not really a feature, but it's convenient to handle it as such */
 289 #define FEATURE_IDF             BIT(15)
 290 #define FEATURE_TCO             BIT(16)
 291
 292 static const char *i801_feature_names[] = {
 293         "SMBus PEC",
 294         "Block buffer",
 295         "Block process call",
 296         "I2C block read",
 297         "Interrupt",
 298         "SMBus Host Notify",
 299 };
 300
 301 static unsigned int disable_features;
 302 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 303 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 304         "\t\t  0x01  disable SMBus PEC\n"
 305         "\t\t  0x02  disable the block buffer\n"
 306         "\t\t  0x08  disable the I2C block read functionality\n"
 307         "\t\t  0x10  don't use interrupts\n"
 308         "\t\t  0x20  disable SMBus Host Notify ");
 309
 310 /* Make sure the SMBus host is ready to start transmitting.
 311    Return 0 if it is, -EBUSY if it is not. */
 312 static int i801_check_pre(struct i801_priv *priv)
 313 {
 314         int status;
 315
 316         status = inb_p(SMBHSTSTS(priv));
 317         if (status & SMBHSTSTS_HOST_BUSY) {
 318                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 319                 return -EBUSY;
 320         }
 321
 322         status &= STATUS_FLAGS;
 323         if (status) {
 324                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 325                         status);
 326                 outb_p(status, SMBHSTSTS(priv));
 327                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 328                 if (status) {
 329                         dev_err(&priv->pci_dev->dev,
 330                                 "Failed clearing status flags (%02x)\n",
 331                                 status);
 332                         return -EBUSY;
 333                 }
 334         }
 335
 336         /*
 337          * Clear CRC status if needed.
 338          * During normal operation, i801_check_post() takes care
 339          * of it after every operation.  We do it here only in case
 340          * the hardware was already in this state when the driver
 341          * started.
 342          */
 343         if (priv->features & FEATURE_SMBUS_PEC) {
 344                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 345                 if (status) {
 346                         dev_dbg(&priv->pci_dev->dev,
 347                                 "Clearing aux status flags (%02x)\n", status);
 348                         outb_p(status, SMBAUXSTS(priv));
 349                         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 350                         if (status) {
 351                                 dev_err(&priv->pci_dev->dev,
 352                                         "Failed clearing aux status flags (%02x)\n",
 353                                         status);
 354                                 return -EBUSY;
 355                         }
 356                 }
 357         }
 358
 359         return 0;
 360 }
 361
 362 /*
 363  * Convert the status register to an error code, and clear it.
 364  * Note that status only contains the bits we want to clear, not the
 365  * actual register value.
 366  */
 367 static int i801_check_post(struct i801_priv *priv, int status)
 368 {
 369         int result = 0;
 370
 371         /*
 372          * If the SMBus is still busy, we give up
 373          * Note: This timeout condition only happens when using polling
 374          * transactions.  For interrupt operation, NAK/timeout is indicated by
 375          * DEV_ERR.
 376          */
 377         if (unlikely(status < 0)) {
 378                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 379                 /* try to stop the current command */
 380                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 381                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 382                        SMBHSTCNT(priv));
 383                 usleep_range(1000, 2000);
 384                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 385                        SMBHSTCNT(priv));
 386
 387                 /* Check if it worked */
 388                 status = inb_p(SMBHSTSTS(priv));
 389                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 390                     !(status & SMBHSTSTS_FAILED))
 391                         dev_err(&priv->pci_dev->dev,
 392                                 "Failed terminating the transaction\n");
 393                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 394                 return -ETIMEDOUT;
 395         }
 396
 397         if (status & SMBHSTSTS_FAILED) {
 398                 result = -EIO;
 399                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 400         }
 401         if (status & SMBHSTSTS_DEV_ERR) {
 402                 /*
 403                  * This may be a PEC error, check and clear it.
 404                  *
 405                  * AUXSTS is handled differently from HSTSTS.
 406                  * For HSTSTS, i801_isr() or i801_wait_intr()
 407                  * has already cleared the error bits in hardware,
 408                  * and we are passed a copy of the original value
 409                  * in "status".
 410                  * For AUXSTS, the hardware register is left
 411                  * for us to handle here.
 412                  * This is asymmetric, slightly iffy, but safe,
 413                  * since all this code is serialized and the CRCE
 414                  * bit is harmless as long as it's cleared before
 415                  * the next operation.
 416                  */
 417                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 418                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 419                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 420                         result = -EBADMSG;
 421                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 422                 } else {
 423                         result = -ENXIO;
 424                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 425                 }
 426         }
 427         if (status & SMBHSTSTS_BUS_ERR) {
 428                 result = -EAGAIN;
 429                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 430         }
 431
 432         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 433         outb_p(status, SMBHSTSTS(priv));
 434
 435         return result;
 436 }
 437
 438 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 439 static int i801_wait_intr(struct i801_priv *priv)
 440 {
 441         int timeout = 0;
 442         int status;
 443
 444         /* We will always wait for a fraction of a second! */
 445         do {
 446                 usleep_range(250, 500);
 447                 status = inb_p(SMBHSTSTS(priv));
 448         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 449                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 450                  (timeout++ < MAX_RETRIES));
 451
 452         if (timeout > MAX_RETRIES) {
 453                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 454                 return -ETIMEDOUT;
 455         }
 456         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 457 }
 458
 459 /* Wait for either BYTE_DONE or an error flag being set */
 460 static int i801_wait_byte_done(struct i801_priv *priv)
 461 {
 462         int timeout = 0;
 463         int status;
 464
 465         /* We will always wait for a fraction of a second! */
 466         do {
 467                 usleep_range(250, 500);
 468                 status = inb_p(SMBHSTSTS(priv));
 469         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 470                  (timeout++ < MAX_RETRIES));
 471
 472         if (timeout > MAX_RETRIES) {
 473                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 474                 return -ETIMEDOUT;
 475         }
 476         return status & STATUS_ERROR_FLAGS;
 477 }
 478
 479 static int i801_transaction(struct i801_priv *priv, int xact)
 480 {
 481         int status;
 482         int result;
 483         const struct i2c_adapter *adap = &priv->adapter;
 484
 485         result = i801_check_pre(priv);
 486         if (result < 0)
 487                 return result;
 488
 489         if (priv->features & FEATURE_IRQ) {
 490                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 491                        SMBHSTCNT(priv));
 492                 result = wait_event_timeout(priv->waitq,
 493                                             (status = priv->status),
 494                                             adap->timeout);
 495                 if (!result) {
 496                         status = -ETIMEDOUT;
 497                         dev_warn(&priv->pci_dev->dev,
 498                                  "Timeout waiting for interrupt!\n");
 499                 }
 500                 priv->status = 0;
 501                 return i801_check_post(priv, status);
 502         }
 503
 504         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 505          * SMBSCMD are passed in xact */
 506         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 507
 508         status = i801_wait_intr(priv);
 509         return i801_check_post(priv, status);
 510 }
 511
 512 static int i801_block_transaction_by_block(struct i801_priv *priv,
 513                                            union i2c_smbus_data *data,
 514                                            char read_write, int hwpec)
 515 {
 516         int i, len;
 517         int status;
 518
 519         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 520
 521         /* Use 32-byte buffer to process this transaction */
 522         if (read_write == I2C_SMBUS_WRITE) {
 523                 len = data->block[0];
 524                 outb_p(len, SMBHSTDAT0(priv));
 525                 for (i = 0; i < len; i++)
 526                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 527         }
 528
 529         status = i801_transaction(priv, I801_BLOCK_DATA |
 530                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 531         if (status)
 532                 return status;
 533
 534         if (read_write == I2C_SMBUS_READ) {
 535                 len = inb_p(SMBHSTDAT0(priv));
 536                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 537                         return -EPROTO;
 538
 539                 data->block[0] = len;
 540                 for (i = 0; i < len; i++)
 541                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 542         }
 543         return 0;
 544 }
 545
 546 static void i801_isr_byte_done(struct i801_priv *priv)
 547 {
 548         if (priv->is_read) {
 549                 /* For SMBus block reads, length is received with first byte */
 550                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 551                     (priv->count == 0)) {
 552                         priv->len = inb_p(SMBHSTDAT0(priv));
 553                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 554                                 dev_err(&priv->pci_dev->dev,
 555                                         "Illegal SMBus block read size %d\n",
 556                                         priv->len);
 557                                 /* FIXME: Recover */
 558                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 559                         } else {
 560                                 dev_dbg(&priv->pci_dev->dev,
 561                                         "SMBus block read size is %d\n",
 562                                         priv->len);
 563                         }
 564                         priv->data[-1] = priv->len;
 565                 }
 566
 567                 /* Read next byte */
 568                 if (priv->count < priv->len)
 569                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 570                 else
 571                         dev_dbg(&priv->pci_dev->dev,
 572                                 "Discarding extra byte on block read\n");
 573
 574                 /* Set LAST_BYTE for last byte of read transaction */
 575                 if (priv->count == priv->len - 1)
 576                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 577                                SMBHSTCNT(priv));
 578         } else if (priv->count < priv->len - 1) {
 579                 /* Write next byte, except for IRQ after last byte */
 580                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 581         }
 582
 583         /* Clear BYTE_DONE to continue with next byte */
 584         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 585 }
 586
 587 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 588 {
 589         unsigned short addr;
 590
 591         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 592
 593         /*
 594          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 595          * always returns 0. Our current implementation doesn't provide
 596          * data, so we just ignore it.
 597          */
 598         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 599
 600         /* clear Host Notify bit and return */
 601         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 602         return IRQ_HANDLED;
 603 }
 604
 605 /*
 606  * There are three kinds of interrupts:
 607  *
 608  * 1) i801 signals transaction completion with one of these interrupts:
 609  *      INTR - Success
 610  *      DEV_ERR - Invalid command, NAK or communication timeout
 611  *      BUS_ERR - SMI# transaction collision
 612  *      FAILED - transaction was canceled due to a KILL request
 613  *    When any of these occur, update ->status and wake up the waitq.
 614  *    ->status must be cleared before kicking off the next transaction.
 615  *
 616  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 617  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 618  *
 619  * 3) Host Notify interrupts
 620  */
 621 static irqreturn_t i801_isr(int irq, void *dev_id)
 622 {
 623         struct i801_priv *priv = dev_id;
 624         u16 pcists;
 625         u8 status;
 626
 627         /* Confirm this is our interrupt */
 628         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 629         if (!(pcists & SMBPCISTS_INTS))
 630                 return IRQ_NONE;
 631
 632         if (priv->features & FEATURE_HOST_NOTIFY) {
 633                 status = inb_p(SMBSLVSTS(priv));
 634                 if (status & SMBSLVSTS_HST_NTFY_STS)
 635                         return i801_host_notify_isr(priv);
 636         }
 637
 638         status = inb_p(SMBHSTSTS(priv));
 639         if (status & SMBHSTSTS_BYTE_DONE)
 640                 i801_isr_byte_done(priv);
 641
 642         /*
 643          * Clear irq sources and report transaction result.
 644          * ->status must be cleared before the next transaction is started.
 645          */
 646         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 647         if (status) {
 648                 outb_p(status, SMBHSTSTS(priv));
 649                 priv->status = status;
 650                 wake_up(&priv->waitq);
 651         }
 652
 653         return IRQ_HANDLED;
 654 }
 655
 656 /*
 657  * For "byte-by-byte" block transactions:
 658  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 659  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 660  */
 661 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 662                                                union i2c_smbus_data *data,
 663                                                char read_write, int command,
 664                                                int hwpec)
 665 {
 666         int i, len;
 667         int smbcmd;
 668         int status;
 669         int result;
 670         const struct i2c_adapter *adap = &priv->adapter;
 671
 672         result = i801_check_pre(priv);
 673         if (result < 0)
 674                 return result;
 675
 676         len = data->block[0];
 677
 678         if (read_write == I2C_SMBUS_WRITE) {
 679                 outb_p(len, SMBHSTDAT0(priv));
 680                 outb_p(data->block[1], SMBBLKDAT(priv));
 681         }
 682
 683         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 684             read_write == I2C_SMBUS_READ)
 685                 smbcmd = I801_I2C_BLOCK_DATA;
 686         else
 687                 smbcmd = I801_BLOCK_DATA;
 688
 689         if (priv->features & FEATURE_IRQ) {
 690                 priv->is_read = (read_write == I2C_SMBUS_READ);
 691                 if (len == 1 && priv->is_read)
 692                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 693                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 694                 priv->len = len;
 695                 priv->count = 0;
 696                 priv->data = &data->block[1];
 697
 698                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 699                 result = wait_event_timeout(priv->waitq,
 700                                             (status = priv->status),
 701                                             adap->timeout);
 702                 if (!result) {
 703                         status = -ETIMEDOUT;
 704                         dev_warn(&priv->pci_dev->dev,
 705                                  "Timeout waiting for interrupt!\n");
 706                 }
 707                 priv->status = 0;
 708                 return i801_check_post(priv, status);
 709         }
 710
 711         for (i = 1; i <= len; i++) {
 712                 if (i == len && read_write == I2C_SMBUS_READ)
 713                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 714                 outb_p(smbcmd, SMBHSTCNT(priv));
 715
 716                 if (i == 1)
 717                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 718                                SMBHSTCNT(priv));
 719
 720                 status = i801_wait_byte_done(priv);
 721                 if (status)
 722                         goto exit;
 723
 724                 if (i == 1 && read_write == I2C_SMBUS_READ
 725                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 726                         len = inb_p(SMBHSTDAT0(priv));
 727                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 728                                 dev_err(&priv->pci_dev->dev,
 729                                         "Illegal SMBus block read size %d\n",
 730                                         len);
 731                                 /* Recover */
 732                                 while (inb_p(SMBHSTSTS(priv)) &
 733                                        SMBHSTSTS_HOST_BUSY)
 734                                         outb_p(SMBHSTSTS_BYTE_DONE,
 735                                                SMBHSTSTS(priv));
 736                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 737                                 return -EPROTO;
 738                         }
 739                         data->block[0] = len;
 740                 }
 741
 742                 /* Retrieve/store value in SMBBLKDAT */
 743                 if (read_write == I2C_SMBUS_READ)
 744                         data->block[i] = inb_p(SMBBLKDAT(priv));
 745                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 746                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 747
 748                 /* signals SMBBLKDAT ready */
 749                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 750         }
 751
 752         status = i801_wait_intr(priv);
 753 exit:
 754         return i801_check_post(priv, status);
 755 }
 756
 757 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 758 {
 759         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 760         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 761                 return -EIO;
 762         return 0;
 763 }
 764
 765 /* Block transaction function */
 766 static int i801_block_transaction(struct i801_priv *priv,
 767                                   union i2c_smbus_data *data, char read_write,
 768                                   int command, int hwpec)
 769 {
 770         int result = 0;
 771         unsigned char hostc;
 772
 773         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 774                 if (read_write == I2C_SMBUS_WRITE) {
 775                         /* set I2C_EN bit in configuration register */
 776                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 777                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 778                                               hostc | SMBHSTCFG_I2C_EN);
 779                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 780                         dev_err(&priv->pci_dev->dev,
 781                                 "I2C block read is unsupported!\n");
 782                         return -EOPNOTSUPP;
 783                 }
 784         }
 785
 786         if (read_write == I2C_SMBUS_WRITE
 787          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 788                 if (data->block[0] < 1)
 789                         data->block[0] = 1;
 790                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 791                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 792         } else {
 793                 data->block[0] = 32;    /* max for SMBus block reads */
 794         }
 795
 796         /* Experience has shown that the block buffer can only be used for
 797            SMBus (not I2C) block transactions, even though the datasheet
 798            doesn't mention this limitation. */
 799         if ((priv->features & FEATURE_BLOCK_BUFFER)
 800          && command != I2C_SMBUS_I2C_BLOCK_DATA
 801          && i801_set_block_buffer_mode(priv) == 0)
 802                 result = i801_block_transaction_by_block(priv, data,
 803                                                          read_write, hwpec);
 804         else
 805                 result = i801_block_transaction_byte_by_byte(priv, data,
 806                                                              read_write,
 807                                                              command, hwpec);
 808
 809         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 810          && read_write == I2C_SMBUS_WRITE) {
 811                 /* restore saved configuration register value */
 812                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 813         }
 814         return result;
 815 }
 816
 817 /* Return negative errno on error. */
 818 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 819                        unsigned short flags, char read_write, u8 command,
 820                        int size, union i2c_smbus_data *data)
 821 {
 822         int hwpec;
 823         int block = 0;
 824         int ret = 0, xact = 0;
 825         struct i801_priv *priv = i2c_get_adapdata(adap);
 826
 827         mutex_lock(&priv->acpi_lock);
 828         if (priv->acpi_reserved) {
 829                 mutex_unlock(&priv->acpi_lock);
 830                 return -EBUSY;
 831         }
 832
 833         pm_runtime_get_sync(&priv->pci_dev->dev);
 834
 835         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 836                 && size != I2C_SMBUS_QUICK
 837                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 838
 839         switch (size) {
 840         case I2C_SMBUS_QUICK:
 841                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 842                        SMBHSTADD(priv));
 843                 xact = I801_QUICK;
 844                 break;
 845         case I2C_SMBUS_BYTE:
 846                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 847                        SMBHSTADD(priv));
 848                 if (read_write == I2C_SMBUS_WRITE)
 849                         outb_p(command, SMBHSTCMD(priv));
 850                 xact = I801_BYTE;
 851                 break;
 852         case I2C_SMBUS_BYTE_DATA:
 853                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 854                        SMBHSTADD(priv));
 855                 outb_p(command, SMBHSTCMD(priv));
 856                 if (read_write == I2C_SMBUS_WRITE)
 857                         outb_p(data->byte, SMBHSTDAT0(priv));
 858                 xact = I801_BYTE_DATA;
 859                 break;
 860         case I2C_SMBUS_WORD_DATA:
 861                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 862                        SMBHSTADD(priv));
 863                 outb_p(command, SMBHSTCMD(priv));
 864                 if (read_write == I2C_SMBUS_WRITE) {
 865                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 866                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 867                 }
 868                 xact = I801_WORD_DATA;
 869                 break;
 870         case I2C_SMBUS_BLOCK_DATA:
 871                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 872                        SMBHSTADD(priv));
 873                 outb_p(command, SMBHSTCMD(priv));
 874                 block = 1;
 875                 break;
 876         case I2C_SMBUS_I2C_BLOCK_DATA:
 877                 /*
 878                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 879                  * bit should be cleared here, even when reading.
 880                  * However if SPD Write Disable is set (Lynx Point and later),
 881                  * the read will fail if we don't set the R/#W bit.
 882                  */
 883                 outb_p(((addr & 0x7f) << 1) |
 884                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 885                         (read_write & 0x01) : 0),
 886                        SMBHSTADD(priv));
 887                 if (read_write == I2C_SMBUS_READ) {
 888                         /* NB: page 240 of ICH5 datasheet also shows
 889                          * that DATA1 is the cmd field when reading */
 890                         outb_p(command, SMBHSTDAT1(priv));
 891                 } else
 892                         outb_p(command, SMBHSTCMD(priv));
 893                 block = 1;
 894                 break;
 895         default:
 896                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 897                         size);
 898                 ret = -EOPNOTSUPP;
 899                 goto out;
 900         }
 901
 902         if (hwpec)      /* enable/disable hardware PEC */
 903                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 904         else
 905                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 906                        SMBAUXCTL(priv));
 907
 908         if (block)
 909                 ret = i801_block_transaction(priv, data, read_write, size,
 910                                              hwpec);
 911         else
 912                 ret = i801_transaction(priv, xact);
 913
 914         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 915            time, so we forcibly disable it after every transaction. Turn off
 916            E32B for the same reason. */
 917         if (hwpec || block)
 918                 outb_p(inb_p(SMBAUXCTL(priv)) &
 919                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 920
 921         if (block)
 922                 goto out;
 923         if (ret)
 924                 goto out;
 925         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 926                 goto out;
 927
 928         switch (xact & 0x7f) {
 929         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 930         case I801_BYTE_DATA:
 931                 data->byte = inb_p(SMBHSTDAT0(priv));
 932                 break;
 933         case I801_WORD_DATA:
 934                 data->word = inb_p(SMBHSTDAT0(priv)) +
 935                              (inb_p(SMBHSTDAT1(priv)) << 8);
 936                 break;
 937         }
 938
 939 out:
 940         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 941         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 942         mutex_unlock(&priv->acpi_lock);
 943         return ret;
 944 }
 945
 946
 947 static u32 i801_func(struct i2c_adapter *adapter)
 948 {
 949         struct i801_priv *priv = i2c_get_adapdata(adapter);
 950
 951         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 952                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 953                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 954                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 955                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 956                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 957                ((priv->features & FEATURE_HOST_NOTIFY) ?
 958                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 959 }
 960
 961 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 962 {
 963         struct i801_priv *priv = i2c_get_adapdata(adapter);
 964
 965         if (!(priv->features & FEATURE_HOST_NOTIFY))
 966                 return;
 967
 968         priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
 969
 970         if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
 971                 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
 972                        SMBSLVCMD(priv));
 973
 974         /* clear Host Notify bit to allow a new notification */
 975         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 976 }
 977
 978 static void i801_disable_host_notify(struct i801_priv *priv)
 979 {
 980         if (!(priv->features & FEATURE_HOST_NOTIFY))
 981                 return;
 982
 983         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 984 }
 985
 986 static const struct i2c_algorithm smbus_algorithm = {
 987         .smbus_xfer     = i801_access,
 988         .functionality  = i801_func,
 989 };
 990
 991 static const struct pci_device_id i801_ids[] = {
 992         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 993         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 994         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 995         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 996         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 997         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 998         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 999         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1000         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1001         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1002         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1003         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1004         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1005         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1006         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1007         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1008         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1009         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1010         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1011         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1012         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1013         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1014         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1015         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1016         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1017         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1018         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1019         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1020         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1021         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1022         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1023         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1024         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1025         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1026         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1027         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1028         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1029         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1030         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1031         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1032         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1033         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1034         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1035         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1036         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1037         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1038         { 0, }
1039 };
1040
1041 MODULE_DEVICE_TABLE(pci, i801_ids);
1042
1043 #if defined CONFIG_X86 && defined CONFIG_DMI
1044 static unsigned char apanel_addr;
1045
1046 /* Scan the system ROM for the signature "FJKEYINF" */
1047 static __init const void __iomem *bios_signature(const void __iomem *bios)
1048 {
1049         ssize_t offset;
1050         const unsigned char signature[] = "FJKEYINF";
1051
1052         for (offset = 0; offset < 0x10000; offset += 0x10) {
1053                 if (check_signature(bios + offset, signature,
1054                                     sizeof(signature)-1))
1055                         return bios + offset;
1056         }
1057         return NULL;
1058 }
1059
1060 static void __init input_apanel_init(void)
1061 {
1062         void __iomem *bios;
1063         const void __iomem *p;
1064
1065         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1066         p = bios_signature(bios);
1067         if (p) {
1068                 /* just use the first address */
1069                 apanel_addr = readb(p + 8 + 3) >> 1;
1070         }
1071         iounmap(bios);
1072 }
1073
1074 struct dmi_onboard_device_info {
1075         const char *name;
1076         u8 type;
1077         unsigned short i2c_addr;
1078         const char *i2c_type;
1079 };
1080
1081 static const struct dmi_onboard_device_info dmi_devices[] = {
1082         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1083         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1084         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1085 };
1086
1087 static void dmi_check_onboard_device(u8 type, const char *name,
1088                                      struct i2c_adapter *adap)
1089 {
1090         int i;
1091         struct i2c_board_info info;
1092
1093         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1094                 /* & ~0x80, ignore enabled/disabled bit */
1095                 if ((type & ~0x80) != dmi_devices[i].type)
1096                         continue;
1097                 if (strcasecmp(name, dmi_devices[i].name))
1098                         continue;
1099
1100                 memset(&info, 0, sizeof(struct i2c_board_info));
1101                 info.addr = dmi_devices[i].i2c_addr;
1102                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1103                 i2c_new_device(adap, &info);
1104                 break;
1105         }
1106 }
1107
1108 /* We use our own function to check for onboard devices instead of
1109    dmi_find_device() as some buggy BIOS's have the devices we are interested
1110    in marked as disabled */
1111 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1112 {
1113         int i, count;
1114
1115         if (dm->type != 10)
1116                 return;
1117
1118         count = (dm->length - sizeof(struct dmi_header)) / 2;
1119         for (i = 0; i < count; i++) {
1120                 const u8 *d = (char *)(dm + 1) + (i * 2);
1121                 const char *name = ((char *) dm) + dm->length;
1122                 u8 type = d[0];
1123                 u8 s = d[1];
1124
1125                 if (!s)
1126                         continue;
1127                 s--;
1128                 while (s > 0 && name[0]) {
1129                         name += strlen(name) + 1;
1130                         s--;
1131                 }
1132                 if (name[0] == 0) /* Bogus string reference */
1133                         continue;
1134
1135                 dmi_check_onboard_device(type, name, adap);
1136         }
1137 }
1138
1139 /* Register optional slaves */
1140 static void i801_probe_optional_slaves(struct i801_priv *priv)
1141 {
1142         /* Only register slaves on main SMBus channel */
1143         if (priv->features & FEATURE_IDF)
1144                 return;
1145
1146         if (apanel_addr) {
1147                 struct i2c_board_info info;
1148
1149                 memset(&info, 0, sizeof(struct i2c_board_info));
1150                 info.addr = apanel_addr;
1151                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1152                 i2c_new_device(&priv->adapter, &info);
1153         }
1154
1155         if (dmi_name_in_vendors("FUJITSU"))
1156                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1157 }
1158 #else
1159 static void __init input_apanel_init(void) {}
1160 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1161 #endif  /* CONFIG_X86 && CONFIG_DMI */
1162
1163 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1164 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1165         .gpio_chip = "gpio_ich",
1166         .values = { 0x02, 0x03 },
1167         .n_values = 2,
1168         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1169         .gpios = { 52, 53 },
1170         .n_gpios = 2,
1171 };
1172
1173 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1174         .gpio_chip = "gpio_ich",
1175         .values = { 0x02, 0x03, 0x01 },
1176         .n_values = 3,
1177         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1178         .gpios = { 52, 53 },
1179         .n_gpios = 2,
1180 };
1181
1182 static const struct dmi_system_id mux_dmi_table[] = {
1183         {
1184                 .matches = {
1185                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1186                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1187                 },
1188                 .driver_data = &i801_mux_config_asus_z8_d12,
1189         },
1190         {
1191                 .matches = {
1192                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1193                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1194                 },
1195                 .driver_data = &i801_mux_config_asus_z8_d12,
1196         },
1197         {
1198                 .matches = {
1199                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1200                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1201                 },
1202                 .driver_data = &i801_mux_config_asus_z8_d12,
1203         },
1204         {
1205                 .matches = {
1206                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1207                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1208                 },
1209                 .driver_data = &i801_mux_config_asus_z8_d12,
1210         },
1211         {
1212                 .matches = {
1213                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1214                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1215                 },
1216                 .driver_data = &i801_mux_config_asus_z8_d12,
1217         },
1218         {
1219                 .matches = {
1220                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1221                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1222                 },
1223                 .driver_data = &i801_mux_config_asus_z8_d12,
1224         },
1225         {
1226                 .matches = {
1227                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1228                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1229                 },
1230                 .driver_data = &i801_mux_config_asus_z8_d18,
1231         },
1232         {
1233                 .matches = {
1234                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1235                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1236                 },
1237                 .driver_data = &i801_mux_config_asus_z8_d18,
1238         },
1239         {
1240                 .matches = {
1241                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1242                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1243                 },
1244                 .driver_data = &i801_mux_config_asus_z8_d12,
1245         },
1246         { }
1247 };
1248
1249 /* Setup multiplexing if needed */
1250 static int i801_add_mux(struct i801_priv *priv)
1251 {
1252         struct device *dev = &priv->adapter.dev;
1253         const struct i801_mux_config *mux_config;
1254         struct i2c_mux_gpio_platform_data gpio_data;
1255         int err;
1256
1257         if (!priv->mux_drvdata)
1258                 return 0;
1259         mux_config = priv->mux_drvdata;
1260
1261         /* Prepare the platform data */
1262         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1263         gpio_data.parent = priv->adapter.nr;
1264         gpio_data.values = mux_config->values;
1265         gpio_data.n_values = mux_config->n_values;
1266         gpio_data.classes = mux_config->classes;
1267         gpio_data.gpio_chip = mux_config->gpio_chip;
1268         gpio_data.gpios = mux_config->gpios;
1269         gpio_data.n_gpios = mux_config->n_gpios;
1270         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1271
1272         /* Register the mux device */
1273         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1274                                 PLATFORM_DEVID_AUTO, &gpio_data,
1275                                 sizeof(struct i2c_mux_gpio_platform_data));
1276         if (IS_ERR(priv->mux_pdev)) {
1277                 err = PTR_ERR(priv->mux_pdev);
1278                 priv->mux_pdev = NULL;
1279                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1280                 return err;
1281         }
1282
1283         return 0;
1284 }
1285
1286 static void i801_del_mux(struct i801_priv *priv)
1287 {
1288         if (priv->mux_pdev)
1289                 platform_device_unregister(priv->mux_pdev);
1290 }
1291
1292 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1293 {
1294         const struct dmi_system_id *id;
1295         const struct i801_mux_config *mux_config;
1296         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1297         int i;
1298
1299         id = dmi_first_match(mux_dmi_table);
1300         if (id) {
1301                 /* Remove branch classes from trunk */
1302                 mux_config = id->driver_data;
1303                 for (i = 0; i < mux_config->n_values; i++)
1304                         class &= ~mux_config->classes[i];
1305
1306                 /* Remember for later */
1307                 priv->mux_drvdata = mux_config;
1308         }
1309
1310         return class;
1311 }
1312 #else
1313 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1314 static inline void i801_del_mux(struct i801_priv *priv) { }
1315
1316 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1317 {
1318         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1319 }
1320 #endif
1321
1322 static const struct itco_wdt_platform_data tco_platform_data = {
1323         .name = "Intel PCH",
1324         .version = 4,
1325 };
1326
1327 static DEFINE_SPINLOCK(p2sb_spinlock);
1328
1329 static void i801_add_tco(struct i801_priv *priv)
1330 {
1331         struct pci_dev *pci_dev = priv->pci_dev;
1332         struct resource tco_res[3], *res;
1333         struct platform_device *pdev;
1334         unsigned int devfn;
1335         u32 tco_base, tco_ctl;
1336         u32 base_addr, ctrl_val;
1337         u64 base64_addr;
1338         u8 hidden;
1339
1340         if (!(priv->features & FEATURE_TCO))
1341                 return;
1342
1343         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1344         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1345         if (!(tco_ctl & TCOCTL_EN))
1346                 return;
1347
1348         memset(tco_res, 0, sizeof(tco_res));
1349
1350         res = &tco_res[ICH_RES_IO_TCO];
1351         res->start = tco_base & ~1;
1352         res->end = res->start + 32 - 1;
1353         res->flags = IORESOURCE_IO;
1354
1355         /*
1356          * Power Management registers.
1357          */
1358         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1359         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1360
1361         res = &tco_res[ICH_RES_IO_SMI];
1362         res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1363         res->end = res->start + 3;
1364         res->flags = IORESOURCE_IO;
1365
1366         /*
1367          * Enable the ACPI I/O space.
1368          */
1369         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1370         ctrl_val |= ACPICTRL_EN;
1371         pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1372
1373         /*
1374          * We must access the NO_REBOOT bit over the Primary to Sideband
1375          * bridge (P2SB). The BIOS prevents the P2SB device from being
1376          * enumerated by the PCI subsystem, so we need to unhide/hide it
1377          * to lookup the P2SB BAR.
1378          */
1379         spin_lock(&p2sb_spinlock);
1380
1381         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1382
1383         /* Unhide the P2SB device, if it is hidden */
1384         pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1385         if (hidden)
1386                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1387
1388         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1389         base64_addr = base_addr & 0xfffffff0;
1390
1391         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1392         base64_addr |= (u64)base_addr << 32;
1393
1394         /* Hide the P2SB device, if it was hidden before */
1395         if (hidden)
1396                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1397         spin_unlock(&p2sb_spinlock);
1398
1399         res = &tco_res[ICH_RES_MEM_OFF];
1400         res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1401         res->end = res->start + 3;
1402         res->flags = IORESOURCE_MEM;
1403
1404         pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1405                                                  tco_res, 3, &tco_platform_data,
1406                                                  sizeof(tco_platform_data));
1407         if (IS_ERR(pdev)) {
1408                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1409                 return;
1410         }
1411
1412         priv->tco_pdev = pdev;
1413 }
1414
1415 #ifdef CONFIG_ACPI
1416 static acpi_status
1417 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1418                      u64 *value, void *handler_context, void *region_context)
1419 {
1420         struct i801_priv *priv = handler_context;
1421         struct pci_dev *pdev = priv->pci_dev;
1422         acpi_status status;
1423
1424         /*
1425          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1426          * further access from the driver itself. This device is now owned
1427          * by the system firmware.
1428          */
1429         mutex_lock(&priv->acpi_lock);
1430
1431         if (!priv->acpi_reserved) {
1432                 priv->acpi_reserved = true;
1433
1434                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1435                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1436
1437                 /*
1438                  * BIOS is accessing the host controller so prevent it from
1439                  * suspending automatically from now on.
1440                  */
1441                 pm_runtime_get_sync(&pdev->dev);
1442         }
1443
1444         if ((function & ACPI_IO_MASK) == ACPI_READ)
1445                 status = acpi_os_read_port(address, (u32 *)value, bits);
1446         else
1447                 status = acpi_os_write_port(address, (u32)*value, bits);
1448
1449         mutex_unlock(&priv->acpi_lock);
1450
1451         return status;
1452 }
1453
1454 static int i801_acpi_probe(struct i801_priv *priv)
1455 {
1456         struct acpi_device *adev;
1457         acpi_status status;
1458
1459         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1460         if (adev) {
1461                 status = acpi_install_address_space_handler(adev->handle,
1462                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1463                                 NULL, priv);
1464                 if (ACPI_SUCCESS(status))
1465                         return 0;
1466         }
1467
1468         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1469 }
1470
1471 static void i801_acpi_remove(struct i801_priv *priv)
1472 {
1473         struct acpi_device *adev;
1474
1475         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1476         if (!adev)
1477                 return;
1478
1479         acpi_remove_address_space_handler(adev->handle,
1480                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1481
1482         mutex_lock(&priv->acpi_lock);
1483         if (priv->acpi_reserved)
1484                 pm_runtime_put(&priv->pci_dev->dev);
1485         mutex_unlock(&priv->acpi_lock);
1486 }
1487 #else
1488 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1489 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1490 #endif
1491
1492 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1493 {
1494         unsigned char temp;
1495         int err, i;
1496         struct i801_priv *priv;
1497
1498         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1499         if (!priv)
1500                 return -ENOMEM;
1501
1502         i2c_set_adapdata(&priv->adapter, priv);
1503         priv->adapter.owner = THIS_MODULE;
1504         priv->adapter.class = i801_get_adapter_class(priv);
1505         priv->adapter.algo = &smbus_algorithm;
1506         priv->adapter.dev.parent = &dev->dev;
1507         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1508         priv->adapter.retries = 3;
1509         mutex_init(&priv->acpi_lock);
1510
1511         priv->pci_dev = dev;
1512         switch (dev->device) {
1513         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1514         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1515         case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1516         case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1517         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1518         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1519         case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1520         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1521         case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1522                 priv->features |= FEATURE_I2C_BLOCK_READ;
1523                 priv->features |= FEATURE_IRQ;
1524                 priv->features |= FEATURE_SMBUS_PEC;
1525                 priv->features |= FEATURE_BLOCK_BUFFER;
1526                 /* If we have ACPI based watchdog use that instead */
1527                 if (!acpi_has_watchdog())
1528                         priv->features |= FEATURE_TCO;
1529                 priv->features |= FEATURE_HOST_NOTIFY;
1530                 break;
1531
1532         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1533         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1534         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1535         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1536         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1537         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1538                 priv->features |= FEATURE_IDF;
1539                 /* fall through */
1540         default:
1541                 priv->features |= FEATURE_I2C_BLOCK_READ;
1542                 priv->features |= FEATURE_IRQ;
1543                 /* fall through */
1544         case PCI_DEVICE_ID_INTEL_82801DB_3:
1545                 priv->features |= FEATURE_SMBUS_PEC;
1546                 priv->features |= FEATURE_BLOCK_BUFFER;
1547                 /* fall through */
1548         case PCI_DEVICE_ID_INTEL_82801CA_3:
1549                 priv->features |= FEATURE_HOST_NOTIFY;
1550                 /* fall through */
1551         case PCI_DEVICE_ID_INTEL_82801BA_2:
1552         case PCI_DEVICE_ID_INTEL_82801AB_3:
1553         case PCI_DEVICE_ID_INTEL_82801AA_3:
1554                 break;
1555         }
1556
1557         /* Disable features on user request */
1558         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1559                 if (priv->features & disable_features & (1 << i))
1560                         dev_notice(&dev->dev, "%s disabled by user\n",
1561                                    i801_feature_names[i]);
1562         }
1563         priv->features &= ~disable_features;
1564
1565         err = pcim_enable_device(dev);
1566         if (err) {
1567                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1568                         err);
1569                 return err;
1570         }
1571         pcim_pin_device(dev);
1572
1573         /* Determine the address of the SMBus area */
1574         priv->smba = pci_resource_start(dev, SMBBAR);
1575         if (!priv->smba) {
1576                 dev_err(&dev->dev,
1577                         "SMBus base address uninitialized, upgrade BIOS\n");
1578                 return -ENODEV;
1579         }
1580
1581         if (i801_acpi_probe(priv))
1582                 return -ENODEV;
1583
1584         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1585                                  dev_driver_string(&dev->dev));
1586         if (err) {
1587                 dev_err(&dev->dev,
1588                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1589                         priv->smba,
1590                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1591                 i801_acpi_remove(priv);
1592                 return err;
1593         }
1594
1595         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1596         priv->original_hstcfg = temp;
1597         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1598         if (!(temp & SMBHSTCFG_HST_EN)) {
1599                 dev_info(&dev->dev, "Enabling SMBus device\n");
1600                 temp |= SMBHSTCFG_HST_EN;
1601         }
1602         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1603
1604         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1605                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1606                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1607                 priv->features &= ~FEATURE_IRQ;
1608         }
1609         if (temp & SMBHSTCFG_SPD_WD)
1610                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1611
1612         /* Clear special mode bits */
1613         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1614                 outb_p(inb_p(SMBAUXCTL(priv)) &
1615                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1616
1617         /* Default timeout in interrupt mode: 200 ms */
1618         priv->adapter.timeout = HZ / 5;
1619
1620         if (dev->irq == IRQ_NOTCONNECTED)
1621                 priv->features &= ~FEATURE_IRQ;
1622
1623         if (priv->features & FEATURE_IRQ) {
1624                 u16 pcictl, pcists;
1625
1626                 /* Complain if an interrupt is already pending */
1627                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1628                 if (pcists & SMBPCISTS_INTS)
1629                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1630
1631                 /* Check if interrupts have been disabled */
1632                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1633                 if (pcictl & SMBPCICTL_INTDIS) {
1634                         dev_info(&dev->dev, "Interrupts are disabled\n");
1635                         priv->features &= ~FEATURE_IRQ;
1636                 }
1637         }
1638
1639         if (priv->features & FEATURE_IRQ) {
1640                 init_waitqueue_head(&priv->waitq);
1641
1642                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1643                                        IRQF_SHARED,
1644                                        dev_driver_string(&dev->dev), priv);
1645                 if (err) {
1646                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1647                                 dev->irq, err);
1648                         priv->features &= ~FEATURE_IRQ;
1649                 }
1650         }
1651         dev_info(&dev->dev, "SMBus using %s\n",
1652                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1653
1654         i801_add_tco(priv);
1655
1656         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1657                 "SMBus I801 adapter at %04lx", priv->smba);
1658         err = i2c_add_adapter(&priv->adapter);
1659         if (err) {
1660                 i801_acpi_remove(priv);
1661                 return err;
1662         }
1663
1664         i801_enable_host_notify(&priv->adapter);
1665
1666         i801_probe_optional_slaves(priv);
1667         /* We ignore errors - multiplexing is optional */
1668         i801_add_mux(priv);
1669
1670         pci_set_drvdata(dev, priv);
1671
1672         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1673         pm_runtime_use_autosuspend(&dev->dev);
1674         pm_runtime_put_autosuspend(&dev->dev);
1675         pm_runtime_allow(&dev->dev);
1676
1677         return 0;
1678 }
1679
1680 static void i801_remove(struct pci_dev *dev)
1681 {
1682         struct i801_priv *priv = pci_get_drvdata(dev);
1683
1684         pm_runtime_forbid(&dev->dev);
1685         pm_runtime_get_noresume(&dev->dev);
1686
1687         i801_disable_host_notify(priv);
1688         i801_del_mux(priv);
1689         i2c_del_adapter(&priv->adapter);
1690         i801_acpi_remove(priv);
1691         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1692
1693         platform_device_unregister(priv->tco_pdev);
1694
1695         /*
1696          * do not call pci_disable_device(dev) since it can cause hard hangs on
1697          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1698          */
1699 }
1700
1701 #ifdef CONFIG_PM
1702 static int i801_suspend(struct device *dev)
1703 {
1704         struct pci_dev *pci_dev = to_pci_dev(dev);
1705         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1706
1707         pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1708         return 0;
1709 }
1710
1711 static int i801_resume(struct device *dev)
1712 {
1713         struct pci_dev *pci_dev = to_pci_dev(dev);
1714         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1715
1716         i801_enable_host_notify(&priv->adapter);
1717
1718         return 0;
1719 }
1720 #endif
1721
1722 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1723                             i801_resume, NULL);
1724
1725 static struct pci_driver i801_driver = {
1726         .name           = "i801_smbus",
1727         .id_table       = i801_ids,
1728         .probe          = i801_probe,
1729         .remove         = i801_remove,
1730         .driver         = {
1731                 .pm     = &i801_pm_ops,
1732         },
1733 };
1734
1735 static int __init i2c_i801_init(void)
1736 {
1737         if (dmi_name_in_vendors("FUJITSU"))
1738                 input_apanel_init();
1739         return pci_register_driver(&i801_driver);
1740 }
1741
1742 static void __exit i2c_i801_exit(void)
1743 {
1744         pci_unregister_driver(&i801_driver);
1745 }
1746
1747 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1748 MODULE_DESCRIPTION("I801 SMBus driver");
1749 MODULE_LICENSE("GPL");
1750
1751 module_init(i2c_i801_init);
1752 module_exit(i2c_i801_exit);