drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2012  Jean Delvare <khali@linux-fr.org>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25   Supports the following Intel I/O Controller Hubs (ICH):
  26
  27                                   I/O                     Block   I2C
  28                                   region  SMBus   Block   proc.   block
  29   Chip name             PCI ID    size    PEC     buffer  call    read
  30   ----------------------------------------------------------------------
  31   82801AA  (ICH)        0x2413     16      no      no      no      no
  32   82801AB  (ICH0)       0x2423     16      no      no      no      no
  33   82801BA  (ICH2)       0x2443     16      no      no      no      no
  34   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  35   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  36   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  37   6300ESB               0x25a4     32     hard     yes     yes     yes
  38   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  39   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  40   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  41   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  42   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  43   EP80579 (Tolapai)     0x5032     32     hard     yes     yes     yes
  44   ICH10                 0x3a30     32     hard     yes     yes     yes
  45   ICH10                 0x3a60     32     hard     yes     yes     yes
  46   5/3400 Series (PCH)   0x3b30     32     hard     yes     yes     yes
  47   6 Series (PCH)        0x1c22     32     hard     yes     yes     yes
  48   Patsburg (PCH)        0x1d22     32     hard     yes     yes     yes
  49   Patsburg (PCH) IDF    0x1d70     32     hard     yes     yes     yes
  50   Patsburg (PCH) IDF    0x1d71     32     hard     yes     yes     yes
  51   Patsburg (PCH) IDF    0x1d72     32     hard     yes     yes     yes
  52   DH89xxCC (PCH)        0x2330     32     hard     yes     yes     yes
  53   Panther Point (PCH)   0x1e22     32     hard     yes     yes     yes
  54   Lynx Point (PCH)      0x8c22     32     hard     yes     yes     yes
  55   Lynx Point-LP (PCH)   0x9c22     32     hard     yes     yes     yes
  56
  57   Features supported by this driver:
  58   Software PEC                     no
  59   Hardware PEC                     yes
  60   Block buffer                     yes
  61   Block process call transaction   no
  62   I2C block read transaction       yes  (doesn't use the block buffer)
  63   Slave mode                       no
  64   Interrupt processing             yes
  65
  66   See the file Documentation/i2c/busses/i2c-i801 for details.
  67 */
  68
  69 #include <linux/interrupt.h>
  70 #include <linux/module.h>
  71 #include <linux/pci.h>
  72 #include <linux/kernel.h>
  73 #include <linux/stddef.h>
  74 #include <linux/delay.h>
  75 #include <linux/ioport.h>
  76 #include <linux/init.h>
  77 #include <linux/i2c.h>
  78 #include <linux/acpi.h>
  79 #include <linux/io.h>
  80 #include <linux/dmi.h>
  81 #include <linux/slab.h>
  82 #include <linux/wait.h>
  83 #include <linux/err.h>
  84
  85 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
  86                 defined CONFIG_DMI
  87 #include <linux/gpio.h>
  88 #include <linux/i2c-mux-gpio.h>
  89 #include <linux/platform_device.h>
  90 #endif
  91
  92 /* I801 SMBus address offsets */
  93 #define SMBHSTSTS(p)    (0 + (p)->smba)
  94 #define SMBHSTCNT(p)    (2 + (p)->smba)
  95 #define SMBHSTCMD(p)    (3 + (p)->smba)
  96 #define SMBHSTADD(p)    (4 + (p)->smba)
  97 #define SMBHSTDAT0(p)   (5 + (p)->smba)
  98 #define SMBHSTDAT1(p)   (6 + (p)->smba)
  99 #define SMBBLKDAT(p)    (7 + (p)->smba)
 100 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 101 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 102 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 103
 104 /* PCI Address Constants */
 105 #define SMBBAR          4
 106 #define SMBPCISTS       0x006
 107 #define SMBHSTCFG       0x040
 108
 109 /* Host status bits for SMBPCISTS */
 110 #define SMBPCISTS_INTS          0x08
 111
 112 /* Host configuration bits for SMBHSTCFG */
 113 #define SMBHSTCFG_HST_EN        1
 114 #define SMBHSTCFG_SMB_SMI_EN    2
 115 #define SMBHSTCFG_I2C_EN        4
 116
 117 /* Auxiliary control register bits, ICH4+ only */
 118 #define SMBAUXCTL_CRC           1
 119 #define SMBAUXCTL_E32B          2
 120
 121 /* Other settings */
 122 #define MAX_RETRIES             400
 123
 124 /* I801 command constants */
 125 #define I801_QUICK              0x00
 126 #define I801_BYTE               0x04
 127 #define I801_BYTE_DATA          0x08
 128 #define I801_WORD_DATA          0x0C
 129 #define I801_PROC_CALL          0x10    /* unimplemented */
 130 #define I801_BLOCK_DATA         0x14
 131 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 132
 133 /* I801 Host Control register bits */
 134 #define SMBHSTCNT_INTREN        0x01
 135 #define SMBHSTCNT_KILL          0x02
 136 #define SMBHSTCNT_LAST_BYTE     0x20
 137 #define SMBHSTCNT_START         0x40
 138 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 139
 140 /* I801 Hosts Status register bits */
 141 #define SMBHSTSTS_BYTE_DONE     0x80
 142 #define SMBHSTSTS_INUSE_STS     0x40
 143 #define SMBHSTSTS_SMBALERT_STS  0x20
 144 #define SMBHSTSTS_FAILED        0x10
 145 #define SMBHSTSTS_BUS_ERR       0x08
 146 #define SMBHSTSTS_DEV_ERR       0x04
 147 #define SMBHSTSTS_INTR          0x02
 148 #define SMBHSTSTS_HOST_BUSY     0x01
 149
 150 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 151                                  SMBHSTSTS_DEV_ERR)
 152
 153 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 154                                  STATUS_ERROR_FLAGS)
 155
 156 /* Older devices have their ID defined in <linux/pci_ids.h> */
 157 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS   0x1c22
 158 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS      0x1d22
 159 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 160 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
 161 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
 162 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
 163 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS  0x1e22
 164 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS      0x2330
 165 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
 166 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS     0x8c22
 167 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS  0x9c22
 168
 169 struct i801_mux_config {
 170         char *gpio_chip;
 171         unsigned values[3];
 172         int n_values;
 173         unsigned classes[3];
 174         unsigned gpios[2];              /* Relative to gpio_chip->base */
 175         int n_gpios;
 176 };
 177
 178 struct i801_priv {
 179         struct i2c_adapter adapter;
 180         unsigned long smba;
 181         unsigned char original_hstcfg;
 182         struct pci_dev *pci_dev;
 183         unsigned int features;
 184
 185         /* isr processing */
 186         wait_queue_head_t waitq;
 187         u8 status;
 188
 189         /* Command state used by isr for byte-by-byte block transactions */
 190         u8 cmd;
 191         bool is_read;
 192         int count;
 193         int len;
 194         u8 *data;
 195
 196 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 197                 defined CONFIG_DMI
 198         const struct i801_mux_config *mux_drvdata;
 199         struct platform_device *mux_pdev;
 200 #endif
 201 };
 202
 203 static struct pci_driver i801_driver;
 204
 205 #define FEATURE_SMBUS_PEC       (1 << 0)
 206 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 207 #define FEATURE_BLOCK_PROC      (1 << 2)
 208 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 209 #define FEATURE_IRQ             (1 << 4)
 210 /* Not really a feature, but it's convenient to handle it as such */
 211 #define FEATURE_IDF             (1 << 15)
 212
 213 static const char *i801_feature_names[] = {
 214         "SMBus PEC",
 215         "Block buffer",
 216         "Block process call",
 217         "I2C block read",
 218         "Interrupt",
 219 };
 220
 221 static unsigned int disable_features;
 222 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 223 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 224
 225 /* Make sure the SMBus host is ready to start transmitting.
 226    Return 0 if it is, -EBUSY if it is not. */
 227 static int i801_check_pre(struct i801_priv *priv)
 228 {
 229         int status;
 230
 231         status = inb_p(SMBHSTSTS(priv));
 232         if (status & SMBHSTSTS_HOST_BUSY) {
 233                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 234                 return -EBUSY;
 235         }
 236
 237         status &= STATUS_FLAGS;
 238         if (status) {
 239                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 240                         status);
 241                 outb_p(status, SMBHSTSTS(priv));
 242                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 243                 if (status) {
 244                         dev_err(&priv->pci_dev->dev,
 245                                 "Failed clearing status flags (%02x)\n",
 246                                 status);
 247                         return -EBUSY;
 248                 }
 249         }
 250
 251         return 0;
 252 }
 253
 254 /*
 255  * Convert the status register to an error code, and clear it.
 256  * Note that status only contains the bits we want to clear, not the
 257  * actual register value.
 258  */
 259 static int i801_check_post(struct i801_priv *priv, int status)
 260 {
 261         int result = 0;
 262
 263         /*
 264          * If the SMBus is still busy, we give up
 265          * Note: This timeout condition only happens when using polling
 266          * transactions.  For interrupt operation, NAK/timeout is indicated by
 267          * DEV_ERR.
 268          */
 269         if (unlikely(status < 0)) {
 270                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 271                 /* try to stop the current command */
 272                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 273                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 274                        SMBHSTCNT(priv));
 275                 usleep_range(1000, 2000);
 276                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 277                        SMBHSTCNT(priv));
 278
 279                 /* Check if it worked */
 280                 status = inb_p(SMBHSTSTS(priv));
 281                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 282                     !(status & SMBHSTSTS_FAILED))
 283                         dev_err(&priv->pci_dev->dev,
 284                                 "Failed terminating the transaction\n");
 285                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 286                 return -ETIMEDOUT;
 287         }
 288
 289         if (status & SMBHSTSTS_FAILED) {
 290                 result = -EIO;
 291                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 292         }
 293         if (status & SMBHSTSTS_DEV_ERR) {
 294                 result = -ENXIO;
 295                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 296         }
 297         if (status & SMBHSTSTS_BUS_ERR) {
 298                 result = -EAGAIN;
 299                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 300         }
 301
 302         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 303         outb_p(status, SMBHSTSTS(priv));
 304
 305         return result;
 306 }
 307
 308 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 309 static int i801_wait_intr(struct i801_priv *priv)
 310 {
 311         int timeout = 0;
 312         int status;
 313
 314         /* We will always wait for a fraction of a second! */
 315         do {
 316                 usleep_range(250, 500);
 317                 status = inb_p(SMBHSTSTS(priv));
 318         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 319                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 320                  (timeout++ < MAX_RETRIES));
 321
 322         if (timeout > MAX_RETRIES) {
 323                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 324                 return -ETIMEDOUT;
 325         }
 326         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 327 }
 328
 329 /* Wait for either BYTE_DONE or an error flag being set */
 330 static int i801_wait_byte_done(struct i801_priv *priv)
 331 {
 332         int timeout = 0;
 333         int status;
 334
 335         /* We will always wait for a fraction of a second! */
 336         do {
 337                 usleep_range(250, 500);
 338                 status = inb_p(SMBHSTSTS(priv));
 339         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 340                  (timeout++ < MAX_RETRIES));
 341
 342         if (timeout > MAX_RETRIES) {
 343                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 344                 return -ETIMEDOUT;
 345         }
 346         return status & STATUS_ERROR_FLAGS;
 347 }
 348
 349 static int i801_transaction(struct i801_priv *priv, int xact)
 350 {
 351         int status;
 352         int result;
 353
 354         result = i801_check_pre(priv);
 355         if (result < 0)
 356                 return result;
 357
 358         if (priv->features & FEATURE_IRQ) {
 359                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 360                        SMBHSTCNT(priv));
 361                 wait_event(priv->waitq, (status = priv->status));
 362                 priv->status = 0;
 363                 return i801_check_post(priv, status);
 364         }
 365
 366         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 367          * SMBSCMD are passed in xact */
 368         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 369
 370         status = i801_wait_intr(priv);
 371         return i801_check_post(priv, status);
 372 }
 373
 374 static int i801_block_transaction_by_block(struct i801_priv *priv,
 375                                            union i2c_smbus_data *data,
 376                                            char read_write, int hwpec)
 377 {
 378         int i, len;
 379         int status;
 380
 381         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 382
 383         /* Use 32-byte buffer to process this transaction */
 384         if (read_write == I2C_SMBUS_WRITE) {
 385                 len = data->block[0];
 386                 outb_p(len, SMBHSTDAT0(priv));
 387                 for (i = 0; i < len; i++)
 388                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 389         }
 390
 391         status = i801_transaction(priv, I801_BLOCK_DATA |
 392                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 393         if (status)
 394                 return status;
 395
 396         if (read_write == I2C_SMBUS_READ) {
 397                 len = inb_p(SMBHSTDAT0(priv));
 398                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 399                         return -EPROTO;
 400
 401                 data->block[0] = len;
 402                 for (i = 0; i < len; i++)
 403                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 404         }
 405         return 0;
 406 }
 407
 408 static void i801_isr_byte_done(struct i801_priv *priv)
 409 {
 410         if (priv->is_read) {
 411                 /* For SMBus block reads, length is received with first byte */
 412                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 413                     (priv->count == 0)) {
 414                         priv->len = inb_p(SMBHSTDAT0(priv));
 415                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 416                                 dev_err(&priv->pci_dev->dev,
 417                                         "Illegal SMBus block read size %d\n",
 418                                         priv->len);
 419                                 /* FIXME: Recover */
 420                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 421                         } else {
 422                                 dev_dbg(&priv->pci_dev->dev,
 423                                         "SMBus block read size is %d\n",
 424                                         priv->len);
 425                         }
 426                         priv->data[-1] = priv->len;
 427                 }
 428
 429                 /* Read next byte */
 430                 if (priv->count < priv->len)
 431                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 432                 else
 433                         dev_dbg(&priv->pci_dev->dev,
 434                                 "Discarding extra byte on block read\n");
 435
 436                 /* Set LAST_BYTE for last byte of read transaction */
 437                 if (priv->count == priv->len - 1)
 438                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 439                                SMBHSTCNT(priv));
 440         } else if (priv->count < priv->len - 1) {
 441                 /* Write next byte, except for IRQ after last byte */
 442                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 443         }
 444
 445         /* Clear BYTE_DONE to continue with next byte */
 446         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 447 }
 448
 449 /*
 450  * There are two kinds of interrupts:
 451  *
 452  * 1) i801 signals transaction completion with one of these interrupts:
 453  *      INTR - Success
 454  *      DEV_ERR - Invalid command, NAK or communication timeout
 455  *      BUS_ERR - SMI# transaction collision
 456  *      FAILED - transaction was canceled due to a KILL request
 457  *    When any of these occur, update ->status and wake up the waitq.
 458  *    ->status must be cleared before kicking off the next transaction.
 459  *
 460  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 461  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 462  */
 463 static irqreturn_t i801_isr(int irq, void *dev_id)
 464 {
 465         struct i801_priv *priv = dev_id;
 466         u16 pcists;
 467         u8 status;
 468
 469         /* Confirm this is our interrupt */
 470         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 471         if (!(pcists & SMBPCISTS_INTS))
 472                 return IRQ_NONE;
 473
 474         status = inb_p(SMBHSTSTS(priv));
 475         if (status != 0x42)
 476                 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
 477
 478         if (status & SMBHSTSTS_BYTE_DONE)
 479                 i801_isr_byte_done(priv);
 480
 481         /*
 482          * Clear irq sources and report transaction result.
 483          * ->status must be cleared before the next transaction is started.
 484          */
 485         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 486         if (status) {
 487                 outb_p(status, SMBHSTSTS(priv));
 488                 priv->status |= status;
 489                 wake_up(&priv->waitq);
 490         }
 491
 492         return IRQ_HANDLED;
 493 }
 494
 495 /*
 496  * For "byte-by-byte" block transactions:
 497  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 498  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 499  */
 500 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 501                                                union i2c_smbus_data *data,
 502                                                char read_write, int command,
 503                                                int hwpec)
 504 {
 505         int i, len;
 506         int smbcmd;
 507         int status;
 508         int result;
 509
 510         result = i801_check_pre(priv);
 511         if (result < 0)
 512                 return result;
 513
 514         len = data->block[0];
 515
 516         if (read_write == I2C_SMBUS_WRITE) {
 517                 outb_p(len, SMBHSTDAT0(priv));
 518                 outb_p(data->block[1], SMBBLKDAT(priv));
 519         }
 520
 521         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 522             read_write == I2C_SMBUS_READ)
 523                 smbcmd = I801_I2C_BLOCK_DATA;
 524         else
 525                 smbcmd = I801_BLOCK_DATA;
 526
 527         if (priv->features & FEATURE_IRQ) {
 528                 priv->is_read = (read_write == I2C_SMBUS_READ);
 529                 if (len == 1 && priv->is_read)
 530                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 531                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 532                 priv->len = len;
 533                 priv->count = 0;
 534                 priv->data = &data->block[1];
 535
 536                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 537                 wait_event(priv->waitq, (status = priv->status));
 538                 priv->status = 0;
 539                 return i801_check_post(priv, status);
 540         }
 541
 542         for (i = 1; i <= len; i++) {
 543                 if (i == len && read_write == I2C_SMBUS_READ)
 544                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 545                 outb_p(smbcmd, SMBHSTCNT(priv));
 546
 547                 if (i == 1)
 548                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 549                                SMBHSTCNT(priv));
 550
 551                 status = i801_wait_byte_done(priv);
 552                 if (status)
 553                         goto exit;
 554
 555                 if (i == 1 && read_write == I2C_SMBUS_READ
 556                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 557                         len = inb_p(SMBHSTDAT0(priv));
 558                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 559                                 dev_err(&priv->pci_dev->dev,
 560                                         "Illegal SMBus block read size %d\n",
 561                                         len);
 562                                 /* Recover */
 563                                 while (inb_p(SMBHSTSTS(priv)) &
 564                                        SMBHSTSTS_HOST_BUSY)
 565                                         outb_p(SMBHSTSTS_BYTE_DONE,
 566                                                SMBHSTSTS(priv));
 567                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 568                                 return -EPROTO;
 569                         }
 570                         data->block[0] = len;
 571                 }
 572
 573                 /* Retrieve/store value in SMBBLKDAT */
 574                 if (read_write == I2C_SMBUS_READ)
 575                         data->block[i] = inb_p(SMBBLKDAT(priv));
 576                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 577                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 578
 579                 /* signals SMBBLKDAT ready */
 580                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 581         }
 582
 583         status = i801_wait_intr(priv);
 584 exit:
 585         return i801_check_post(priv, status);
 586 }
 587
 588 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 589 {
 590         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 591         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 592                 return -EIO;
 593         return 0;
 594 }
 595
 596 /* Block transaction function */
 597 static int i801_block_transaction(struct i801_priv *priv,
 598                                   union i2c_smbus_data *data, char read_write,
 599                                   int command, int hwpec)
 600 {
 601         int result = 0;
 602         unsigned char hostc;
 603
 604         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 605                 if (read_write == I2C_SMBUS_WRITE) {
 606                         /* set I2C_EN bit in configuration register */
 607                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 608                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 609                                               hostc | SMBHSTCFG_I2C_EN);
 610                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 611                         dev_err(&priv->pci_dev->dev,
 612                                 "I2C block read is unsupported!\n");
 613                         return -EOPNOTSUPP;
 614                 }
 615         }
 616
 617         if (read_write == I2C_SMBUS_WRITE
 618          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 619                 if (data->block[0] < 1)
 620                         data->block[0] = 1;
 621                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 622                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 623         } else {
 624                 data->block[0] = 32;    /* max for SMBus block reads */
 625         }
 626
 627         /* Experience has shown that the block buffer can only be used for
 628            SMBus (not I2C) block transactions, even though the datasheet
 629            doesn't mention this limitation. */
 630         if ((priv->features & FEATURE_BLOCK_BUFFER)
 631          && command != I2C_SMBUS_I2C_BLOCK_DATA
 632          && i801_set_block_buffer_mode(priv) == 0)
 633                 result = i801_block_transaction_by_block(priv, data,
 634                                                          read_write, hwpec);
 635         else
 636                 result = i801_block_transaction_byte_by_byte(priv, data,
 637                                                              read_write,
 638                                                              command, hwpec);
 639
 640         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 641          && read_write == I2C_SMBUS_WRITE) {
 642                 /* restore saved configuration register value */
 643                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 644         }
 645         return result;
 646 }
 647
 648 /* Return negative errno on error. */
 649 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 650                        unsigned short flags, char read_write, u8 command,
 651                        int size, union i2c_smbus_data *data)
 652 {
 653         int hwpec;
 654         int block = 0;
 655         int ret, xact = 0;
 656         struct i801_priv *priv = i2c_get_adapdata(adap);
 657
 658         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 659                 && size != I2C_SMBUS_QUICK
 660                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 661
 662         switch (size) {
 663         case I2C_SMBUS_QUICK:
 664                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 665                        SMBHSTADD(priv));
 666                 xact = I801_QUICK;
 667                 break;
 668         case I2C_SMBUS_BYTE:
 669                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 670                        SMBHSTADD(priv));
 671                 if (read_write == I2C_SMBUS_WRITE)
 672                         outb_p(command, SMBHSTCMD(priv));
 673                 xact = I801_BYTE;
 674                 break;
 675         case I2C_SMBUS_BYTE_DATA:
 676                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 677                        SMBHSTADD(priv));
 678                 outb_p(command, SMBHSTCMD(priv));
 679                 if (read_write == I2C_SMBUS_WRITE)
 680                         outb_p(data->byte, SMBHSTDAT0(priv));
 681                 xact = I801_BYTE_DATA;
 682                 break;
 683         case I2C_SMBUS_WORD_DATA:
 684                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 685                        SMBHSTADD(priv));
 686                 outb_p(command, SMBHSTCMD(priv));
 687                 if (read_write == I2C_SMBUS_WRITE) {
 688                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 689                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 690                 }
 691                 xact = I801_WORD_DATA;
 692                 break;
 693         case I2C_SMBUS_BLOCK_DATA:
 694                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 695                        SMBHSTADD(priv));
 696                 outb_p(command, SMBHSTCMD(priv));
 697                 block = 1;
 698                 break;
 699         case I2C_SMBUS_I2C_BLOCK_DATA:
 700                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 701                  * bit should be cleared here, even when reading */
 702                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 703                 if (read_write == I2C_SMBUS_READ) {
 704                         /* NB: page 240 of ICH5 datasheet also shows
 705                          * that DATA1 is the cmd field when reading */
 706                         outb_p(command, SMBHSTDAT1(priv));
 707                 } else
 708                         outb_p(command, SMBHSTCMD(priv));
 709                 block = 1;
 710                 break;
 711         default:
 712                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 713                         size);
 714                 return -EOPNOTSUPP;
 715         }
 716
 717         if (hwpec)      /* enable/disable hardware PEC */
 718                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 719         else
 720                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 721                        SMBAUXCTL(priv));
 722
 723         if (block)
 724                 ret = i801_block_transaction(priv, data, read_write, size,
 725                                              hwpec);
 726         else
 727                 ret = i801_transaction(priv, xact);
 728
 729         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 730            time, so we forcibly disable it after every transaction. Turn off
 731            E32B for the same reason. */
 732         if (hwpec || block)
 733                 outb_p(inb_p(SMBAUXCTL(priv)) &
 734                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 735
 736         if (block)
 737                 return ret;
 738         if (ret)
 739                 return ret;
 740         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 741                 return 0;
 742
 743         switch (xact & 0x7f) {
 744         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 745         case I801_BYTE_DATA:
 746                 data->byte = inb_p(SMBHSTDAT0(priv));
 747                 break;
 748         case I801_WORD_DATA:
 749                 data->word = inb_p(SMBHSTDAT0(priv)) +
 750                              (inb_p(SMBHSTDAT1(priv)) << 8);
 751                 break;
 752         }
 753         return 0;
 754 }
 755
 756
 757 static u32 i801_func(struct i2c_adapter *adapter)
 758 {
 759         struct i801_priv *priv = i2c_get_adapdata(adapter);
 760
 761         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 762                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 763                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 764                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 765                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 766                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 767 }
 768
 769 static const struct i2c_algorithm smbus_algorithm = {
 770         .smbus_xfer     = i801_access,
 771         .functionality  = i801_func,
 772 };
 773
 774 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
 775         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 776         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 777         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 778         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 779         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 780         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 781         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 782         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 783         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 784         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 785         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 786         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 787         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 788         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 789         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 790         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 791         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 792         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 793         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 794         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 795         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 796         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 797         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 798         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 799         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 800         { 0, }
 801 };
 802
 803 MODULE_DEVICE_TABLE(pci, i801_ids);
 804
 805 #if defined CONFIG_X86 && defined CONFIG_DMI
 806 static unsigned char apanel_addr;
 807
 808 /* Scan the system ROM for the signature "FJKEYINF" */
 809 static __init const void __iomem *bios_signature(const void __iomem *bios)
 810 {
 811         ssize_t offset;
 812         const unsigned char signature[] = "FJKEYINF";
 813
 814         for (offset = 0; offset < 0x10000; offset += 0x10) {
 815                 if (check_signature(bios + offset, signature,
 816                                     sizeof(signature)-1))
 817                         return bios + offset;
 818         }
 819         return NULL;
 820 }
 821
 822 static void __init input_apanel_init(void)
 823 {
 824         void __iomem *bios;
 825         const void __iomem *p;
 826
 827         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 828         p = bios_signature(bios);
 829         if (p) {
 830                 /* just use the first address */
 831                 apanel_addr = readb(p + 8 + 3) >> 1;
 832         }
 833         iounmap(bios);
 834 }
 835
 836 struct dmi_onboard_device_info {
 837         const char *name;
 838         u8 type;
 839         unsigned short i2c_addr;
 840         const char *i2c_type;
 841 };
 842
 843 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 844         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 845         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 846         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 847 };
 848
 849 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 850                                                struct i2c_adapter *adap)
 851 {
 852         int i;
 853         struct i2c_board_info info;
 854
 855         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 856                 /* & ~0x80, ignore enabled/disabled bit */
 857                 if ((type & ~0x80) != dmi_devices[i].type)
 858                         continue;
 859                 if (strcasecmp(name, dmi_devices[i].name))
 860                         continue;
 861
 862                 memset(&info, 0, sizeof(struct i2c_board_info));
 863                 info.addr = dmi_devices[i].i2c_addr;
 864                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 865                 i2c_new_device(adap, &info);
 866                 break;
 867         }
 868 }
 869
 870 /* We use our own function to check for onboard devices instead of
 871    dmi_find_device() as some buggy BIOS's have the devices we are interested
 872    in marked as disabled */
 873 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 874                                                 void *adap)
 875 {
 876         int i, count;
 877
 878         if (dm->type != 10)
 879                 return;
 880
 881         count = (dm->length - sizeof(struct dmi_header)) / 2;
 882         for (i = 0; i < count; i++) {
 883                 const u8 *d = (char *)(dm + 1) + (i * 2);
 884                 const char *name = ((char *) dm) + dm->length;
 885                 u8 type = d[0];
 886                 u8 s = d[1];
 887
 888                 if (!s)
 889                         continue;
 890                 s--;
 891                 while (s > 0 && name[0]) {
 892                         name += strlen(name) + 1;
 893                         s--;
 894                 }
 895                 if (name[0] == 0) /* Bogus string reference */
 896                         continue;
 897
 898                 dmi_check_onboard_device(type, name, adap);
 899         }
 900 }
 901
 902 /* Register optional slaves */
 903 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
 904 {
 905         /* Only register slaves on main SMBus channel */
 906         if (priv->features & FEATURE_IDF)
 907                 return;
 908
 909         if (apanel_addr) {
 910                 struct i2c_board_info info;
 911
 912                 memset(&info, 0, sizeof(struct i2c_board_info));
 913                 info.addr = apanel_addr;
 914                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 915                 i2c_new_device(&priv->adapter, &info);
 916         }
 917
 918         if (dmi_name_in_vendors("FUJITSU"))
 919                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 920 }
 921 #else
 922 static void __init input_apanel_init(void) {}
 923 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
 924 #endif  /* CONFIG_X86 && CONFIG_DMI */
 925
 926 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 927                 defined CONFIG_DMI
 928 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
 929         .gpio_chip = "gpio_ich",
 930         .values = { 0x02, 0x03 },
 931         .n_values = 2,
 932         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
 933         .gpios = { 52, 53 },
 934         .n_gpios = 2,
 935 };
 936
 937 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
 938         .gpio_chip = "gpio_ich",
 939         .values = { 0x02, 0x03, 0x01 },
 940         .n_values = 3,
 941         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
 942         .gpios = { 52, 53 },
 943         .n_gpios = 2,
 944 };
 945
 946 static struct dmi_system_id __devinitdata mux_dmi_table[] = {
 947         {
 948                 .matches = {
 949                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 950                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
 951                 },
 952                 .driver_data = &i801_mux_config_asus_z8_d12,
 953         },
 954         {
 955                 .matches = {
 956                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 957                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
 958                 },
 959                 .driver_data = &i801_mux_config_asus_z8_d12,
 960         },
 961         {
 962                 .matches = {
 963                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 964                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
 965                 },
 966                 .driver_data = &i801_mux_config_asus_z8_d12,
 967         },
 968         {
 969                 .matches = {
 970                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 971                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
 972                 },
 973                 .driver_data = &i801_mux_config_asus_z8_d12,
 974         },
 975         {
 976                 .matches = {
 977                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 978                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
 979                 },
 980                 .driver_data = &i801_mux_config_asus_z8_d12,
 981         },
 982         {
 983                 .matches = {
 984                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 985                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
 986                 },
 987                 .driver_data = &i801_mux_config_asus_z8_d12,
 988         },
 989         {
 990                 .matches = {
 991                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 992                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
 993                 },
 994                 .driver_data = &i801_mux_config_asus_z8_d18,
 995         },
 996         {
 997                 .matches = {
 998                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 999                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1000                 },
1001                 .driver_data = &i801_mux_config_asus_z8_d18,
1002         },
1003         {
1004                 .matches = {
1005                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1006                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1007                 },
1008                 .driver_data = &i801_mux_config_asus_z8_d12,
1009         },
1010         { }
1011 };
1012
1013 /* Setup multiplexing if needed */
1014 static int __devinit i801_add_mux(struct i801_priv *priv)
1015 {
1016         struct device *dev = &priv->adapter.dev;
1017         const struct i801_mux_config *mux_config;
1018         struct i2c_mux_gpio_platform_data gpio_data;
1019         int err;
1020
1021         if (!priv->mux_drvdata)
1022                 return 0;
1023         mux_config = priv->mux_drvdata;
1024
1025         /* Prepare the platform data */
1026         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1027         gpio_data.parent = priv->adapter.nr;
1028         gpio_data.values = mux_config->values;
1029         gpio_data.n_values = mux_config->n_values;
1030         gpio_data.classes = mux_config->classes;
1031         gpio_data.gpio_chip = mux_config->gpio_chip;
1032         gpio_data.gpios = mux_config->gpios;
1033         gpio_data.n_gpios = mux_config->n_gpios;
1034         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1035
1036         /* Register the mux device */
1037         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1038                                 PLATFORM_DEVID_AUTO, &gpio_data,
1039                                 sizeof(struct i2c_mux_gpio_platform_data));
1040         if (IS_ERR(priv->mux_pdev)) {
1041                 err = PTR_ERR(priv->mux_pdev);
1042                 priv->mux_pdev = NULL;
1043                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1044                 return err;
1045         }
1046
1047         return 0;
1048 }
1049
1050 static void __devexit i801_del_mux(struct i801_priv *priv)
1051 {
1052         if (priv->mux_pdev)
1053                 platform_device_unregister(priv->mux_pdev);
1054 }
1055
1056 static unsigned int __devinit i801_get_adapter_class(struct i801_priv *priv)
1057 {
1058         const struct dmi_system_id *id;
1059         const struct i801_mux_config *mux_config;
1060         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1061         int i;
1062
1063         id = dmi_first_match(mux_dmi_table);
1064         if (id) {
1065                 /* Remove branch classes from trunk */
1066                 mux_config = id->driver_data;
1067                 for (i = 0; i < mux_config->n_values; i++)
1068                         class &= ~mux_config->classes[i];
1069
1070                 /* Remember for later */
1071                 priv->mux_drvdata = mux_config;
1072         }
1073
1074         return class;
1075 }
1076 #else
1077 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1078 static inline void i801_del_mux(struct i801_priv *priv) { }
1079
1080 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1081 {
1082         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1083 }
1084 #endif
1085
1086 static int __devinit i801_probe(struct pci_dev *dev,
1087                                 const struct pci_device_id *id)
1088 {
1089         unsigned char temp;
1090         int err, i;
1091         struct i801_priv *priv;
1092
1093         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1094         if (!priv)
1095                 return -ENOMEM;
1096
1097         i2c_set_adapdata(&priv->adapter, priv);
1098         priv->adapter.owner = THIS_MODULE;
1099         priv->adapter.class = i801_get_adapter_class(priv);
1100         priv->adapter.algo = &smbus_algorithm;
1101
1102         priv->pci_dev = dev;
1103         switch (dev->device) {
1104         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1105         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1106         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1107                 priv->features |= FEATURE_IDF;
1108                 /* fall through */
1109         default:
1110                 priv->features |= FEATURE_I2C_BLOCK_READ;
1111                 /* fall through */
1112         case PCI_DEVICE_ID_INTEL_82801DB_3:
1113                 priv->features |= FEATURE_SMBUS_PEC;
1114                 priv->features |= FEATURE_BLOCK_BUFFER;
1115                 /* fall through */
1116         case PCI_DEVICE_ID_INTEL_82801CA_3:
1117         case PCI_DEVICE_ID_INTEL_82801BA_2:
1118         case PCI_DEVICE_ID_INTEL_82801AB_3:
1119         case PCI_DEVICE_ID_INTEL_82801AA_3:
1120                 break;
1121         }
1122
1123         /* IRQ processing tested on CougarPoint PCH, ICH5, ICH7-M and ICH10 */
1124         if (dev->device == PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS ||
1125             dev->device == PCI_DEVICE_ID_INTEL_82801EB_3 ||
1126             dev->device == PCI_DEVICE_ID_INTEL_ICH7_17 ||
1127             dev->device == PCI_DEVICE_ID_INTEL_ICH8_5 ||
1128             dev->device == PCI_DEVICE_ID_INTEL_ICH9_6 ||
1129             dev->device == PCI_DEVICE_ID_INTEL_ICH10_4 ||
1130             dev->device == PCI_DEVICE_ID_INTEL_ICH10_5)
1131                 priv->features |= FEATURE_IRQ;
1132
1133         /* Disable features on user request */
1134         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1135                 if (priv->features & disable_features & (1 << i))
1136                         dev_notice(&dev->dev, "%s disabled by user\n",
1137                                    i801_feature_names[i]);
1138         }
1139         priv->features &= ~disable_features;
1140
1141         err = pci_enable_device(dev);
1142         if (err) {
1143                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1144                         err);
1145                 goto exit;
1146         }
1147
1148         /* Determine the address of the SMBus area */
1149         priv->smba = pci_resource_start(dev, SMBBAR);
1150         if (!priv->smba) {
1151                 dev_err(&dev->dev, "SMBus base address uninitialized, "
1152                         "upgrade BIOS\n");
1153                 err = -ENODEV;
1154                 goto exit;
1155         }
1156
1157         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1158         if (err) {
1159                 err = -ENODEV;
1160                 goto exit;
1161         }
1162
1163         err = pci_request_region(dev, SMBBAR, i801_driver.name);
1164         if (err) {
1165                 dev_err(&dev->dev, "Failed to request SMBus region "
1166                         "0x%lx-0x%Lx\n", priv->smba,
1167                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1168                 goto exit;
1169         }
1170
1171         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1172         priv->original_hstcfg = temp;
1173         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1174         if (!(temp & SMBHSTCFG_HST_EN)) {
1175                 dev_info(&dev->dev, "Enabling SMBus device\n");
1176                 temp |= SMBHSTCFG_HST_EN;
1177         }
1178         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1179
1180         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1181                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1182                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1183                 priv->features &= ~FEATURE_IRQ;
1184         }
1185
1186         /* Clear special mode bits */
1187         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1188                 outb_p(inb_p(SMBAUXCTL(priv)) &
1189                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1190
1191         if (priv->features & FEATURE_IRQ) {
1192                 init_waitqueue_head(&priv->waitq);
1193
1194                 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1195                                   i801_driver.name, priv);
1196                 if (err) {
1197                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1198                                 dev->irq, err);
1199                         goto exit_release;
1200                 }
1201                 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1202         }
1203
1204         /* set up the sysfs linkage to our parent device */
1205         priv->adapter.dev.parent = &dev->dev;
1206
1207         /* Retry up to 3 times on lost arbitration */
1208         priv->adapter.retries = 3;
1209
1210         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1211                 "SMBus I801 adapter at %04lx", priv->smba);
1212         err = i2c_add_adapter(&priv->adapter);
1213         if (err) {
1214                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1215                 goto exit_free_irq;
1216         }
1217
1218         i801_probe_optional_slaves(priv);
1219         /* We ignore errors - multiplexing is optional */
1220         i801_add_mux(priv);
1221
1222         pci_set_drvdata(dev, priv);
1223
1224         return 0;
1225
1226 exit_free_irq:
1227         if (priv->features & FEATURE_IRQ)
1228                 free_irq(dev->irq, priv);
1229 exit_release:
1230         pci_release_region(dev, SMBBAR);
1231 exit:
1232         kfree(priv);
1233         return err;
1234 }
1235
1236 static void __devexit i801_remove(struct pci_dev *dev)
1237 {
1238         struct i801_priv *priv = pci_get_drvdata(dev);
1239
1240         i801_del_mux(priv);
1241         i2c_del_adapter(&priv->adapter);
1242         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1243
1244         if (priv->features & FEATURE_IRQ)
1245                 free_irq(dev->irq, priv);
1246         pci_release_region(dev, SMBBAR);
1247
1248         pci_set_drvdata(dev, NULL);
1249         kfree(priv);
1250         /*
1251          * do not call pci_disable_device(dev) since it can cause hard hangs on
1252          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1253          */
1254 }
1255
1256 #ifdef CONFIG_PM
1257 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1258 {
1259         struct i801_priv *priv = pci_get_drvdata(dev);
1260
1261         pci_save_state(dev);
1262         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1263         pci_set_power_state(dev, pci_choose_state(dev, mesg));
1264         return 0;
1265 }
1266
1267 static int i801_resume(struct pci_dev *dev)
1268 {
1269         pci_set_power_state(dev, PCI_D0);
1270         pci_restore_state(dev);
1271         return pci_enable_device(dev);
1272 }
1273 #else
1274 #define i801_suspend NULL
1275 #define i801_resume NULL
1276 #endif
1277
1278 static struct pci_driver i801_driver = {
1279         .name           = "i801_smbus",
1280         .id_table       = i801_ids,
1281         .probe          = i801_probe,
1282         .remove         = __devexit_p(i801_remove),
1283         .suspend        = i801_suspend,
1284         .resume         = i801_resume,
1285 };
1286
1287 static int __init i2c_i801_init(void)
1288 {
1289         if (dmi_name_in_vendors("FUJITSU"))
1290                 input_apanel_init();
1291         return pci_register_driver(&i801_driver);
1292 }
1293
1294 static void __exit i2c_i801_exit(void)
1295 {
1296         pci_unregister_driver(&i801_driver);
1297 }
1298
1299 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
1300               "Jean Delvare <khali@linux-fr.org>");
1301 MODULE_DESCRIPTION("I801 SMBus driver");
1302 MODULE_LICENSE("GPL");
1303
1304 module_init(i2c_i801_init);
1305 module_exit(i2c_i801_exit);