drivers/i2c/busses/i2c-davinci.c

   1 /*
   2  * TI DAVINCI I2C adapter driver.
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  * Copyright (C) 2007 MontaVista Software Inc.
   6  *
   7  * Updated by Vinod & Sudhakar Feb 2005
   8  *
   9  * ----------------------------------------------------------------------------
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  * ----------------------------------------------------------------------------
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/delay.h>
  26 #include <linux/i2c.h>
  27 #include <linux/clk.h>
  28 #include <linux/errno.h>
  29 #include <linux/sched.h>
  30 #include <linux/err.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/io.h>
  34 #include <linux/slab.h>
  35 #include <linux/cpufreq.h>
  36 #include <linux/gpio/consumer.h>
  37 #include <linux/of_device.h>
  38 #include <linux/platform_data/i2c-davinci.h>
  39 #include <linux/pm_runtime.h>
  40
  41 /* ----- global defines ----------------------------------------------- */
  42
  43 #define DAVINCI_I2C_TIMEOUT     (1*HZ)
  44 #define DAVINCI_I2C_MAX_TRIES   2
  45 #define DAVINCI_I2C_OWN_ADDRESS 0x08
  46 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_SCD | \
  47                                  DAVINCI_I2C_IMR_ARDY | \
  48                                  DAVINCI_I2C_IMR_NACK | \
  49                                  DAVINCI_I2C_IMR_AL)
  50
  51 #define DAVINCI_I2C_OAR_REG     0x00
  52 #define DAVINCI_I2C_IMR_REG     0x04
  53 #define DAVINCI_I2C_STR_REG     0x08
  54 #define DAVINCI_I2C_CLKL_REG    0x0c
  55 #define DAVINCI_I2C_CLKH_REG    0x10
  56 #define DAVINCI_I2C_CNT_REG     0x14
  57 #define DAVINCI_I2C_DRR_REG     0x18
  58 #define DAVINCI_I2C_SAR_REG     0x1c
  59 #define DAVINCI_I2C_DXR_REG     0x20
  60 #define DAVINCI_I2C_MDR_REG     0x24
  61 #define DAVINCI_I2C_IVR_REG     0x28
  62 #define DAVINCI_I2C_EMDR_REG    0x2c
  63 #define DAVINCI_I2C_PSC_REG     0x30
  64 #define DAVINCI_I2C_FUNC_REG    0x48
  65 #define DAVINCI_I2C_DIR_REG     0x4c
  66 #define DAVINCI_I2C_DIN_REG     0x50
  67 #define DAVINCI_I2C_DOUT_REG    0x54
  68 #define DAVINCI_I2C_DSET_REG    0x58
  69 #define DAVINCI_I2C_DCLR_REG    0x5c
  70
  71 #define DAVINCI_I2C_IVR_AAS     0x07
  72 #define DAVINCI_I2C_IVR_SCD     0x06
  73 #define DAVINCI_I2C_IVR_XRDY    0x05
  74 #define DAVINCI_I2C_IVR_RDR     0x04
  75 #define DAVINCI_I2C_IVR_ARDY    0x03
  76 #define DAVINCI_I2C_IVR_NACK    0x02
  77 #define DAVINCI_I2C_IVR_AL      0x01
  78
  79 #define DAVINCI_I2C_STR_BB      BIT(12)
  80 #define DAVINCI_I2C_STR_RSFULL  BIT(11)
  81 #define DAVINCI_I2C_STR_SCD     BIT(5)
  82 #define DAVINCI_I2C_STR_ARDY    BIT(2)
  83 #define DAVINCI_I2C_STR_NACK    BIT(1)
  84 #define DAVINCI_I2C_STR_AL      BIT(0)
  85
  86 #define DAVINCI_I2C_MDR_NACK    BIT(15)
  87 #define DAVINCI_I2C_MDR_STT     BIT(13)
  88 #define DAVINCI_I2C_MDR_STP     BIT(11)
  89 #define DAVINCI_I2C_MDR_MST     BIT(10)
  90 #define DAVINCI_I2C_MDR_TRX     BIT(9)
  91 #define DAVINCI_I2C_MDR_XA      BIT(8)
  92 #define DAVINCI_I2C_MDR_RM      BIT(7)
  93 #define DAVINCI_I2C_MDR_IRS     BIT(5)
  94
  95 #define DAVINCI_I2C_IMR_AAS     BIT(6)
  96 #define DAVINCI_I2C_IMR_SCD     BIT(5)
  97 #define DAVINCI_I2C_IMR_XRDY    BIT(4)
  98 #define DAVINCI_I2C_IMR_RRDY    BIT(3)
  99 #define DAVINCI_I2C_IMR_ARDY    BIT(2)
 100 #define DAVINCI_I2C_IMR_NACK    BIT(1)
 101 #define DAVINCI_I2C_IMR_AL      BIT(0)
 102
 103 /* set SDA and SCL as GPIO */
 104 #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
 105
 106 /* set SCL as output when used as GPIO*/
 107 #define DAVINCI_I2C_DIR_PDIR0   BIT(0)
 108 /* set SDA as output when used as GPIO*/
 109 #define DAVINCI_I2C_DIR_PDIR1   BIT(1)
 110
 111 /* read SCL GPIO level */
 112 #define DAVINCI_I2C_DIN_PDIN0 BIT(0)
 113 /* read SDA GPIO level */
 114 #define DAVINCI_I2C_DIN_PDIN1 BIT(1)
 115
 116 /*set the SCL GPIO high */
 117 #define DAVINCI_I2C_DSET_PDSET0 BIT(0)
 118 /*set the SDA GPIO high */
 119 #define DAVINCI_I2C_DSET_PDSET1 BIT(1)
 120
 121 /* set the SCL GPIO low */
 122 #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
 123 /* set the SDA GPIO low */
 124 #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
 125
 126 /* timeout for pm runtime autosuspend */
 127 #define DAVINCI_I2C_PM_TIMEOUT  1000    /* ms */
 128
 129 struct davinci_i2c_dev {
 130         struct device           *dev;
 131         void __iomem            *base;
 132         struct completion       cmd_complete;
 133         struct clk              *clk;
 134         int                     cmd_err;
 135         u8                      *buf;
 136         size_t                  buf_len;
 137         int                     irq;
 138         int                     stop;
 139         u8                      terminate;
 140         struct i2c_adapter      adapter;
 141 #ifdef CONFIG_CPU_FREQ
 142         struct notifier_block   freq_transition;
 143 #endif
 144         struct davinci_i2c_platform_data *pdata;
 145 };
 146
 147 /* default platform data to use if not supplied in the platform_device */
 148 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
 149         .bus_freq       = 100,
 150         .bus_delay      = 0,
 151 };
 152
 153 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
 154                                          int reg, u16 val)
 155 {
 156         writew_relaxed(val, i2c_dev->base + reg);
 157 }
 158
 159 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 160 {
 161         return readw_relaxed(i2c_dev->base + reg);
 162 }
 163
 164 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
 165                                                                 int val)
 166 {
 167         u16 w;
 168
 169         w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
 170         if (!val)       /* put I2C into reset */
 171                 w &= ~DAVINCI_I2C_MDR_IRS;
 172         else            /* take I2C out of reset */
 173                 w |= DAVINCI_I2C_MDR_IRS;
 174
 175         davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
 176 }
 177
 178 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
 179 {
 180         struct davinci_i2c_platform_data *pdata = dev->pdata;
 181         u16 psc;
 182         u32 clk;
 183         u32 d;
 184         u32 clkh;
 185         u32 clkl;
 186         u32 input_clock = clk_get_rate(dev->clk);
 187         struct device_node *of_node = dev->dev->of_node;
 188
 189         /* NOTE: I2C Clock divider programming info
 190          * As per I2C specs the following formulas provide prescaler
 191          * and low/high divider values
 192          * input clk --> PSC Div -----------> ICCL/H Div --> output clock
 193          *                       module clk
 194          *
 195          * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
 196          *
 197          * Thus,
 198          * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
 199          *
 200          * where if PSC == 0, d = 7,
 201          *       if PSC == 1, d = 6
 202          *       if PSC > 1 , d = 5
 203          *
 204          * Note:
 205          * d is always 6 on Keystone I2C controller
 206          */
 207
 208         /*
 209          * Both Davinci and current Keystone User Guides recommend a value
 210          * between 7MHz and 12MHz. In reality 7MHz module clock doesn't
 211          * always produce enough margin between SDA and SCL transitions.
 212          * Measurements show that the higher the module clock is, the
 213          * bigger is the margin, providing more reliable communication.
 214          * So we better target for 12MHz.
 215          */
 216         psc = (input_clock / 12000000) - 1;
 217         if ((input_clock / (psc + 1)) > 12000000)
 218                 psc++;  /* better to run under spec than over */
 219         d = (psc >= 2) ? 5 : 7 - psc;
 220
 221         if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
 222                 d = 6;
 223
 224         clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
 225         /* Avoid driving the bus too fast because of rounding errors above */
 226         if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
 227                 clk++;
 228         /*
 229          * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
 230          * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
 231          * to LOW ratio as 1 to 2 is more safe.
 232          */
 233         if (pdata->bus_freq > 100)
 234                 clkl = (clk << 1) / 3;
 235         else
 236                 clkl = (clk >> 1);
 237         /*
 238          * It's not always possible to have 1 to 2 ratio when d=7, so fall back
 239          * to minimal possible clkh in this case.
 240          *
 241          * Note:
 242          * CLKH is not allowed to be 0, in this case I2C clock is not generated
 243          * at all
 244          */
 245         if (clk > clkl + d) {
 246                 clkh = clk - clkl - d;
 247                 clkl -= d;
 248         } else {
 249                 clkh = 1;
 250                 clkl = clk - (d << 1);
 251         }
 252
 253         davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
 254         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
 255         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
 256
 257         dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
 258 }
 259
 260 /*
 261  * This function configures I2C and brings I2C out of reset.
 262  * This function is called during I2C init function. This function
 263  * also gets called if I2C encounters any errors.
 264  */
 265 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 266 {
 267         struct davinci_i2c_platform_data *pdata = dev->pdata;
 268
 269         /* put I2C into reset */
 270         davinci_i2c_reset_ctrl(dev, 0);
 271
 272         /* compute clock dividers */
 273         i2c_davinci_calc_clk_dividers(dev);
 274
 275         /* Respond at reserved "SMBus Host" slave address" (and zero);
 276          * we seem to have no option to not respond...
 277          */
 278         davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
 279
 280         dev_dbg(dev->dev, "PSC  = %d\n",
 281                 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
 282         dev_dbg(dev->dev, "CLKL = %d\n",
 283                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
 284         dev_dbg(dev->dev, "CLKH = %d\n",
 285                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
 286         dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
 287                 pdata->bus_freq, pdata->bus_delay);
 288
 289
 290         /* Take the I2C module out of reset: */
 291         davinci_i2c_reset_ctrl(dev, 1);
 292
 293         /* Enable interrupts */
 294         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 295
 296         return 0;
 297 }
 298
 299 /*
 300  * This routine does i2c bus recovery by using i2c_generic_scl_recovery
 301  * which is provided by I2C Bus recovery infrastructure.
 302  */
 303 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
 304 {
 305         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 306
 307         /* Disable interrupts */
 308         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
 309
 310         /* put I2C into reset */
 311         davinci_i2c_reset_ctrl(dev, 0);
 312 }
 313
 314 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
 315 {
 316         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 317
 318         i2c_davinci_init(dev);
 319 }
 320
 321 static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
 322         .recover_bus = i2c_generic_scl_recovery,
 323         .prepare_recovery = davinci_i2c_prepare_recovery,
 324         .unprepare_recovery = davinci_i2c_unprepare_recovery,
 325 };
 326
 327 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
 328 {
 329         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 330
 331         if (val)
 332                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
 333                                       DAVINCI_I2C_DSET_PDSET0);
 334         else
 335                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
 336                                       DAVINCI_I2C_DCLR_PDCLR0);
 337 }
 338
 339 static int davinci_i2c_get_scl(struct i2c_adapter *adap)
 340 {
 341         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 342         int val;
 343
 344         /* read the state of SCL */
 345         val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
 346         return val & DAVINCI_I2C_DIN_PDIN0;
 347 }
 348
 349 static int davinci_i2c_get_sda(struct i2c_adapter *adap)
 350 {
 351         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 352         int val;
 353
 354         /* read the state of SDA */
 355         val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
 356         return val & DAVINCI_I2C_DIN_PDIN1;
 357 }
 358
 359 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
 360 {
 361         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 362
 363         davinci_i2c_prepare_recovery(adap);
 364
 365         /* SCL output, SDA input */
 366         davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
 367
 368         /* change to GPIO mode */
 369         davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
 370                               DAVINCI_I2C_FUNC_PFUNC0);
 371 }
 372
 373 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
 374 {
 375         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 376
 377         /* change back to I2C mode */
 378         davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
 379
 380         davinci_i2c_unprepare_recovery(adap);
 381 }
 382
 383 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
 384         .recover_bus = i2c_generic_scl_recovery,
 385         .set_scl = davinci_i2c_set_scl,
 386         .get_scl = davinci_i2c_get_scl,
 387         .get_sda = davinci_i2c_get_sda,
 388         .prepare_recovery = davinci_i2c_scl_prepare_recovery,
 389         .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
 390 };
 391
 392 /*
 393  * Waiting for bus not busy
 394  */
 395 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
 396 {
 397         unsigned long timeout = jiffies + dev->adapter.timeout;
 398
 399         do {
 400                 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
 401                         return 0;
 402                 schedule_timeout_uninterruptible(1);
 403         } while (time_before_eq(jiffies, timeout));
 404
 405         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 406         i2c_recover_bus(&dev->adapter);
 407
 408         /*
 409          * if bus is still "busy" here, it's most probably a HW problem like
 410          * short-circuit
 411          */
 412         if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
 413                 return -EIO;
 414
 415         return 0;
 416 }
 417
 418 /*
 419  * Low level master read/write transaction. This function is called
 420  * from i2c_davinci_xfer.
 421  */
 422 static int
 423 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
 424 {
 425         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 426         struct davinci_i2c_platform_data *pdata = dev->pdata;
 427         u32 flag;
 428         u16 w;
 429         unsigned long time_left;
 430
 431         if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
 432                 dev_warn(dev->dev, "transfer to own address aborted\n");
 433                 return -EADDRNOTAVAIL;
 434         }
 435
 436         /* Introduce a delay, required for some boards (e.g Davinci EVM) */
 437         if (pdata->bus_delay)
 438                 udelay(pdata->bus_delay);
 439
 440         /* set the slave address */
 441         davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
 442
 443         dev->buf = msg->buf;
 444         dev->buf_len = msg->len;
 445         dev->stop = stop;
 446
 447         davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
 448
 449         reinit_completion(&dev->cmd_complete);
 450         dev->cmd_err = 0;
 451
 452         /* Take I2C out of reset and configure it as master */
 453         flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
 454
 455         /* if the slave address is ten bit address, enable XA bit */
 456         if (msg->flags & I2C_M_TEN)
 457                 flag |= DAVINCI_I2C_MDR_XA;
 458         if (!(msg->flags & I2C_M_RD))
 459                 flag |= DAVINCI_I2C_MDR_TRX;
 460         if (msg->len == 0)
 461                 flag |= DAVINCI_I2C_MDR_RM;
 462
 463         /* Enable receive or transmit interrupts */
 464         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
 465         if (msg->flags & I2C_M_RD)
 466                 w |= DAVINCI_I2C_IMR_RRDY;
 467         else
 468                 w |= DAVINCI_I2C_IMR_XRDY;
 469         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
 470
 471         dev->terminate = 0;
 472
 473         /*
 474          * Write mode register first as needed for correct behaviour
 475          * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
 476          * occurring before we have loaded DXR
 477          */
 478         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 479
 480         /*
 481          * First byte should be set here, not after interrupt,
 482          * because transmit-data-ready interrupt can come before
 483          * NACK-interrupt during sending of previous message and
 484          * ICDXR may have wrong data
 485          * It also saves us one interrupt, slightly faster
 486          */
 487         if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
 488                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
 489                 dev->buf_len--;
 490         }
 491
 492         /* Set STT to begin transmit now DXR is loaded */
 493         flag |= DAVINCI_I2C_MDR_STT;
 494         if (stop && msg->len != 0)
 495                 flag |= DAVINCI_I2C_MDR_STP;
 496         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 497
 498         time_left = wait_for_completion_timeout(&dev->cmd_complete,
 499                                                 dev->adapter.timeout);
 500         if (!time_left) {
 501                 dev_err(dev->dev, "controller timed out\n");
 502                 i2c_recover_bus(adap);
 503                 dev->buf_len = 0;
 504                 return -ETIMEDOUT;
 505         }
 506         if (dev->buf_len) {
 507                 /* This should be 0 if all bytes were transferred
 508                  * or dev->cmd_err denotes an error.
 509                  */
 510                 dev_err(dev->dev, "abnormal termination buf_len=%zu\n",
 511                         dev->buf_len);
 512                 dev->terminate = 1;
 513                 wmb();
 514                 dev->buf_len = 0;
 515                 return -EREMOTEIO;
 516         }
 517
 518         /* no error */
 519         if (likely(!dev->cmd_err))
 520                 return msg->len;
 521
 522         /* We have an error */
 523         if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
 524                 i2c_davinci_init(dev);
 525                 return -EIO;
 526         }
 527
 528         if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
 529                 if (msg->flags & I2C_M_IGNORE_NAK)
 530                         return msg->len;
 531                 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 532                 w |= DAVINCI_I2C_MDR_STP;
 533                 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 534                 return -EREMOTEIO;
 535         }
 536         return -EIO;
 537 }
 538
 539 /*
 540  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
 541  */
 542 static int
 543 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 544 {
 545         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 546         int i;
 547         int ret;
 548
 549         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 550
 551         ret = pm_runtime_get_sync(dev->dev);
 552         if (ret < 0) {
 553                 dev_err(dev->dev, "Failed to runtime_get device: %d\n", ret);
 554                 pm_runtime_put_noidle(dev->dev);
 555                 return ret;
 556         }
 557
 558         ret = i2c_davinci_wait_bus_not_busy(dev);
 559         if (ret < 0) {
 560                 dev_warn(dev->dev, "timeout waiting for bus ready\n");
 561                 goto out;
 562         }
 563
 564         for (i = 0; i < num; i++) {
 565                 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 566                 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
 567                         ret);
 568                 if (ret < 0)
 569                         goto out;
 570         }
 571
 572         ret = num;
 573
 574 out:
 575         pm_runtime_mark_last_busy(dev->dev);
 576         pm_runtime_put_autosuspend(dev->dev);
 577
 578         return ret;
 579 }
 580
 581 static u32 i2c_davinci_func(struct i2c_adapter *adap)
 582 {
 583         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 584 }
 585
 586 static void terminate_read(struct davinci_i2c_dev *dev)
 587 {
 588         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 589         w |= DAVINCI_I2C_MDR_NACK;
 590         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 591
 592         /* Throw away data */
 593         davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
 594         if (!dev->terminate)
 595                 dev_err(dev->dev, "RDR IRQ while no data requested\n");
 596 }
 597 static void terminate_write(struct davinci_i2c_dev *dev)
 598 {
 599         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 600         w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
 601         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 602
 603         if (!dev->terminate)
 604                 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
 605 }
 606
 607 /*
 608  * Interrupt service routine. This gets called whenever an I2C interrupt
 609  * occurs.
 610  */
 611 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
 612 {
 613         struct davinci_i2c_dev *dev = dev_id;
 614         u32 stat;
 615         int count = 0;
 616         u16 w;
 617
 618         if (pm_runtime_suspended(dev->dev))
 619                 return IRQ_NONE;
 620
 621         while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
 622                 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
 623                 if (count++ == 100) {
 624                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 625                         break;
 626                 }
 627
 628                 switch (stat) {
 629                 case DAVINCI_I2C_IVR_AL:
 630                         /* Arbitration lost, must retry */
 631                         dev->cmd_err |= DAVINCI_I2C_STR_AL;
 632                         dev->buf_len = 0;
 633                         complete(&dev->cmd_complete);
 634                         break;
 635
 636                 case DAVINCI_I2C_IVR_NACK:
 637                         dev->cmd_err |= DAVINCI_I2C_STR_NACK;
 638                         dev->buf_len = 0;
 639                         complete(&dev->cmd_complete);
 640                         break;
 641
 642                 case DAVINCI_I2C_IVR_ARDY:
 643                         davinci_i2c_write_reg(dev,
 644                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
 645                         if (((dev->buf_len == 0) && (dev->stop != 0)) ||
 646                             (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
 647                                 w = davinci_i2c_read_reg(dev,
 648                                                          DAVINCI_I2C_MDR_REG);
 649                                 w |= DAVINCI_I2C_MDR_STP;
 650                                 davinci_i2c_write_reg(dev,
 651                                                       DAVINCI_I2C_MDR_REG, w);
 652                         }
 653                         complete(&dev->cmd_complete);
 654                         break;
 655
 656                 case DAVINCI_I2C_IVR_RDR:
 657                         if (dev->buf_len) {
 658                                 *dev->buf++ =
 659                                     davinci_i2c_read_reg(dev,
 660                                                          DAVINCI_I2C_DRR_REG);
 661                                 dev->buf_len--;
 662                                 if (dev->buf_len)
 663                                         continue;
 664
 665                                 davinci_i2c_write_reg(dev,
 666                                         DAVINCI_I2C_STR_REG,
 667                                         DAVINCI_I2C_IMR_RRDY);
 668                         } else {
 669                                 /* signal can terminate transfer */
 670                                 terminate_read(dev);
 671                         }
 672                         break;
 673
 674                 case DAVINCI_I2C_IVR_XRDY:
 675                         if (dev->buf_len) {
 676                                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
 677                                                       *dev->buf++);
 678                                 dev->buf_len--;
 679                                 if (dev->buf_len)
 680                                         continue;
 681
 682                                 w = davinci_i2c_read_reg(dev,
 683                                                          DAVINCI_I2C_IMR_REG);
 684                                 w &= ~DAVINCI_I2C_IMR_XRDY;
 685                                 davinci_i2c_write_reg(dev,
 686                                                       DAVINCI_I2C_IMR_REG,
 687                                                       w);
 688                         } else {
 689                                 /* signal can terminate transfer */
 690                                 terminate_write(dev);
 691                         }
 692                         break;
 693
 694                 case DAVINCI_I2C_IVR_SCD:
 695                         davinci_i2c_write_reg(dev,
 696                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
 697                         complete(&dev->cmd_complete);
 698                         break;
 699
 700                 case DAVINCI_I2C_IVR_AAS:
 701                         dev_dbg(dev->dev, "Address as slave interrupt\n");
 702                         break;
 703
 704                 default:
 705                         dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
 706                         break;
 707                 }
 708         }
 709
 710         return count ? IRQ_HANDLED : IRQ_NONE;
 711 }
 712
 713 #ifdef CONFIG_CPU_FREQ
 714 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
 715                                      unsigned long val, void *data)
 716 {
 717         struct davinci_i2c_dev *dev;
 718
 719         dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
 720
 721         i2c_lock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
 722         if (val == CPUFREQ_PRECHANGE) {
 723                 davinci_i2c_reset_ctrl(dev, 0);
 724         } else if (val == CPUFREQ_POSTCHANGE) {
 725                 i2c_davinci_calc_clk_dividers(dev);
 726                 davinci_i2c_reset_ctrl(dev, 1);
 727         }
 728         i2c_unlock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
 729
 730         return 0;
 731 }
 732
 733 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 734 {
 735         dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
 736
 737         return cpufreq_register_notifier(&dev->freq_transition,
 738                                          CPUFREQ_TRANSITION_NOTIFIER);
 739 }
 740
 741 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 742 {
 743         cpufreq_unregister_notifier(&dev->freq_transition,
 744                                     CPUFREQ_TRANSITION_NOTIFIER);
 745 }
 746 #else
 747 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 748 {
 749         return 0;
 750 }
 751
 752 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 753 {
 754 }
 755 #endif
 756
 757 static const struct i2c_algorithm i2c_davinci_algo = {
 758         .master_xfer    = i2c_davinci_xfer,
 759         .functionality  = i2c_davinci_func,
 760 };
 761
 762 static const struct of_device_id davinci_i2c_of_match[] = {
 763         {.compatible = "ti,davinci-i2c", },
 764         {.compatible = "ti,keystone-i2c", },
 765         {},
 766 };
 767 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
 768
 769 static int davinci_i2c_probe(struct platform_device *pdev)
 770 {
 771         struct davinci_i2c_dev *dev;
 772         struct i2c_adapter *adap;
 773         struct resource *mem;
 774         struct i2c_bus_recovery_info *rinfo;
 775         int r, irq;
 776
 777         irq = platform_get_irq(pdev, 0);
 778         if (irq <= 0) {
 779                 if (!irq)
 780                         irq = -ENXIO;
 781                 if (irq != -EPROBE_DEFER)
 782                         dev_err(&pdev->dev,
 783                                 "can't get irq resource ret=%d\n", irq);
 784                 return irq;
 785         }
 786
 787         dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
 788                         GFP_KERNEL);
 789         if (!dev) {
 790                 dev_err(&pdev->dev, "Memory allocation failed\n");
 791                 return -ENOMEM;
 792         }
 793
 794         init_completion(&dev->cmd_complete);
 795
 796         dev->dev = &pdev->dev;
 797         dev->irq = irq;
 798         dev->pdata = dev_get_platdata(&pdev->dev);
 799         platform_set_drvdata(pdev, dev);
 800
 801         if (!dev->pdata && pdev->dev.of_node) {
 802                 u32 prop;
 803
 804                 dev->pdata = devm_kzalloc(&pdev->dev,
 805                         sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
 806                 if (!dev->pdata)
 807                         return -ENOMEM;
 808
 809                 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
 810                         sizeof(struct davinci_i2c_platform_data));
 811                 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 812                         &prop))
 813                         dev->pdata->bus_freq = prop / 1000;
 814
 815                 dev->pdata->has_pfunc =
 816                         of_property_read_bool(pdev->dev.of_node,
 817                                               "ti,has-pfunc");
 818         } else if (!dev->pdata) {
 819                 dev->pdata = &davinci_i2c_platform_data_default;
 820         }
 821
 822         dev->clk = devm_clk_get(&pdev->dev, NULL);
 823         if (IS_ERR(dev->clk))
 824                 return PTR_ERR(dev->clk);
 825
 826         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 827         dev->base = devm_ioremap_resource(&pdev->dev, mem);
 828         if (IS_ERR(dev->base)) {
 829                 return PTR_ERR(dev->base);
 830         }
 831
 832         pm_runtime_set_autosuspend_delay(dev->dev,
 833                                          DAVINCI_I2C_PM_TIMEOUT);
 834         pm_runtime_use_autosuspend(dev->dev);
 835
 836         pm_runtime_enable(dev->dev);
 837
 838         r = pm_runtime_get_sync(dev->dev);
 839         if (r < 0) {
 840                 dev_err(dev->dev, "failed to runtime_get device: %d\n", r);
 841                 pm_runtime_put_noidle(dev->dev);
 842                 return r;
 843         }
 844
 845         i2c_davinci_init(dev);
 846
 847         r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
 848                         pdev->name, dev);
 849         if (r) {
 850                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
 851                 goto err_unuse_clocks;
 852         }
 853
 854         r = i2c_davinci_cpufreq_register(dev);
 855         if (r) {
 856                 dev_err(&pdev->dev, "failed to register cpufreq\n");
 857                 goto err_unuse_clocks;
 858         }
 859
 860         adap = &dev->adapter;
 861         i2c_set_adapdata(adap, dev);
 862         adap->owner = THIS_MODULE;
 863         adap->class = I2C_CLASS_DEPRECATED;
 864         strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
 865         adap->algo = &i2c_davinci_algo;
 866         adap->dev.parent = &pdev->dev;
 867         adap->timeout = DAVINCI_I2C_TIMEOUT;
 868         adap->dev.of_node = pdev->dev.of_node;
 869
 870         if (dev->pdata->has_pfunc)
 871                 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
 872         else if (dev->pdata->gpio_recovery) {
 873                 rinfo =  &davinci_i2c_gpio_recovery_info;
 874                 adap->bus_recovery_info = rinfo;
 875                 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl",
 876                                                   GPIOD_OUT_HIGH_OPEN_DRAIN);
 877                 if (IS_ERR(rinfo->scl_gpiod)) {
 878                         r = PTR_ERR(rinfo->scl_gpiod);
 879                         goto err_unuse_clocks;
 880                 }
 881                 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
 882                 if (IS_ERR(rinfo->sda_gpiod)) {
 883                         r = PTR_ERR(rinfo->sda_gpiod);
 884                         goto err_unuse_clocks;
 885                 }
 886         }
 887
 888         adap->nr = pdev->id;
 889         r = i2c_add_numbered_adapter(adap);
 890         if (r)
 891                 goto err_unuse_clocks;
 892
 893         pm_runtime_mark_last_busy(dev->dev);
 894         pm_runtime_put_autosuspend(dev->dev);
 895
 896         return 0;
 897
 898 err_unuse_clocks:
 899         pm_runtime_dont_use_autosuspend(dev->dev);
 900         pm_runtime_put_sync(dev->dev);
 901         pm_runtime_disable(dev->dev);
 902
 903         return r;
 904 }
 905
 906 static int davinci_i2c_remove(struct platform_device *pdev)
 907 {
 908         struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
 909         int ret;
 910
 911         i2c_davinci_cpufreq_deregister(dev);
 912
 913         i2c_del_adapter(&dev->adapter);
 914
 915         ret = pm_runtime_get_sync(&pdev->dev);
 916         if (ret < 0) {
 917                 pm_runtime_put_noidle(&pdev->dev);
 918                 return ret;
 919         }
 920
 921         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
 922
 923         pm_runtime_dont_use_autosuspend(dev->dev);
 924         pm_runtime_put_sync(dev->dev);
 925         pm_runtime_disable(dev->dev);
 926
 927         return 0;
 928 }
 929
 930 #ifdef CONFIG_PM
 931 static int davinci_i2c_suspend(struct device *dev)
 932 {
 933         struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 934
 935         /* put I2C into reset */
 936         davinci_i2c_reset_ctrl(i2c_dev, 0);
 937
 938         return 0;
 939 }
 940
 941 static int davinci_i2c_resume(struct device *dev)
 942 {
 943         struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 944
 945         /* take I2C out of reset */
 946         davinci_i2c_reset_ctrl(i2c_dev, 1);
 947
 948         return 0;
 949 }
 950
 951 static const struct dev_pm_ops davinci_i2c_pm = {
 952         .suspend        = davinci_i2c_suspend,
 953         .resume         = davinci_i2c_resume,
 954         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 955                                       pm_runtime_force_resume)
 956 };
 957
 958 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
 959 #else
 960 #define davinci_i2c_pm_ops NULL
 961 #endif
 962
 963 /* work with hotplug and coldplug */
 964 MODULE_ALIAS("platform:i2c_davinci");
 965
 966 static struct platform_driver davinci_i2c_driver = {
 967         .probe          = davinci_i2c_probe,
 968         .remove         = davinci_i2c_remove,
 969         .driver         = {
 970                 .name   = "i2c_davinci",
 971                 .pm     = davinci_i2c_pm_ops,
 972                 .of_match_table = davinci_i2c_of_match,
 973         },
 974 };
 975
 976 /* I2C may be needed to bring up other drivers */
 977 static int __init davinci_i2c_init_driver(void)
 978 {
 979         return platform_driver_register(&davinci_i2c_driver);
 980 }
 981 subsys_initcall(davinci_i2c_init_driver);
 982
 983 static void __exit davinci_i2c_exit_driver(void)
 984 {
 985         platform_driver_unregister(&davinci_i2c_driver);
 986 }
 987 module_exit(davinci_i2c_exit_driver);
 988
 989 MODULE_AUTHOR("Texas Instruments India");
 990 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
 991 MODULE_LICENSE("GPL");