Merge branch 'for-2636/i2c/nuc' into next-i2c
[sfrench/cifs-2.6.git] / drivers / i2c / busses / i2c-davinci.c
1 /*
2  * TI DAVINCI I2C adapter driver.
3  *
4  * Copyright (C) 2006 Texas Instruments.
5  * Copyright (C) 2007 MontaVista Software Inc.
6  *
7  * Updated by Vinod & Sudhakar Feb 2005
8  *
9  * ----------------------------------------------------------------------------
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24  * ----------------------------------------------------------------------------
25  *
26  */
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/i2c.h>
31 #include <linux/clk.h>
32 #include <linux/errno.h>
33 #include <linux/sched.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/platform_device.h>
37 #include <linux/io.h>
38 #include <linux/slab.h>
39 #include <linux/cpufreq.h>
40 #include <linux/gpio.h>
41
42 #include <mach/hardware.h>
43 #include <mach/i2c.h>
44
45 /* ----- global defines ----------------------------------------------- */
46
47 #define DAVINCI_I2C_TIMEOUT     (1*HZ)
48 #define DAVINCI_I2C_MAX_TRIES   2
49 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
50                                  DAVINCI_I2C_IMR_SCD | \
51                                  DAVINCI_I2C_IMR_ARDY | \
52                                  DAVINCI_I2C_IMR_NACK | \
53                                  DAVINCI_I2C_IMR_AL)
54
55 #define DAVINCI_I2C_OAR_REG     0x00
56 #define DAVINCI_I2C_IMR_REG     0x04
57 #define DAVINCI_I2C_STR_REG     0x08
58 #define DAVINCI_I2C_CLKL_REG    0x0c
59 #define DAVINCI_I2C_CLKH_REG    0x10
60 #define DAVINCI_I2C_CNT_REG     0x14
61 #define DAVINCI_I2C_DRR_REG     0x18
62 #define DAVINCI_I2C_SAR_REG     0x1c
63 #define DAVINCI_I2C_DXR_REG     0x20
64 #define DAVINCI_I2C_MDR_REG     0x24
65 #define DAVINCI_I2C_IVR_REG     0x28
66 #define DAVINCI_I2C_EMDR_REG    0x2c
67 #define DAVINCI_I2C_PSC_REG     0x30
68
69 #define DAVINCI_I2C_IVR_AAS     0x07
70 #define DAVINCI_I2C_IVR_SCD     0x06
71 #define DAVINCI_I2C_IVR_XRDY    0x05
72 #define DAVINCI_I2C_IVR_RDR     0x04
73 #define DAVINCI_I2C_IVR_ARDY    0x03
74 #define DAVINCI_I2C_IVR_NACK    0x02
75 #define DAVINCI_I2C_IVR_AL      0x01
76
77 #define DAVINCI_I2C_STR_BB      BIT(12)
78 #define DAVINCI_I2C_STR_RSFULL  BIT(11)
79 #define DAVINCI_I2C_STR_SCD     BIT(5)
80 #define DAVINCI_I2C_STR_ARDY    BIT(2)
81 #define DAVINCI_I2C_STR_NACK    BIT(1)
82 #define DAVINCI_I2C_STR_AL      BIT(0)
83
84 #define DAVINCI_I2C_MDR_NACK    BIT(15)
85 #define DAVINCI_I2C_MDR_STT     BIT(13)
86 #define DAVINCI_I2C_MDR_STP     BIT(11)
87 #define DAVINCI_I2C_MDR_MST     BIT(10)
88 #define DAVINCI_I2C_MDR_TRX     BIT(9)
89 #define DAVINCI_I2C_MDR_XA      BIT(8)
90 #define DAVINCI_I2C_MDR_RM      BIT(7)
91 #define DAVINCI_I2C_MDR_IRS     BIT(5)
92
93 #define DAVINCI_I2C_IMR_AAS     BIT(6)
94 #define DAVINCI_I2C_IMR_SCD     BIT(5)
95 #define DAVINCI_I2C_IMR_XRDY    BIT(4)
96 #define DAVINCI_I2C_IMR_RRDY    BIT(3)
97 #define DAVINCI_I2C_IMR_ARDY    BIT(2)
98 #define DAVINCI_I2C_IMR_NACK    BIT(1)
99 #define DAVINCI_I2C_IMR_AL      BIT(0)
100
101 struct davinci_i2c_dev {
102         struct device           *dev;
103         void __iomem            *base;
104         struct completion       cmd_complete;
105         struct clk              *clk;
106         int                     cmd_err;
107         u8                      *buf;
108         size_t                  buf_len;
109         int                     irq;
110         int                     stop;
111         u8                      terminate;
112         struct i2c_adapter      adapter;
113 #ifdef CONFIG_CPU_FREQ
114         struct completion       xfr_complete;
115         struct notifier_block   freq_transition;
116 #endif
117 };
118
119 /* default platform data to use if not supplied in the platform_device */
120 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
121         .bus_freq       = 100,
122         .bus_delay      = 0,
123 };
124
125 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
126                                          int reg, u16 val)
127 {
128         __raw_writew(val, i2c_dev->base + reg);
129 }
130
131 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
132 {
133         return __raw_readw(i2c_dev->base + reg);
134 }
135
136 /* Generate a pulse on the i2c clock pin. */
137 static void generic_i2c_clock_pulse(unsigned int scl_pin)
138 {
139         u16 i;
140
141         if (scl_pin) {
142                 /* Send high and low on the SCL line */
143                 for (i = 0; i < 9; i++) {
144                         gpio_set_value(scl_pin, 0);
145                         udelay(20);
146                         gpio_set_value(scl_pin, 1);
147                         udelay(20);
148                 }
149         }
150 }
151
152 /* This routine does i2c bus recovery as specified in the
153  * i2c protocol Rev. 03 section 3.16 titled "Bus clear"
154  */
155 static void i2c_recover_bus(struct davinci_i2c_dev *dev)
156 {
157         u32 flag = 0;
158         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
159
160         dev_err(dev->dev, "initiating i2c bus recovery\n");
161         /* Send NACK to the slave */
162         flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
163         flag |=  DAVINCI_I2C_MDR_NACK;
164         /* write the data into mode register */
165         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
166         if (pdata)
167                 generic_i2c_clock_pulse(pdata->scl_pin);
168         /* Send STOP */
169         flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
170         flag |= DAVINCI_I2C_MDR_STP;
171         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
172 }
173
174 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
175                                                                 int val)
176 {
177         u16 w;
178
179         w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
180         if (!val)       /* put I2C into reset */
181                 w &= ~DAVINCI_I2C_MDR_IRS;
182         else            /* take I2C out of reset */
183                 w |= DAVINCI_I2C_MDR_IRS;
184
185         davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
186 }
187
188 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
189 {
190         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
191         u16 psc;
192         u32 clk;
193         u32 d;
194         u32 clkh;
195         u32 clkl;
196         u32 input_clock = clk_get_rate(dev->clk);
197
198         /* NOTE: I2C Clock divider programming info
199          * As per I2C specs the following formulas provide prescaler
200          * and low/high divider values
201          * input clk --> PSC Div -----------> ICCL/H Div --> output clock
202          *                       module clk
203          *
204          * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
205          *
206          * Thus,
207          * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
208          *
209          * where if PSC == 0, d = 7,
210          *       if PSC == 1, d = 6
211          *       if PSC > 1 , d = 5
212          */
213
214         /* get minimum of 7 MHz clock, but max of 12 MHz */
215         psc = (input_clock / 7000000) - 1;
216         if ((input_clock / (psc + 1)) > 12000000)
217                 psc++;  /* better to run under spec than over */
218         d = (psc >= 2) ? 5 : 7 - psc;
219
220         clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
221         clkh = clk >> 1;
222         clkl = clk - clkh;
223
224         davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
225         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
226         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
227
228         dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
229 }
230
231 /*
232  * This function configures I2C and brings I2C out of reset.
233  * This function is called during I2C init function. This function
234  * also gets called if I2C encounters any errors.
235  */
236 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
237 {
238         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
239
240         if (!pdata)
241                 pdata = &davinci_i2c_platform_data_default;
242
243         /* put I2C into reset */
244         davinci_i2c_reset_ctrl(dev, 0);
245
246         /* compute clock dividers */
247         i2c_davinci_calc_clk_dividers(dev);
248
249         /* Respond at reserved "SMBus Host" slave address" (and zero);
250          * we seem to have no option to not respond...
251          */
252         davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
253
254         dev_dbg(dev->dev, "PSC  = %d\n",
255                 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
256         dev_dbg(dev->dev, "CLKL = %d\n",
257                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
258         dev_dbg(dev->dev, "CLKH = %d\n",
259                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
260         dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
261                 pdata->bus_freq, pdata->bus_delay);
262
263         /* Take the I2C module out of reset: */
264         davinci_i2c_reset_ctrl(dev, 1);
265
266         /* Enable interrupts */
267         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
268
269         return 0;
270 }
271
272 /*
273  * Waiting for bus not busy
274  */
275 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
276                                          char allow_sleep)
277 {
278         unsigned long timeout;
279         static u16 to_cnt;
280
281         timeout = jiffies + dev->adapter.timeout;
282         while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
283                & DAVINCI_I2C_STR_BB) {
284                 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
285                         if (time_after(jiffies, timeout)) {
286                                 dev_warn(dev->dev,
287                                 "timeout waiting for bus ready\n");
288                                 to_cnt++;
289                                 return -ETIMEDOUT;
290                         } else {
291                                 to_cnt = 0;
292                                 i2c_recover_bus(dev);
293                                 i2c_davinci_init(dev);
294                         }
295                 }
296                 if (allow_sleep)
297                         schedule_timeout(1);
298         }
299
300         return 0;
301 }
302
303 /*
304  * Low level master read/write transaction. This function is called
305  * from i2c_davinci_xfer.
306  */
307 static int
308 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
309 {
310         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
311         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
312         u32 flag;
313         u16 w;
314         int r;
315
316         if (!pdata)
317                 pdata = &davinci_i2c_platform_data_default;
318         /* Introduce a delay, required for some boards (e.g Davinci EVM) */
319         if (pdata->bus_delay)
320                 udelay(pdata->bus_delay);
321
322         /* set the slave address */
323         davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
324
325         dev->buf = msg->buf;
326         dev->buf_len = msg->len;
327         dev->stop = stop;
328
329         davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
330
331         INIT_COMPLETION(dev->cmd_complete);
332         dev->cmd_err = 0;
333
334         /* Take I2C out of reset, configure it as master and set the
335          * start bit */
336         flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT;
337
338         /* if the slave address is ten bit address, enable XA bit */
339         if (msg->flags & I2C_M_TEN)
340                 flag |= DAVINCI_I2C_MDR_XA;
341         if (!(msg->flags & I2C_M_RD))
342                 flag |= DAVINCI_I2C_MDR_TRX;
343         if (stop)
344                 flag |= DAVINCI_I2C_MDR_STP;
345         if (msg->len == 0) {
346                 flag |= DAVINCI_I2C_MDR_RM;
347                 flag &= ~DAVINCI_I2C_MDR_STP;
348         }
349
350         /* Enable receive or transmit interrupts */
351         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
352         if (msg->flags & I2C_M_RD)
353                 w |= DAVINCI_I2C_IMR_RRDY;
354         else
355                 w |= DAVINCI_I2C_IMR_XRDY;
356         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
357
358         dev->terminate = 0;
359
360         /* write the data into mode register */
361         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
362
363         /*
364          * First byte should be set here, not after interrupt,
365          * because transmit-data-ready interrupt can come before
366          * NACK-interrupt during sending of previous message and
367          * ICDXR may have wrong data
368          */
369         if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
370                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
371                 dev->buf_len--;
372         }
373
374         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
375                                                       dev->adapter.timeout);
376         if (r == 0) {
377                 dev_err(dev->dev, "controller timed out\n");
378                 i2c_recover_bus(dev);
379                 i2c_davinci_init(dev);
380                 dev->buf_len = 0;
381                 return -ETIMEDOUT;
382         }
383         if (dev->buf_len) {
384                 /* This should be 0 if all bytes were transferred
385                  * or dev->cmd_err denotes an error.
386                  * A signal may have aborted the transfer.
387                  */
388                 if (r >= 0) {
389                         dev_err(dev->dev, "abnormal termination buf_len=%i\n",
390                                 dev->buf_len);
391                         r = -EREMOTEIO;
392                 }
393                 dev->terminate = 1;
394                 wmb();
395                 dev->buf_len = 0;
396         }
397         if (r < 0)
398                 return r;
399
400         /* no error */
401         if (likely(!dev->cmd_err))
402                 return msg->len;
403
404         /* We have an error */
405         if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
406                 i2c_davinci_init(dev);
407                 return -EIO;
408         }
409
410         if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
411                 if (msg->flags & I2C_M_IGNORE_NAK)
412                         return msg->len;
413                 if (stop) {
414                         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
415                         w |= DAVINCI_I2C_MDR_STP;
416                         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
417                 }
418                 return -EREMOTEIO;
419         }
420         return -EIO;
421 }
422
423 /*
424  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
425  */
426 static int
427 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
428 {
429         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
430         int i;
431         int ret;
432
433         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
434
435         ret = i2c_davinci_wait_bus_not_busy(dev, 1);
436         if (ret < 0) {
437                 dev_warn(dev->dev, "timeout waiting for bus ready\n");
438                 return ret;
439         }
440
441         for (i = 0; i < num; i++) {
442                 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
443                 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
444                         ret);
445                 if (ret < 0)
446                         return ret;
447         }
448
449 #ifdef CONFIG_CPU_FREQ
450         complete(&dev->xfr_complete);
451 #endif
452
453         return num;
454 }
455
456 static u32 i2c_davinci_func(struct i2c_adapter *adap)
457 {
458         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
459 }
460
461 static void terminate_read(struct davinci_i2c_dev *dev)
462 {
463         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
464         w |= DAVINCI_I2C_MDR_NACK;
465         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
466
467         /* Throw away data */
468         davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
469         if (!dev->terminate)
470                 dev_err(dev->dev, "RDR IRQ while no data requested\n");
471 }
472 static void terminate_write(struct davinci_i2c_dev *dev)
473 {
474         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
475         w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
476         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
477
478         if (!dev->terminate)
479                 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
480 }
481
482 /*
483  * Interrupt service routine. This gets called whenever an I2C interrupt
484  * occurs.
485  */
486 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
487 {
488         struct davinci_i2c_dev *dev = dev_id;
489         u32 stat;
490         int count = 0;
491         u16 w;
492
493         while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
494                 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
495                 if (count++ == 100) {
496                         dev_warn(dev->dev, "Too much work in one IRQ\n");
497                         break;
498                 }
499
500                 switch (stat) {
501                 case DAVINCI_I2C_IVR_AL:
502                         /* Arbitration lost, must retry */
503                         dev->cmd_err |= DAVINCI_I2C_STR_AL;
504                         dev->buf_len = 0;
505                         complete(&dev->cmd_complete);
506                         break;
507
508                 case DAVINCI_I2C_IVR_NACK:
509                         dev->cmd_err |= DAVINCI_I2C_STR_NACK;
510                         dev->buf_len = 0;
511                         complete(&dev->cmd_complete);
512                         break;
513
514                 case DAVINCI_I2C_IVR_ARDY:
515                         davinci_i2c_write_reg(dev,
516                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
517                         if (((dev->buf_len == 0) && (dev->stop != 0)) ||
518                             (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
519                                 w = davinci_i2c_read_reg(dev,
520                                                          DAVINCI_I2C_MDR_REG);
521                                 w |= DAVINCI_I2C_MDR_STP;
522                                 davinci_i2c_write_reg(dev,
523                                                       DAVINCI_I2C_MDR_REG, w);
524                         }
525                         complete(&dev->cmd_complete);
526                         break;
527
528                 case DAVINCI_I2C_IVR_RDR:
529                         if (dev->buf_len) {
530                                 *dev->buf++ =
531                                     davinci_i2c_read_reg(dev,
532                                                          DAVINCI_I2C_DRR_REG);
533                                 dev->buf_len--;
534                                 if (dev->buf_len)
535                                         continue;
536
537                                 davinci_i2c_write_reg(dev,
538                                         DAVINCI_I2C_STR_REG,
539                                         DAVINCI_I2C_IMR_RRDY);
540                         } else {
541                                 /* signal can terminate transfer */
542                                 terminate_read(dev);
543                         }
544                         break;
545
546                 case DAVINCI_I2C_IVR_XRDY:
547                         if (dev->buf_len) {
548                                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
549                                                       *dev->buf++);
550                                 dev->buf_len--;
551                                 if (dev->buf_len)
552                                         continue;
553
554                                 w = davinci_i2c_read_reg(dev,
555                                                          DAVINCI_I2C_IMR_REG);
556                                 w &= ~DAVINCI_I2C_IMR_XRDY;
557                                 davinci_i2c_write_reg(dev,
558                                                       DAVINCI_I2C_IMR_REG,
559                                                       w);
560                         } else {
561                                 /* signal can terminate transfer */
562                                 terminate_write(dev);
563                         }
564                         break;
565
566                 case DAVINCI_I2C_IVR_SCD:
567                         davinci_i2c_write_reg(dev,
568                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
569                         complete(&dev->cmd_complete);
570                         break;
571
572                 case DAVINCI_I2C_IVR_AAS:
573                         dev_dbg(dev->dev, "Address as slave interrupt\n");
574                         break;
575
576                 default:
577                         dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
578                         break;
579                 }
580         }
581
582         return count ? IRQ_HANDLED : IRQ_NONE;
583 }
584
585 #ifdef CONFIG_CPU_FREQ
586 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
587                                      unsigned long val, void *data)
588 {
589         struct davinci_i2c_dev *dev;
590
591         dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
592         if (val == CPUFREQ_PRECHANGE) {
593                 wait_for_completion(&dev->xfr_complete);
594                 davinci_i2c_reset_ctrl(dev, 0);
595         } else if (val == CPUFREQ_POSTCHANGE) {
596                 i2c_davinci_calc_clk_dividers(dev);
597                 davinci_i2c_reset_ctrl(dev, 1);
598         }
599
600         return 0;
601 }
602
603 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
604 {
605         dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
606
607         return cpufreq_register_notifier(&dev->freq_transition,
608                                          CPUFREQ_TRANSITION_NOTIFIER);
609 }
610
611 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
612 {
613         cpufreq_unregister_notifier(&dev->freq_transition,
614                                     CPUFREQ_TRANSITION_NOTIFIER);
615 }
616 #else
617 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
618 {
619         return 0;
620 }
621
622 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
623 {
624 }
625 #endif
626
627 static struct i2c_algorithm i2c_davinci_algo = {
628         .master_xfer    = i2c_davinci_xfer,
629         .functionality  = i2c_davinci_func,
630 };
631
632 static int davinci_i2c_probe(struct platform_device *pdev)
633 {
634         struct davinci_i2c_dev *dev;
635         struct i2c_adapter *adap;
636         struct resource *mem, *irq, *ioarea;
637         int r;
638
639         /* NOTE: driver uses the static register mapping */
640         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641         if (!mem) {
642                 dev_err(&pdev->dev, "no mem resource?\n");
643                 return -ENODEV;
644         }
645
646         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
647         if (!irq) {
648                 dev_err(&pdev->dev, "no irq resource?\n");
649                 return -ENODEV;
650         }
651
652         ioarea = request_mem_region(mem->start, resource_size(mem),
653                                     pdev->name);
654         if (!ioarea) {
655                 dev_err(&pdev->dev, "I2C region already claimed\n");
656                 return -EBUSY;
657         }
658
659         dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
660         if (!dev) {
661                 r = -ENOMEM;
662                 goto err_release_region;
663         }
664
665         init_completion(&dev->cmd_complete);
666 #ifdef CONFIG_CPU_FREQ
667         init_completion(&dev->xfr_complete);
668 #endif
669         dev->dev = get_device(&pdev->dev);
670         dev->irq = irq->start;
671         platform_set_drvdata(pdev, dev);
672
673         dev->clk = clk_get(&pdev->dev, NULL);
674         if (IS_ERR(dev->clk)) {
675                 r = -ENODEV;
676                 goto err_free_mem;
677         }
678         clk_enable(dev->clk);
679
680         dev->base = ioremap(mem->start, resource_size(mem));
681         if (!dev->base) {
682                 r = -EBUSY;
683                 goto err_mem_ioremap;
684         }
685
686         i2c_davinci_init(dev);
687
688         r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
689         if (r) {
690                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
691                 goto err_unuse_clocks;
692         }
693
694         r = i2c_davinci_cpufreq_register(dev);
695         if (r) {
696                 dev_err(&pdev->dev, "failed to register cpufreq\n");
697                 goto err_free_irq;
698         }
699
700         adap = &dev->adapter;
701         i2c_set_adapdata(adap, dev);
702         adap->owner = THIS_MODULE;
703         adap->class = I2C_CLASS_HWMON;
704         strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
705         adap->algo = &i2c_davinci_algo;
706         adap->dev.parent = &pdev->dev;
707         adap->timeout = DAVINCI_I2C_TIMEOUT;
708
709         adap->nr = pdev->id;
710         r = i2c_add_numbered_adapter(adap);
711         if (r) {
712                 dev_err(&pdev->dev, "failure adding adapter\n");
713                 goto err_free_irq;
714         }
715
716         return 0;
717
718 err_free_irq:
719         free_irq(dev->irq, dev);
720 err_unuse_clocks:
721         iounmap(dev->base);
722 err_mem_ioremap:
723         clk_disable(dev->clk);
724         clk_put(dev->clk);
725         dev->clk = NULL;
726 err_free_mem:
727         platform_set_drvdata(pdev, NULL);
728         put_device(&pdev->dev);
729         kfree(dev);
730 err_release_region:
731         release_mem_region(mem->start, resource_size(mem));
732
733         return r;
734 }
735
736 static int davinci_i2c_remove(struct platform_device *pdev)
737 {
738         struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
739         struct resource *mem;
740
741         i2c_davinci_cpufreq_deregister(dev);
742
743         platform_set_drvdata(pdev, NULL);
744         i2c_del_adapter(&dev->adapter);
745         put_device(&pdev->dev);
746
747         clk_disable(dev->clk);
748         clk_put(dev->clk);
749         dev->clk = NULL;
750
751         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
752         free_irq(IRQ_I2C, dev);
753         iounmap(dev->base);
754         kfree(dev);
755
756         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
757         release_mem_region(mem->start, resource_size(mem));
758         return 0;
759 }
760
761 #ifdef CONFIG_PM
762 static int davinci_i2c_suspend(struct device *dev)
763 {
764         struct platform_device *pdev = to_platform_device(dev);
765         struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
766
767         /* put I2C into reset */
768         davinci_i2c_reset_ctrl(i2c_dev, 0);
769         clk_disable(i2c_dev->clk);
770
771         return 0;
772 }
773
774 static int davinci_i2c_resume(struct device *dev)
775 {
776         struct platform_device *pdev = to_platform_device(dev);
777         struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
778
779         clk_enable(i2c_dev->clk);
780         /* take I2C out of reset */
781         davinci_i2c_reset_ctrl(i2c_dev, 1);
782
783         return 0;
784 }
785
786 static const struct dev_pm_ops davinci_i2c_pm = {
787         .suspend        = davinci_i2c_suspend,
788         .resume         = davinci_i2c_resume,
789 };
790
791 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
792 #else
793 #define davinci_i2c_pm_ops NULL
794 #endif
795
796 /* work with hotplug and coldplug */
797 MODULE_ALIAS("platform:i2c_davinci");
798
799 static struct platform_driver davinci_i2c_driver = {
800         .probe          = davinci_i2c_probe,
801         .remove         = davinci_i2c_remove,
802         .driver         = {
803                 .name   = "i2c_davinci",
804                 .owner  = THIS_MODULE,
805                 .pm     = davinci_i2c_pm_ops,
806         },
807 };
808
809 /* I2C may be needed to bring up other drivers */
810 static int __init davinci_i2c_init_driver(void)
811 {
812         return platform_driver_register(&davinci_i2c_driver);
813 }
814 subsys_initcall(davinci_i2c_init_driver);
815
816 static void __exit davinci_i2c_exit_driver(void)
817 {
818         platform_driver_unregister(&davinci_i2c_driver);
819 }
820 module_exit(davinci_i2c_exit_driver);
821
822 MODULE_AUTHOR("Texas Instruments India");
823 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
824 MODULE_LICENSE("GPL");