drivers/i2c/busses/i2c-at91.c

   1 /*
   2  *  i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
   3  *
   4  *  Copyright (C) 2011 Weinmann Medical GmbH
   5  *  Author: Nikolaus Voss <n.voss@weinmann.de>
   6  *
   7  *  Evolved from original work by:
   8  *  Copyright (C) 2004 Rick Bronson
   9  *  Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
  10  *
  11  *  Borrowed heavily from original work by:
  12  *  Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License as published by
  16  *  the Free Software Foundation; either version 2 of the License, or
  17  *  (at your option) any later version.
  18  */
  19
  20 #include <linux/clk.h>
  21 #include <linux/completion.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/err.h>
  25 #include <linux/i2c.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/slab.h>
  33 #include <linux/platform_data/dma-atmel.h>
  34
  35 #define DEFAULT_TWI_CLK_HZ              100000          /* max 400 Kbits/s */
  36 #define AT91_I2C_TIMEOUT        msecs_to_jiffies(100)   /* transfer timeout */
  37 #define AT91_I2C_DMA_THRESHOLD  8                       /* enable DMA if transfer size is bigger than this threshold */
  38
  39 /* AT91 TWI register definitions */
  40 #define AT91_TWI_CR             0x0000  /* Control Register */
  41 #define AT91_TWI_START          0x0001  /* Send a Start Condition */
  42 #define AT91_TWI_STOP           0x0002  /* Send a Stop Condition */
  43 #define AT91_TWI_MSEN           0x0004  /* Master Transfer Enable */
  44 #define AT91_TWI_SVDIS          0x0020  /* Slave Transfer Disable */
  45 #define AT91_TWI_QUICK          0x0040  /* SMBus quick command */
  46 #define AT91_TWI_SWRST          0x0080  /* Software Reset */
  47
  48 #define AT91_TWI_MMR            0x0004  /* Master Mode Register */
  49 #define AT91_TWI_IADRSZ_1       0x0100  /* Internal Device Address Size */
  50 #define AT91_TWI_MREAD          0x1000  /* Master Read Direction */
  51
  52 #define AT91_TWI_IADR           0x000c  /* Internal Address Register */
  53
  54 #define AT91_TWI_CWGR           0x0010  /* Clock Waveform Generator Reg */
  55
  56 #define AT91_TWI_SR             0x0020  /* Status Register */
  57 #define AT91_TWI_TXCOMP         0x0001  /* Transmission Complete */
  58 #define AT91_TWI_RXRDY          0x0002  /* Receive Holding Register Ready */
  59 #define AT91_TWI_TXRDY          0x0004  /* Transmit Holding Register Ready */
  60
  61 #define AT91_TWI_OVRE           0x0040  /* Overrun Error */
  62 #define AT91_TWI_UNRE           0x0080  /* Underrun Error */
  63 #define AT91_TWI_NACK           0x0100  /* Not Acknowledged */
  64
  65 #define AT91_TWI_IER            0x0024  /* Interrupt Enable Register */
  66 #define AT91_TWI_IDR            0x0028  /* Interrupt Disable Register */
  67 #define AT91_TWI_IMR            0x002c  /* Interrupt Mask Register */
  68 #define AT91_TWI_RHR            0x0030  /* Receive Holding Register */
  69 #define AT91_TWI_THR            0x0034  /* Transmit Holding Register */
  70
  71 struct at91_twi_pdata {
  72         unsigned clk_max_div;
  73         unsigned clk_offset;
  74         bool has_unre_flag;
  75         bool has_dma_support;
  76         struct at_dma_slave dma_slave;
  77 };
  78
  79 struct at91_twi_dma {
  80         struct dma_chan *chan_rx;
  81         struct dma_chan *chan_tx;
  82         struct scatterlist sg;
  83         struct dma_async_tx_descriptor *data_desc;
  84         enum dma_data_direction direction;
  85         bool buf_mapped;
  86         bool xfer_in_progress;
  87 };
  88
  89 struct at91_twi_dev {
  90         struct device *dev;
  91         void __iomem *base;
  92         struct completion cmd_complete;
  93         struct clk *clk;
  94         u8 *buf;
  95         size_t buf_len;
  96         struct i2c_msg *msg;
  97         int irq;
  98         unsigned imr;
  99         unsigned transfer_status;
 100         struct i2c_adapter adapter;
 101         unsigned twi_cwgr_reg;
 102         struct at91_twi_pdata *pdata;
 103         bool use_dma;
 104         bool recv_len_abort;
 105         struct at91_twi_dma dma;
 106 };
 107
 108 static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
 109 {
 110         return readl_relaxed(dev->base + reg);
 111 }
 112
 113 static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
 114 {
 115         writel_relaxed(val, dev->base + reg);
 116 }
 117
 118 static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
 119 {
 120         at91_twi_write(dev, AT91_TWI_IDR,
 121                        AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY);
 122 }
 123
 124 static void at91_twi_irq_save(struct at91_twi_dev *dev)
 125 {
 126         dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & 0x7;
 127         at91_disable_twi_interrupts(dev);
 128 }
 129
 130 static void at91_twi_irq_restore(struct at91_twi_dev *dev)
 131 {
 132         at91_twi_write(dev, AT91_TWI_IER, dev->imr);
 133 }
 134
 135 static void at91_init_twi_bus(struct at91_twi_dev *dev)
 136 {
 137         at91_disable_twi_interrupts(dev);
 138         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
 139         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
 140         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
 141         at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
 142 }
 143
 144 /*
 145  * Calculate symmetric clock as stated in datasheet:
 146  * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
 147  */
 148 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 149 {
 150         int ckdiv, cdiv, div;
 151         struct at91_twi_pdata *pdata = dev->pdata;
 152         int offset = pdata->clk_offset;
 153         int max_ckdiv = pdata->clk_max_div;
 154
 155         div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
 156                                        2 * twi_clk) - offset);
 157         ckdiv = fls(div >> 8);
 158         cdiv = div >> ckdiv;
 159
 160         if (ckdiv > max_ckdiv) {
 161                 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
 162                          ckdiv, max_ckdiv);
 163                 ckdiv = max_ckdiv;
 164                 cdiv = 255;
 165         }
 166
 167         dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
 168         dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
 169 }
 170
 171 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
 172 {
 173         struct at91_twi_dma *dma = &dev->dma;
 174
 175         at91_twi_irq_save(dev);
 176
 177         if (dma->xfer_in_progress) {
 178                 if (dma->direction == DMA_FROM_DEVICE)
 179                         dmaengine_terminate_all(dma->chan_rx);
 180                 else
 181                         dmaengine_terminate_all(dma->chan_tx);
 182                 dma->xfer_in_progress = false;
 183         }
 184         if (dma->buf_mapped) {
 185                 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg),
 186                                  dev->buf_len, dma->direction);
 187                 dma->buf_mapped = false;
 188         }
 189
 190         at91_twi_irq_restore(dev);
 191 }
 192
 193 static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
 194 {
 195         if (dev->buf_len <= 0)
 196                 return;
 197
 198         at91_twi_write(dev, AT91_TWI_THR, *dev->buf);
 199
 200         /* send stop when last byte has been written */
 201         if (--dev->buf_len == 0)
 202                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
 203
 204         dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
 205
 206         ++dev->buf;
 207 }
 208
 209 static void at91_twi_write_data_dma_callback(void *data)
 210 {
 211         struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
 212
 213         dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
 214                          dev->buf_len, DMA_TO_DEVICE);
 215
 216         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
 217 }
 218
 219 static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
 220 {
 221         dma_addr_t dma_addr;
 222         struct dma_async_tx_descriptor *txdesc;
 223         struct at91_twi_dma *dma = &dev->dma;
 224         struct dma_chan *chan_tx = dma->chan_tx;
 225
 226         if (dev->buf_len <= 0)
 227                 return;
 228
 229         dma->direction = DMA_TO_DEVICE;
 230
 231         at91_twi_irq_save(dev);
 232         dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
 233                                   DMA_TO_DEVICE);
 234         if (dma_mapping_error(dev->dev, dma_addr)) {
 235                 dev_err(dev->dev, "dma map failed\n");
 236                 return;
 237         }
 238         dma->buf_mapped = true;
 239         at91_twi_irq_restore(dev);
 240         sg_dma_len(&dma->sg) = dev->buf_len;
 241         sg_dma_address(&dma->sg) = dma_addr;
 242
 243         txdesc = dmaengine_prep_slave_sg(chan_tx, &dma->sg, 1, DMA_MEM_TO_DEV,
 244                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 245         if (!txdesc) {
 246                 dev_err(dev->dev, "dma prep slave sg failed\n");
 247                 goto error;
 248         }
 249
 250         txdesc->callback = at91_twi_write_data_dma_callback;
 251         txdesc->callback_param = dev;
 252
 253         dma->xfer_in_progress = true;
 254         dmaengine_submit(txdesc);
 255         dma_async_issue_pending(chan_tx);
 256
 257         return;
 258
 259 error:
 260         at91_twi_dma_cleanup(dev);
 261 }
 262
 263 static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
 264 {
 265         if (dev->buf_len <= 0)
 266                 return;
 267
 268         *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff;
 269         --dev->buf_len;
 270
 271         /* return if aborting, we only needed to read RHR to clear RXRDY*/
 272         if (dev->recv_len_abort)
 273                 return;
 274
 275         /* handle I2C_SMBUS_BLOCK_DATA */
 276         if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
 277                 /* ensure length byte is a valid value */
 278                 if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) {
 279                         dev->msg->flags &= ~I2C_M_RECV_LEN;
 280                         dev->buf_len += *dev->buf;
 281                         dev->msg->len = dev->buf_len + 1;
 282                         dev_dbg(dev->dev, "received block length %d\n",
 283                                          dev->buf_len);
 284                 } else {
 285                         /* abort and send the stop by reading one more byte */
 286                         dev->recv_len_abort = true;
 287                         dev->buf_len = 1;
 288                 }
 289         }
 290
 291         /* send stop if second but last byte has been read */
 292         if (dev->buf_len == 1)
 293                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
 294
 295         dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
 296
 297         ++dev->buf;
 298 }
 299
 300 static void at91_twi_read_data_dma_callback(void *data)
 301 {
 302         struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
 303
 304         dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
 305                          dev->buf_len, DMA_FROM_DEVICE);
 306
 307         /* The last two bytes have to be read without using dma */
 308         dev->buf += dev->buf_len - 2;
 309         dev->buf_len = 2;
 310         at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_RXRDY);
 311 }
 312
 313 static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
 314 {
 315         dma_addr_t dma_addr;
 316         struct dma_async_tx_descriptor *rxdesc;
 317         struct at91_twi_dma *dma = &dev->dma;
 318         struct dma_chan *chan_rx = dma->chan_rx;
 319
 320         dma->direction = DMA_FROM_DEVICE;
 321
 322         /* Keep in mind that we won't use dma to read the last two bytes */
 323         at91_twi_irq_save(dev);
 324         dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len - 2,
 325                                   DMA_FROM_DEVICE);
 326         if (dma_mapping_error(dev->dev, dma_addr)) {
 327                 dev_err(dev->dev, "dma map failed\n");
 328                 return;
 329         }
 330         dma->buf_mapped = true;
 331         at91_twi_irq_restore(dev);
 332         dma->sg.dma_address = dma_addr;
 333         sg_dma_len(&dma->sg) = dev->buf_len - 2;
 334
 335         rxdesc = dmaengine_prep_slave_sg(chan_rx, &dma->sg, 1, DMA_DEV_TO_MEM,
 336                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 337         if (!rxdesc) {
 338                 dev_err(dev->dev, "dma prep slave sg failed\n");
 339                 goto error;
 340         }
 341
 342         rxdesc->callback = at91_twi_read_data_dma_callback;
 343         rxdesc->callback_param = dev;
 344
 345         dma->xfer_in_progress = true;
 346         dmaengine_submit(rxdesc);
 347         dma_async_issue_pending(dma->chan_rx);
 348
 349         return;
 350
 351 error:
 352         at91_twi_dma_cleanup(dev);
 353 }
 354
 355 static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
 356 {
 357         struct at91_twi_dev *dev = dev_id;
 358         const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
 359         const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
 360
 361         if (!irqstatus)
 362                 return IRQ_NONE;
 363         else if (irqstatus & AT91_TWI_RXRDY)
 364                 at91_twi_read_next_byte(dev);
 365         else if (irqstatus & AT91_TWI_TXRDY)
 366                 at91_twi_write_next_byte(dev);
 367
 368         /* catch error flags */
 369         dev->transfer_status |= status;
 370
 371         if (irqstatus & AT91_TWI_TXCOMP) {
 372                 at91_disable_twi_interrupts(dev);
 373                 complete(&dev->cmd_complete);
 374         }
 375
 376         return IRQ_HANDLED;
 377 }
 378
 379 static int at91_do_twi_transfer(struct at91_twi_dev *dev)
 380 {
 381         int ret;
 382         bool has_unre_flag = dev->pdata->has_unre_flag;
 383
 384         dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
 385                 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
 386
 387         reinit_completion(&dev->cmd_complete);
 388         dev->transfer_status = 0;
 389
 390         if (!dev->buf_len) {
 391                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
 392                 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
 393         } else if (dev->msg->flags & I2C_M_RD) {
 394                 unsigned start_flags = AT91_TWI_START;
 395
 396                 if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
 397                         dev_err(dev->dev, "RXRDY still set!");
 398                         at91_twi_read(dev, AT91_TWI_RHR);
 399                 }
 400
 401                 /* if only one byte is to be read, immediately stop transfer */
 402                 if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
 403                         start_flags |= AT91_TWI_STOP;
 404                 at91_twi_write(dev, AT91_TWI_CR, start_flags);
 405                 /*
 406                  * When using dma, the last byte has to be read manually in
 407                  * order to not send the stop command too late and then
 408                  * to receive extra data. In practice, there are some issues
 409                  * if you use the dma to read n-1 bytes because of latency.
 410                  * Reading n-2 bytes with dma and the two last ones manually
 411                  * seems to be the best solution.
 412                  */
 413                 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
 414                         at91_twi_read_data_dma(dev);
 415                         /*
 416                          * It is important to enable TXCOMP irq here because
 417                          * doing it only when transferring the last two bytes
 418                          * will mask NACK errors since TXCOMP is set when a
 419                          * NACK occurs.
 420                          */
 421                         at91_twi_write(dev, AT91_TWI_IER,
 422                                AT91_TWI_TXCOMP);
 423                 } else
 424                         at91_twi_write(dev, AT91_TWI_IER,
 425                                AT91_TWI_TXCOMP | AT91_TWI_RXRDY);
 426         } else {
 427                 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
 428                         at91_twi_write_data_dma(dev);
 429                         at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
 430                 } else {
 431                         at91_twi_write_next_byte(dev);
 432                         at91_twi_write(dev, AT91_TWI_IER,
 433                                 AT91_TWI_TXCOMP | AT91_TWI_TXRDY);
 434                 }
 435         }
 436
 437         ret = wait_for_completion_io_timeout(&dev->cmd_complete,
 438                                              dev->adapter.timeout);
 439         if (ret == 0) {
 440                 dev_err(dev->dev, "controller timed out\n");
 441                 at91_init_twi_bus(dev);
 442                 ret = -ETIMEDOUT;
 443                 goto error;
 444         }
 445         if (dev->transfer_status & AT91_TWI_NACK) {
 446                 dev_dbg(dev->dev, "received nack\n");
 447                 ret = -EREMOTEIO;
 448                 goto error;
 449         }
 450         if (dev->transfer_status & AT91_TWI_OVRE) {
 451                 dev_err(dev->dev, "overrun while reading\n");
 452                 ret = -EIO;
 453                 goto error;
 454         }
 455         if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
 456                 dev_err(dev->dev, "underrun while writing\n");
 457                 ret = -EIO;
 458                 goto error;
 459         }
 460         if (dev->recv_len_abort) {
 461                 dev_err(dev->dev, "invalid smbus block length recvd\n");
 462                 ret = -EPROTO;
 463                 goto error;
 464         }
 465
 466         dev_dbg(dev->dev, "transfer complete\n");
 467
 468         return 0;
 469
 470 error:
 471         at91_twi_dma_cleanup(dev);
 472         return ret;
 473 }
 474
 475 static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
 476 {
 477         struct at91_twi_dev *dev = i2c_get_adapdata(adap);
 478         int ret;
 479         unsigned int_addr_flag = 0;
 480         struct i2c_msg *m_start = msg;
 481
 482         dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
 483
 484         /*
 485          * The hardware can handle at most two messages concatenated by a
 486          * repeated start via it's internal address feature.
 487          */
 488         if (num > 2) {
 489                 dev_err(dev->dev,
 490                         "cannot handle more than two concatenated messages.\n");
 491                 return 0;
 492         } else if (num == 2) {
 493                 int internal_address = 0;
 494                 int i;
 495
 496                 if (msg->flags & I2C_M_RD) {
 497                         dev_err(dev->dev, "first transfer must be write.\n");
 498                         return -EINVAL;
 499                 }
 500                 if (msg->len > 3) {
 501                         dev_err(dev->dev, "first message size must be <= 3.\n");
 502                         return -EINVAL;
 503                 }
 504
 505                 /* 1st msg is put into the internal address, start with 2nd */
 506                 m_start = &msg[1];
 507                 for (i = 0; i < msg->len; ++i) {
 508                         const unsigned addr = msg->buf[msg->len - 1 - i];
 509
 510                         internal_address |= addr << (8 * i);
 511                         int_addr_flag += AT91_TWI_IADRSZ_1;
 512                 }
 513                 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
 514         }
 515
 516         at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag
 517                        | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
 518
 519         dev->buf_len = m_start->len;
 520         dev->buf = m_start->buf;
 521         dev->msg = m_start;
 522         dev->recv_len_abort = false;
 523
 524         ret = at91_do_twi_transfer(dev);
 525
 526         return (ret < 0) ? ret : num;
 527 }
 528
 529 static u32 at91_twi_func(struct i2c_adapter *adapter)
 530 {
 531         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 532                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
 533 }
 534
 535 static struct i2c_algorithm at91_twi_algorithm = {
 536         .master_xfer    = at91_twi_xfer,
 537         .functionality  = at91_twi_func,
 538 };
 539
 540 static struct at91_twi_pdata at91rm9200_config = {
 541         .clk_max_div = 5,
 542         .clk_offset = 3,
 543         .has_unre_flag = true,
 544         .has_dma_support = false,
 545 };
 546
 547 static struct at91_twi_pdata at91sam9261_config = {
 548         .clk_max_div = 5,
 549         .clk_offset = 4,
 550         .has_unre_flag = false,
 551         .has_dma_support = false,
 552 };
 553
 554 static struct at91_twi_pdata at91sam9260_config = {
 555         .clk_max_div = 7,
 556         .clk_offset = 4,
 557         .has_unre_flag = false,
 558         .has_dma_support = false,
 559 };
 560
 561 static struct at91_twi_pdata at91sam9g20_config = {
 562         .clk_max_div = 7,
 563         .clk_offset = 4,
 564         .has_unre_flag = false,
 565         .has_dma_support = false,
 566 };
 567
 568 static struct at91_twi_pdata at91sam9g10_config = {
 569         .clk_max_div = 7,
 570         .clk_offset = 4,
 571         .has_unre_flag = false,
 572         .has_dma_support = false,
 573 };
 574
 575 static const struct platform_device_id at91_twi_devtypes[] = {
 576         {
 577                 .name = "i2c-at91rm9200",
 578                 .driver_data = (unsigned long) &at91rm9200_config,
 579         }, {
 580                 .name = "i2c-at91sam9261",
 581                 .driver_data = (unsigned long) &at91sam9261_config,
 582         }, {
 583                 .name = "i2c-at91sam9260",
 584                 .driver_data = (unsigned long) &at91sam9260_config,
 585         }, {
 586                 .name = "i2c-at91sam9g20",
 587                 .driver_data = (unsigned long) &at91sam9g20_config,
 588         }, {
 589                 .name = "i2c-at91sam9g10",
 590                 .driver_data = (unsigned long) &at91sam9g10_config,
 591         }, {
 592                 /* sentinel */
 593         }
 594 };
 595
 596 #if defined(CONFIG_OF)
 597 static struct at91_twi_pdata at91sam9x5_config = {
 598         .clk_max_div = 7,
 599         .clk_offset = 4,
 600         .has_unre_flag = false,
 601         .has_dma_support = true,
 602 };
 603
 604 static const struct of_device_id atmel_twi_dt_ids[] = {
 605         {
 606                 .compatible = "atmel,at91rm9200-i2c",
 607                 .data = &at91rm9200_config,
 608         } , {
 609                 .compatible = "atmel,at91sam9260-i2c",
 610                 .data = &at91sam9260_config,
 611         } , {
 612                 .compatible = "atmel,at91sam9261-i2c",
 613                 .data = &at91sam9261_config,
 614         } , {
 615                 .compatible = "atmel,at91sam9g20-i2c",
 616                 .data = &at91sam9g20_config,
 617         } , {
 618                 .compatible = "atmel,at91sam9g10-i2c",
 619                 .data = &at91sam9g10_config,
 620         }, {
 621                 .compatible = "atmel,at91sam9x5-i2c",
 622                 .data = &at91sam9x5_config,
 623         }, {
 624                 /* sentinel */
 625         }
 626 };
 627 MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
 628 #endif
 629
 630 static bool filter(struct dma_chan *chan, void *pdata)
 631 {
 632         struct at91_twi_pdata *sl_pdata = pdata;
 633         struct at_dma_slave *sl;
 634
 635         if (!sl_pdata)
 636                 return false;
 637
 638         sl = &sl_pdata->dma_slave;
 639         if (sl && (sl->dma_dev == chan->device->dev)) {
 640                 chan->private = sl;
 641                 return true;
 642         } else {
 643                 return false;
 644         }
 645 }
 646
 647 static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
 648 {
 649         int ret = 0;
 650         struct at91_twi_pdata *pdata = dev->pdata;
 651         struct dma_slave_config slave_config;
 652         struct at91_twi_dma *dma = &dev->dma;
 653         dma_cap_mask_t mask;
 654
 655         memset(&slave_config, 0, sizeof(slave_config));
 656         slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
 657         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 658         slave_config.src_maxburst = 1;
 659         slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
 660         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 661         slave_config.dst_maxburst = 1;
 662         slave_config.device_fc = false;
 663
 664         dma_cap_zero(mask);
 665         dma_cap_set(DMA_SLAVE, mask);
 666
 667         dma->chan_tx = dma_request_slave_channel_compat(mask, filter, pdata,
 668                                                         dev->dev, "tx");
 669         if (!dma->chan_tx) {
 670                 dev_err(dev->dev, "can't get a DMA channel for tx\n");
 671                 ret = -EBUSY;
 672                 goto error;
 673         }
 674
 675         dma->chan_rx = dma_request_slave_channel_compat(mask, filter, pdata,
 676                                                         dev->dev, "rx");
 677         if (!dma->chan_rx) {
 678                 dev_err(dev->dev, "can't get a DMA channel for rx\n");
 679                 ret = -EBUSY;
 680                 goto error;
 681         }
 682
 683         slave_config.direction = DMA_MEM_TO_DEV;
 684         if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
 685                 dev_err(dev->dev, "failed to configure tx channel\n");
 686                 ret = -EINVAL;
 687                 goto error;
 688         }
 689
 690         slave_config.direction = DMA_DEV_TO_MEM;
 691         if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
 692                 dev_err(dev->dev, "failed to configure rx channel\n");
 693                 ret = -EINVAL;
 694                 goto error;
 695         }
 696
 697         sg_init_table(&dma->sg, 1);
 698         dma->buf_mapped = false;
 699         dma->xfer_in_progress = false;
 700
 701         dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 702                  dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 703
 704         return ret;
 705
 706 error:
 707         dev_info(dev->dev, "can't use DMA\n");
 708         if (dma->chan_rx)
 709                 dma_release_channel(dma->chan_rx);
 710         if (dma->chan_tx)
 711                 dma_release_channel(dma->chan_tx);
 712         return ret;
 713 }
 714
 715 static struct at91_twi_pdata *at91_twi_get_driver_data(
 716                                         struct platform_device *pdev)
 717 {
 718         if (pdev->dev.of_node) {
 719                 const struct of_device_id *match;
 720                 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
 721                 if (!match)
 722                         return NULL;
 723                 return (struct at91_twi_pdata *)match->data;
 724         }
 725         return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
 726 }
 727
 728 static int at91_twi_probe(struct platform_device *pdev)
 729 {
 730         struct at91_twi_dev *dev;
 731         struct resource *mem;
 732         int rc;
 733         u32 phy_addr;
 734         u32 bus_clk_rate;
 735
 736         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 737         if (!dev)
 738                 return -ENOMEM;
 739         init_completion(&dev->cmd_complete);
 740         dev->dev = &pdev->dev;
 741
 742         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 743         if (!mem)
 744                 return -ENODEV;
 745         phy_addr = mem->start;
 746
 747         dev->pdata = at91_twi_get_driver_data(pdev);
 748         if (!dev->pdata)
 749                 return -ENODEV;
 750
 751         dev->base = devm_ioremap_resource(&pdev->dev, mem);
 752         if (IS_ERR(dev->base))
 753                 return PTR_ERR(dev->base);
 754
 755         dev->irq = platform_get_irq(pdev, 0);
 756         if (dev->irq < 0)
 757                 return dev->irq;
 758
 759         rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
 760                          dev_name(dev->dev), dev);
 761         if (rc) {
 762                 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
 763                 return rc;
 764         }
 765
 766         platform_set_drvdata(pdev, dev);
 767
 768         dev->clk = devm_clk_get(dev->dev, NULL);
 769         if (IS_ERR(dev->clk)) {
 770                 dev_err(dev->dev, "no clock defined\n");
 771                 return -ENODEV;
 772         }
 773         clk_prepare_enable(dev->clk);
 774
 775         if (dev->pdata->has_dma_support) {
 776                 if (at91_twi_configure_dma(dev, phy_addr) == 0)
 777                         dev->use_dma = true;
 778         }
 779
 780         rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
 781                         &bus_clk_rate);
 782         if (rc)
 783                 bus_clk_rate = DEFAULT_TWI_CLK_HZ;
 784
 785         at91_calc_twi_clock(dev, bus_clk_rate);
 786         at91_init_twi_bus(dev);
 787
 788         snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
 789         i2c_set_adapdata(&dev->adapter, dev);
 790         dev->adapter.owner = THIS_MODULE;
 791         dev->adapter.class = I2C_CLASS_DEPRECATED;
 792         dev->adapter.algo = &at91_twi_algorithm;
 793         dev->adapter.dev.parent = dev->dev;
 794         dev->adapter.nr = pdev->id;
 795         dev->adapter.timeout = AT91_I2C_TIMEOUT;
 796         dev->adapter.dev.of_node = pdev->dev.of_node;
 797
 798         rc = i2c_add_numbered_adapter(&dev->adapter);
 799         if (rc) {
 800                 dev_err(dev->dev, "Adapter %s registration failed\n",
 801                         dev->adapter.name);
 802                 clk_disable_unprepare(dev->clk);
 803                 return rc;
 804         }
 805
 806         dev_info(dev->dev, "AT91 i2c bus driver.\n");
 807         return 0;
 808 }
 809
 810 static int at91_twi_remove(struct platform_device *pdev)
 811 {
 812         struct at91_twi_dev *dev = platform_get_drvdata(pdev);
 813
 814         i2c_del_adapter(&dev->adapter);
 815         clk_disable_unprepare(dev->clk);
 816
 817         return 0;
 818 }
 819
 820 #ifdef CONFIG_PM
 821
 822 static int at91_twi_runtime_suspend(struct device *dev)
 823 {
 824         struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
 825
 826         clk_disable(twi_dev->clk);
 827
 828         return 0;
 829 }
 830
 831 static int at91_twi_runtime_resume(struct device *dev)
 832 {
 833         struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
 834
 835         return clk_enable(twi_dev->clk);
 836 }
 837
 838 static const struct dev_pm_ops at91_twi_pm = {
 839         .runtime_suspend        = at91_twi_runtime_suspend,
 840         .runtime_resume         = at91_twi_runtime_resume,
 841 };
 842
 843 #define at91_twi_pm_ops (&at91_twi_pm)
 844 #else
 845 #define at91_twi_pm_ops NULL
 846 #endif
 847
 848 static struct platform_driver at91_twi_driver = {
 849         .probe          = at91_twi_probe,
 850         .remove         = at91_twi_remove,
 851         .id_table       = at91_twi_devtypes,
 852         .driver         = {
 853                 .name   = "at91_i2c",
 854                 .owner  = THIS_MODULE,
 855                 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
 856                 .pm     = at91_twi_pm_ops,
 857         },
 858 };
 859
 860 static int __init at91_twi_init(void)
 861 {
 862         return platform_driver_register(&at91_twi_driver);
 863 }
 864
 865 static void __exit at91_twi_exit(void)
 866 {
 867         platform_driver_unregister(&at91_twi_driver);
 868 }
 869
 870 subsys_initcall(at91_twi_init);
 871 module_exit(at91_twi_exit);
 872
 873 MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
 874 MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
 875 MODULE_LICENSE("GPL");
 876 MODULE_ALIAS("platform:at91_i2c");