drivers/gpu/host1x/dev.c

   1 /*
   2  * Tegra host1x driver
   3  *
   4  * Copyright (c) 2010-2013, NVIDIA Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of.h>
  26 #include <linux/slab.h>
  27
  28 #define CREATE_TRACE_POINTS
  29 #include <trace/events/host1x.h>
  30 #undef CREATE_TRACE_POINTS
  31
  32 #include "bus.h"
  33 #include "channel.h"
  34 #include "debug.h"
  35 #include "dev.h"
  36 #include "intr.h"
  37
  38 #include "hw/host1x01.h"
  39 #include "hw/host1x02.h"
  40 #include "hw/host1x04.h"
  41 #include "hw/host1x05.h"
  42
  43 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
  44 {
  45         void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  46
  47         writel(v, sync_regs + r);
  48 }
  49
  50 u32 host1x_sync_readl(struct host1x *host1x, u32 r)
  51 {
  52         void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  53
  54         return readl(sync_regs + r);
  55 }
  56
  57 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
  58 {
  59         writel(v, ch->regs + r);
  60 }
  61
  62 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
  63 {
  64         return readl(ch->regs + r);
  65 }
  66
  67 static const struct host1x_info host1x01_info = {
  68         .nb_channels = 8,
  69         .nb_pts = 32,
  70         .nb_mlocks = 16,
  71         .nb_bases = 8,
  72         .init = host1x01_init,
  73         .sync_offset = 0x3000,
  74         .dma_mask = DMA_BIT_MASK(32),
  75 };
  76
  77 static const struct host1x_info host1x02_info = {
  78         .nb_channels = 9,
  79         .nb_pts = 32,
  80         .nb_mlocks = 16,
  81         .nb_bases = 12,
  82         .init = host1x02_init,
  83         .sync_offset = 0x3000,
  84         .dma_mask = DMA_BIT_MASK(32),
  85 };
  86
  87 static const struct host1x_info host1x04_info = {
  88         .nb_channels = 12,
  89         .nb_pts = 192,
  90         .nb_mlocks = 16,
  91         .nb_bases = 64,
  92         .init = host1x04_init,
  93         .sync_offset = 0x2100,
  94         .dma_mask = DMA_BIT_MASK(34),
  95 };
  96
  97 static const struct host1x_info host1x05_info = {
  98         .nb_channels = 14,
  99         .nb_pts = 192,
 100         .nb_mlocks = 16,
 101         .nb_bases = 64,
 102         .init = host1x05_init,
 103         .sync_offset = 0x2100,
 104         .dma_mask = DMA_BIT_MASK(34),
 105 };
 106
 107 static const struct of_device_id host1x_of_match[] = {
 108         { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
 109         { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
 110         { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
 111         { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
 112         { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
 113         { },
 114 };
 115 MODULE_DEVICE_TABLE(of, host1x_of_match);
 116
 117 static int host1x_probe(struct platform_device *pdev)
 118 {
 119         const struct of_device_id *id;
 120         struct host1x *host;
 121         struct resource *regs;
 122         int syncpt_irq;
 123         int err;
 124
 125         id = of_match_device(host1x_of_match, &pdev->dev);
 126         if (!id)
 127                 return -EINVAL;
 128
 129         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 130         if (!regs) {
 131                 dev_err(&pdev->dev, "failed to get registers\n");
 132                 return -ENXIO;
 133         }
 134
 135         syncpt_irq = platform_get_irq(pdev, 0);
 136         if (syncpt_irq < 0) {
 137                 dev_err(&pdev->dev, "failed to get IRQ\n");
 138                 return -ENXIO;
 139         }
 140
 141         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 142         if (!host)
 143                 return -ENOMEM;
 144
 145         mutex_init(&host->devices_lock);
 146         INIT_LIST_HEAD(&host->devices);
 147         INIT_LIST_HEAD(&host->list);
 148         host->dev = &pdev->dev;
 149         host->info = id->data;
 150
 151         /* set common host1x device data */
 152         platform_set_drvdata(pdev, host);
 153
 154         host->regs = devm_ioremap_resource(&pdev->dev, regs);
 155         if (IS_ERR(host->regs))
 156                 return PTR_ERR(host->regs);
 157
 158         dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
 159
 160         if (host->info->init) {
 161                 err = host->info->init(host);
 162                 if (err)
 163                         return err;
 164         }
 165
 166         host->clk = devm_clk_get(&pdev->dev, NULL);
 167         if (IS_ERR(host->clk)) {
 168                 dev_err(&pdev->dev, "failed to get clock\n");
 169                 err = PTR_ERR(host->clk);
 170                 return err;
 171         }
 172
 173         host->rst = devm_reset_control_get(&pdev->dev, "host1x");
 174         if (IS_ERR(host->rst)) {
 175                 err = PTR_ERR(host->rst);
 176                 dev_err(&pdev->dev, "failed to get reset: %d\n", err);
 177                 return err;
 178         }
 179
 180         if (iommu_present(&platform_bus_type)) {
 181                 struct iommu_domain_geometry *geometry;
 182                 unsigned long order;
 183
 184                 host->domain = iommu_domain_alloc(&platform_bus_type);
 185                 if (!host->domain)
 186                         return -ENOMEM;
 187
 188                 err = iommu_attach_device(host->domain, &pdev->dev);
 189                 if (err == -ENODEV) {
 190                         iommu_domain_free(host->domain);
 191                         host->domain = NULL;
 192                         goto skip_iommu;
 193                 } else if (err) {
 194                         goto fail_free_domain;
 195                 }
 196
 197                 geometry = &host->domain->geometry;
 198
 199                 order = __ffs(host->domain->pgsize_bitmap);
 200                 init_iova_domain(&host->iova, 1UL << order,
 201                                  geometry->aperture_start >> order,
 202                                  geometry->aperture_end >> order);
 203                 host->iova_end = geometry->aperture_end;
 204         }
 205
 206 skip_iommu:
 207         err = host1x_channel_list_init(&host->channel_list,
 208                                        host->info->nb_channels);
 209         if (err) {
 210                 dev_err(&pdev->dev, "failed to initialize channel list\n");
 211                 goto fail_detach_device;
 212         }
 213
 214         err = clk_prepare_enable(host->clk);
 215         if (err < 0) {
 216                 dev_err(&pdev->dev, "failed to enable clock\n");
 217                 goto fail_free_channels;
 218         }
 219
 220         err = reset_control_deassert(host->rst);
 221         if (err < 0) {
 222                 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
 223                 goto fail_unprepare_disable;
 224         }
 225
 226         err = host1x_syncpt_init(host);
 227         if (err) {
 228                 dev_err(&pdev->dev, "failed to initialize syncpts\n");
 229                 goto fail_reset_assert;
 230         }
 231
 232         err = host1x_intr_init(host, syncpt_irq);
 233         if (err) {
 234                 dev_err(&pdev->dev, "failed to initialize interrupts\n");
 235                 goto fail_deinit_syncpt;
 236         }
 237
 238         host1x_debug_init(host);
 239
 240         err = host1x_register(host);
 241         if (err < 0)
 242                 goto fail_deinit_intr;
 243
 244         return 0;
 245
 246 fail_deinit_intr:
 247         host1x_intr_deinit(host);
 248 fail_deinit_syncpt:
 249         host1x_syncpt_deinit(host);
 250 fail_reset_assert:
 251         reset_control_assert(host->rst);
 252 fail_unprepare_disable:
 253         clk_disable_unprepare(host->clk);
 254 fail_free_channels:
 255         host1x_channel_list_free(&host->channel_list);
 256 fail_detach_device:
 257         if (host->domain) {
 258                 put_iova_domain(&host->iova);
 259                 iommu_detach_device(host->domain, &pdev->dev);
 260         }
 261 fail_free_domain:
 262         if (host->domain)
 263                 iommu_domain_free(host->domain);
 264
 265         return err;
 266 }
 267
 268 static int host1x_remove(struct platform_device *pdev)
 269 {
 270         struct host1x *host = platform_get_drvdata(pdev);
 271
 272         host1x_unregister(host);
 273         host1x_intr_deinit(host);
 274         host1x_syncpt_deinit(host);
 275         reset_control_assert(host->rst);
 276         clk_disable_unprepare(host->clk);
 277
 278         if (host->domain) {
 279                 put_iova_domain(&host->iova);
 280                 iommu_detach_device(host->domain, &pdev->dev);
 281                 iommu_domain_free(host->domain);
 282         }
 283
 284         return 0;
 285 }
 286
 287 static struct platform_driver tegra_host1x_driver = {
 288         .driver = {
 289                 .name = "tegra-host1x",
 290                 .of_match_table = host1x_of_match,
 291         },
 292         .probe = host1x_probe,
 293         .remove = host1x_remove,
 294 };
 295
 296 static struct platform_driver * const drivers[] = {
 297         &tegra_host1x_driver,
 298         &tegra_mipi_driver,
 299 };
 300
 301 static int __init tegra_host1x_init(void)
 302 {
 303         int err;
 304
 305         err = bus_register(&host1x_bus_type);
 306         if (err < 0)
 307                 return err;
 308
 309         err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
 310         if (err < 0)
 311                 bus_unregister(&host1x_bus_type);
 312
 313         return err;
 314 }
 315 module_init(tegra_host1x_init);
 316
 317 static void __exit tegra_host1x_exit(void)
 318 {
 319         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
 320         bus_unregister(&host1x_bus_type);
 321 }
 322 module_exit(tegra_host1x_exit);
 323
 324 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
 325 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
 326 MODULE_DESCRIPTION("Host1x driver for Tegra products");
 327 MODULE_LICENSE("GPL");