drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /**************************************************************************
   3  *
   4  * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27 #include <linux/module.h>
  28 #include <linux/console.h>
  29
  30 #include <drm/drmP.h>
  31 #include "vmwgfx_drv.h"
  32 #include "vmwgfx_binding.h"
  33 #include "ttm_object.h"
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_bo_driver.h>
  36 #include <drm/ttm/ttm_module.h>
  37 #include <linux/intel-iommu.h>
  38
  39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  40 #define VMWGFX_CHIP_SVGAII 0
  41 #define VMW_FB_RESERVATION 0
  42
  43 #define VMW_MIN_INITIAL_WIDTH 800
  44 #define VMW_MIN_INITIAL_HEIGHT 600
  45
  46 #ifndef VMWGFX_GIT_VERSION
  47 #define VMWGFX_GIT_VERSION "Unknown"
  48 #endif
  49
  50 #define VMWGFX_REPO "In Tree"
  51
  52 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE)
  53
  54
  55 /**
  56  * Fully encoded drm commands. Might move to vmw_drm.h
  57  */
  58
  59 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  60         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  61                  struct drm_vmw_getparam_arg)
  62 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  63         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  64                 union drm_vmw_alloc_dmabuf_arg)
  65 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  66         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  67                 struct drm_vmw_unref_dmabuf_arg)
  68 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  69         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  70                  struct drm_vmw_cursor_bypass_arg)
  71
  72 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  73         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  74                  struct drm_vmw_control_stream_arg)
  75 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  76         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  77                  struct drm_vmw_stream_arg)
  78 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  79         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  80                  struct drm_vmw_stream_arg)
  81
  82 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  83         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  84                 struct drm_vmw_context_arg)
  85 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  86         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  87                 struct drm_vmw_context_arg)
  88 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  89         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  90                  union drm_vmw_surface_create_arg)
  91 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  92         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  93                  struct drm_vmw_surface_arg)
  94 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  95         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  96                  union drm_vmw_surface_reference_arg)
  97 #define DRM_IOCTL_VMW_EXECBUF                                   \
  98         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  99                 struct drm_vmw_execbuf_arg)
 100 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
 101         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
 102                  struct drm_vmw_get_3d_cap_arg)
 103 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
 104         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
 105                  struct drm_vmw_fence_wait_arg)
 106 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
 107         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
 108                  struct drm_vmw_fence_signaled_arg)
 109 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
 110         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
 111                  struct drm_vmw_fence_arg)
 112 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
 113         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
 114                  struct drm_vmw_fence_event_arg)
 115 #define DRM_IOCTL_VMW_PRESENT                                   \
 116         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
 117                  struct drm_vmw_present_arg)
 118 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
 119         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
 120                  struct drm_vmw_present_readback_arg)
 121 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
 122         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
 123                  struct drm_vmw_update_layout_arg)
 124 #define DRM_IOCTL_VMW_CREATE_SHADER                             \
 125         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,      \
 126                  struct drm_vmw_shader_create_arg)
 127 #define DRM_IOCTL_VMW_UNREF_SHADER                              \
 128         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,        \
 129                  struct drm_vmw_shader_arg)
 130 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE                         \
 131         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,  \
 132                  union drm_vmw_gb_surface_create_arg)
 133 #define DRM_IOCTL_VMW_GB_SURFACE_REF                            \
 134         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,     \
 135                  union drm_vmw_gb_surface_reference_arg)
 136 #define DRM_IOCTL_VMW_SYNCCPU                                   \
 137         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,             \
 138                  struct drm_vmw_synccpu_arg)
 139 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT                   \
 140         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT,    \
 141                 struct drm_vmw_context_arg)
 142 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT                             \
 143         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT,      \
 144                 union drm_vmw_gb_surface_create_ext_arg)
 145 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT                                \
 146         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT,         \
 147                 union drm_vmw_gb_surface_reference_ext_arg)
 148
 149 /**
 150  * The core DRM version of this macro doesn't account for
 151  * DRM_COMMAND_BASE.
 152  */
 153
 154 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 155   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
 156
 157 /**
 158  * Ioctl definitions.
 159  */
 160
 161 static const struct drm_ioctl_desc vmw_ioctls[] = {
 162         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 163                       DRM_AUTH | DRM_RENDER_ALLOW),
 164         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl,
 165                       DRM_AUTH | DRM_RENDER_ALLOW),
 166         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
 167                       DRM_RENDER_ALLOW),
 168         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 169                       vmw_kms_cursor_bypass_ioctl,
 170                       DRM_MASTER),
 171
 172         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 173                       DRM_MASTER),
 174         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 175                       DRM_MASTER),
 176         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 177                       DRM_MASTER),
 178
 179         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 180                       DRM_AUTH | DRM_RENDER_ALLOW),
 181         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 182                       DRM_RENDER_ALLOW),
 183         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 184                       DRM_AUTH | DRM_RENDER_ALLOW),
 185         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 186                       DRM_RENDER_ALLOW),
 187         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 188                       DRM_AUTH | DRM_RENDER_ALLOW),
 189         VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
 190                       DRM_RENDER_ALLOW),
 191         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 192                       DRM_RENDER_ALLOW),
 193         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 194                       vmw_fence_obj_signaled_ioctl,
 195                       DRM_RENDER_ALLOW),
 196         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 197                       DRM_RENDER_ALLOW),
 198         VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
 199                       DRM_AUTH | DRM_RENDER_ALLOW),
 200         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 201                       DRM_AUTH | DRM_RENDER_ALLOW),
 202
 203         /* these allow direct access to the framebuffers mark as master only */
 204         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
 205                       DRM_MASTER | DRM_AUTH),
 206         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
 207                       vmw_present_readback_ioctl,
 208                       DRM_MASTER | DRM_AUTH),
 209         /*
 210          * The permissions of the below ioctl are overridden in
 211          * vmw_generic_ioctl(). We require either
 212          * DRM_MASTER or capable(CAP_SYS_ADMIN).
 213          */
 214         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
 215                       vmw_kms_update_layout_ioctl,
 216                       DRM_RENDER_ALLOW),
 217         VMW_IOCTL_DEF(VMW_CREATE_SHADER,
 218                       vmw_shader_define_ioctl,
 219                       DRM_AUTH | DRM_RENDER_ALLOW),
 220         VMW_IOCTL_DEF(VMW_UNREF_SHADER,
 221                       vmw_shader_destroy_ioctl,
 222                       DRM_RENDER_ALLOW),
 223         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
 224                       vmw_gb_surface_define_ioctl,
 225                       DRM_AUTH | DRM_RENDER_ALLOW),
 226         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
 227                       vmw_gb_surface_reference_ioctl,
 228                       DRM_AUTH | DRM_RENDER_ALLOW),
 229         VMW_IOCTL_DEF(VMW_SYNCCPU,
 230                       vmw_user_bo_synccpu_ioctl,
 231                       DRM_RENDER_ALLOW),
 232         VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
 233                       vmw_extended_context_define_ioctl,
 234                       DRM_AUTH | DRM_RENDER_ALLOW),
 235         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT,
 236                       vmw_gb_surface_define_ext_ioctl,
 237                       DRM_AUTH | DRM_RENDER_ALLOW),
 238         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT,
 239                       vmw_gb_surface_reference_ext_ioctl,
 240                       DRM_AUTH | DRM_RENDER_ALLOW),
 241 };
 242
 243 static const struct pci_device_id vmw_pci_id_list[] = {
 244         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 245         {0, 0, 0}
 246 };
 247 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
 248
 249 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
 250 static int vmw_force_iommu;
 251 static int vmw_restrict_iommu;
 252 static int vmw_force_coherent;
 253 static int vmw_restrict_dma_mask;
 254 static int vmw_assume_16bpp;
 255
 256 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 257 static void vmw_master_init(struct vmw_master *);
 258 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 259                               void *ptr);
 260
 261 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 262 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 263 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
 264 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
 265 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
 266 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
 267 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
 268 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
 269 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
 270 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
 271 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
 272 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
 273
 274
 275 static void vmw_print_capabilities2(uint32_t capabilities2)
 276 {
 277         DRM_INFO("Capabilities2:\n");
 278         if (capabilities2 & SVGA_CAP2_GROW_OTABLE)
 279                 DRM_INFO("  Grow oTable.\n");
 280         if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)
 281                 DRM_INFO("  IntraSurface copy.\n");
 282 }
 283
 284 static void vmw_print_capabilities(uint32_t capabilities)
 285 {
 286         DRM_INFO("Capabilities:\n");
 287         if (capabilities & SVGA_CAP_RECT_COPY)
 288                 DRM_INFO("  Rect copy.\n");
 289         if (capabilities & SVGA_CAP_CURSOR)
 290                 DRM_INFO("  Cursor.\n");
 291         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 292                 DRM_INFO("  Cursor bypass.\n");
 293         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 294                 DRM_INFO("  Cursor bypass 2.\n");
 295         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 296                 DRM_INFO("  8bit emulation.\n");
 297         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 298                 DRM_INFO("  Alpha cursor.\n");
 299         if (capabilities & SVGA_CAP_3D)
 300                 DRM_INFO("  3D.\n");
 301         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 302                 DRM_INFO("  Extended Fifo.\n");
 303         if (capabilities & SVGA_CAP_MULTIMON)
 304                 DRM_INFO("  Multimon.\n");
 305         if (capabilities & SVGA_CAP_PITCHLOCK)
 306                 DRM_INFO("  Pitchlock.\n");
 307         if (capabilities & SVGA_CAP_IRQMASK)
 308                 DRM_INFO("  Irq mask.\n");
 309         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 310                 DRM_INFO("  Display Topology.\n");
 311         if (capabilities & SVGA_CAP_GMR)
 312                 DRM_INFO("  GMR.\n");
 313         if (capabilities & SVGA_CAP_TRACES)
 314                 DRM_INFO("  Traces.\n");
 315         if (capabilities & SVGA_CAP_GMR2)
 316                 DRM_INFO("  GMR2.\n");
 317         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 318                 DRM_INFO("  Screen Object 2.\n");
 319         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
 320                 DRM_INFO("  Command Buffers.\n");
 321         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
 322                 DRM_INFO("  Command Buffers 2.\n");
 323         if (capabilities & SVGA_CAP_GBOBJECTS)
 324                 DRM_INFO("  Guest Backed Resources.\n");
 325         if (capabilities & SVGA_CAP_DX)
 326                 DRM_INFO("  DX Features.\n");
 327         if (capabilities & SVGA_CAP_HP_CMD_QUEUE)
 328                 DRM_INFO("  HP Command Queue.\n");
 329 }
 330
 331 /**
 332  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 333  *
 334  * @dev_priv: A device private structure.
 335  *
 336  * This function creates a small buffer object that holds the query
 337  * result for dummy queries emitted as query barriers.
 338  * The function will then map the first page and initialize a pending
 339  * occlusion query result structure, Finally it will unmap the buffer.
 340  * No interruptible waits are done within this function.
 341  *
 342  * Returns an error if bo creation or initialization fails.
 343  */
 344 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
 345 {
 346         int ret;
 347         struct vmw_buffer_object *vbo;
 348         struct ttm_bo_kmap_obj map;
 349         volatile SVGA3dQueryResult *result;
 350         bool dummy;
 351
 352         /*
 353          * Create the vbo as pinned, so that a tryreserve will
 354          * immediately succeed. This is because we're the only
 355          * user of the bo currently.
 356          */
 357         vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
 358         if (!vbo)
 359                 return -ENOMEM;
 360
 361         ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE,
 362                           &vmw_sys_ne_placement, false,
 363                           &vmw_bo_bo_free);
 364         if (unlikely(ret != 0))
 365                 return ret;
 366
 367         ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
 368         BUG_ON(ret != 0);
 369         vmw_bo_pin_reserved(vbo, true);
 370
 371         ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
 372         if (likely(ret == 0)) {
 373                 result = ttm_kmap_obj_virtual(&map, &dummy);
 374                 result->totalSize = sizeof(*result);
 375                 result->state = SVGA3D_QUERYSTATE_PENDING;
 376                 result->result32 = 0xff;
 377                 ttm_bo_kunmap(&map);
 378         }
 379         vmw_bo_pin_reserved(vbo, false);
 380         ttm_bo_unreserve(&vbo->base);
 381
 382         if (unlikely(ret != 0)) {
 383                 DRM_ERROR("Dummy query buffer map failed.\n");
 384                 vmw_bo_unreference(&vbo);
 385         } else
 386                 dev_priv->dummy_query_bo = vbo;
 387
 388         return ret;
 389 }
 390
 391 /**
 392  * vmw_request_device_late - Perform late device setup
 393  *
 394  * @dev_priv: Pointer to device private.
 395  *
 396  * This function performs setup of otables and enables large command
 397  * buffer submission. These tasks are split out to a separate function
 398  * because it reverts vmw_release_device_early and is intended to be used
 399  * by an error path in the hibernation code.
 400  */
 401 static int vmw_request_device_late(struct vmw_private *dev_priv)
 402 {
 403         int ret;
 404
 405         if (dev_priv->has_mob) {
 406                 ret = vmw_otables_setup(dev_priv);
 407                 if (unlikely(ret != 0)) {
 408                         DRM_ERROR("Unable to initialize "
 409                                   "guest Memory OBjects.\n");
 410                         return ret;
 411                 }
 412         }
 413
 414         if (dev_priv->cman) {
 415                 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
 416                                                256*4096, 2*4096);
 417                 if (ret) {
 418                         struct vmw_cmdbuf_man *man = dev_priv->cman;
 419
 420                         dev_priv->cman = NULL;
 421                         vmw_cmdbuf_man_destroy(man);
 422                 }
 423         }
 424
 425         return 0;
 426 }
 427
 428 static int vmw_request_device(struct vmw_private *dev_priv)
 429 {
 430         int ret;
 431
 432         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 433         if (unlikely(ret != 0)) {
 434                 DRM_ERROR("Unable to initialize FIFO.\n");
 435                 return ret;
 436         }
 437         vmw_fence_fifo_up(dev_priv->fman);
 438         dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
 439         if (IS_ERR(dev_priv->cman)) {
 440                 dev_priv->cman = NULL;
 441                 dev_priv->has_dx = false;
 442         }
 443
 444         ret = vmw_request_device_late(dev_priv);
 445         if (ret)
 446                 goto out_no_mob;
 447
 448         ret = vmw_dummy_query_bo_create(dev_priv);
 449         if (unlikely(ret != 0))
 450                 goto out_no_query_bo;
 451
 452         return 0;
 453
 454 out_no_query_bo:
 455         if (dev_priv->cman)
 456                 vmw_cmdbuf_remove_pool(dev_priv->cman);
 457         if (dev_priv->has_mob) {
 458                 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
 459                 vmw_otables_takedown(dev_priv);
 460         }
 461         if (dev_priv->cman)
 462                 vmw_cmdbuf_man_destroy(dev_priv->cman);
 463 out_no_mob:
 464         vmw_fence_fifo_down(dev_priv->fman);
 465         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 466         return ret;
 467 }
 468
 469 /**
 470  * vmw_release_device_early - Early part of fifo takedown.
 471  *
 472  * @dev_priv: Pointer to device private struct.
 473  *
 474  * This is the first part of command submission takedown, to be called before
 475  * buffer management is taken down.
 476  */
 477 static void vmw_release_device_early(struct vmw_private *dev_priv)
 478 {
 479         /*
 480          * Previous destructions should've released
 481          * the pinned bo.
 482          */
 483
 484         BUG_ON(dev_priv->pinned_bo != NULL);
 485
 486         vmw_bo_unreference(&dev_priv->dummy_query_bo);
 487         if (dev_priv->cman)
 488                 vmw_cmdbuf_remove_pool(dev_priv->cman);
 489
 490         if (dev_priv->has_mob) {
 491                 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
 492                 vmw_otables_takedown(dev_priv);
 493         }
 494 }
 495
 496 /**
 497  * vmw_release_device_late - Late part of fifo takedown.
 498  *
 499  * @dev_priv: Pointer to device private struct.
 500  *
 501  * This is the last part of the command submission takedown, to be called when
 502  * command submission is no longer needed. It may wait on pending fences.
 503  */
 504 static void vmw_release_device_late(struct vmw_private *dev_priv)
 505 {
 506         vmw_fence_fifo_down(dev_priv->fman);
 507         if (dev_priv->cman)
 508                 vmw_cmdbuf_man_destroy(dev_priv->cman);
 509
 510         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 511 }
 512
 513 /**
 514  * Sets the initial_[width|height] fields on the given vmw_private.
 515  *
 516  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
 517  * clamping the value to fb_max_[width|height] fields and the
 518  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 519  * If the values appear to be invalid, set them to
 520  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 521  */
 522 static void vmw_get_initial_size(struct vmw_private *dev_priv)
 523 {
 524         uint32_t width;
 525         uint32_t height;
 526
 527         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
 528         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
 529
 530         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
 531         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
 532
 533         if (width > dev_priv->fb_max_width ||
 534             height > dev_priv->fb_max_height) {
 535
 536                 /*
 537                  * This is a host error and shouldn't occur.
 538                  */
 539
 540                 width = VMW_MIN_INITIAL_WIDTH;
 541                 height = VMW_MIN_INITIAL_HEIGHT;
 542         }
 543
 544         dev_priv->initial_width = width;
 545         dev_priv->initial_height = height;
 546 }
 547
 548 /**
 549  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
 550  * system.
 551  *
 552  * @dev_priv: Pointer to a struct vmw_private
 553  *
 554  * This functions tries to determine the IOMMU setup and what actions
 555  * need to be taken by the driver to make system pages visible to the
 556  * device.
 557  * If this function decides that DMA is not possible, it returns -EINVAL.
 558  * The driver may then try to disable features of the device that require
 559  * DMA.
 560  */
 561 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
 562 {
 563         static const char *names[vmw_dma_map_max] = {
 564                 [vmw_dma_phys] = "Using physical TTM page addresses.",
 565                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
 566                 [vmw_dma_map_populate] = "Keeping DMA mappings.",
 567                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
 568         const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
 569
 570         if (intel_iommu_enabled) {
 571                 dev_priv->map_mode = vmw_dma_map_populate;
 572                 goto out_fixup;
 573         }
 574
 575         if (!(vmw_force_iommu || vmw_force_coherent)) {
 576                 dev_priv->map_mode = vmw_dma_phys;
 577                 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 578                 return 0;
 579         }
 580
 581         dev_priv->map_mode = vmw_dma_map_populate;
 582
 583         if (dma_ops && dma_ops->sync_single_for_cpu)
 584                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 585 #ifdef CONFIG_SWIOTLB
 586         if (swiotlb_nr_tbl() == 0)
 587                 dev_priv->map_mode = vmw_dma_map_populate;
 588 #endif
 589
 590 out_fixup:
 591         if (dev_priv->map_mode == vmw_dma_map_populate &&
 592             vmw_restrict_iommu)
 593                 dev_priv->map_mode = vmw_dma_map_bind;
 594
 595         if (vmw_force_coherent)
 596                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 597
 598         /* No TTM coherent page pool? FIXME: Ask TTM instead! */
 599         if (!(IS_ENABLED(CONFIG_SWIOTLB) || IS_ENABLED(CONFIG_INTEL_IOMMU)) &&
 600             (dev_priv->map_mode == vmw_dma_alloc_coherent))
 601                 return -EINVAL;
 602
 603         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 604
 605         return 0;
 606 }
 607
 608 /**
 609  * vmw_dma_masks - set required page- and dma masks
 610  *
 611  * @dev: Pointer to struct drm-device
 612  *
 613  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
 614  * restriction also for 64-bit systems.
 615  */
 616 static int vmw_dma_masks(struct vmw_private *dev_priv)
 617 {
 618         struct drm_device *dev = dev_priv->dev;
 619
 620         if (intel_iommu_enabled &&
 621             (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
 622                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
 623                 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
 624         }
 625         return 0;
 626 }
 627
 628 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 629 {
 630         struct vmw_private *dev_priv;
 631         int ret;
 632         uint32_t svga_id;
 633         enum vmw_res_type i;
 634         bool refuse_dma = false;
 635         char host_log[100] = {0};
 636
 637         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 638         if (unlikely(!dev_priv)) {
 639                 DRM_ERROR("Failed allocating a device private struct.\n");
 640                 return -ENOMEM;
 641         }
 642
 643         pci_set_master(dev->pdev);
 644
 645         dev_priv->dev = dev;
 646         dev_priv->vmw_chipset = chipset;
 647         dev_priv->last_read_seqno = (uint32_t) -100;
 648         mutex_init(&dev_priv->cmdbuf_mutex);
 649         mutex_init(&dev_priv->release_mutex);
 650         mutex_init(&dev_priv->binding_mutex);
 651         mutex_init(&dev_priv->global_kms_state_mutex);
 652         ttm_lock_init(&dev_priv->reservation_sem);
 653         spin_lock_init(&dev_priv->resource_lock);
 654         spin_lock_init(&dev_priv->hw_lock);
 655         spin_lock_init(&dev_priv->waiter_lock);
 656         spin_lock_init(&dev_priv->cap_lock);
 657         spin_lock_init(&dev_priv->svga_lock);
 658         spin_lock_init(&dev_priv->cursor_lock);
 659
 660         for (i = vmw_res_context; i < vmw_res_max; ++i) {
 661                 idr_init(&dev_priv->res_idr[i]);
 662                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
 663         }
 664
 665         mutex_init(&dev_priv->init_mutex);
 666         init_waitqueue_head(&dev_priv->fence_queue);
 667         init_waitqueue_head(&dev_priv->fifo_queue);
 668         dev_priv->fence_queue_waiters = 0;
 669         dev_priv->fifo_queue_waiters = 0;
 670
 671         dev_priv->used_memory_size = 0;
 672
 673         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 674         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 675         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 676
 677         dev_priv->assume_16bpp = !!vmw_assume_16bpp;
 678
 679         dev_priv->enable_fb = enable_fbdev;
 680
 681         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 682         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 683         if (svga_id != SVGA_ID_2) {
 684                 ret = -ENOSYS;
 685                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
 686                 goto out_err0;
 687         }
 688
 689         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 690
 691         if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
 692                 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
 693         }
 694
 695
 696         ret = vmw_dma_select_mode(dev_priv);
 697         if (unlikely(ret != 0)) {
 698                 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
 699                 refuse_dma = true;
 700         }
 701
 702         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 703         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 704         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 705         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 706
 707         vmw_get_initial_size(dev_priv);
 708
 709         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 710                 dev_priv->max_gmr_ids =
 711                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 712                 dev_priv->max_gmr_pages =
 713                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 714                 dev_priv->memory_size =
 715                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 716                 dev_priv->memory_size -= dev_priv->vram_size;
 717         } else {
 718                 /*
 719                  * An arbitrary limit of 512MiB on surface
 720                  * memory. But all HWV8 hardware supports GMR2.
 721                  */
 722                 dev_priv->memory_size = 512*1024*1024;
 723         }
 724         dev_priv->max_mob_pages = 0;
 725         dev_priv->max_mob_size = 0;
 726         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 727                 uint64_t mem_size =
 728                         vmw_read(dev_priv,
 729                                  SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
 730
 731                 /*
 732                  * Workaround for low memory 2D VMs to compensate for the
 733                  * allocation taken by fbdev
 734                  */
 735                 if (!(dev_priv->capabilities & SVGA_CAP_3D))
 736                         mem_size *= 3;
 737
 738                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
 739                 dev_priv->prim_bb_mem =
 740                         vmw_read(dev_priv,
 741                                  SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
 742                 dev_priv->max_mob_size =
 743                         vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
 744                 dev_priv->stdu_max_width =
 745                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
 746                 dev_priv->stdu_max_height =
 747                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
 748
 749                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 750                           SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
 751                 dev_priv->texture_max_width = vmw_read(dev_priv,
 752                                                        SVGA_REG_DEV_CAP);
 753                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 754                           SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
 755                 dev_priv->texture_max_height = vmw_read(dev_priv,
 756                                                         SVGA_REG_DEV_CAP);
 757         } else {
 758                 dev_priv->texture_max_width = 8192;
 759                 dev_priv->texture_max_height = 8192;
 760                 dev_priv->prim_bb_mem = dev_priv->vram_size;
 761         }
 762
 763         vmw_print_capabilities(dev_priv->capabilities);
 764         if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
 765                 vmw_print_capabilities2(dev_priv->capabilities2);
 766
 767         ret = vmw_dma_masks(dev_priv);
 768         if (unlikely(ret != 0))
 769                 goto out_err0;
 770
 771         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 772                 DRM_INFO("Max GMR ids is %u\n",
 773                          (unsigned)dev_priv->max_gmr_ids);
 774                 DRM_INFO("Max number of GMR pages is %u\n",
 775                          (unsigned)dev_priv->max_gmr_pages);
 776                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 777                          (unsigned)dev_priv->memory_size / 1024);
 778         }
 779         DRM_INFO("Maximum display memory size is %u kiB\n",
 780                  dev_priv->prim_bb_mem / 1024);
 781         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 782                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 783         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 784                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 785
 786         vmw_master_init(&dev_priv->fbdev_master);
 787         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 788         dev_priv->active_master = &dev_priv->fbdev_master;
 789
 790         dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
 791                                        dev_priv->mmio_size, MEMREMAP_WB);
 792
 793         if (unlikely(dev_priv->mmio_virt == NULL)) {
 794                 ret = -ENOMEM;
 795                 DRM_ERROR("Failed mapping MMIO.\n");
 796                 goto out_err0;
 797         }
 798
 799         /* Need mmio memory to check for fifo pitchlock cap. */
 800         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 801             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 802             !vmw_fifo_have_pitchlock(dev_priv)) {
 803                 ret = -ENOSYS;
 804                 DRM_ERROR("Hardware has no pitchlock\n");
 805                 goto out_err4;
 806         }
 807
 808         dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12,
 809                                                 &vmw_prime_dmabuf_ops);
 810
 811         if (unlikely(dev_priv->tdev == NULL)) {
 812                 DRM_ERROR("Unable to initialize TTM object management.\n");
 813                 ret = -ENOMEM;
 814                 goto out_err4;
 815         }
 816
 817         dev->dev_private = dev_priv;
 818
 819         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 820         dev_priv->stealth = (ret != 0);
 821         if (dev_priv->stealth) {
 822                 /**
 823                  * Request at least the mmio PCI resource.
 824                  */
 825
 826                 DRM_INFO("It appears like vesafb is loaded. "
 827                          "Ignore above error if any.\n");
 828                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 829                 if (unlikely(ret != 0)) {
 830                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 831                         goto out_no_device;
 832                 }
 833         }
 834
 835         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 836                 ret = vmw_irq_install(dev, dev->pdev->irq);
 837                 if (ret != 0) {
 838                         DRM_ERROR("Failed installing irq: %d\n", ret);
 839                         goto out_no_irq;
 840                 }
 841         }
 842
 843         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 844         if (unlikely(dev_priv->fman == NULL)) {
 845                 ret = -ENOMEM;
 846                 goto out_no_fman;
 847         }
 848
 849         ret = ttm_bo_device_init(&dev_priv->bdev,
 850                                  &vmw_bo_driver,
 851                                  dev->anon_inode->i_mapping,
 852                                  VMWGFX_FILE_PAGE_OFFSET,
 853                                  false);
 854         if (unlikely(ret != 0)) {
 855                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 856                 goto out_no_bdev;
 857         }
 858
 859         /*
 860          * Enable VRAM, but initially don't use it until SVGA is enabled and
 861          * unhidden.
 862          */
 863         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 864                              (dev_priv->vram_size >> PAGE_SHIFT));
 865         if (unlikely(ret != 0)) {
 866                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 867                 goto out_no_vram;
 868         }
 869         dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
 870
 871         dev_priv->has_gmr = true;
 872         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
 873             refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 874                                          VMW_PL_GMR) != 0) {
 875                 DRM_INFO("No GMR memory available. "
 876                          "Graphics memory resources are very limited.\n");
 877                 dev_priv->has_gmr = false;
 878         }
 879
 880         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 881                 dev_priv->has_mob = true;
 882                 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
 883                                    VMW_PL_MOB) != 0) {
 884                         DRM_INFO("No MOB memory available. "
 885                                  "3D will be disabled.\n");
 886                         dev_priv->has_mob = false;
 887                 }
 888         }
 889
 890         if (dev_priv->has_mob) {
 891                 spin_lock(&dev_priv->cap_lock);
 892                 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
 893                 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
 894                 spin_unlock(&dev_priv->cap_lock);
 895         }
 896
 897         vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN);
 898         ret = vmw_kms_init(dev_priv);
 899         if (unlikely(ret != 0))
 900                 goto out_no_kms;
 901         vmw_overlay_init(dev_priv);
 902
 903         ret = vmw_request_device(dev_priv);
 904         if (ret)
 905                 goto out_no_fifo;
 906
 907         if (dev_priv->has_dx) {
 908                 /*
 909                  * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1
 910                  * support
 911                  */
 912                 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) {
 913                         vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 914                                         SVGA3D_DEVCAP_SM41);
 915                         dev_priv->has_sm4_1 = vmw_read(dev_priv,
 916                                                         SVGA_REG_DEV_CAP);
 917                 }
 918         }
 919
 920         DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
 921         DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC)
 922                  ? "yes." : "no.");
 923         DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no.");
 924
 925         snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
 926                 VMWGFX_REPO, VMWGFX_GIT_VERSION);
 927         vmw_host_log(host_log);
 928
 929         memset(host_log, 0, sizeof(host_log));
 930         snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
 931                 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
 932                 VMWGFX_DRIVER_PATCHLEVEL);
 933         vmw_host_log(host_log);
 934
 935         if (dev_priv->enable_fb) {
 936                 vmw_fifo_resource_inc(dev_priv);
 937                 vmw_svga_enable(dev_priv);
 938                 vmw_fb_init(dev_priv);
 939         }
 940
 941         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 942         register_pm_notifier(&dev_priv->pm_nb);
 943
 944         return 0;
 945
 946 out_no_fifo:
 947         vmw_overlay_close(dev_priv);
 948         vmw_kms_close(dev_priv);
 949 out_no_kms:
 950         if (dev_priv->has_mob)
 951                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 952         if (dev_priv->has_gmr)
 953                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 954         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 955 out_no_vram:
 956         (void)ttm_bo_device_release(&dev_priv->bdev);
 957 out_no_bdev:
 958         vmw_fence_manager_takedown(dev_priv->fman);
 959 out_no_fman:
 960         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 961                 vmw_irq_uninstall(dev_priv->dev);
 962 out_no_irq:
 963         if (dev_priv->stealth)
 964                 pci_release_region(dev->pdev, 2);
 965         else
 966                 pci_release_regions(dev->pdev);
 967 out_no_device:
 968         ttm_object_device_release(&dev_priv->tdev);
 969 out_err4:
 970         memunmap(dev_priv->mmio_virt);
 971 out_err0:
 972         for (i = vmw_res_context; i < vmw_res_max; ++i)
 973                 idr_destroy(&dev_priv->res_idr[i]);
 974
 975         if (dev_priv->ctx.staged_bindings)
 976                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
 977         kfree(dev_priv);
 978         return ret;
 979 }
 980
 981 static void vmw_driver_unload(struct drm_device *dev)
 982 {
 983         struct vmw_private *dev_priv = vmw_priv(dev);
 984         enum vmw_res_type i;
 985
 986         unregister_pm_notifier(&dev_priv->pm_nb);
 987
 988         if (dev_priv->ctx.res_ht_initialized)
 989                 drm_ht_remove(&dev_priv->ctx.res_ht);
 990         vfree(dev_priv->ctx.cmd_bounce);
 991         if (dev_priv->enable_fb) {
 992                 vmw_fb_off(dev_priv);
 993                 vmw_fb_close(dev_priv);
 994                 vmw_fifo_resource_dec(dev_priv);
 995                 vmw_svga_disable(dev_priv);
 996         }
 997
 998         vmw_kms_close(dev_priv);
 999         vmw_overlay_close(dev_priv);
1000
1001         if (dev_priv->has_gmr)
1002                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
1003         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
1004
1005         vmw_release_device_early(dev_priv);
1006         if (dev_priv->has_mob)
1007                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
1008         (void) ttm_bo_device_release(&dev_priv->bdev);
1009         vmw_release_device_late(dev_priv);
1010         vmw_fence_manager_takedown(dev_priv->fman);
1011         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1012                 vmw_irq_uninstall(dev_priv->dev);
1013         if (dev_priv->stealth)
1014                 pci_release_region(dev->pdev, 2);
1015         else
1016                 pci_release_regions(dev->pdev);
1017
1018         ttm_object_device_release(&dev_priv->tdev);
1019         memunmap(dev_priv->mmio_virt);
1020         if (dev_priv->ctx.staged_bindings)
1021                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1022
1023         for (i = vmw_res_context; i < vmw_res_max; ++i)
1024                 idr_destroy(&dev_priv->res_idr[i]);
1025
1026         kfree(dev_priv);
1027 }
1028
1029 static void vmw_postclose(struct drm_device *dev,
1030                          struct drm_file *file_priv)
1031 {
1032         struct vmw_fpriv *vmw_fp;
1033
1034         vmw_fp = vmw_fpriv(file_priv);
1035
1036         if (vmw_fp->locked_master) {
1037                 struct vmw_master *vmaster =
1038                         vmw_master(vmw_fp->locked_master);
1039
1040                 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1041                 ttm_vt_unlock(&vmaster->lock);
1042                 drm_master_put(&vmw_fp->locked_master);
1043         }
1044
1045         ttm_object_file_release(&vmw_fp->tfile);
1046         kfree(vmw_fp);
1047 }
1048
1049 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1050 {
1051         struct vmw_private *dev_priv = vmw_priv(dev);
1052         struct vmw_fpriv *vmw_fp;
1053         int ret = -ENOMEM;
1054
1055         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1056         if (unlikely(!vmw_fp))
1057                 return ret;
1058
1059         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1060         if (unlikely(vmw_fp->tfile == NULL))
1061                 goto out_no_tfile;
1062
1063         file_priv->driver_priv = vmw_fp;
1064
1065         return 0;
1066
1067 out_no_tfile:
1068         kfree(vmw_fp);
1069         return ret;
1070 }
1071
1072 static struct vmw_master *vmw_master_check(struct drm_device *dev,
1073                                            struct drm_file *file_priv,
1074                                            unsigned int flags)
1075 {
1076         int ret;
1077         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1078         struct vmw_master *vmaster;
1079
1080         if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH))
1081                 return NULL;
1082
1083         ret = mutex_lock_interruptible(&dev->master_mutex);
1084         if (unlikely(ret != 0))
1085                 return ERR_PTR(-ERESTARTSYS);
1086
1087         if (drm_is_current_master(file_priv)) {
1088                 mutex_unlock(&dev->master_mutex);
1089                 return NULL;
1090         }
1091
1092         /*
1093          * Check if we were previously master, but now dropped. In that
1094          * case, allow at least render node functionality.
1095          */
1096         if (vmw_fp->locked_master) {
1097                 mutex_unlock(&dev->master_mutex);
1098
1099                 if (flags & DRM_RENDER_ALLOW)
1100                         return NULL;
1101
1102                 DRM_ERROR("Dropped master trying to access ioctl that "
1103                           "requires authentication.\n");
1104                 return ERR_PTR(-EACCES);
1105         }
1106         mutex_unlock(&dev->master_mutex);
1107
1108         /*
1109          * Take the TTM lock. Possibly sleep waiting for the authenticating
1110          * master to become master again, or for a SIGTERM if the
1111          * authenticating master exits.
1112          */
1113         vmaster = vmw_master(file_priv->master);
1114         ret = ttm_read_lock(&vmaster->lock, true);
1115         if (unlikely(ret != 0))
1116                 vmaster = ERR_PTR(ret);
1117
1118         return vmaster;
1119 }
1120
1121 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1122                               unsigned long arg,
1123                               long (*ioctl_func)(struct file *, unsigned int,
1124                                                  unsigned long))
1125 {
1126         struct drm_file *file_priv = filp->private_data;
1127         struct drm_device *dev = file_priv->minor->dev;
1128         unsigned int nr = DRM_IOCTL_NR(cmd);
1129         struct vmw_master *vmaster;
1130         unsigned int flags;
1131         long ret;
1132
1133         /*
1134          * Do extra checking on driver private ioctls.
1135          */
1136
1137         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1138             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1139                 const struct drm_ioctl_desc *ioctl =
1140                         &vmw_ioctls[nr - DRM_COMMAND_BASE];
1141
1142                 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1143                         ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1144                         if (unlikely(ret != 0))
1145                                 return ret;
1146
1147                         if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1148                                 goto out_io_encoding;
1149
1150                         return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1151                                                         _IOC_SIZE(cmd));
1152                 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1153                         if (!drm_is_current_master(file_priv) &&
1154                             !capable(CAP_SYS_ADMIN))
1155                                 return -EACCES;
1156                 }
1157
1158                 if (unlikely(ioctl->cmd != cmd))
1159                         goto out_io_encoding;
1160
1161                 flags = ioctl->flags;
1162         } else if (!drm_ioctl_flags(nr, &flags))
1163                 return -EINVAL;
1164
1165         vmaster = vmw_master_check(dev, file_priv, flags);
1166         if (IS_ERR(vmaster)) {
1167                 ret = PTR_ERR(vmaster);
1168
1169                 if (ret != -ERESTARTSYS)
1170                         DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1171                                  nr, ret);
1172                 return ret;
1173         }
1174
1175         ret = ioctl_func(filp, cmd, arg);
1176         if (vmaster)
1177                 ttm_read_unlock(&vmaster->lock);
1178
1179         return ret;
1180
1181 out_io_encoding:
1182         DRM_ERROR("Invalid command format, ioctl %d\n",
1183                   nr - DRM_COMMAND_BASE);
1184
1185         return -EINVAL;
1186 }
1187
1188 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1189                                unsigned long arg)
1190 {
1191         return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1192 }
1193
1194 #ifdef CONFIG_COMPAT
1195 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1196                              unsigned long arg)
1197 {
1198         return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1199 }
1200 #endif
1201
1202 static void vmw_lastclose(struct drm_device *dev)
1203 {
1204 }
1205
1206 static void vmw_master_init(struct vmw_master *vmaster)
1207 {
1208         ttm_lock_init(&vmaster->lock);
1209 }
1210
1211 static int vmw_master_create(struct drm_device *dev,
1212                              struct drm_master *master)
1213 {
1214         struct vmw_master *vmaster;
1215
1216         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1217         if (unlikely(!vmaster))
1218                 return -ENOMEM;
1219
1220         vmw_master_init(vmaster);
1221         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1222         master->driver_priv = vmaster;
1223
1224         return 0;
1225 }
1226
1227 static void vmw_master_destroy(struct drm_device *dev,
1228                                struct drm_master *master)
1229 {
1230         struct vmw_master *vmaster = vmw_master(master);
1231
1232         master->driver_priv = NULL;
1233         kfree(vmaster);
1234 }
1235
1236 static int vmw_master_set(struct drm_device *dev,
1237                           struct drm_file *file_priv,
1238                           bool from_open)
1239 {
1240         struct vmw_private *dev_priv = vmw_priv(dev);
1241         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1242         struct vmw_master *active = dev_priv->active_master;
1243         struct vmw_master *vmaster = vmw_master(file_priv->master);
1244         int ret = 0;
1245
1246         if (active) {
1247                 BUG_ON(active != &dev_priv->fbdev_master);
1248                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1249                 if (unlikely(ret != 0))
1250                         return ret;
1251
1252                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1253                 dev_priv->active_master = NULL;
1254         }
1255
1256         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1257         if (!from_open) {
1258                 ttm_vt_unlock(&vmaster->lock);
1259                 BUG_ON(vmw_fp->locked_master != file_priv->master);
1260                 drm_master_put(&vmw_fp->locked_master);
1261         }
1262
1263         dev_priv->active_master = vmaster;
1264         drm_sysfs_hotplug_event(dev);
1265
1266         return 0;
1267 }
1268
1269 static void vmw_master_drop(struct drm_device *dev,
1270                             struct drm_file *file_priv)
1271 {
1272         struct vmw_private *dev_priv = vmw_priv(dev);
1273         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1274         struct vmw_master *vmaster = vmw_master(file_priv->master);
1275         int ret;
1276
1277         /**
1278          * Make sure the master doesn't disappear while we have
1279          * it locked.
1280          */
1281
1282         vmw_fp->locked_master = drm_master_get(file_priv->master);
1283         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1284         vmw_kms_legacy_hotspot_clear(dev_priv);
1285         if (unlikely((ret != 0))) {
1286                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1287                 drm_master_put(&vmw_fp->locked_master);
1288         }
1289
1290         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1291
1292         if (!dev_priv->enable_fb)
1293                 vmw_svga_disable(dev_priv);
1294
1295         dev_priv->active_master = &dev_priv->fbdev_master;
1296         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1297         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1298 }
1299
1300 /**
1301  * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1302  *
1303  * @dev_priv: Pointer to device private struct.
1304  * Needs the reservation sem to be held in non-exclusive mode.
1305  */
1306 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1307 {
1308         spin_lock(&dev_priv->svga_lock);
1309         if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1310                 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1311                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1312         }
1313         spin_unlock(&dev_priv->svga_lock);
1314 }
1315
1316 /**
1317  * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1318  *
1319  * @dev_priv: Pointer to device private struct.
1320  */
1321 void vmw_svga_enable(struct vmw_private *dev_priv)
1322 {
1323         (void) ttm_read_lock(&dev_priv->reservation_sem, false);
1324         __vmw_svga_enable(dev_priv);
1325         ttm_read_unlock(&dev_priv->reservation_sem);
1326 }
1327
1328 /**
1329  * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1330  *
1331  * @dev_priv: Pointer to device private struct.
1332  * Needs the reservation sem to be held in exclusive mode.
1333  * Will not empty VRAM. VRAM must be emptied by caller.
1334  */
1335 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1336 {
1337         spin_lock(&dev_priv->svga_lock);
1338         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1339                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1340                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1341                           SVGA_REG_ENABLE_HIDE |
1342                           SVGA_REG_ENABLE_ENABLE);
1343         }
1344         spin_unlock(&dev_priv->svga_lock);
1345 }
1346
1347 /**
1348  * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1349  * running.
1350  *
1351  * @dev_priv: Pointer to device private struct.
1352  * Will empty VRAM.
1353  */
1354 void vmw_svga_disable(struct vmw_private *dev_priv)
1355 {
1356         /*
1357          * Disabling SVGA will turn off device modesetting capabilities, so
1358          * notify KMS about that so that it doesn't cache atomic state that
1359          * isn't valid anymore, for example crtcs turned on.
1360          * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1361          * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1362          * end up with lock order reversal. Thus, a master may actually perform
1363          * a new modeset just after we call vmw_kms_lost_device() and race with
1364          * vmw_svga_disable(), but that should at worst cause atomic KMS state
1365          * to be inconsistent with the device, causing modesetting problems.
1366          *
1367          */
1368         vmw_kms_lost_device(dev_priv->dev);
1369         ttm_write_lock(&dev_priv->reservation_sem, false);
1370         spin_lock(&dev_priv->svga_lock);
1371         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1372                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1373                 spin_unlock(&dev_priv->svga_lock);
1374                 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1375                         DRM_ERROR("Failed evicting VRAM buffers.\n");
1376                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1377                           SVGA_REG_ENABLE_HIDE |
1378                           SVGA_REG_ENABLE_ENABLE);
1379         } else
1380                 spin_unlock(&dev_priv->svga_lock);
1381         ttm_write_unlock(&dev_priv->reservation_sem);
1382 }
1383
1384 static void vmw_remove(struct pci_dev *pdev)
1385 {
1386         struct drm_device *dev = pci_get_drvdata(pdev);
1387
1388         pci_disable_device(pdev);
1389         drm_put_dev(dev);
1390 }
1391
1392 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1393                               void *ptr)
1394 {
1395         struct vmw_private *dev_priv =
1396                 container_of(nb, struct vmw_private, pm_nb);
1397
1398         switch (val) {
1399         case PM_HIBERNATION_PREPARE:
1400                 /*
1401                  * Take the reservation sem in write mode, which will make sure
1402                  * there are no other processes holding a buffer object
1403                  * reservation, meaning we should be able to evict all buffer
1404                  * objects if needed.
1405                  * Once user-space processes have been frozen, we can release
1406                  * the lock again.
1407                  */
1408                 ttm_suspend_lock(&dev_priv->reservation_sem);
1409                 dev_priv->suspend_locked = true;
1410                 break;
1411         case PM_POST_HIBERNATION:
1412         case PM_POST_RESTORE:
1413                 if (READ_ONCE(dev_priv->suspend_locked)) {
1414                         dev_priv->suspend_locked = false;
1415                         ttm_suspend_unlock(&dev_priv->reservation_sem);
1416                 }
1417                 break;
1418         default:
1419                 break;
1420         }
1421         return 0;
1422 }
1423
1424 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1425 {
1426         struct drm_device *dev = pci_get_drvdata(pdev);
1427         struct vmw_private *dev_priv = vmw_priv(dev);
1428
1429         if (dev_priv->refuse_hibernation)
1430                 return -EBUSY;
1431
1432         pci_save_state(pdev);
1433         pci_disable_device(pdev);
1434         pci_set_power_state(pdev, PCI_D3hot);
1435         return 0;
1436 }
1437
1438 static int vmw_pci_resume(struct pci_dev *pdev)
1439 {
1440         pci_set_power_state(pdev, PCI_D0);
1441         pci_restore_state(pdev);
1442         return pci_enable_device(pdev);
1443 }
1444
1445 static int vmw_pm_suspend(struct device *kdev)
1446 {
1447         struct pci_dev *pdev = to_pci_dev(kdev);
1448         struct pm_message dummy;
1449
1450         dummy.event = 0;
1451
1452         return vmw_pci_suspend(pdev, dummy);
1453 }
1454
1455 static int vmw_pm_resume(struct device *kdev)
1456 {
1457         struct pci_dev *pdev = to_pci_dev(kdev);
1458
1459         return vmw_pci_resume(pdev);
1460 }
1461
1462 static int vmw_pm_freeze(struct device *kdev)
1463 {
1464         struct pci_dev *pdev = to_pci_dev(kdev);
1465         struct drm_device *dev = pci_get_drvdata(pdev);
1466         struct vmw_private *dev_priv = vmw_priv(dev);
1467         int ret;
1468
1469         /*
1470          * Unlock for vmw_kms_suspend.
1471          * No user-space processes should be running now.
1472          */
1473         ttm_suspend_unlock(&dev_priv->reservation_sem);
1474         ret = vmw_kms_suspend(dev_priv->dev);
1475         if (ret) {
1476                 ttm_suspend_lock(&dev_priv->reservation_sem);
1477                 DRM_ERROR("Failed to freeze modesetting.\n");
1478                 return ret;
1479         }
1480         if (dev_priv->enable_fb)
1481                 vmw_fb_off(dev_priv);
1482
1483         ttm_suspend_lock(&dev_priv->reservation_sem);
1484         vmw_execbuf_release_pinned_bo(dev_priv);
1485         vmw_resource_evict_all(dev_priv);
1486         vmw_release_device_early(dev_priv);
1487         ttm_bo_swapout_all(&dev_priv->bdev);
1488         if (dev_priv->enable_fb)
1489                 vmw_fifo_resource_dec(dev_priv);
1490         if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1491                 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1492                 if (dev_priv->enable_fb)
1493                         vmw_fifo_resource_inc(dev_priv);
1494                 WARN_ON(vmw_request_device_late(dev_priv));
1495                 dev_priv->suspend_locked = false;
1496                 ttm_suspend_unlock(&dev_priv->reservation_sem);
1497                 if (dev_priv->suspend_state)
1498                         vmw_kms_resume(dev);
1499                 if (dev_priv->enable_fb)
1500                         vmw_fb_on(dev_priv);
1501                 return -EBUSY;
1502         }
1503
1504         vmw_fence_fifo_down(dev_priv->fman);
1505         __vmw_svga_disable(dev_priv);
1506
1507         vmw_release_device_late(dev_priv);
1508         return 0;
1509 }
1510
1511 static int vmw_pm_restore(struct device *kdev)
1512 {
1513         struct pci_dev *pdev = to_pci_dev(kdev);
1514         struct drm_device *dev = pci_get_drvdata(pdev);
1515         struct vmw_private *dev_priv = vmw_priv(dev);
1516         int ret;
1517
1518         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1519         (void) vmw_read(dev_priv, SVGA_REG_ID);
1520
1521         if (dev_priv->enable_fb)
1522                 vmw_fifo_resource_inc(dev_priv);
1523
1524         ret = vmw_request_device(dev_priv);
1525         if (ret)
1526                 return ret;
1527
1528         if (dev_priv->enable_fb)
1529                 __vmw_svga_enable(dev_priv);
1530
1531         vmw_fence_fifo_up(dev_priv->fman);
1532         dev_priv->suspend_locked = false;
1533         ttm_suspend_unlock(&dev_priv->reservation_sem);
1534         if (dev_priv->suspend_state)
1535                 vmw_kms_resume(dev_priv->dev);
1536
1537         if (dev_priv->enable_fb)
1538                 vmw_fb_on(dev_priv);
1539
1540         return 0;
1541 }
1542
1543 static const struct dev_pm_ops vmw_pm_ops = {
1544         .freeze = vmw_pm_freeze,
1545         .thaw = vmw_pm_restore,
1546         .restore = vmw_pm_restore,
1547         .suspend = vmw_pm_suspend,
1548         .resume = vmw_pm_resume,
1549 };
1550
1551 static const struct file_operations vmwgfx_driver_fops = {
1552         .owner = THIS_MODULE,
1553         .open = drm_open,
1554         .release = drm_release,
1555         .unlocked_ioctl = vmw_unlocked_ioctl,
1556         .mmap = vmw_mmap,
1557         .poll = vmw_fops_poll,
1558         .read = vmw_fops_read,
1559 #if defined(CONFIG_COMPAT)
1560         .compat_ioctl = vmw_compat_ioctl,
1561 #endif
1562         .llseek = noop_llseek,
1563 };
1564
1565 static struct drm_driver driver = {
1566         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1567         DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC,
1568         .load = vmw_driver_load,
1569         .unload = vmw_driver_unload,
1570         .lastclose = vmw_lastclose,
1571         .get_vblank_counter = vmw_get_vblank_counter,
1572         .enable_vblank = vmw_enable_vblank,
1573         .disable_vblank = vmw_disable_vblank,
1574         .ioctls = vmw_ioctls,
1575         .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1576         .master_create = vmw_master_create,
1577         .master_destroy = vmw_master_destroy,
1578         .master_set = vmw_master_set,
1579         .master_drop = vmw_master_drop,
1580         .open = vmw_driver_open,
1581         .postclose = vmw_postclose,
1582
1583         .dumb_create = vmw_dumb_create,
1584         .dumb_map_offset = vmw_dumb_map_offset,
1585         .dumb_destroy = vmw_dumb_destroy,
1586
1587         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1588         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1589
1590         .fops = &vmwgfx_driver_fops,
1591         .name = VMWGFX_DRIVER_NAME,
1592         .desc = VMWGFX_DRIVER_DESC,
1593         .date = VMWGFX_DRIVER_DATE,
1594         .major = VMWGFX_DRIVER_MAJOR,
1595         .minor = VMWGFX_DRIVER_MINOR,
1596         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1597 };
1598
1599 static struct pci_driver vmw_pci_driver = {
1600         .name = VMWGFX_DRIVER_NAME,
1601         .id_table = vmw_pci_id_list,
1602         .probe = vmw_probe,
1603         .remove = vmw_remove,
1604         .driver = {
1605                 .pm = &vmw_pm_ops
1606         }
1607 };
1608
1609 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1610 {
1611         return drm_get_pci_dev(pdev, ent, &driver);
1612 }
1613
1614 static int __init vmwgfx_init(void)
1615 {
1616         int ret;
1617
1618         if (vgacon_text_force())
1619                 return -EINVAL;
1620
1621         ret = pci_register_driver(&vmw_pci_driver);
1622         if (ret)
1623                 DRM_ERROR("Failed initializing DRM.\n");
1624         return ret;
1625 }
1626
1627 static void __exit vmwgfx_exit(void)
1628 {
1629         pci_unregister_driver(&vmw_pci_driver);
1630 }
1631
1632 module_init(vmwgfx_init);
1633 module_exit(vmwgfx_exit);
1634
1635 MODULE_AUTHOR("VMware Inc. and others");
1636 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1637 MODULE_LICENSE("GPL and additional rights");
1638 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1639                __stringify(VMWGFX_DRIVER_MINOR) "."
1640                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1641                "0");