drivers/gpu/drm/vc4/vc4_hdmi.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /**
  21  * DOC: VC4 Falcon HDMI module
  22  *
  23  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  24  * the unit operates off of the HSM clock from CPRMAN.  It also
  25  * internally uses the PLLH_PIX clock for the PHY.
  26  *
  27  * HDMI infoframes are kept within a small packet ram, where each
  28  * packet can be individually enabled for including in a frame.
  29  *
  30  * HDMI audio is implemented entirely within the HDMI IP block.  A
  31  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  32  * and transfers them over an internal MAI (multi-channel audio
  33  * interconnect) bus to the encoder side for insertion into the video
  34  * blank regions.
  35  *
  36  * The driver's HDMI encoder does not yet support power management.
  37  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  38  * continuously running, and only the HDMI logic and packet ram are
  39  * powered off/on at disable/enable time.
  40  *
  41  * The driver does not yet support CEC control, though the HDMI
  42  * encoder block has CEC support.
  43  */
  44
  45 #include <drm/drm_atomic_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_edid.h>
  48 #include <linux/clk.h>
  49 #include <linux/component.h>
  50 #include <linux/i2c.h>
  51 #include <linux/of_address.h>
  52 #include <linux/of_gpio.h>
  53 #include <linux/of_platform.h>
  54 #include <linux/pm_runtime.h>
  55 #include <linux/rational.h>
  56 #include <sound/dmaengine_pcm.h>
  57 #include <sound/pcm_drm_eld.h>
  58 #include <sound/pcm_params.h>
  59 #include <sound/soc.h>
  60 #include "media/cec.h"
  61 #include "vc4_drv.h"
  62 #include "vc4_regs.h"
  63
  64 #define HSM_CLOCK_FREQ 163682864
  65 #define CEC_CLOCK_FREQ 40000
  66 #define CEC_CLOCK_DIV  (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
  67
  68 /* HDMI audio information */
  69 struct vc4_hdmi_audio {
  70         struct snd_soc_card card;
  71         struct snd_soc_dai_link link;
  72         int samplerate;
  73         int channels;
  74         struct snd_dmaengine_dai_dma_data dma_data;
  75         struct snd_pcm_substream *substream;
  76 };
  77
  78 /* General HDMI hardware state. */
  79 struct vc4_hdmi {
  80         struct platform_device *pdev;
  81
  82         struct drm_encoder *encoder;
  83         struct drm_connector *connector;
  84
  85         struct vc4_hdmi_audio audio;
  86
  87         struct i2c_adapter *ddc;
  88         void __iomem *hdmicore_regs;
  89         void __iomem *hd_regs;
  90         int hpd_gpio;
  91         bool hpd_active_low;
  92
  93         struct cec_adapter *cec_adap;
  94         struct cec_msg cec_rx_msg;
  95         bool cec_tx_ok;
  96         bool cec_irq_was_rx;
  97
  98         struct clk *pixel_clock;
  99         struct clk *hsm_clock;
 100 };
 101
 102 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
 103 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
 104 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
 105 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
 106
 107 /* VC4 HDMI encoder KMS struct */
 108 struct vc4_hdmi_encoder {
 109         struct vc4_encoder base;
 110         bool hdmi_monitor;
 111         bool limited_rgb_range;
 112         bool rgb_range_selectable;
 113 };
 114
 115 static inline struct vc4_hdmi_encoder *
 116 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
 117 {
 118         return container_of(encoder, struct vc4_hdmi_encoder, base.base);
 119 }
 120
 121 /* VC4 HDMI connector KMS struct */
 122 struct vc4_hdmi_connector {
 123         struct drm_connector base;
 124
 125         /* Since the connector is attached to just the one encoder,
 126          * this is the reference to it so we can do the best_encoder()
 127          * hook.
 128          */
 129         struct drm_encoder *encoder;
 130 };
 131
 132 static inline struct vc4_hdmi_connector *
 133 to_vc4_hdmi_connector(struct drm_connector *connector)
 134 {
 135         return container_of(connector, struct vc4_hdmi_connector, base);
 136 }
 137
 138 #define HDMI_REG(reg) { reg, #reg }
 139 static const struct {
 140         u32 reg;
 141         const char *name;
 142 } hdmi_regs[] = {
 143         HDMI_REG(VC4_HDMI_CORE_REV),
 144         HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
 145         HDMI_REG(VC4_HDMI_HOTPLUG_INT),
 146         HDMI_REG(VC4_HDMI_HOTPLUG),
 147         HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP),
 148         HDMI_REG(VC4_HDMI_MAI_CONFIG),
 149         HDMI_REG(VC4_HDMI_MAI_FORMAT),
 150         HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG),
 151         HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
 152         HDMI_REG(VC4_HDMI_HORZA),
 153         HDMI_REG(VC4_HDMI_HORZB),
 154         HDMI_REG(VC4_HDMI_FIFO_CTL),
 155         HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
 156         HDMI_REG(VC4_HDMI_VERTA0),
 157         HDMI_REG(VC4_HDMI_VERTA1),
 158         HDMI_REG(VC4_HDMI_VERTB0),
 159         HDMI_REG(VC4_HDMI_VERTB1),
 160         HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
 161         HDMI_REG(VC4_HDMI_TX_PHY_CTL0),
 162
 163         HDMI_REG(VC4_HDMI_CEC_CNTRL_1),
 164         HDMI_REG(VC4_HDMI_CEC_CNTRL_2),
 165         HDMI_REG(VC4_HDMI_CEC_CNTRL_3),
 166         HDMI_REG(VC4_HDMI_CEC_CNTRL_4),
 167         HDMI_REG(VC4_HDMI_CEC_CNTRL_5),
 168         HDMI_REG(VC4_HDMI_CPU_STATUS),
 169         HDMI_REG(VC4_HDMI_CPU_MASK_STATUS),
 170
 171         HDMI_REG(VC4_HDMI_CEC_RX_DATA_1),
 172         HDMI_REG(VC4_HDMI_CEC_RX_DATA_2),
 173         HDMI_REG(VC4_HDMI_CEC_RX_DATA_3),
 174         HDMI_REG(VC4_HDMI_CEC_RX_DATA_4),
 175         HDMI_REG(VC4_HDMI_CEC_TX_DATA_1),
 176         HDMI_REG(VC4_HDMI_CEC_TX_DATA_2),
 177         HDMI_REG(VC4_HDMI_CEC_TX_DATA_3),
 178         HDMI_REG(VC4_HDMI_CEC_TX_DATA_4),
 179 };
 180
 181 static const struct {
 182         u32 reg;
 183         const char *name;
 184 } hd_regs[] = {
 185         HDMI_REG(VC4_HD_M_CTL),
 186         HDMI_REG(VC4_HD_MAI_CTL),
 187         HDMI_REG(VC4_HD_MAI_THR),
 188         HDMI_REG(VC4_HD_MAI_FMT),
 189         HDMI_REG(VC4_HD_MAI_SMP),
 190         HDMI_REG(VC4_HD_VID_CTL),
 191         HDMI_REG(VC4_HD_CSC_CTL),
 192         HDMI_REG(VC4_HD_FRAME_COUNT),
 193 };
 194
 195 #ifdef CONFIG_DEBUG_FS
 196 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 197 {
 198         struct drm_info_node *node = (struct drm_info_node *)m->private;
 199         struct drm_device *dev = node->minor->dev;
 200         struct vc4_dev *vc4 = to_vc4_dev(dev);
 201         int i;
 202
 203         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 204                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 205                            hdmi_regs[i].name, hdmi_regs[i].reg,
 206                            HDMI_READ(hdmi_regs[i].reg));
 207         }
 208
 209         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 210                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 211                            hd_regs[i].name, hd_regs[i].reg,
 212                            HD_READ(hd_regs[i].reg));
 213         }
 214
 215         return 0;
 216 }
 217 #endif /* CONFIG_DEBUG_FS */
 218
 219 static void vc4_hdmi_dump_regs(struct drm_device *dev)
 220 {
 221         struct vc4_dev *vc4 = to_vc4_dev(dev);
 222         int i;
 223
 224         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 225                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 226                          hdmi_regs[i].reg, hdmi_regs[i].name,
 227                          HDMI_READ(hdmi_regs[i].reg));
 228         }
 229         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 230                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 231                          hd_regs[i].reg, hd_regs[i].name,
 232                          HD_READ(hd_regs[i].reg));
 233         }
 234 }
 235
 236 static enum drm_connector_status
 237 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 238 {
 239         struct drm_device *dev = connector->dev;
 240         struct vc4_dev *vc4 = to_vc4_dev(dev);
 241
 242         if (vc4->hdmi->hpd_gpio) {
 243                 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
 244                     vc4->hdmi->hpd_active_low)
 245                         return connector_status_connected;
 246                 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
 247                 return connector_status_disconnected;
 248         }
 249
 250         if (drm_probe_ddc(vc4->hdmi->ddc))
 251                 return connector_status_connected;
 252
 253         if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 254                 return connector_status_connected;
 255         cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
 256         return connector_status_disconnected;
 257 }
 258
 259 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 260 {
 261         drm_connector_unregister(connector);
 262         drm_connector_cleanup(connector);
 263 }
 264
 265 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 266 {
 267         struct vc4_hdmi_connector *vc4_connector =
 268                 to_vc4_hdmi_connector(connector);
 269         struct drm_encoder *encoder = vc4_connector->encoder;
 270         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 271         struct drm_device *dev = connector->dev;
 272         struct vc4_dev *vc4 = to_vc4_dev(dev);
 273         int ret = 0;
 274         struct edid *edid;
 275
 276         edid = drm_get_edid(connector, vc4->hdmi->ddc);
 277         cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
 278         if (!edid)
 279                 return -ENODEV;
 280
 281         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 282
 283         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
 284                 vc4_encoder->rgb_range_selectable =
 285                         drm_rgb_quant_range_selectable(edid);
 286         }
 287
 288         drm_mode_connector_update_edid_property(connector, edid);
 289         ret = drm_add_edid_modes(connector, edid);
 290         drm_edid_to_eld(connector, edid);
 291         kfree(edid);
 292
 293         return ret;
 294 }
 295
 296 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 297         .detect = vc4_hdmi_connector_detect,
 298         .fill_modes = drm_helper_probe_single_connector_modes,
 299         .destroy = vc4_hdmi_connector_destroy,
 300         .reset = drm_atomic_helper_connector_reset,
 301         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 302         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 303 };
 304
 305 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 306         .get_modes = vc4_hdmi_connector_get_modes,
 307 };
 308
 309 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
 310                                                      struct drm_encoder *encoder)
 311 {
 312         struct drm_connector *connector;
 313         struct vc4_hdmi_connector *hdmi_connector;
 314
 315         hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
 316                                       GFP_KERNEL);
 317         if (!hdmi_connector)
 318                 return ERR_PTR(-ENOMEM);
 319         connector = &hdmi_connector->base;
 320
 321         hdmi_connector->encoder = encoder;
 322
 323         drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
 324                            DRM_MODE_CONNECTOR_HDMIA);
 325         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 326
 327         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 328                              DRM_CONNECTOR_POLL_DISCONNECT);
 329
 330         connector->interlace_allowed = 1;
 331         connector->doublescan_allowed = 0;
 332
 333         drm_mode_connector_attach_encoder(connector, encoder);
 334
 335         return connector;
 336 }
 337
 338 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
 339 {
 340         drm_encoder_cleanup(encoder);
 341 }
 342
 343 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
 344         .destroy = vc4_hdmi_encoder_destroy,
 345 };
 346
 347 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 348                                 enum hdmi_infoframe_type type)
 349 {
 350         struct drm_device *dev = encoder->dev;
 351         struct vc4_dev *vc4 = to_vc4_dev(dev);
 352         u32 packet_id = type - 0x80;
 353
 354         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 355                    HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 356
 357         return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
 358                           BIT(packet_id)), 100);
 359 }
 360
 361 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 362                                      union hdmi_infoframe *frame)
 363 {
 364         struct drm_device *dev = encoder->dev;
 365         struct vc4_dev *vc4 = to_vc4_dev(dev);
 366         u32 packet_id = frame->any.type - 0x80;
 367         u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
 368         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 369         ssize_t len, i;
 370         int ret;
 371
 372         WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 373                     VC4_HDMI_RAM_PACKET_ENABLE),
 374                   "Packet RAM has to be on to store the packet.");
 375
 376         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 377         if (len < 0)
 378                 return;
 379
 380         ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
 381         if (ret) {
 382                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 383                 return;
 384         }
 385
 386         for (i = 0; i < len; i += 7) {
 387                 HDMI_WRITE(packet_reg,
 388                            buffer[i + 0] << 0 |
 389                            buffer[i + 1] << 8 |
 390                            buffer[i + 2] << 16);
 391                 packet_reg += 4;
 392
 393                 HDMI_WRITE(packet_reg,
 394                            buffer[i + 3] << 0 |
 395                            buffer[i + 4] << 8 |
 396                            buffer[i + 5] << 16 |
 397                            buffer[i + 6] << 24);
 398                 packet_reg += 4;
 399         }
 400
 401         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 402                    HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 403         ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
 404                         BIT(packet_id)), 100);
 405         if (ret)
 406                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 407 }
 408
 409 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 410 {
 411         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 412         struct drm_crtc *crtc = encoder->crtc;
 413         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 414         union hdmi_infoframe frame;
 415         int ret;
 416
 417         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
 418         if (ret < 0) {
 419                 DRM_ERROR("couldn't fill AVI infoframe\n");
 420                 return;
 421         }
 422
 423         drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode,
 424                                            vc4_encoder->limited_rgb_range ?
 425                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 426                                            HDMI_QUANTIZATION_RANGE_FULL,
 427                                            vc4_encoder->rgb_range_selectable);
 428
 429         vc4_hdmi_write_infoframe(encoder, &frame);
 430 }
 431
 432 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 433 {
 434         union hdmi_infoframe frame;
 435         int ret;
 436
 437         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 438         if (ret < 0) {
 439                 DRM_ERROR("couldn't fill SPD infoframe\n");
 440                 return;
 441         }
 442
 443         frame.spd.sdi = HDMI_SPD_SDI_PC;
 444
 445         vc4_hdmi_write_infoframe(encoder, &frame);
 446 }
 447
 448 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 449 {
 450         struct drm_device *drm = encoder->dev;
 451         struct vc4_dev *vc4 = drm->dev_private;
 452         struct vc4_hdmi *hdmi = vc4->hdmi;
 453         union hdmi_infoframe frame;
 454         int ret;
 455
 456         ret = hdmi_audio_infoframe_init(&frame.audio);
 457
 458         frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
 459         frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
 460         frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
 461         frame.audio.channels = hdmi->audio.channels;
 462
 463         vc4_hdmi_write_infoframe(encoder, &frame);
 464 }
 465
 466 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 467 {
 468         vc4_hdmi_set_avi_infoframe(encoder);
 469         vc4_hdmi_set_spd_infoframe(encoder);
 470 }
 471
 472 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 473 {
 474         struct drm_device *dev = encoder->dev;
 475         struct vc4_dev *vc4 = to_vc4_dev(dev);
 476         struct vc4_hdmi *hdmi = vc4->hdmi;
 477         int ret;
 478
 479         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
 480
 481         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 482         HD_WRITE(VC4_HD_VID_CTL,
 483                  HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 484
 485         clk_disable_unprepare(hdmi->pixel_clock);
 486
 487         ret = pm_runtime_put(&hdmi->pdev->dev);
 488         if (ret < 0)
 489                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 490 }
 491
 492 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 493 {
 494         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 495         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 496         struct drm_device *dev = encoder->dev;
 497         struct vc4_dev *vc4 = to_vc4_dev(dev);
 498         struct vc4_hdmi *hdmi = vc4->hdmi;
 499         bool debug_dump_regs = false;
 500         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 501         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 502         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 503         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 504         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 505                                    VC4_HDMI_VERTA_VSP) |
 506                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 507                                    VC4_HDMI_VERTA_VFP) |
 508                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 509         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 510                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 511                                    VC4_HDMI_VERTB_VBP));
 512         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 513                           VC4_SET_FIELD(mode->crtc_vtotal -
 514                                         mode->crtc_vsync_end -
 515                                         interlaced,
 516                                         VC4_HDMI_VERTB_VBP));
 517         u32 csc_ctl;
 518         int ret;
 519
 520         ret = pm_runtime_get_sync(&hdmi->pdev->dev);
 521         if (ret < 0) {
 522                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 523                 return;
 524         }
 525
 526         ret = clk_set_rate(hdmi->pixel_clock,
 527                            mode->clock * 1000 *
 528                            ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
 529         if (ret) {
 530                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 531                 return;
 532         }
 533
 534         ret = clk_prepare_enable(hdmi->pixel_clock);
 535         if (ret) {
 536                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 537                 return;
 538         }
 539
 540         HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
 541                    VC4_HDMI_SW_RESET_HDMI |
 542                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 543
 544         HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
 545
 546         /* PHY should be in reset, like
 547          * vc4_hdmi_encoder_disable() does.
 548          */
 549         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 550
 551         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
 552
 553         if (debug_dump_regs) {
 554                 DRM_INFO("HDMI regs before:\n");
 555                 vc4_hdmi_dump_regs(dev);
 556         }
 557
 558         HD_WRITE(VC4_HD_VID_CTL, 0);
 559
 560         HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 561                    HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 562                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 563                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 564
 565         HDMI_WRITE(VC4_HDMI_HORZA,
 566                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 567                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 568                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 569                                  VC4_HDMI_HORZA_HAP));
 570
 571         HDMI_WRITE(VC4_HDMI_HORZB,
 572                    VC4_SET_FIELD((mode->htotal -
 573                                   mode->hsync_end) * pixel_rep,
 574                                  VC4_HDMI_HORZB_HBP) |
 575                    VC4_SET_FIELD((mode->hsync_end -
 576                                   mode->hsync_start) * pixel_rep,
 577                                  VC4_HDMI_HORZB_HSP) |
 578                    VC4_SET_FIELD((mode->hsync_start -
 579                                   mode->hdisplay) * pixel_rep,
 580                                  VC4_HDMI_HORZB_HFP));
 581
 582         HDMI_WRITE(VC4_HDMI_VERTA0, verta);
 583         HDMI_WRITE(VC4_HDMI_VERTA1, verta);
 584
 585         HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
 586         HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
 587
 588         HD_WRITE(VC4_HD_VID_CTL,
 589                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 590                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 591
 592         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 593                                 VC4_HD_CSC_CTL_ORDER);
 594
 595         if (vc4_encoder->hdmi_monitor &&
 596             drm_default_rgb_quant_range(mode) ==
 597             HDMI_QUANTIZATION_RANGE_LIMITED) {
 598                 /* CEA VICs other than #1 requre limited range RGB
 599                  * output unless overridden by an AVI infoframe.
 600                  * Apply a colorspace conversion to squash 0-255 down
 601                  * to 16-235.  The matrix here is:
 602                  *
 603                  * [ 0      0      0.8594 16]
 604                  * [ 0      0.8594 0      16]
 605                  * [ 0.8594 0      0      16]
 606                  * [ 0      0      0       1]
 607                  */
 608                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 609                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 610                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 611                                          VC4_HD_CSC_CTL_MODE);
 612
 613                 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
 614                 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
 615                 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
 616                 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
 617                 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
 618                 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
 619                 vc4_encoder->limited_rgb_range = true;
 620         } else {
 621                 vc4_encoder->limited_rgb_range = false;
 622         }
 623
 624         /* The RGB order applies even when CSC is disabled. */
 625         HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
 626
 627         HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 628
 629         if (debug_dump_regs) {
 630                 DRM_INFO("HDMI regs after:\n");
 631                 vc4_hdmi_dump_regs(dev);
 632         }
 633
 634         HD_WRITE(VC4_HD_VID_CTL,
 635                  HD_READ(VC4_HD_VID_CTL) |
 636                  VC4_HD_VID_CTL_ENABLE |
 637                  VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 638                  VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
 639
 640         if (vc4_encoder->hdmi_monitor) {
 641                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 642                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 643                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 644
 645                 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 646                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 647                 WARN_ONCE(ret, "Timeout waiting for "
 648                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 649         } else {
 650                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 651                            HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 652                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 653                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 654                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 655                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 656
 657                 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 658                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 659                 WARN_ONCE(ret, "Timeout waiting for "
 660                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 661         }
 662
 663         if (vc4_encoder->hdmi_monitor) {
 664                 u32 drift;
 665
 666                 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 667                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 668                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 669                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 670                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 671
 672                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 673                            VC4_HDMI_RAM_PACKET_ENABLE);
 674
 675                 vc4_hdmi_set_infoframes(encoder);
 676
 677                 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
 678                 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 679
 680                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 681                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 682                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 683                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 684                 udelay(1000);
 685                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 686                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 687                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 688                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 689
 690                 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
 691                                VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 692                 WARN_ONCE(ret, "Timeout waiting for "
 693                           "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 694         }
 695 }
 696
 697 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 698         .disable = vc4_hdmi_encoder_disable,
 699         .enable = vc4_hdmi_encoder_enable,
 700 };
 701
 702 /* HDMI audio codec callbacks */
 703 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
 704 {
 705         struct drm_device *drm = hdmi->encoder->dev;
 706         struct vc4_dev *vc4 = to_vc4_dev(drm);
 707         u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
 708         unsigned long n, m;
 709
 710         rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
 711                                     VC4_HD_MAI_SMP_N_MASK >>
 712                                     VC4_HD_MAI_SMP_N_SHIFT,
 713                                     (VC4_HD_MAI_SMP_M_MASK >>
 714                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
 715                                     &n, &m);
 716
 717         HD_WRITE(VC4_HD_MAI_SMP,
 718                  VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
 719                  VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
 720 }
 721
 722 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
 723 {
 724         struct drm_encoder *encoder = hdmi->encoder;
 725         struct drm_crtc *crtc = encoder->crtc;
 726         struct drm_device *drm = encoder->dev;
 727         struct vc4_dev *vc4 = to_vc4_dev(drm);
 728         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 729         u32 samplerate = hdmi->audio.samplerate;
 730         u32 n, cts;
 731         u64 tmp;
 732
 733         n = 128 * samplerate / 1000;
 734         tmp = (u64)(mode->clock * 1000) * n;
 735         do_div(tmp, 128 * samplerate);
 736         cts = tmp;
 737
 738         HDMI_WRITE(VC4_HDMI_CRP_CFG,
 739                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
 740                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
 741
 742         /*
 743          * We could get slightly more accurate clocks in some cases by
 744          * providing a CTS_1 value.  The two CTS values are alternated
 745          * between based on the period fields
 746          */
 747         HDMI_WRITE(VC4_HDMI_CTS_0, cts);
 748         HDMI_WRITE(VC4_HDMI_CTS_1, cts);
 749 }
 750
 751 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
 752 {
 753         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
 754
 755         return snd_soc_card_get_drvdata(card);
 756 }
 757
 758 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
 759                                   struct snd_soc_dai *dai)
 760 {
 761         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 762         struct drm_encoder *encoder = hdmi->encoder;
 763         struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
 764         int ret;
 765
 766         if (hdmi->audio.substream && hdmi->audio.substream != substream)
 767                 return -EINVAL;
 768
 769         hdmi->audio.substream = substream;
 770
 771         /*
 772          * If the HDMI encoder hasn't probed, or the encoder is
 773          * currently in DVI mode, treat the codec dai as missing.
 774          */
 775         if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 776                                 VC4_HDMI_RAM_PACKET_ENABLE))
 777                 return -ENODEV;
 778
 779         ret = snd_pcm_hw_constraint_eld(substream->runtime,
 780                                         hdmi->connector->eld);
 781         if (ret)
 782                 return ret;
 783
 784         return 0;
 785 }
 786
 787 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 788 {
 789         return 0;
 790 }
 791
 792 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
 793 {
 794         struct drm_encoder *encoder = hdmi->encoder;
 795         struct drm_device *drm = encoder->dev;
 796         struct device *dev = &hdmi->pdev->dev;
 797         struct vc4_dev *vc4 = to_vc4_dev(drm);
 798         int ret;
 799
 800         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
 801         if (ret)
 802                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
 803
 804         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
 805         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
 806         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
 807 }
 808
 809 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
 810                                     struct snd_soc_dai *dai)
 811 {
 812         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 813
 814         if (substream != hdmi->audio.substream)
 815                 return;
 816
 817         vc4_hdmi_audio_reset(hdmi);
 818
 819         hdmi->audio.substream = NULL;
 820 }
 821
 822 /* HDMI audio codec callbacks */
 823 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
 824                                     struct snd_pcm_hw_params *params,
 825                                     struct snd_soc_dai *dai)
 826 {
 827         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 828         struct drm_encoder *encoder = hdmi->encoder;
 829         struct drm_device *drm = encoder->dev;
 830         struct device *dev = &hdmi->pdev->dev;
 831         struct vc4_dev *vc4 = to_vc4_dev(drm);
 832         u32 audio_packet_config, channel_mask;
 833         u32 channel_map, i;
 834
 835         if (substream != hdmi->audio.substream)
 836                 return -EINVAL;
 837
 838         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
 839                 params_rate(params), params_width(params),
 840                 params_channels(params));
 841
 842         hdmi->audio.channels = params_channels(params);
 843         hdmi->audio.samplerate = params_rate(params);
 844
 845         HD_WRITE(VC4_HD_MAI_CTL,
 846                  VC4_HD_MAI_CTL_RESET |
 847                  VC4_HD_MAI_CTL_FLUSH |
 848                  VC4_HD_MAI_CTL_DLATE |
 849                  VC4_HD_MAI_CTL_ERRORE |
 850                  VC4_HD_MAI_CTL_ERRORF);
 851
 852         vc4_hdmi_audio_set_mai_clock(hdmi);
 853
 854         audio_packet_config =
 855                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
 856                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
 857                 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
 858
 859         channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
 860         audio_packet_config |= VC4_SET_FIELD(channel_mask,
 861                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
 862
 863         /* Set the MAI threshold.  This logic mimics the firmware's. */
 864         if (hdmi->audio.samplerate > 96000) {
 865                 HD_WRITE(VC4_HD_MAI_THR,
 866                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
 867                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 868         } else if (hdmi->audio.samplerate > 48000) {
 869                 HD_WRITE(VC4_HD_MAI_THR,
 870                          VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
 871                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 872         } else {
 873                 HD_WRITE(VC4_HD_MAI_THR,
 874                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
 875                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
 876                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
 877                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
 878         }
 879
 880         HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
 881                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
 882                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
 883
 884         channel_map = 0;
 885         for (i = 0; i < 8; i++) {
 886                 if (channel_mask & BIT(i))
 887                         channel_map |= i << (3 * i);
 888         }
 889
 890         HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
 891         HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
 892         vc4_hdmi_set_n_cts(hdmi);
 893
 894         return 0;
 895 }
 896
 897 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
 898                                   struct snd_soc_dai *dai)
 899 {
 900         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 901         struct drm_encoder *encoder = hdmi->encoder;
 902         struct drm_device *drm = encoder->dev;
 903         struct vc4_dev *vc4 = to_vc4_dev(drm);
 904
 905         switch (cmd) {
 906         case SNDRV_PCM_TRIGGER_START:
 907                 vc4_hdmi_set_audio_infoframe(encoder);
 908                 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
 909                            HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
 910                            ~VC4_HDMI_TX_PHY_RNG_PWRDN);
 911                 HD_WRITE(VC4_HD_MAI_CTL,
 912                          VC4_SET_FIELD(hdmi->audio.channels,
 913                                        VC4_HD_MAI_CTL_CHNUM) |
 914                          VC4_HD_MAI_CTL_ENABLE);
 915                 break;
 916         case SNDRV_PCM_TRIGGER_STOP:
 917                 HD_WRITE(VC4_HD_MAI_CTL,
 918                          VC4_HD_MAI_CTL_DLATE |
 919                          VC4_HD_MAI_CTL_ERRORE |
 920                          VC4_HD_MAI_CTL_ERRORF);
 921                 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
 922                            HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
 923                            VC4_HDMI_TX_PHY_RNG_PWRDN);
 924                 break;
 925         default:
 926                 break;
 927         }
 928
 929         return 0;
 930 }
 931
 932 static inline struct vc4_hdmi *
 933 snd_component_to_hdmi(struct snd_soc_component *component)
 934 {
 935         struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
 936
 937         return snd_soc_card_get_drvdata(card);
 938 }
 939
 940 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
 941                                        struct snd_ctl_elem_info *uinfo)
 942 {
 943         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 944         struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
 945
 946         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 947         uinfo->count = sizeof(hdmi->connector->eld);
 948
 949         return 0;
 950 }
 951
 952 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
 953                                       struct snd_ctl_elem_value *ucontrol)
 954 {
 955         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 956         struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
 957
 958         memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
 959                sizeof(hdmi->connector->eld));
 960
 961         return 0;
 962 }
 963
 964 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
 965         {
 966                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
 967                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 968                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 969                 .name = "ELD",
 970                 .info = vc4_hdmi_audio_eld_ctl_info,
 971                 .get = vc4_hdmi_audio_eld_ctl_get,
 972         },
 973 };
 974
 975 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
 976         SND_SOC_DAPM_OUTPUT("TX"),
 977 };
 978
 979 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
 980         { "TX", NULL, "Playback" },
 981 };
 982
 983 static const struct snd_soc_codec_driver vc4_hdmi_audio_codec_drv = {
 984         .component_driver = {
 985                 .controls = vc4_hdmi_audio_controls,
 986                 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
 987                 .dapm_widgets = vc4_hdmi_audio_widgets,
 988                 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
 989                 .dapm_routes = vc4_hdmi_audio_routes,
 990                 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
 991         },
 992 };
 993
 994 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
 995         .startup = vc4_hdmi_audio_startup,
 996         .shutdown = vc4_hdmi_audio_shutdown,
 997         .hw_params = vc4_hdmi_audio_hw_params,
 998         .set_fmt = vc4_hdmi_audio_set_fmt,
 999         .trigger = vc4_hdmi_audio_trigger,
1000 };
1001
1002 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1003         .name = "vc4-hdmi-hifi",
1004         .playback = {
1005                 .stream_name = "Playback",
1006                 .channels_min = 2,
1007                 .channels_max = 8,
1008                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1009                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1010                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1011                          SNDRV_PCM_RATE_192000,
1012                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1013         },
1014 };
1015
1016 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1017         .name = "vc4-hdmi-cpu-dai-component",
1018 };
1019
1020 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1021 {
1022         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1023
1024         snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1025
1026         return 0;
1027 }
1028
1029 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1030         .name = "vc4-hdmi-cpu-dai",
1031         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1032         .playback = {
1033                 .stream_name = "Playback",
1034                 .channels_min = 1,
1035                 .channels_max = 8,
1036                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1037                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1038                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1039                          SNDRV_PCM_RATE_192000,
1040                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1041         },
1042         .ops = &vc4_hdmi_audio_dai_ops,
1043 };
1044
1045 static const struct snd_dmaengine_pcm_config pcm_conf = {
1046         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1047         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1048 };
1049
1050 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1051 {
1052         struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1053         struct snd_soc_card *card = &hdmi->audio.card;
1054         struct device *dev = &hdmi->pdev->dev;
1055         const __be32 *addr;
1056         int ret;
1057
1058         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1059                 dev_warn(dev,
1060                          "'dmas' DT property is missing, no HDMI audio\n");
1061                 return 0;
1062         }
1063
1064         /*
1065          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1066          * the bus address specified in the DT, because the physical address
1067          * (the one returned by platform_get_resource()) is not appropriate
1068          * for DMA transfers.
1069          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1070          */
1071         addr = of_get_address(dev->of_node, 1, NULL, NULL);
1072         hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1073         hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1074         hdmi->audio.dma_data.maxburst = 2;
1075
1076         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1077         if (ret) {
1078                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1079                 return ret;
1080         }
1081
1082         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1083                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1084         if (ret) {
1085                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1086                 return ret;
1087         }
1088
1089         /* register codec and codec dai */
1090         ret = snd_soc_register_codec(dev, &vc4_hdmi_audio_codec_drv,
1091                                      &vc4_hdmi_audio_codec_dai_drv, 1);
1092         if (ret) {
1093                 dev_err(dev, "Could not register codec: %d\n", ret);
1094                 return ret;
1095         }
1096
1097         dai_link->name = "MAI";
1098         dai_link->stream_name = "MAI PCM";
1099         dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1100         dai_link->cpu_dai_name = dev_name(dev);
1101         dai_link->codec_name = dev_name(dev);
1102         dai_link->platform_name = dev_name(dev);
1103
1104         card->dai_link = dai_link;
1105         card->num_links = 1;
1106         card->name = "vc4-hdmi";
1107         card->dev = dev;
1108
1109         /*
1110          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1111          * stores a pointer to the snd card object in dev->driver_data. This
1112          * means we cannot use it for something else. The hdmi back-pointer is
1113          * now stored in card->drvdata and should be retrieved with
1114          * snd_soc_card_get_drvdata() if needed.
1115          */
1116         snd_soc_card_set_drvdata(card, hdmi);
1117         ret = devm_snd_soc_register_card(dev, card);
1118         if (ret) {
1119                 dev_err(dev, "Could not register sound card: %d\n", ret);
1120                 goto unregister_codec;
1121         }
1122
1123         return 0;
1124
1125 unregister_codec:
1126         snd_soc_unregister_codec(dev);
1127
1128         return ret;
1129 }
1130
1131 static void vc4_hdmi_audio_cleanup(struct vc4_hdmi *hdmi)
1132 {
1133         struct device *dev = &hdmi->pdev->dev;
1134
1135         /*
1136          * If drvdata is not set this means the audio card was not
1137          * registered, just skip codec unregistration in this case.
1138          */
1139         if (dev_get_drvdata(dev))
1140                 snd_soc_unregister_codec(dev);
1141 }
1142
1143 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1144 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1145 {
1146         struct vc4_dev *vc4 = priv;
1147         struct vc4_hdmi *hdmi = vc4->hdmi;
1148
1149         if (hdmi->cec_irq_was_rx) {
1150                 if (hdmi->cec_rx_msg.len)
1151                         cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
1152         } else if (hdmi->cec_tx_ok) {
1153                 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
1154                                   0, 0, 0, 0);
1155         } else {
1156                 /*
1157                  * This CEC implementation makes 1 retry, so if we
1158                  * get a NACK, then that means it made 2 attempts.
1159                  */
1160                 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
1161                                   0, 2, 0, 0);
1162         }
1163         return IRQ_HANDLED;
1164 }
1165
1166 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
1167 {
1168         struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
1169         unsigned int i;
1170
1171         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1172                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1173         for (i = 0; i < msg->len; i += 4) {
1174                 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
1175
1176                 msg->msg[i] = val & 0xff;
1177                 msg->msg[i + 1] = (val >> 8) & 0xff;
1178                 msg->msg[i + 2] = (val >> 16) & 0xff;
1179                 msg->msg[i + 3] = (val >> 24) & 0xff;
1180         }
1181 }
1182
1183 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1184 {
1185         struct vc4_dev *vc4 = priv;
1186         struct vc4_hdmi *hdmi = vc4->hdmi;
1187         u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
1188         u32 cntrl1, cntrl5;
1189
1190         if (!(stat & VC4_HDMI_CPU_CEC))
1191                 return IRQ_NONE;
1192         hdmi->cec_rx_msg.len = 0;
1193         cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1194         cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1195         hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1196         if (hdmi->cec_irq_was_rx) {
1197                 vc4_cec_read_msg(vc4, cntrl1);
1198                 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1199                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1200                 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1201         } else {
1202                 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1203                 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1204         }
1205         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1206         HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1207
1208         return IRQ_WAKE_THREAD;
1209 }
1210
1211 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1212 {
1213         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1214         /* clock period in microseconds */
1215         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1216         u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1217
1218         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1219                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1220                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1221         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1222                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1223
1224         if (enable) {
1225                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1226                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1227                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
1228                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
1229                          ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1230                          ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1231                          ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1232                          ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1233                          ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1234                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
1235                          ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1236                          ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1237                          ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1238                          ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1239                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
1240                          ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1241                          ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1242                          ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1243                          ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1244
1245                 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1246         } else {
1247                 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1248                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1249                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1250         }
1251         return 0;
1252 }
1253
1254 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1255 {
1256         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1257
1258         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
1259                    (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1260                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1261         return 0;
1262 }
1263
1264 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1265                                       u32 signal_free_time, struct cec_msg *msg)
1266 {
1267         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1268         u32 val;
1269         unsigned int i;
1270
1271         for (i = 0; i < msg->len; i += 4)
1272                 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
1273                            (msg->msg[i]) |
1274                            (msg->msg[i + 1] << 8) |
1275                            (msg->msg[i + 2] << 16) |
1276                            (msg->msg[i + 3] << 24));
1277
1278         val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1279         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1280         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1281         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1282         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1283         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1284
1285         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1286         return 0;
1287 }
1288
1289 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1290         .adap_enable = vc4_hdmi_cec_adap_enable,
1291         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1292         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1293 };
1294 #endif
1295
1296 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1297 {
1298         struct platform_device *pdev = to_platform_device(dev);
1299         struct drm_device *drm = dev_get_drvdata(master);
1300         struct vc4_dev *vc4 = drm->dev_private;
1301         struct vc4_hdmi *hdmi;
1302         struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1303         struct device_node *ddc_node;
1304         u32 value;
1305         int ret;
1306
1307         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1308         if (!hdmi)
1309                 return -ENOMEM;
1310
1311         vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1312                                         GFP_KERNEL);
1313         if (!vc4_hdmi_encoder)
1314                 return -ENOMEM;
1315         vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1316         hdmi->encoder = &vc4_hdmi_encoder->base.base;
1317
1318         hdmi->pdev = pdev;
1319         hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1320         if (IS_ERR(hdmi->hdmicore_regs))
1321                 return PTR_ERR(hdmi->hdmicore_regs);
1322
1323         hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1324         if (IS_ERR(hdmi->hd_regs))
1325                 return PTR_ERR(hdmi->hd_regs);
1326
1327         hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1328         if (IS_ERR(hdmi->pixel_clock)) {
1329                 DRM_ERROR("Failed to get pixel clock\n");
1330                 return PTR_ERR(hdmi->pixel_clock);
1331         }
1332         hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1333         if (IS_ERR(hdmi->hsm_clock)) {
1334                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1335                 return PTR_ERR(hdmi->hsm_clock);
1336         }
1337
1338         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1339         if (!ddc_node) {
1340                 DRM_ERROR("Failed to find ddc node in device tree\n");
1341                 return -ENODEV;
1342         }
1343
1344         hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1345         of_node_put(ddc_node);
1346         if (!hdmi->ddc) {
1347                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1348                 return -EPROBE_DEFER;
1349         }
1350
1351         /* This is the rate that is set by the firmware.  The number
1352          * needs to be a bit higher than the pixel clock rate
1353          * (generally 148.5Mhz).
1354          */
1355         ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
1356         if (ret) {
1357                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1358                 goto err_put_i2c;
1359         }
1360
1361         ret = clk_prepare_enable(hdmi->hsm_clock);
1362         if (ret) {
1363                 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1364                           ret);
1365                 goto err_put_i2c;
1366         }
1367
1368         /* Only use the GPIO HPD pin if present in the DT, otherwise
1369          * we'll use the HDMI core's register.
1370          */
1371         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1372                 enum of_gpio_flags hpd_gpio_flags;
1373
1374                 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1375                                                          "hpd-gpios", 0,
1376                                                          &hpd_gpio_flags);
1377                 if (hdmi->hpd_gpio < 0) {
1378                         ret = hdmi->hpd_gpio;
1379                         goto err_unprepare_hsm;
1380                 }
1381
1382                 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1383         }
1384
1385         vc4->hdmi = hdmi;
1386
1387         /* HDMI core must be enabled. */
1388         if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1389                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1390                 udelay(1);
1391                 HD_WRITE(VC4_HD_M_CTL, 0);
1392
1393                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1394         }
1395         pm_runtime_enable(dev);
1396
1397         drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
1398                          DRM_MODE_ENCODER_TMDS, NULL);
1399         drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1400
1401         hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
1402         if (IS_ERR(hdmi->connector)) {
1403                 ret = PTR_ERR(hdmi->connector);
1404                 goto err_destroy_encoder;
1405         }
1406 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1407         hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1408                                               vc4, "vc4",
1409                                               CEC_CAP_TRANSMIT |
1410                                               CEC_CAP_LOG_ADDRS |
1411                                               CEC_CAP_PASSTHROUGH |
1412                                               CEC_CAP_RC, 1);
1413         ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
1414         if (ret < 0)
1415                 goto err_destroy_conn;
1416         HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
1417         value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1418         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1419         /*
1420          * Set the logical address to Unregistered and set the clock
1421          * divider: the hsm_clock rate and this divider setting will
1422          * give a 40 kHz CEC clock.
1423          */
1424         value |= VC4_HDMI_CEC_ADDR_MASK |
1425                  (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1426         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
1427         ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1428                                         vc4_cec_irq_handler,
1429                                         vc4_cec_irq_handler_thread, 0,
1430                                         "vc4 hdmi cec", vc4);
1431         if (ret)
1432                 goto err_delete_cec_adap;
1433         ret = cec_register_adapter(hdmi->cec_adap, dev);
1434         if (ret < 0)
1435                 goto err_delete_cec_adap;
1436 #endif
1437
1438         ret = vc4_hdmi_audio_init(hdmi);
1439         if (ret)
1440                 goto err_destroy_encoder;
1441
1442         return 0;
1443
1444 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1445 err_delete_cec_adap:
1446         cec_delete_adapter(hdmi->cec_adap);
1447 err_destroy_conn:
1448         vc4_hdmi_connector_destroy(hdmi->connector);
1449 #endif
1450 err_destroy_encoder:
1451         vc4_hdmi_encoder_destroy(hdmi->encoder);
1452 err_unprepare_hsm:
1453         clk_disable_unprepare(hdmi->hsm_clock);
1454         pm_runtime_disable(dev);
1455 err_put_i2c:
1456         put_device(&hdmi->ddc->dev);
1457
1458         return ret;
1459 }
1460
1461 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1462                             void *data)
1463 {
1464         struct drm_device *drm = dev_get_drvdata(master);
1465         struct vc4_dev *vc4 = drm->dev_private;
1466         struct vc4_hdmi *hdmi = vc4->hdmi;
1467
1468         vc4_hdmi_audio_cleanup(hdmi);
1469         cec_unregister_adapter(hdmi->cec_adap);
1470         vc4_hdmi_connector_destroy(hdmi->connector);
1471         vc4_hdmi_encoder_destroy(hdmi->encoder);
1472
1473         clk_disable_unprepare(hdmi->hsm_clock);
1474         pm_runtime_disable(dev);
1475
1476         put_device(&hdmi->ddc->dev);
1477
1478         vc4->hdmi = NULL;
1479 }
1480
1481 static const struct component_ops vc4_hdmi_ops = {
1482         .bind   = vc4_hdmi_bind,
1483         .unbind = vc4_hdmi_unbind,
1484 };
1485
1486 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1487 {
1488         return component_add(&pdev->dev, &vc4_hdmi_ops);
1489 }
1490
1491 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1492 {
1493         component_del(&pdev->dev, &vc4_hdmi_ops);
1494         return 0;
1495 }
1496
1497 static const struct of_device_id vc4_hdmi_dt_match[] = {
1498         { .compatible = "brcm,bcm2835-hdmi" },
1499         {}
1500 };
1501
1502 struct platform_driver vc4_hdmi_driver = {
1503         .probe = vc4_hdmi_dev_probe,
1504         .remove = vc4_hdmi_dev_remove,
1505         .driver = {
1506                 .name = "vc4_hdmi",
1507                 .of_match_table = vc4_hdmi_dt_match,
1508         },
1509 };