drivers/gpu/drm/v3d/v3d_gem.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2014-2018 Broadcom */
   3
   4 #include <drm/drmP.h>
   5 #include <drm/drm_syncobj.h>
   6 #include <linux/module.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/pm_runtime.h>
   9 #include <linux/device.h>
  10 #include <linux/io.h>
  11 #include <linux/sched/signal.h>
  12
  13 #include "uapi/drm/v3d_drm.h"
  14 #include "v3d_drv.h"
  15 #include "v3d_regs.h"
  16 #include "v3d_trace.h"
  17
  18 static void
  19 v3d_init_core(struct v3d_dev *v3d, int core)
  20 {
  21         /* Set OVRTMUOUT, which means that the texture sampler uniform
  22          * configuration's tmu output type field is used, instead of
  23          * using the hardware default behavior based on the texture
  24          * type.  If you want the default behavior, you can still put
  25          * "2" in the indirect texture state's output_type field.
  26          */
  27         V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT);
  28
  29         /* Whenever we flush the L2T cache, we always want to flush
  30          * the whole thing.
  31          */
  32         V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0);
  33         V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0);
  34 }
  35
  36 /* Sets invariant state for the HW. */
  37 static void
  38 v3d_init_hw_state(struct v3d_dev *v3d)
  39 {
  40         v3d_init_core(v3d, 0);
  41 }
  42
  43 static void
  44 v3d_idle_axi(struct v3d_dev *v3d, int core)
  45 {
  46         V3D_CORE_WRITE(core, V3D_GMP_CFG, V3D_GMP_CFG_STOP_REQ);
  47
  48         if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS) &
  49                       (V3D_GMP_STATUS_RD_COUNT_MASK |
  50                        V3D_GMP_STATUS_WR_COUNT_MASK |
  51                        V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) {
  52                 DRM_ERROR("Failed to wait for safe GMP shutdown\n");
  53         }
  54 }
  55
  56 static void
  57 v3d_idle_gca(struct v3d_dev *v3d)
  58 {
  59         if (v3d->ver >= 41)
  60                 return;
  61
  62         V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN);
  63
  64         if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) &
  65                       V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) ==
  66                      V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) {
  67                 DRM_ERROR("Failed to wait for safe GCA shutdown\n");
  68         }
  69 }
  70
  71 static void
  72 v3d_reset_v3d(struct v3d_dev *v3d)
  73 {
  74         int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION);
  75
  76         if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) {
  77                 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0,
  78                                  V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT);
  79                 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0);
  80
  81                 /* GFXH-1383: The SW_INIT may cause a stray write to address 0
  82                  * of the unit, so reset it to its power-on value here.
  83                  */
  84                 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK);
  85         } else {
  86                 WARN_ON_ONCE(V3D_GET_FIELD(version,
  87                                            V3D_TOP_GR_BRIDGE_MAJOR) != 7);
  88                 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1,
  89                                  V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT);
  90                 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0);
  91         }
  92
  93         v3d_init_hw_state(v3d);
  94 }
  95
  96 void
  97 v3d_reset(struct v3d_dev *v3d)
  98 {
  99         struct drm_device *dev = &v3d->drm;
 100
 101         DRM_ERROR("Resetting GPU.\n");
 102         trace_v3d_reset_begin(dev);
 103
 104         /* XXX: only needed for safe powerdown, not reset. */
 105         if (false)
 106                 v3d_idle_axi(v3d, 0);
 107
 108         v3d_idle_gca(v3d);
 109         v3d_reset_v3d(v3d);
 110
 111         v3d_mmu_set_page_table(v3d);
 112         v3d_irq_reset(v3d);
 113
 114         trace_v3d_reset_end(dev);
 115 }
 116
 117 static void
 118 v3d_flush_l3(struct v3d_dev *v3d)
 119 {
 120         if (v3d->ver < 41) {
 121                 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL);
 122
 123                 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
 124                               gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH);
 125
 126                 if (v3d->ver < 33) {
 127                         V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
 128                                       gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH);
 129                 }
 130         }
 131 }
 132
 133 /* Invalidates the (read-only) L2 cache. */
 134 static void
 135 v3d_invalidate_l2(struct v3d_dev *v3d, int core)
 136 {
 137         V3D_CORE_WRITE(core, V3D_CTL_L2CACTL,
 138                        V3D_L2CACTL_L2CCLR |
 139                        V3D_L2CACTL_L2CENA);
 140 }
 141
 142 static void
 143 v3d_invalidate_l1td(struct v3d_dev *v3d, int core)
 144 {
 145         V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
 146         if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
 147                        V3D_L2TCACTL_L2TFLS), 100)) {
 148                 DRM_ERROR("Timeout waiting for L1T write combiner flush\n");
 149         }
 150 }
 151
 152 /* Invalidates texture L2 cachelines */
 153 static void
 154 v3d_flush_l2t(struct v3d_dev *v3d, int core)
 155 {
 156         v3d_invalidate_l1td(v3d, core);
 157
 158         V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
 159                        V3D_L2TCACTL_L2TFLS |
 160                        V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM));
 161         if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
 162                        V3D_L2TCACTL_L2TFLS), 100)) {
 163                 DRM_ERROR("Timeout waiting for L2T flush\n");
 164         }
 165 }
 166
 167 /* Invalidates the slice caches.  These are read-only caches. */
 168 static void
 169 v3d_invalidate_slices(struct v3d_dev *v3d, int core)
 170 {
 171         V3D_CORE_WRITE(core, V3D_CTL_SLCACTL,
 172                        V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) |
 173                        V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) |
 174                        V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
 175                        V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC));
 176 }
 177
 178 /* Invalidates texture L2 cachelines */
 179 static void
 180 v3d_invalidate_l2t(struct v3d_dev *v3d, int core)
 181 {
 182         V3D_CORE_WRITE(core,
 183                        V3D_CTL_L2TCACTL,
 184                        V3D_L2TCACTL_L2TFLS |
 185                        V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAR, V3D_L2TCACTL_FLM));
 186         if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
 187                        V3D_L2TCACTL_L2TFLS), 100)) {
 188                 DRM_ERROR("Timeout waiting for L2T invalidate\n");
 189         }
 190 }
 191
 192 void
 193 v3d_invalidate_caches(struct v3d_dev *v3d)
 194 {
 195         v3d_flush_l3(v3d);
 196
 197         v3d_invalidate_l2(v3d, 0);
 198         v3d_invalidate_slices(v3d, 0);
 199         v3d_flush_l2t(v3d, 0);
 200 }
 201
 202 void
 203 v3d_flush_caches(struct v3d_dev *v3d)
 204 {
 205         v3d_invalidate_l1td(v3d, 0);
 206         v3d_invalidate_l2t(v3d, 0);
 207 }
 208
 209 static void
 210 v3d_attach_object_fences(struct v3d_exec_info *exec)
 211 {
 212         struct dma_fence *out_fence = exec->render_done_fence;
 213         int i;
 214
 215         for (i = 0; i < exec->bo_count; i++) {
 216                 /* XXX: Use shared fences for read-only objects. */
 217                 reservation_object_add_excl_fence(exec->bo[i]->resv, out_fence);
 218         }
 219 }
 220
 221 static void
 222 v3d_unlock_bo_reservations(struct drm_device *dev,
 223                            struct v3d_exec_info *exec,
 224                            struct ww_acquire_ctx *acquire_ctx)
 225 {
 226         int i;
 227
 228         for (i = 0; i < exec->bo_count; i++)
 229                 ww_mutex_unlock(&exec->bo[i]->resv->lock);
 230
 231         ww_acquire_fini(acquire_ctx);
 232 }
 233
 234 /* Takes the reservation lock on all the BOs being referenced, so that
 235  * at queue submit time we can update the reservations.
 236  *
 237  * We don't lock the RCL the tile alloc/state BOs, or overflow memory
 238  * (all of which are on exec->unref_list).  They're entirely private
 239  * to v3d, so we don't attach dma-buf fences to them.
 240  */
 241 static int
 242 v3d_lock_bo_reservations(struct drm_device *dev,
 243                          struct v3d_exec_info *exec,
 244                          struct ww_acquire_ctx *acquire_ctx)
 245 {
 246         int contended_lock = -1;
 247         int i, ret;
 248
 249         ww_acquire_init(acquire_ctx, &reservation_ww_class);
 250
 251 retry:
 252         if (contended_lock != -1) {
 253                 struct v3d_bo *bo = exec->bo[contended_lock];
 254
 255                 ret = ww_mutex_lock_slow_interruptible(&bo->resv->lock,
 256                                                        acquire_ctx);
 257                 if (ret) {
 258                         ww_acquire_done(acquire_ctx);
 259                         return ret;
 260                 }
 261         }
 262
 263         for (i = 0; i < exec->bo_count; i++) {
 264                 if (i == contended_lock)
 265                         continue;
 266
 267                 ret = ww_mutex_lock_interruptible(&exec->bo[i]->resv->lock,
 268                                                   acquire_ctx);
 269                 if (ret) {
 270                         int j;
 271
 272                         for (j = 0; j < i; j++)
 273                                 ww_mutex_unlock(&exec->bo[j]->resv->lock);
 274
 275                         if (contended_lock != -1 && contended_lock >= i) {
 276                                 struct v3d_bo *bo = exec->bo[contended_lock];
 277
 278                                 ww_mutex_unlock(&bo->resv->lock);
 279                         }
 280
 281                         if (ret == -EDEADLK) {
 282                                 contended_lock = i;
 283                                 goto retry;
 284                         }
 285
 286                         ww_acquire_done(acquire_ctx);
 287                         return ret;
 288                 }
 289         }
 290
 291         ww_acquire_done(acquire_ctx);
 292
 293         /* Reserve space for our shared (read-only) fence references,
 294          * before we commit the CL to the hardware.
 295          */
 296         for (i = 0; i < exec->bo_count; i++) {
 297                 ret = reservation_object_reserve_shared(exec->bo[i]->resv, 1);
 298                 if (ret) {
 299                         v3d_unlock_bo_reservations(dev, exec, acquire_ctx);
 300                         return ret;
 301                 }
 302         }
 303
 304         return 0;
 305 }
 306
 307 /**
 308  * v3d_cl_lookup_bos() - Sets up exec->bo[] with the GEM objects
 309  * referenced by the job.
 310  * @dev: DRM device
 311  * @file_priv: DRM file for this fd
 312  * @exec: V3D job being set up
 313  *
 314  * The command validator needs to reference BOs by their index within
 315  * the submitted job's BO list.  This does the validation of the job's
 316  * BO list and reference counting for the lifetime of the job.
 317  *
 318  * Note that this function doesn't need to unreference the BOs on
 319  * failure, because that will happen at v3d_exec_cleanup() time.
 320  */
 321 static int
 322 v3d_cl_lookup_bos(struct drm_device *dev,
 323                   struct drm_file *file_priv,
 324                   struct drm_v3d_submit_cl *args,
 325                   struct v3d_exec_info *exec)
 326 {
 327         u32 *handles;
 328         int ret = 0;
 329         int i;
 330
 331         exec->bo_count = args->bo_handle_count;
 332
 333         if (!exec->bo_count) {
 334                 /* See comment on bo_index for why we have to check
 335                  * this.
 336                  */
 337                 DRM_DEBUG("Rendering requires BOs\n");
 338                 return -EINVAL;
 339         }
 340
 341         exec->bo = kvmalloc_array(exec->bo_count,
 342                                   sizeof(struct drm_gem_cma_object *),
 343                                   GFP_KERNEL | __GFP_ZERO);
 344         if (!exec->bo) {
 345                 DRM_DEBUG("Failed to allocate validated BO pointers\n");
 346                 return -ENOMEM;
 347         }
 348
 349         handles = kvmalloc_array(exec->bo_count, sizeof(u32), GFP_KERNEL);
 350         if (!handles) {
 351                 ret = -ENOMEM;
 352                 DRM_DEBUG("Failed to allocate incoming GEM handles\n");
 353                 goto fail;
 354         }
 355
 356         if (copy_from_user(handles,
 357                            (void __user *)(uintptr_t)args->bo_handles,
 358                            exec->bo_count * sizeof(u32))) {
 359                 ret = -EFAULT;
 360                 DRM_DEBUG("Failed to copy in GEM handles\n");
 361                 goto fail;
 362         }
 363
 364         spin_lock(&file_priv->table_lock);
 365         for (i = 0; i < exec->bo_count; i++) {
 366                 struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
 367                                                      handles[i]);
 368                 if (!bo) {
 369                         DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
 370                                   i, handles[i]);
 371                         ret = -ENOENT;
 372                         spin_unlock(&file_priv->table_lock);
 373                         goto fail;
 374                 }
 375                 drm_gem_object_get(bo);
 376                 exec->bo[i] = to_v3d_bo(bo);
 377         }
 378         spin_unlock(&file_priv->table_lock);
 379
 380 fail:
 381         kvfree(handles);
 382         return ret;
 383 }
 384
 385 static void
 386 v3d_exec_cleanup(struct kref *ref)
 387 {
 388         struct v3d_exec_info *exec = container_of(ref, struct v3d_exec_info,
 389                                                   refcount);
 390         struct v3d_dev *v3d = exec->v3d;
 391         unsigned int i;
 392         struct v3d_bo *bo, *save;
 393
 394         dma_fence_put(exec->bin.in_fence);
 395         dma_fence_put(exec->render.in_fence);
 396
 397         dma_fence_put(exec->bin.done_fence);
 398         dma_fence_put(exec->render.done_fence);
 399
 400         dma_fence_put(exec->bin_done_fence);
 401         dma_fence_put(exec->render_done_fence);
 402
 403         for (i = 0; i < exec->bo_count; i++)
 404                 drm_gem_object_put_unlocked(&exec->bo[i]->base);
 405         kvfree(exec->bo);
 406
 407         list_for_each_entry_safe(bo, save, &exec->unref_list, unref_head) {
 408                 drm_gem_object_put_unlocked(&bo->base);
 409         }
 410
 411         pm_runtime_mark_last_busy(v3d->dev);
 412         pm_runtime_put_autosuspend(v3d->dev);
 413
 414         kfree(exec);
 415 }
 416
 417 void v3d_exec_put(struct v3d_exec_info *exec)
 418 {
 419         kref_put(&exec->refcount, v3d_exec_cleanup);
 420 }
 421
 422 int
 423 v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
 424                   struct drm_file *file_priv)
 425 {
 426         int ret;
 427         struct drm_v3d_wait_bo *args = data;
 428         struct drm_gem_object *gem_obj;
 429         struct v3d_bo *bo;
 430         ktime_t start = ktime_get();
 431         u64 delta_ns;
 432         unsigned long timeout_jiffies =
 433                 nsecs_to_jiffies_timeout(args->timeout_ns);
 434
 435         if (args->pad != 0)
 436                 return -EINVAL;
 437
 438         gem_obj = drm_gem_object_lookup(file_priv, args->handle);
 439         if (!gem_obj) {
 440                 DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
 441                 return -EINVAL;
 442         }
 443         bo = to_v3d_bo(gem_obj);
 444
 445         ret = reservation_object_wait_timeout_rcu(bo->resv,
 446                                                   true, true,
 447                                                   timeout_jiffies);
 448
 449         if (ret == 0)
 450                 ret = -ETIME;
 451         else if (ret > 0)
 452                 ret = 0;
 453
 454         /* Decrement the user's timeout, in case we got interrupted
 455          * such that the ioctl will be restarted.
 456          */
 457         delta_ns = ktime_to_ns(ktime_sub(ktime_get(), start));
 458         if (delta_ns < args->timeout_ns)
 459                 args->timeout_ns -= delta_ns;
 460         else
 461                 args->timeout_ns = 0;
 462
 463         /* Asked to wait beyond the jiffie/scheduler precision? */
 464         if (ret == -ETIME && args->timeout_ns)
 465                 ret = -EAGAIN;
 466
 467         drm_gem_object_put_unlocked(gem_obj);
 468
 469         return ret;
 470 }
 471
 472 /**
 473  * v3d_submit_cl_ioctl() - Submits a job (frame) to the V3D.
 474  * @dev: DRM device
 475  * @data: ioctl argument
 476  * @file_priv: DRM file for this fd
 477  *
 478  * This is the main entrypoint for userspace to submit a 3D frame to
 479  * the GPU.  Userspace provides the binner command list (if
 480  * applicable), and the kernel sets up the render command list to draw
 481  * to the framebuffer described in the ioctl, using the command lists
 482  * that the 3D engine's binner will produce.
 483  */
 484 int
 485 v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
 486                     struct drm_file *file_priv)
 487 {
 488         struct v3d_dev *v3d = to_v3d_dev(dev);
 489         struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
 490         struct drm_v3d_submit_cl *args = data;
 491         struct v3d_exec_info *exec;
 492         struct ww_acquire_ctx acquire_ctx;
 493         struct drm_syncobj *sync_out;
 494         int ret = 0;
 495
 496         if (args->pad != 0) {
 497                 DRM_INFO("pad must be zero: %d\n", args->pad);
 498                 return -EINVAL;
 499         }
 500
 501         exec = kcalloc(1, sizeof(*exec), GFP_KERNEL);
 502         if (!exec)
 503                 return -ENOMEM;
 504
 505         ret = pm_runtime_get_sync(v3d->dev);
 506         if (ret < 0) {
 507                 kfree(exec);
 508                 return ret;
 509         }
 510
 511         kref_init(&exec->refcount);
 512
 513         ret = drm_syncobj_find_fence(file_priv, args->in_sync_bcl,
 514                                      0, 0, &exec->bin.in_fence);
 515         if (ret == -EINVAL)
 516                 goto fail;
 517
 518         ret = drm_syncobj_find_fence(file_priv, args->in_sync_rcl,
 519                                      0, 0, &exec->render.in_fence);
 520         if (ret == -EINVAL)
 521                 goto fail;
 522
 523         exec->qma = args->qma;
 524         exec->qms = args->qms;
 525         exec->qts = args->qts;
 526         exec->bin.exec = exec;
 527         exec->bin.start = args->bcl_start;
 528         exec->bin.end = args->bcl_end;
 529         exec->render.exec = exec;
 530         exec->render.start = args->rcl_start;
 531         exec->render.end = args->rcl_end;
 532         exec->v3d = v3d;
 533         INIT_LIST_HEAD(&exec->unref_list);
 534
 535         ret = v3d_cl_lookup_bos(dev, file_priv, args, exec);
 536         if (ret)
 537                 goto fail;
 538
 539         ret = v3d_lock_bo_reservations(dev, exec, &acquire_ctx);
 540         if (ret)
 541                 goto fail;
 542
 543         mutex_lock(&v3d->sched_lock);
 544         if (exec->bin.start != exec->bin.end) {
 545                 ret = drm_sched_job_init(&exec->bin.base,
 546                                          &v3d_priv->sched_entity[V3D_BIN],
 547                                          v3d_priv);
 548                 if (ret)
 549                         goto fail_unreserve;
 550
 551                 exec->bin_done_fence =
 552                         dma_fence_get(&exec->bin.base.s_fence->finished);
 553
 554                 kref_get(&exec->refcount); /* put by scheduler job completion */
 555                 drm_sched_entity_push_job(&exec->bin.base,
 556                                           &v3d_priv->sched_entity[V3D_BIN]);
 557         }
 558
 559         ret = drm_sched_job_init(&exec->render.base,
 560                                  &v3d_priv->sched_entity[V3D_RENDER],
 561                                  v3d_priv);
 562         if (ret)
 563                 goto fail_unreserve;
 564
 565         exec->render_done_fence =
 566                 dma_fence_get(&exec->render.base.s_fence->finished);
 567
 568         kref_get(&exec->refcount); /* put by scheduler job completion */
 569         drm_sched_entity_push_job(&exec->render.base,
 570                                   &v3d_priv->sched_entity[V3D_RENDER]);
 571         mutex_unlock(&v3d->sched_lock);
 572
 573         v3d_attach_object_fences(exec);
 574
 575         v3d_unlock_bo_reservations(dev, exec, &acquire_ctx);
 576
 577         /* Update the return sync object for the */
 578         sync_out = drm_syncobj_find(file_priv, args->out_sync);
 579         if (sync_out) {
 580                 drm_syncobj_replace_fence(sync_out, 0,
 581                                           exec->render_done_fence);
 582                 drm_syncobj_put(sync_out);
 583         }
 584
 585         v3d_exec_put(exec);
 586
 587         return 0;
 588
 589 fail_unreserve:
 590         mutex_unlock(&v3d->sched_lock);
 591         v3d_unlock_bo_reservations(dev, exec, &acquire_ctx);
 592 fail:
 593         v3d_exec_put(exec);
 594
 595         return ret;
 596 }
 597
 598 int
 599 v3d_gem_init(struct drm_device *dev)
 600 {
 601         struct v3d_dev *v3d = to_v3d_dev(dev);
 602         u32 pt_size = 4096 * 1024;
 603         int ret, i;
 604
 605         for (i = 0; i < V3D_MAX_QUEUES; i++)
 606                 v3d->queue[i].fence_context = dma_fence_context_alloc(1);
 607
 608         spin_lock_init(&v3d->mm_lock);
 609         spin_lock_init(&v3d->job_lock);
 610         mutex_init(&v3d->bo_lock);
 611         mutex_init(&v3d->reset_lock);
 612         mutex_init(&v3d->sched_lock);
 613
 614         /* Note: We don't allocate address 0.  Various bits of HW
 615          * treat 0 as special, such as the occlusion query counters
 616          * where 0 means "disabled".
 617          */
 618         drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1);
 619
 620         v3d->pt = dma_alloc_wc(v3d->dev, pt_size,
 621                                &v3d->pt_paddr,
 622                                GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
 623         if (!v3d->pt) {
 624                 drm_mm_takedown(&v3d->mm);
 625                 dev_err(v3d->dev,
 626                         "Failed to allocate page tables. "
 627                         "Please ensure you have CMA enabled.\n");
 628                 return -ENOMEM;
 629         }
 630
 631         v3d_init_hw_state(v3d);
 632         v3d_mmu_set_page_table(v3d);
 633
 634         ret = v3d_sched_init(v3d);
 635         if (ret) {
 636                 drm_mm_takedown(&v3d->mm);
 637                 dma_free_coherent(v3d->dev, 4096 * 1024, (void *)v3d->pt,
 638                                   v3d->pt_paddr);
 639         }
 640
 641         return 0;
 642 }
 643
 644 void
 645 v3d_gem_destroy(struct drm_device *dev)
 646 {
 647         struct v3d_dev *v3d = to_v3d_dev(dev);
 648
 649         v3d_sched_fini(v3d);
 650
 651         /* Waiting for exec to finish would need to be done before
 652          * unregistering V3D.
 653          */
 654         WARN_ON(v3d->bin_job);
 655         WARN_ON(v3d->render_job);
 656
 657         drm_mm_takedown(&v3d->mm);
 658
 659         dma_free_coherent(v3d->dev, 4096 * 1024, (void *)v3d->pt, v3d->pt_paddr);
 660 }