drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/delay.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/of_graph.h>
  21 #include <linux/pm_runtime.h>
  22
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_crtc.h>
  26 #include <drm/drm_fb_cma_helper.h>
  27 #include <drm/drm_fourcc.h>
  28 #include <drm/drm_gem_cma_helper.h>
  29 #include <drm/drm_modeset_helper_vtables.h>
  30 #include <drm/drm_print.h>
  31 #include <drm/drm_vblank.h>
  32
  33 #include "tilcdc_drv.h"
  34 #include "tilcdc_regs.h"
  35
  36 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US       1000
  37 #define TILCDC_PALETTE_SIZE                     32
  38 #define TILCDC_PALETTE_FIRST_ENTRY              0x4000
  39
  40 struct tilcdc_crtc {
  41         struct drm_crtc base;
  42
  43         struct drm_plane primary;
  44         const struct tilcdc_panel_info *info;
  45         struct drm_pending_vblank_event *event;
  46         struct mutex enable_lock;
  47         bool enabled;
  48         bool shutdown;
  49         wait_queue_head_t frame_done_wq;
  50         bool frame_done;
  51         spinlock_t irq_lock;
  52
  53         unsigned int lcd_fck_rate;
  54
  55         ktime_t last_vblank;
  56         unsigned int hvtotal_us;
  57
  58         struct drm_framebuffer *next_fb;
  59
  60         /* Only set if an external encoder is connected */
  61         bool simulate_vesa_sync;
  62
  63         int sync_lost_count;
  64         bool frame_intact;
  65         struct work_struct recover_work;
  66
  67         dma_addr_t palette_dma_handle;
  68         u16 *palette_base;
  69         struct completion palette_loaded;
  70 };
  71 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  72
  73 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
  74 {
  75         struct drm_device *dev = crtc->dev;
  76         struct tilcdc_drm_private *priv = dev->dev_private;
  77         struct drm_gem_cma_object *gem;
  78         dma_addr_t start, end;
  79         u64 dma_base_and_ceiling;
  80
  81         gem = drm_fb_cma_get_gem_obj(fb, 0);
  82
  83         start = gem->paddr + fb->offsets[0] +
  84                 crtc->y * fb->pitches[0] +
  85                 crtc->x * fb->format->cpp[0];
  86
  87         end = start + (crtc->mode.vdisplay * fb->pitches[0]);
  88
  89         /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG
  90          * with a single insruction, if available. This should make it more
  91          * unlikely that LCDC would fetch the DMA addresses in the middle of
  92          * an update.
  93          */
  94         if (priv->rev == 1)
  95                 end -= 1;
  96
  97         dma_base_and_ceiling = (u64)end << 32 | start;
  98         tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
  99 }
 100
 101 /*
 102  * The driver currently only supports only true color formats. For
 103  * true color the palette block is bypassed, but a 32 byte palette
 104  * should still be loaded. The first 16-bit entry must be 0x4000 while
 105  * all other entries must be zeroed.
 106  */
 107 static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)
 108 {
 109         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 110         struct drm_device *dev = crtc->dev;
 111         struct tilcdc_drm_private *priv = dev->dev_private;
 112         int ret;
 113
 114         reinit_completion(&tilcdc_crtc->palette_loaded);
 115
 116         /* Tell the LCDC where the palette is located. */
 117         tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,
 118                      tilcdc_crtc->palette_dma_handle);
 119         tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG,
 120                      (u32) tilcdc_crtc->palette_dma_handle +
 121                      TILCDC_PALETTE_SIZE - 1);
 122
 123         /* Set dma load mode for palette loading only. */
 124         tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
 125                           LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY),
 126                           LCDC_PALETTE_LOAD_MODE_MASK);
 127
 128         /* Enable DMA Palette Loaded Interrupt */
 129         if (priv->rev == 1)
 130                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
 131         else
 132                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA);
 133
 134         /* Enable LCDC DMA and wait for palette to be loaded. */
 135         tilcdc_clear_irqstatus(dev, 0xffffffff);
 136         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 137
 138         ret = wait_for_completion_timeout(&tilcdc_crtc->palette_loaded,
 139                                           msecs_to_jiffies(50));
 140         if (ret == 0)
 141                 dev_err(dev->dev, "%s: Palette loading timeout", __func__);
 142
 143         /* Disable LCDC DMA and DMA Palette Loaded Interrupt. */
 144         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 145         if (priv->rev == 1)
 146                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
 147         else
 148                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);
 149 }
 150
 151 static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
 152 {
 153         struct tilcdc_drm_private *priv = dev->dev_private;
 154
 155         tilcdc_clear_irqstatus(dev, 0xffffffff);
 156
 157         if (priv->rev == 1) {
 158                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
 159                         LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
 160                         LCDC_V1_UNDERFLOW_INT_ENA);
 161                 tilcdc_set(dev, LCDC_DMA_CTRL_REG,
 162                         LCDC_V1_END_OF_FRAME_INT_ENA);
 163         } else {
 164                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
 165                         LCDC_V2_UNDERFLOW_INT_ENA |
 166                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 167                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 168         }
 169 }
 170
 171 static void tilcdc_crtc_disable_irqs(struct drm_device *dev)
 172 {
 173         struct tilcdc_drm_private *priv = dev->dev_private;
 174
 175         /* disable irqs that we might have enabled: */
 176         if (priv->rev == 1) {
 177                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 178                         LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
 179                         LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
 180                 tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
 181                         LCDC_V1_END_OF_FRAME_INT_ENA);
 182         } else {
 183                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 184                         LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
 185                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 186                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 187         }
 188 }
 189
 190 static void reset(struct drm_crtc *crtc)
 191 {
 192         struct drm_device *dev = crtc->dev;
 193         struct tilcdc_drm_private *priv = dev->dev_private;
 194
 195         if (priv->rev != 2)
 196                 return;
 197
 198         tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 199         usleep_range(250, 1000);
 200         tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 201 }
 202
 203 /*
 204  * Calculate the percentage difference between the requested pixel clock rate
 205  * and the effective rate resulting from calculating the clock divider value.
 206  */
 207 static unsigned int tilcdc_pclk_diff(unsigned long rate,
 208                                      unsigned long real_rate)
 209 {
 210         int r = rate / 100, rr = real_rate / 100;
 211
 212         return (unsigned int)(abs(((rr - r) * 100) / r));
 213 }
 214
 215 static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
 216 {
 217         struct drm_device *dev = crtc->dev;
 218         struct tilcdc_drm_private *priv = dev->dev_private;
 219         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 220         unsigned long clk_rate, real_rate, req_rate;
 221         unsigned int clkdiv;
 222         int ret;
 223
 224         clkdiv = 2; /* first try using a standard divider of 2 */
 225
 226         /* mode.clock is in KHz, set_rate wants parameter in Hz */
 227         req_rate = crtc->mode.clock * 1000;
 228
 229         ret = clk_set_rate(priv->clk, req_rate * clkdiv);
 230         clk_rate = clk_get_rate(priv->clk);
 231         if (ret < 0 || tilcdc_pclk_diff(req_rate, clk_rate) > 5) {
 232                 /*
 233                  * If we fail to set the clock rate (some architectures don't
 234                  * use the common clock framework yet and may not implement
 235                  * all the clk API calls for every clock), try the next best
 236                  * thing: adjusting the clock divider, unless clk_get_rate()
 237                  * failed as well.
 238                  */
 239                 if (!clk_rate) {
 240                         /* Nothing more we can do. Just bail out. */
 241                         dev_err(dev->dev,
 242                                 "failed to set the pixel clock - unable to read current lcdc clock rate\n");
 243                         return;
 244                 }
 245
 246                 clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate);
 247
 248                 /*
 249                  * Emit a warning if the real clock rate resulting from the
 250                  * calculated divider differs much from the requested rate.
 251                  *
 252                  * 5% is an arbitrary value - LCDs are usually quite tolerant
 253                  * about pixel clock rates.
 254                  */
 255                 real_rate = clkdiv * req_rate;
 256
 257                 if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) {
 258                         dev_warn(dev->dev,
 259                                  "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n",
 260                                  clk_rate, real_rate);
 261                 }
 262         }
 263
 264         tilcdc_crtc->lcd_fck_rate = clk_rate;
 265
 266         DBG("lcd_clk=%u, mode clock=%d, div=%u",
 267             tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);
 268
 269         /* Configure the LCD clock divisor. */
 270         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
 271                      LCDC_RASTER_MODE);
 272
 273         if (priv->rev == 2)
 274                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 275                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 276                                 LCDC_V2_CORE_CLK_EN);
 277 }
 278
 279 static uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode)
 280 {
 281         return (uint) div_u64(1000llu * mode->htotal * mode->vtotal,
 282                               mode->clock);
 283 }
 284
 285 static void tilcdc_crtc_set_mode(struct drm_crtc *crtc)
 286 {
 287         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 288         struct drm_device *dev = crtc->dev;
 289         struct tilcdc_drm_private *priv = dev->dev_private;
 290         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 291         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 292         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 293         struct drm_framebuffer *fb = crtc->primary->state->fb;
 294
 295         if (WARN_ON(!info))
 296                 return;
 297
 298         if (WARN_ON(!fb))
 299                 return;
 300
 301         /* Configure the Burst Size and fifo threshold of DMA: */
 302         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 303         switch (info->dma_burst_sz) {
 304         case 1:
 305                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 306                 break;
 307         case 2:
 308                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 309                 break;
 310         case 4:
 311                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 312                 break;
 313         case 8:
 314                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 315                 break;
 316         case 16:
 317                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 318                 break;
 319         default:
 320                 dev_err(dev->dev, "invalid burst size\n");
 321                 return;
 322         }
 323         reg |= (info->fifo_th << 8);
 324         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 325
 326         /* Configure timings: */
 327         hbp = mode->htotal - mode->hsync_end;
 328         hfp = mode->hsync_start - mode->hdisplay;
 329         hsw = mode->hsync_end - mode->hsync_start;
 330         vbp = mode->vtotal - mode->vsync_end;
 331         vfp = mode->vsync_start - mode->vdisplay;
 332         vsw = mode->vsync_end - mode->vsync_start;
 333
 334         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 335             mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 336
 337         /* Set AC Bias Period and Number of Transitions per Interrupt: */
 338         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 339         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 340                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 341
 342         /*
 343          * subtract one from hfp, hbp, hsw because the hardware uses
 344          * a value of 0 as 1
 345          */
 346         if (priv->rev == 2) {
 347                 /* clear bits we're going to set */
 348                 reg &= ~0x78000033;
 349                 reg |= ((hfp-1) & 0x300) >> 8;
 350                 reg |= ((hbp-1) & 0x300) >> 4;
 351                 reg |= ((hsw-1) & 0x3c0) << 21;
 352         }
 353         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 354
 355         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 356                 (((hbp-1) & 0xff) << 24) |
 357                 (((hfp-1) & 0xff) << 16) |
 358                 (((hsw-1) & 0x3f) << 10);
 359         if (priv->rev == 2)
 360                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 361         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 362
 363         reg = ((mode->vdisplay - 1) & 0x3ff) |
 364                 ((vbp & 0xff) << 24) |
 365                 ((vfp & 0xff) << 16) |
 366                 (((vsw-1) & 0x3f) << 10);
 367         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 368
 369         /*
 370          * be sure to set Bit 10 for the V2 LCDC controller,
 371          * otherwise limited to 1024 pixels width, stopping
 372          * 1920x1080 being supported.
 373          */
 374         if (priv->rev == 2) {
 375                 if ((mode->vdisplay - 1) & 0x400) {
 376                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 377                                 LCDC_LPP_B10);
 378                 } else {
 379                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 380                                 LCDC_LPP_B10);
 381                 }
 382         }
 383
 384         /* Configure display type: */
 385         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 386                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 387                   LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
 388                   0x000ff000 /* Palette Loading Delay bits */);
 389         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 390         if (info->tft_alt_mode)
 391                 reg |= LCDC_TFT_ALT_ENABLE;
 392         if (priv->rev == 2) {
 393                 switch (fb->format->format) {
 394                 case DRM_FORMAT_BGR565:
 395                 case DRM_FORMAT_RGB565:
 396                         break;
 397                 case DRM_FORMAT_XBGR8888:
 398                 case DRM_FORMAT_XRGB8888:
 399                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 400                         /* fallthrough */
 401                 case DRM_FORMAT_BGR888:
 402                 case DRM_FORMAT_RGB888:
 403                         reg |= LCDC_V2_TFT_24BPP_MODE;
 404                         break;
 405                 default:
 406                         dev_err(dev->dev, "invalid pixel format\n");
 407                         return;
 408                 }
 409         }
 410         reg |= info->fdd < 12;
 411         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 412
 413         if (info->invert_pxl_clk)
 414                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 415         else
 416                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 417
 418         if (info->sync_ctrl)
 419                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 420         else
 421                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 422
 423         if (info->sync_edge)
 424                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 425         else
 426                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 427
 428         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 429                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 430         else
 431                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 432
 433         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 434                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 435         else
 436                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 437
 438         if (info->raster_order)
 439                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 440         else
 441                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 442
 443         tilcdc_crtc_set_clk(crtc);
 444
 445         tilcdc_crtc_load_palette(crtc);
 446
 447         set_scanout(crtc, fb);
 448
 449         crtc->hwmode = crtc->state->adjusted_mode;
 450
 451         tilcdc_crtc->hvtotal_us =
 452                 tilcdc_mode_hvtotal(&crtc->hwmode);
 453 }
 454
 455 static void tilcdc_crtc_enable(struct drm_crtc *crtc)
 456 {
 457         struct drm_device *dev = crtc->dev;
 458         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 459         unsigned long flags;
 460
 461         mutex_lock(&tilcdc_crtc->enable_lock);
 462         if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) {
 463                 mutex_unlock(&tilcdc_crtc->enable_lock);
 464                 return;
 465         }
 466
 467         pm_runtime_get_sync(dev->dev);
 468
 469         reset(crtc);
 470
 471         tilcdc_crtc_set_mode(crtc);
 472
 473         tilcdc_crtc_enable_irqs(dev);
 474
 475         tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 476         tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
 477                           LCDC_PALETTE_LOAD_MODE(DATA_ONLY),
 478                           LCDC_PALETTE_LOAD_MODE_MASK);
 479
 480         /* There is no real chance for a race here as the time stamp
 481          * is taken before the raster DMA is started. The spin-lock is
 482          * taken to have a memory barrier after taking the time-stamp
 483          * and to avoid a context switch between taking the stamp and
 484          * enabling the raster.
 485          */
 486         spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 487         tilcdc_crtc->last_vblank = ktime_get();
 488         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 489         spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 490
 491         drm_crtc_vblank_on(crtc);
 492
 493         tilcdc_crtc->enabled = true;
 494         mutex_unlock(&tilcdc_crtc->enable_lock);
 495 }
 496
 497 static void tilcdc_crtc_atomic_enable(struct drm_crtc *crtc,
 498                                       struct drm_crtc_state *old_state)
 499 {
 500         tilcdc_crtc_enable(crtc);
 501 }
 502
 503 static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown)
 504 {
 505         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 506         struct drm_device *dev = crtc->dev;
 507         int ret;
 508
 509         mutex_lock(&tilcdc_crtc->enable_lock);
 510         if (shutdown)
 511                 tilcdc_crtc->shutdown = true;
 512         if (!tilcdc_crtc->enabled) {
 513                 mutex_unlock(&tilcdc_crtc->enable_lock);
 514                 return;
 515         }
 516         tilcdc_crtc->frame_done = false;
 517         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 518
 519         /*
 520          * Wait for framedone irq which will still come before putting
 521          * things to sleep..
 522          */
 523         ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
 524                                  tilcdc_crtc->frame_done,
 525                                  msecs_to_jiffies(500));
 526         if (ret == 0)
 527                 dev_err(dev->dev, "%s: timeout waiting for framedone\n",
 528                         __func__);
 529
 530         drm_crtc_vblank_off(crtc);
 531
 532         tilcdc_crtc_disable_irqs(dev);
 533
 534         pm_runtime_put_sync(dev->dev);
 535
 536         tilcdc_crtc->enabled = false;
 537         mutex_unlock(&tilcdc_crtc->enable_lock);
 538 }
 539
 540 static void tilcdc_crtc_disable(struct drm_crtc *crtc)
 541 {
 542         tilcdc_crtc_off(crtc, false);
 543 }
 544
 545 static void tilcdc_crtc_atomic_disable(struct drm_crtc *crtc,
 546                                        struct drm_crtc_state *old_state)
 547 {
 548         tilcdc_crtc_disable(crtc);
 549 }
 550
 551 void tilcdc_crtc_shutdown(struct drm_crtc *crtc)
 552 {
 553         tilcdc_crtc_off(crtc, true);
 554 }
 555
 556 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
 557 {
 558         return crtc->state && crtc->state->enable && crtc->state->active;
 559 }
 560
 561 static void tilcdc_crtc_recover_work(struct work_struct *work)
 562 {
 563         struct tilcdc_crtc *tilcdc_crtc =
 564                 container_of(work, struct tilcdc_crtc, recover_work);
 565         struct drm_crtc *crtc = &tilcdc_crtc->base;
 566
 567         dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__);
 568
 569         drm_modeset_lock(&crtc->mutex, NULL);
 570
 571         if (!tilcdc_crtc_is_on(crtc))
 572                 goto out;
 573
 574         tilcdc_crtc_disable(crtc);
 575         tilcdc_crtc_enable(crtc);
 576 out:
 577         drm_modeset_unlock(&crtc->mutex);
 578 }
 579
 580 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 581 {
 582         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 583
 584         tilcdc_crtc_shutdown(crtc);
 585
 586         flush_workqueue(priv->wq);
 587
 588         of_node_put(crtc->port);
 589         drm_crtc_cleanup(crtc);
 590 }
 591
 592 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
 593                 struct drm_framebuffer *fb,
 594                 struct drm_pending_vblank_event *event)
 595 {
 596         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 597         struct drm_device *dev = crtc->dev;
 598
 599         if (tilcdc_crtc->event) {
 600                 dev_err(dev->dev, "already pending page flip!\n");
 601                 return -EBUSY;
 602         }
 603
 604         tilcdc_crtc->event = event;
 605
 606         mutex_lock(&tilcdc_crtc->enable_lock);
 607
 608         if (tilcdc_crtc->enabled) {
 609                 unsigned long flags;
 610                 ktime_t next_vblank;
 611                 s64 tdiff;
 612
 613                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 614
 615                 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
 616                                            tilcdc_crtc->hvtotal_us);
 617                 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
 618
 619                 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
 620                         tilcdc_crtc->next_fb = fb;
 621                 else
 622                         set_scanout(crtc, fb);
 623
 624                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 625         }
 626
 627         mutex_unlock(&tilcdc_crtc->enable_lock);
 628
 629         return 0;
 630 }
 631
 632 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 633                 const struct drm_display_mode *mode,
 634                 struct drm_display_mode *adjusted_mode)
 635 {
 636         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 637
 638         if (!tilcdc_crtc->simulate_vesa_sync)
 639                 return true;
 640
 641         /*
 642          * tilcdc does not generate VESA-compliant sync but aligns
 643          * VS on the second edge of HS instead of first edge.
 644          * We use adjusted_mode, to fixup sync by aligning both rising
 645          * edges and add HSKEW offset to fix the sync.
 646          */
 647         adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
 648         adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
 649
 650         if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
 651                 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
 652                 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
 653         } else {
 654                 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
 655                 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
 656         }
 657
 658         return true;
 659 }
 660
 661 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
 662                                     struct drm_crtc_state *state)
 663 {
 664         struct drm_display_mode *mode = &state->mode;
 665         int ret;
 666
 667         /* If we are not active we don't care */
 668         if (!state->active)
 669                 return 0;
 670
 671         if (state->state->planes[0].ptr != crtc->primary ||
 672             state->state->planes[0].state == NULL ||
 673             state->state->planes[0].state->crtc != crtc) {
 674                 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
 675                 return -EINVAL;
 676         }
 677
 678         ret = tilcdc_crtc_mode_valid(crtc, mode);
 679         if (ret) {
 680                 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
 681                 return -EINVAL;
 682         }
 683
 684         return 0;
 685 }
 686
 687 static int tilcdc_crtc_enable_vblank(struct drm_crtc *crtc)
 688 {
 689         return 0;
 690 }
 691
 692 static void tilcdc_crtc_disable_vblank(struct drm_crtc *crtc)
 693 {
 694 }
 695
 696 static void tilcdc_crtc_reset(struct drm_crtc *crtc)
 697 {
 698         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 699         struct drm_device *dev = crtc->dev;
 700         int ret;
 701
 702         drm_atomic_helper_crtc_reset(crtc);
 703
 704         /* Turn the raster off if it for some reason is on. */
 705         pm_runtime_get_sync(dev->dev);
 706         if (tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & LCDC_RASTER_ENABLE) {
 707                 /* Enable DMA Frame Done Interrupt */
 708                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_FRAME_DONE);
 709                 tilcdc_clear_irqstatus(dev, 0xffffffff);
 710
 711                 tilcdc_crtc->frame_done = false;
 712                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 713
 714                 ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
 715                                          tilcdc_crtc->frame_done,
 716                                          msecs_to_jiffies(500));
 717                 if (ret == 0)
 718                         dev_err(dev->dev, "%s: timeout waiting for framedone\n",
 719                                 __func__);
 720         }
 721         pm_runtime_put_sync(dev->dev);
 722 }
 723
 724 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 725         .destroy        = tilcdc_crtc_destroy,
 726         .set_config     = drm_atomic_helper_set_config,
 727         .page_flip      = drm_atomic_helper_page_flip,
 728         .reset          = tilcdc_crtc_reset,
 729         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 730         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 731         .enable_vblank  = tilcdc_crtc_enable_vblank,
 732         .disable_vblank = tilcdc_crtc_disable_vblank,
 733 };
 734
 735 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 736                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 737                 .atomic_check   = tilcdc_crtc_atomic_check,
 738                 .atomic_enable  = tilcdc_crtc_atomic_enable,
 739                 .atomic_disable = tilcdc_crtc_atomic_disable,
 740 };
 741
 742 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 743 {
 744         struct drm_device *dev = crtc->dev;
 745         struct tilcdc_drm_private *priv = dev->dev_private;
 746         int max_width = 0;
 747
 748         if (priv->rev == 1)
 749                 max_width = 1024;
 750         else if (priv->rev == 2)
 751                 max_width = 2048;
 752
 753         return max_width;
 754 }
 755
 756 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 757 {
 758         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 759         unsigned int bandwidth;
 760         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 761
 762         /*
 763          * check to see if the width is within the range that
 764          * the LCD Controller physically supports
 765          */
 766         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 767                 return MODE_VIRTUAL_X;
 768
 769         /* width must be multiple of 16 */
 770         if (mode->hdisplay & 0xf)
 771                 return MODE_VIRTUAL_X;
 772
 773         if (mode->vdisplay > 2048)
 774                 return MODE_VIRTUAL_Y;
 775
 776         DBG("Processing mode %dx%d@%d with pixel clock %d",
 777                 mode->hdisplay, mode->vdisplay,
 778                 drm_mode_vrefresh(mode), mode->clock);
 779
 780         hbp = mode->htotal - mode->hsync_end;
 781         hfp = mode->hsync_start - mode->hdisplay;
 782         hsw = mode->hsync_end - mode->hsync_start;
 783         vbp = mode->vtotal - mode->vsync_end;
 784         vfp = mode->vsync_start - mode->vdisplay;
 785         vsw = mode->vsync_end - mode->vsync_start;
 786
 787         if ((hbp-1) & ~0x3ff) {
 788                 DBG("Pruning mode: Horizontal Back Porch out of range");
 789                 return MODE_HBLANK_WIDE;
 790         }
 791
 792         if ((hfp-1) & ~0x3ff) {
 793                 DBG("Pruning mode: Horizontal Front Porch out of range");
 794                 return MODE_HBLANK_WIDE;
 795         }
 796
 797         if ((hsw-1) & ~0x3ff) {
 798                 DBG("Pruning mode: Horizontal Sync Width out of range");
 799                 return MODE_HSYNC_WIDE;
 800         }
 801
 802         if (vbp & ~0xff) {
 803                 DBG("Pruning mode: Vertical Back Porch out of range");
 804                 return MODE_VBLANK_WIDE;
 805         }
 806
 807         if (vfp & ~0xff) {
 808                 DBG("Pruning mode: Vertical Front Porch out of range");
 809                 return MODE_VBLANK_WIDE;
 810         }
 811
 812         if ((vsw-1) & ~0x3f) {
 813                 DBG("Pruning mode: Vertical Sync Width out of range");
 814                 return MODE_VSYNC_WIDE;
 815         }
 816
 817         /*
 818          * some devices have a maximum allowed pixel clock
 819          * configured from the DT
 820          */
 821         if (mode->clock > priv->max_pixelclock) {
 822                 DBG("Pruning mode: pixel clock too high");
 823                 return MODE_CLOCK_HIGH;
 824         }
 825
 826         /*
 827          * some devices further limit the max horizontal resolution
 828          * configured from the DT
 829          */
 830         if (mode->hdisplay > priv->max_width)
 831                 return MODE_BAD_WIDTH;
 832
 833         /* filter out modes that would require too much memory bandwidth: */
 834         bandwidth = mode->hdisplay * mode->vdisplay *
 835                 drm_mode_vrefresh(mode);
 836         if (bandwidth > priv->max_bandwidth) {
 837                 DBG("Pruning mode: exceeds defined bandwidth limit");
 838                 return MODE_BAD;
 839         }
 840
 841         return MODE_OK;
 842 }
 843
 844 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 845                 const struct tilcdc_panel_info *info)
 846 {
 847         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 848         tilcdc_crtc->info = info;
 849 }
 850
 851 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 852                                         bool simulate_vesa_sync)
 853 {
 854         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 855
 856         tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
 857 }
 858
 859 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 860 {
 861         struct drm_device *dev = crtc->dev;
 862         struct tilcdc_drm_private *priv = dev->dev_private;
 863         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 864
 865         drm_modeset_lock(&crtc->mutex, NULL);
 866         if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) {
 867                 if (tilcdc_crtc_is_on(crtc)) {
 868                         pm_runtime_get_sync(dev->dev);
 869                         tilcdc_crtc_disable(crtc);
 870
 871                         tilcdc_crtc_set_clk(crtc);
 872
 873                         tilcdc_crtc_enable(crtc);
 874                         pm_runtime_put_sync(dev->dev);
 875                 }
 876         }
 877         drm_modeset_unlock(&crtc->mutex);
 878 }
 879
 880 #define SYNC_LOST_COUNT_LIMIT 50
 881
 882 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 883 {
 884         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 885         struct drm_device *dev = crtc->dev;
 886         struct tilcdc_drm_private *priv = dev->dev_private;
 887         uint32_t stat, reg;
 888
 889         stat = tilcdc_read_irqstatus(dev);
 890         tilcdc_clear_irqstatus(dev, stat);
 891
 892         if (stat & LCDC_END_OF_FRAME0) {
 893                 unsigned long flags;
 894                 bool skip_event = false;
 895                 ktime_t now;
 896
 897                 now = ktime_get();
 898
 899                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 900
 901                 tilcdc_crtc->last_vblank = now;
 902
 903                 if (tilcdc_crtc->next_fb) {
 904                         set_scanout(crtc, tilcdc_crtc->next_fb);
 905                         tilcdc_crtc->next_fb = NULL;
 906                         skip_event = true;
 907                 }
 908
 909                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 910
 911                 drm_crtc_handle_vblank(crtc);
 912
 913                 if (!skip_event) {
 914                         struct drm_pending_vblank_event *event;
 915
 916                         spin_lock_irqsave(&dev->event_lock, flags);
 917
 918                         event = tilcdc_crtc->event;
 919                         tilcdc_crtc->event = NULL;
 920                         if (event)
 921                                 drm_crtc_send_vblank_event(crtc, event);
 922
 923                         spin_unlock_irqrestore(&dev->event_lock, flags);
 924                 }
 925
 926                 if (tilcdc_crtc->frame_intact)
 927                         tilcdc_crtc->sync_lost_count = 0;
 928                 else
 929                         tilcdc_crtc->frame_intact = true;
 930         }
 931
 932         if (stat & LCDC_FIFO_UNDERFLOW)
 933                 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow",
 934                                     __func__, stat);
 935
 936         if (stat & LCDC_PL_LOAD_DONE) {
 937                 complete(&tilcdc_crtc->palette_loaded);
 938                 if (priv->rev == 1)
 939                         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 940                                      LCDC_V1_PL_INT_ENA);
 941                 else
 942                         tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 943                                      LCDC_V2_PL_INT_ENA);
 944         }
 945
 946         if (stat & LCDC_SYNC_LOST) {
 947                 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
 948                                     __func__, stat);
 949                 tilcdc_crtc->frame_intact = false;
 950                 if (priv->rev == 1) {
 951                         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
 952                         if (reg & LCDC_RASTER_ENABLE) {
 953                                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 954                                              LCDC_RASTER_ENABLE);
 955                                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
 956                                            LCDC_RASTER_ENABLE);
 957                         }
 958                 } else {
 959                         if (tilcdc_crtc->sync_lost_count++ >
 960                             SYNC_LOST_COUNT_LIMIT) {
 961                                 dev_err(dev->dev,
 962                                         "%s(0x%08x): Sync lost flood detected, recovering",
 963                                         __func__, stat);
 964                                 queue_work(system_wq,
 965                                            &tilcdc_crtc->recover_work);
 966                                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 967                                              LCDC_SYNC_LOST);
 968                                 tilcdc_crtc->sync_lost_count = 0;
 969                         }
 970                 }
 971         }
 972
 973         if (stat & LCDC_FRAME_DONE) {
 974                 tilcdc_crtc->frame_done = true;
 975                 wake_up(&tilcdc_crtc->frame_done_wq);
 976                 /* rev 1 lcdc appears to hang if irq is not disbaled here */
 977                 if (priv->rev == 1)
 978                         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 979                                      LCDC_V1_FRAME_DONE_INT_ENA);
 980         }
 981
 982         /* For revision 2 only */
 983         if (priv->rev == 2) {
 984                 /* Indicate to LCDC that the interrupt service routine has
 985                  * completed, see 13.3.6.1.6 in AM335x TRM.
 986                  */
 987                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 988         }
 989
 990         return IRQ_HANDLED;
 991 }
 992
 993 int tilcdc_crtc_create(struct drm_device *dev)
 994 {
 995         struct tilcdc_drm_private *priv = dev->dev_private;
 996         struct tilcdc_crtc *tilcdc_crtc;
 997         struct drm_crtc *crtc;
 998         int ret;
 999
1000         tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
1001         if (!tilcdc_crtc)
1002                 return -ENOMEM;
1003
1004         init_completion(&tilcdc_crtc->palette_loaded);
1005         tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev,
1006                                         TILCDC_PALETTE_SIZE,
1007                                         &tilcdc_crtc->palette_dma_handle,
1008                                         GFP_KERNEL | __GFP_ZERO);
1009         if (!tilcdc_crtc->palette_base)
1010                 return -ENOMEM;
1011         *tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY;
1012
1013         crtc = &tilcdc_crtc->base;
1014
1015         ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
1016         if (ret < 0)
1017                 goto fail;
1018
1019         mutex_init(&tilcdc_crtc->enable_lock);
1020
1021         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
1022
1023         spin_lock_init(&tilcdc_crtc->irq_lock);
1024         INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);
1025
1026         ret = drm_crtc_init_with_planes(dev, crtc,
1027                                         &tilcdc_crtc->primary,
1028                                         NULL,
1029                                         &tilcdc_crtc_funcs,
1030                                         "tilcdc crtc");
1031         if (ret < 0)
1032                 goto fail;
1033
1034         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
1035
1036         if (priv->is_componentized) {
1037                 crtc->port = of_graph_get_port_by_id(dev->dev->of_node, 0);
1038                 if (!crtc->port) { /* This should never happen */
1039                         dev_err(dev->dev, "Port node not found in %pOF\n",
1040                                 dev->dev->of_node);
1041                         ret = -EINVAL;
1042                         goto fail;
1043                 }
1044         }
1045
1046         priv->crtc = crtc;
1047         return 0;
1048
1049 fail:
1050         tilcdc_crtc_destroy(crtc);
1051         return ret;
1052 }