drivers/gpu/drm/tegra/sor.c

   1 /*
   2  * Copyright (C) 2013 NVIDIA Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/gpio.h>
  13 #include <linux/io.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/reset.h>
  19
  20 #include <soc/tegra/pmc.h>
  21
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_dp_helper.h>
  24 #include <drm/drm_panel.h>
  25
  26 #include "dc.h"
  27 #include "drm.h"
  28 #include "sor.h"
  29 #include "trace.h"
  30
  31 #define SOR_REKEY 0x38
  32
  33 struct tegra_sor_hdmi_settings {
  34         unsigned long frequency;
  35
  36         u8 vcocap;
  37         u8 ichpmp;
  38         u8 loadadj;
  39         u8 termadj;
  40         u8 tx_pu;
  41         u8 bg_vref;
  42
  43         u8 drive_current[4];
  44         u8 preemphasis[4];
  45 };
  46
  47 #if 1
  48 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  49         {
  50                 .frequency = 54000000,
  51                 .vcocap = 0x0,
  52                 .ichpmp = 0x1,
  53                 .loadadj = 0x3,
  54                 .termadj = 0x9,
  55                 .tx_pu = 0x10,
  56                 .bg_vref = 0x8,
  57                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  58                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  59         }, {
  60                 .frequency = 75000000,
  61                 .vcocap = 0x3,
  62                 .ichpmp = 0x1,
  63                 .loadadj = 0x3,
  64                 .termadj = 0x9,
  65                 .tx_pu = 0x40,
  66                 .bg_vref = 0x8,
  67                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  68                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  69         }, {
  70                 .frequency = 150000000,
  71                 .vcocap = 0x3,
  72                 .ichpmp = 0x1,
  73                 .loadadj = 0x3,
  74                 .termadj = 0x9,
  75                 .tx_pu = 0x66,
  76                 .bg_vref = 0x8,
  77                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  78                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  79         }, {
  80                 .frequency = 300000000,
  81                 .vcocap = 0x3,
  82                 .ichpmp = 0x1,
  83                 .loadadj = 0x3,
  84                 .termadj = 0x9,
  85                 .tx_pu = 0x66,
  86                 .bg_vref = 0xa,
  87                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
  88                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
  89         }, {
  90                 .frequency = 600000000,
  91                 .vcocap = 0x3,
  92                 .ichpmp = 0x1,
  93                 .loadadj = 0x3,
  94                 .termadj = 0x9,
  95                 .tx_pu = 0x66,
  96                 .bg_vref = 0x8,
  97                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
  98                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  99         },
 100 };
 101 #else
 102 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 103         {
 104                 .frequency = 75000000,
 105                 .vcocap = 0x3,
 106                 .ichpmp = 0x1,
 107                 .loadadj = 0x3,
 108                 .termadj = 0x9,
 109                 .tx_pu = 0x40,
 110                 .bg_vref = 0x8,
 111                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 112                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 113         }, {
 114                 .frequency = 150000000,
 115                 .vcocap = 0x3,
 116                 .ichpmp = 0x1,
 117                 .loadadj = 0x3,
 118                 .termadj = 0x9,
 119                 .tx_pu = 0x66,
 120                 .bg_vref = 0x8,
 121                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 122                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 123         }, {
 124                 .frequency = 300000000,
 125                 .vcocap = 0x3,
 126                 .ichpmp = 0x6,
 127                 .loadadj = 0x3,
 128                 .termadj = 0x9,
 129                 .tx_pu = 0x66,
 130                 .bg_vref = 0xf,
 131                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 132                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 133         }, {
 134                 .frequency = 600000000,
 135                 .vcocap = 0x3,
 136                 .ichpmp = 0xa,
 137                 .loadadj = 0x3,
 138                 .termadj = 0xb,
 139                 .tx_pu = 0x66,
 140                 .bg_vref = 0xe,
 141                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 142                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 143         },
 144 };
 145 #endif
 146
 147 struct tegra_sor_soc {
 148         bool supports_edp;
 149         bool supports_lvds;
 150         bool supports_hdmi;
 151         bool supports_dp;
 152
 153         const struct tegra_sor_hdmi_settings *settings;
 154         unsigned int num_settings;
 155
 156         const u8 *xbar_cfg;
 157 };
 158
 159 struct tegra_sor;
 160
 161 struct tegra_sor_ops {
 162         const char *name;
 163         int (*probe)(struct tegra_sor *sor);
 164         int (*remove)(struct tegra_sor *sor);
 165 };
 166
 167 struct tegra_sor {
 168         struct host1x_client client;
 169         struct tegra_output output;
 170         struct device *dev;
 171
 172         const struct tegra_sor_soc *soc;
 173         void __iomem *regs;
 174
 175         struct reset_control *rst;
 176         struct clk *clk_parent;
 177         struct clk *clk_safe;
 178         struct clk *clk_out;
 179         struct clk *clk_pad;
 180         struct clk *clk_dp;
 181         struct clk *clk;
 182
 183         struct drm_dp_aux *aux;
 184
 185         struct drm_info_list *debugfs_files;
 186         struct drm_minor *minor;
 187         struct dentry *debugfs;
 188
 189         const struct tegra_sor_ops *ops;
 190
 191         /* for HDMI 2.0 */
 192         struct tegra_sor_hdmi_settings *settings;
 193         unsigned int num_settings;
 194
 195         struct regulator *avdd_io_supply;
 196         struct regulator *vdd_pll_supply;
 197         struct regulator *hdmi_supply;
 198 };
 199
 200 struct tegra_sor_state {
 201         struct drm_connector_state base;
 202
 203         unsigned int bpc;
 204 };
 205
 206 static inline struct tegra_sor_state *
 207 to_sor_state(struct drm_connector_state *state)
 208 {
 209         return container_of(state, struct tegra_sor_state, base);
 210 }
 211
 212 struct tegra_sor_config {
 213         u32 bits_per_pixel;
 214
 215         u32 active_polarity;
 216         u32 active_count;
 217         u32 tu_size;
 218         u32 active_frac;
 219         u32 watermark;
 220
 221         u32 hblank_symbols;
 222         u32 vblank_symbols;
 223 };
 224
 225 static inline struct tegra_sor *
 226 host1x_client_to_sor(struct host1x_client *client)
 227 {
 228         return container_of(client, struct tegra_sor, client);
 229 }
 230
 231 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 232 {
 233         return container_of(output, struct tegra_sor, output);
 234 }
 235
 236 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 237 {
 238         u32 value = readl(sor->regs + (offset << 2));
 239
 240         trace_sor_readl(sor->dev, offset, value);
 241
 242         return value;
 243 }
 244
 245 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 246                                     unsigned int offset)
 247 {
 248         trace_sor_writel(sor->dev, offset, value);
 249         writel(value, sor->regs + (offset << 2));
 250 }
 251
 252 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 253 {
 254         int err;
 255
 256         clk_disable_unprepare(sor->clk);
 257
 258         err = clk_set_parent(sor->clk_out, parent);
 259         if (err < 0)
 260                 return err;
 261
 262         err = clk_prepare_enable(sor->clk);
 263         if (err < 0)
 264                 return err;
 265
 266         return 0;
 267 }
 268
 269 struct tegra_clk_sor_pad {
 270         struct clk_hw hw;
 271         struct tegra_sor *sor;
 272 };
 273
 274 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 275 {
 276         return container_of(hw, struct tegra_clk_sor_pad, hw);
 277 }
 278
 279 static const char * const tegra_clk_sor_pad_parents[] = {
 280         "pll_d2_out0", "pll_dp"
 281 };
 282
 283 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 284 {
 285         struct tegra_clk_sor_pad *pad = to_pad(hw);
 286         struct tegra_sor *sor = pad->sor;
 287         u32 value;
 288
 289         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 290         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 291
 292         switch (index) {
 293         case 0:
 294                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 295                 break;
 296
 297         case 1:
 298                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 299                 break;
 300         }
 301
 302         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 303
 304         return 0;
 305 }
 306
 307 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 308 {
 309         struct tegra_clk_sor_pad *pad = to_pad(hw);
 310         struct tegra_sor *sor = pad->sor;
 311         u8 parent = U8_MAX;
 312         u32 value;
 313
 314         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 315
 316         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 317         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 318         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 319                 parent = 0;
 320                 break;
 321
 322         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 323         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 324                 parent = 1;
 325                 break;
 326         }
 327
 328         return parent;
 329 }
 330
 331 static const struct clk_ops tegra_clk_sor_pad_ops = {
 332         .set_parent = tegra_clk_sor_pad_set_parent,
 333         .get_parent = tegra_clk_sor_pad_get_parent,
 334 };
 335
 336 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 337                                               const char *name)
 338 {
 339         struct tegra_clk_sor_pad *pad;
 340         struct clk_init_data init;
 341         struct clk *clk;
 342
 343         pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 344         if (!pad)
 345                 return ERR_PTR(-ENOMEM);
 346
 347         pad->sor = sor;
 348
 349         init.name = name;
 350         init.flags = 0;
 351         init.parent_names = tegra_clk_sor_pad_parents;
 352         init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
 353         init.ops = &tegra_clk_sor_pad_ops;
 354
 355         pad->hw.init = &init;
 356
 357         clk = devm_clk_register(sor->dev, &pad->hw);
 358
 359         return clk;
 360 }
 361
 362 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
 363                                    struct drm_dp_link *link)
 364 {
 365         unsigned int i;
 366         u8 pattern;
 367         u32 value;
 368         int err;
 369
 370         /* setup lane parameters */
 371         value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
 372                 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
 373                 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
 374                 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
 375         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
 376
 377         value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
 378                 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
 379                 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
 380                 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
 381         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
 382
 383         value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
 384                 SOR_LANE_POSTCURSOR_LANE2(0x00) |
 385                 SOR_LANE_POSTCURSOR_LANE1(0x00) |
 386                 SOR_LANE_POSTCURSOR_LANE0(0x00);
 387         tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
 388
 389         /* disable LVDS mode */
 390         tegra_sor_writel(sor, 0, SOR_LVDS);
 391
 392         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 393         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 394         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 395         value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
 396         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 397
 398         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 399         value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 400                  SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
 401         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 402
 403         usleep_range(10, 100);
 404
 405         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 406         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 407                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 408         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 409
 410         err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
 411         if (err < 0)
 412                 return err;
 413
 414         for (i = 0, value = 0; i < link->num_lanes; i++) {
 415                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 416                                      SOR_DP_TPG_SCRAMBLER_NONE |
 417                                      SOR_DP_TPG_PATTERN_TRAIN1;
 418                 value = (value << 8) | lane;
 419         }
 420
 421         tegra_sor_writel(sor, value, SOR_DP_TPG);
 422
 423         pattern = DP_TRAINING_PATTERN_1;
 424
 425         err = drm_dp_aux_train(sor->aux, link, pattern);
 426         if (err < 0)
 427                 return err;
 428
 429         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 430         value |= SOR_DP_SPARE_SEQ_ENABLE;
 431         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 432         value |= SOR_DP_SPARE_MACRO_SOR_CLK;
 433         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 434
 435         for (i = 0, value = 0; i < link->num_lanes; i++) {
 436                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 437                                      SOR_DP_TPG_SCRAMBLER_NONE |
 438                                      SOR_DP_TPG_PATTERN_TRAIN2;
 439                 value = (value << 8) | lane;
 440         }
 441
 442         tegra_sor_writel(sor, value, SOR_DP_TPG);
 443
 444         pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
 445
 446         err = drm_dp_aux_train(sor->aux, link, pattern);
 447         if (err < 0)
 448                 return err;
 449
 450         for (i = 0, value = 0; i < link->num_lanes; i++) {
 451                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 452                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 453                                      SOR_DP_TPG_PATTERN_NONE;
 454                 value = (value << 8) | lane;
 455         }
 456
 457         tegra_sor_writel(sor, value, SOR_DP_TPG);
 458
 459         pattern = DP_TRAINING_PATTERN_DISABLE;
 460
 461         err = drm_dp_aux_train(sor->aux, link, pattern);
 462         if (err < 0)
 463                 return err;
 464
 465         return 0;
 466 }
 467
 468 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
 469 {
 470         u32 mask = 0x08, adj = 0, value;
 471
 472         /* enable pad calibration logic */
 473         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 474         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 475         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 476
 477         value = tegra_sor_readl(sor, SOR_PLL1);
 478         value |= SOR_PLL1_TMDS_TERM;
 479         tegra_sor_writel(sor, value, SOR_PLL1);
 480
 481         while (mask) {
 482                 adj |= mask;
 483
 484                 value = tegra_sor_readl(sor, SOR_PLL1);
 485                 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 486                 value |= SOR_PLL1_TMDS_TERMADJ(adj);
 487                 tegra_sor_writel(sor, value, SOR_PLL1);
 488
 489                 usleep_range(100, 200);
 490
 491                 value = tegra_sor_readl(sor, SOR_PLL1);
 492                 if (value & SOR_PLL1_TERM_COMPOUT)
 493                         adj &= ~mask;
 494
 495                 mask >>= 1;
 496         }
 497
 498         value = tegra_sor_readl(sor, SOR_PLL1);
 499         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 500         value |= SOR_PLL1_TMDS_TERMADJ(adj);
 501         tegra_sor_writel(sor, value, SOR_PLL1);
 502
 503         /* disable pad calibration logic */
 504         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
 505         value |= SOR_DP_PADCTL_PAD_CAL_PD;
 506         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
 507 }
 508
 509 static void tegra_sor_super_update(struct tegra_sor *sor)
 510 {
 511         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 512         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 513         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 514 }
 515
 516 static void tegra_sor_update(struct tegra_sor *sor)
 517 {
 518         tegra_sor_writel(sor, 0, SOR_STATE0);
 519         tegra_sor_writel(sor, 1, SOR_STATE0);
 520         tegra_sor_writel(sor, 0, SOR_STATE0);
 521 }
 522
 523 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 524 {
 525         u32 value;
 526
 527         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 528         value &= ~SOR_PWM_DIV_MASK;
 529         value |= 0x400; /* period */
 530         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 531
 532         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 533         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 534         value |= 0x400; /* duty cycle */
 535         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 536         value |= SOR_PWM_CTL_TRIGGER;
 537         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 538
 539         timeout = jiffies + msecs_to_jiffies(timeout);
 540
 541         while (time_before(jiffies, timeout)) {
 542                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 543                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 544                         return 0;
 545
 546                 usleep_range(25, 100);
 547         }
 548
 549         return -ETIMEDOUT;
 550 }
 551
 552 static int tegra_sor_attach(struct tegra_sor *sor)
 553 {
 554         unsigned long value, timeout;
 555
 556         /* wake up in normal mode */
 557         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 558         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
 559         value |= SOR_SUPER_STATE_MODE_NORMAL;
 560         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 561         tegra_sor_super_update(sor);
 562
 563         /* attach */
 564         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 565         value |= SOR_SUPER_STATE_ATTACHED;
 566         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 567         tegra_sor_super_update(sor);
 568
 569         timeout = jiffies + msecs_to_jiffies(250);
 570
 571         while (time_before(jiffies, timeout)) {
 572                 value = tegra_sor_readl(sor, SOR_TEST);
 573                 if ((value & SOR_TEST_ATTACHED) != 0)
 574                         return 0;
 575
 576                 usleep_range(25, 100);
 577         }
 578
 579         return -ETIMEDOUT;
 580 }
 581
 582 static int tegra_sor_wakeup(struct tegra_sor *sor)
 583 {
 584         unsigned long value, timeout;
 585
 586         timeout = jiffies + msecs_to_jiffies(250);
 587
 588         /* wait for head to wake up */
 589         while (time_before(jiffies, timeout)) {
 590                 value = tegra_sor_readl(sor, SOR_TEST);
 591                 value &= SOR_TEST_HEAD_MODE_MASK;
 592
 593                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
 594                         return 0;
 595
 596                 usleep_range(25, 100);
 597         }
 598
 599         return -ETIMEDOUT;
 600 }
 601
 602 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
 603 {
 604         u32 value;
 605
 606         value = tegra_sor_readl(sor, SOR_PWR);
 607         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
 608         tegra_sor_writel(sor, value, SOR_PWR);
 609
 610         timeout = jiffies + msecs_to_jiffies(timeout);
 611
 612         while (time_before(jiffies, timeout)) {
 613                 value = tegra_sor_readl(sor, SOR_PWR);
 614                 if ((value & SOR_PWR_TRIGGER) == 0)
 615                         return 0;
 616
 617                 usleep_range(25, 100);
 618         }
 619
 620         return -ETIMEDOUT;
 621 }
 622
 623 struct tegra_sor_params {
 624         /* number of link clocks per line */
 625         unsigned int num_clocks;
 626         /* ratio between input and output */
 627         u64 ratio;
 628         /* precision factor */
 629         u64 precision;
 630
 631         unsigned int active_polarity;
 632         unsigned int active_count;
 633         unsigned int active_frac;
 634         unsigned int tu_size;
 635         unsigned int error;
 636 };
 637
 638 static int tegra_sor_compute_params(struct tegra_sor *sor,
 639                                     struct tegra_sor_params *params,
 640                                     unsigned int tu_size)
 641 {
 642         u64 active_sym, active_count, frac, approx;
 643         u32 active_polarity, active_frac = 0;
 644         const u64 f = params->precision;
 645         s64 error;
 646
 647         active_sym = params->ratio * tu_size;
 648         active_count = div_u64(active_sym, f) * f;
 649         frac = active_sym - active_count;
 650
 651         /* fraction < 0.5 */
 652         if (frac >= (f / 2)) {
 653                 active_polarity = 1;
 654                 frac = f - frac;
 655         } else {
 656                 active_polarity = 0;
 657         }
 658
 659         if (frac != 0) {
 660                 frac = div_u64(f * f,  frac); /* 1/fraction */
 661                 if (frac <= (15 * f)) {
 662                         active_frac = div_u64(frac, f);
 663
 664                         /* round up */
 665                         if (active_polarity)
 666                                 active_frac++;
 667                 } else {
 668                         active_frac = active_polarity ? 1 : 15;
 669                 }
 670         }
 671
 672         if (active_frac == 1)
 673                 active_polarity = 0;
 674
 675         if (active_polarity == 1) {
 676                 if (active_frac) {
 677                         approx = active_count + (active_frac * (f - 1)) * f;
 678                         approx = div_u64(approx, active_frac * f);
 679                 } else {
 680                         approx = active_count + f;
 681                 }
 682         } else {
 683                 if (active_frac)
 684                         approx = active_count + div_u64(f, active_frac);
 685                 else
 686                         approx = active_count;
 687         }
 688
 689         error = div_s64(active_sym - approx, tu_size);
 690         error *= params->num_clocks;
 691
 692         if (error <= 0 && abs(error) < params->error) {
 693                 params->active_count = div_u64(active_count, f);
 694                 params->active_polarity = active_polarity;
 695                 params->active_frac = active_frac;
 696                 params->error = abs(error);
 697                 params->tu_size = tu_size;
 698
 699                 if (error == 0)
 700                         return true;
 701         }
 702
 703         return false;
 704 }
 705
 706 static int tegra_sor_compute_config(struct tegra_sor *sor,
 707                                     const struct drm_display_mode *mode,
 708                                     struct tegra_sor_config *config,
 709                                     struct drm_dp_link *link)
 710 {
 711         const u64 f = 100000, link_rate = link->rate * 1000;
 712         const u64 pclk = mode->clock * 1000;
 713         u64 input, output, watermark, num;
 714         struct tegra_sor_params params;
 715         u32 num_syms_per_line;
 716         unsigned int i;
 717
 718         if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
 719                 return -EINVAL;
 720
 721         output = link_rate * 8 * link->num_lanes;
 722         input = pclk * config->bits_per_pixel;
 723
 724         if (input >= output)
 725                 return -ERANGE;
 726
 727         memset(&params, 0, sizeof(params));
 728         params.ratio = div64_u64(input * f, output);
 729         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
 730         params.precision = f;
 731         params.error = 64 * f;
 732         params.tu_size = 64;
 733
 734         for (i = params.tu_size; i >= 32; i--)
 735                 if (tegra_sor_compute_params(sor, &params, i))
 736                         break;
 737
 738         if (params.active_frac == 0) {
 739                 config->active_polarity = 0;
 740                 config->active_count = params.active_count;
 741
 742                 if (!params.active_polarity)
 743                         config->active_count--;
 744
 745                 config->tu_size = params.tu_size;
 746                 config->active_frac = 1;
 747         } else {
 748                 config->active_polarity = params.active_polarity;
 749                 config->active_count = params.active_count;
 750                 config->active_frac = params.active_frac;
 751                 config->tu_size = params.tu_size;
 752         }
 753
 754         dev_dbg(sor->dev,
 755                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
 756                 config->active_polarity, config->active_count,
 757                 config->tu_size, config->active_frac);
 758
 759         watermark = params.ratio * config->tu_size * (f - params.ratio);
 760         watermark = div_u64(watermark, f);
 761
 762         watermark = div_u64(watermark + params.error, f);
 763         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
 764         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
 765                             (link->num_lanes * 8);
 766
 767         if (config->watermark > 30) {
 768                 config->watermark = 30;
 769                 dev_err(sor->dev,
 770                         "unable to compute TU size, forcing watermark to %u\n",
 771                         config->watermark);
 772         } else if (config->watermark > num_syms_per_line) {
 773                 config->watermark = num_syms_per_line;
 774                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
 775                         config->watermark);
 776         }
 777
 778         /* compute the number of symbols per horizontal blanking interval */
 779         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
 780         config->hblank_symbols = div_u64(num, pclk);
 781
 782         if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
 783                 config->hblank_symbols -= 3;
 784
 785         config->hblank_symbols -= 12 / link->num_lanes;
 786
 787         /* compute the number of symbols per vertical blanking interval */
 788         num = (mode->hdisplay - 25) * link_rate;
 789         config->vblank_symbols = div_u64(num, pclk);
 790         config->vblank_symbols -= 36 / link->num_lanes + 4;
 791
 792         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
 793                 config->vblank_symbols);
 794
 795         return 0;
 796 }
 797
 798 static void tegra_sor_apply_config(struct tegra_sor *sor,
 799                                    const struct tegra_sor_config *config)
 800 {
 801         u32 value;
 802
 803         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 804         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
 805         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
 806         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
 807
 808         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
 809         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
 810         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
 811
 812         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
 813         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
 814
 815         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
 816         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
 817
 818         if (config->active_polarity)
 819                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
 820         else
 821                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
 822
 823         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
 824         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
 825         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
 826
 827         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
 828         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
 829         value |= config->hblank_symbols & 0xffff;
 830         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
 831
 832         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
 833         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
 834         value |= config->vblank_symbols & 0xffff;
 835         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
 836 }
 837
 838 static void tegra_sor_mode_set(struct tegra_sor *sor,
 839                                const struct drm_display_mode *mode,
 840                                struct tegra_sor_state *state)
 841 {
 842         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
 843         unsigned int vbe, vse, hbe, hse, vbs, hbs;
 844         u32 value;
 845
 846         value = tegra_sor_readl(sor, SOR_STATE1);
 847         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
 848         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
 849         value &= ~SOR_STATE_ASY_OWNER_MASK;
 850
 851         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
 852                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
 853
 854         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 855                 value &= ~SOR_STATE_ASY_HSYNCPOL;
 856
 857         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 858                 value |= SOR_STATE_ASY_HSYNCPOL;
 859
 860         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 861                 value &= ~SOR_STATE_ASY_VSYNCPOL;
 862
 863         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 864                 value |= SOR_STATE_ASY_VSYNCPOL;
 865
 866         switch (state->bpc) {
 867         case 16:
 868                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
 869                 break;
 870
 871         case 12:
 872                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
 873                 break;
 874
 875         case 10:
 876                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
 877                 break;
 878
 879         case 8:
 880                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
 881                 break;
 882
 883         case 6:
 884                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
 885                 break;
 886
 887         default:
 888                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
 889                 break;
 890         }
 891
 892         tegra_sor_writel(sor, value, SOR_STATE1);
 893
 894         /*
 895          * TODO: The video timing programming below doesn't seem to match the
 896          * register definitions.
 897          */
 898
 899         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
 900         tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));
 901
 902         /* sync end = sync width - 1 */
 903         vse = mode->vsync_end - mode->vsync_start - 1;
 904         hse = mode->hsync_end - mode->hsync_start - 1;
 905
 906         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
 907         tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));
 908
 909         /* blank end = sync end + back porch */
 910         vbe = vse + (mode->vtotal - mode->vsync_end);
 911         hbe = hse + (mode->htotal - mode->hsync_end);
 912
 913         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
 914         tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));
 915
 916         /* blank start = blank end + active */
 917         vbs = vbe + mode->vdisplay;
 918         hbs = hbe + mode->hdisplay;
 919
 920         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
 921         tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));
 922
 923         /* XXX interlacing support */
 924         tegra_sor_writel(sor, 0x001, SOR_HEAD_STATE5(dc->pipe));
 925 }
 926
 927 static int tegra_sor_detach(struct tegra_sor *sor)
 928 {
 929         unsigned long value, timeout;
 930
 931         /* switch to safe mode */
 932         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 933         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
 934         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 935         tegra_sor_super_update(sor);
 936
 937         timeout = jiffies + msecs_to_jiffies(250);
 938
 939         while (time_before(jiffies, timeout)) {
 940                 value = tegra_sor_readl(sor, SOR_PWR);
 941                 if (value & SOR_PWR_MODE_SAFE)
 942                         break;
 943         }
 944
 945         if ((value & SOR_PWR_MODE_SAFE) == 0)
 946                 return -ETIMEDOUT;
 947
 948         /* go to sleep */
 949         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 950         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
 951         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 952         tegra_sor_super_update(sor);
 953
 954         /* detach */
 955         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 956         value &= ~SOR_SUPER_STATE_ATTACHED;
 957         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 958         tegra_sor_super_update(sor);
 959
 960         timeout = jiffies + msecs_to_jiffies(250);
 961
 962         while (time_before(jiffies, timeout)) {
 963                 value = tegra_sor_readl(sor, SOR_TEST);
 964                 if ((value & SOR_TEST_ATTACHED) == 0)
 965                         break;
 966
 967                 usleep_range(25, 100);
 968         }
 969
 970         if ((value & SOR_TEST_ATTACHED) != 0)
 971                 return -ETIMEDOUT;
 972
 973         return 0;
 974 }
 975
 976 static int tegra_sor_power_down(struct tegra_sor *sor)
 977 {
 978         unsigned long value, timeout;
 979         int err;
 980
 981         value = tegra_sor_readl(sor, SOR_PWR);
 982         value &= ~SOR_PWR_NORMAL_STATE_PU;
 983         value |= SOR_PWR_TRIGGER;
 984         tegra_sor_writel(sor, value, SOR_PWR);
 985
 986         timeout = jiffies + msecs_to_jiffies(250);
 987
 988         while (time_before(jiffies, timeout)) {
 989                 value = tegra_sor_readl(sor, SOR_PWR);
 990                 if ((value & SOR_PWR_TRIGGER) == 0)
 991                         return 0;
 992
 993                 usleep_range(25, 100);
 994         }
 995
 996         if ((value & SOR_PWR_TRIGGER) != 0)
 997                 return -ETIMEDOUT;
 998
 999         /* switch to safe parent clock */
1000         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1001         if (err < 0) {
1002                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1003                 return err;
1004         }
1005
1006         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1007         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1008                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1009         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1010
1011         /* stop lane sequencer */
1012         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1013                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1014         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1015
1016         timeout = jiffies + msecs_to_jiffies(250);
1017
1018         while (time_before(jiffies, timeout)) {
1019                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1020                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1021                         break;
1022
1023                 usleep_range(25, 100);
1024         }
1025
1026         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1027                 return -ETIMEDOUT;
1028
1029         value = tegra_sor_readl(sor, SOR_PLL2);
1030         value |= SOR_PLL2_PORT_POWERDOWN;
1031         tegra_sor_writel(sor, value, SOR_PLL2);
1032
1033         usleep_range(20, 100);
1034
1035         value = tegra_sor_readl(sor, SOR_PLL0);
1036         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1037         tegra_sor_writel(sor, value, SOR_PLL0);
1038
1039         value = tegra_sor_readl(sor, SOR_PLL2);
1040         value |= SOR_PLL2_SEQ_PLLCAPPD;
1041         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1042         tegra_sor_writel(sor, value, SOR_PLL2);
1043
1044         usleep_range(20, 100);
1045
1046         return 0;
1047 }
1048
1049 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1050 {
1051         u32 value;
1052
1053         timeout = jiffies + msecs_to_jiffies(timeout);
1054
1055         while (time_before(jiffies, timeout)) {
1056                 value = tegra_sor_readl(sor, SOR_CRCA);
1057                 if (value & SOR_CRCA_VALID)
1058                         return 0;
1059
1060                 usleep_range(100, 200);
1061         }
1062
1063         return -ETIMEDOUT;
1064 }
1065
1066 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1067 {
1068         struct drm_info_node *node = s->private;
1069         struct tegra_sor *sor = node->info_ent->data;
1070         struct drm_crtc *crtc = sor->output.encoder.crtc;
1071         struct drm_device *drm = node->minor->dev;
1072         int err = 0;
1073         u32 value;
1074
1075         drm_modeset_lock_all(drm);
1076
1077         if (!crtc || !crtc->state->active) {
1078                 err = -EBUSY;
1079                 goto unlock;
1080         }
1081
1082         value = tegra_sor_readl(sor, SOR_STATE1);
1083         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1084         tegra_sor_writel(sor, value, SOR_STATE1);
1085
1086         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1087         value |= SOR_CRC_CNTRL_ENABLE;
1088         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1089
1090         value = tegra_sor_readl(sor, SOR_TEST);
1091         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1092         tegra_sor_writel(sor, value, SOR_TEST);
1093
1094         err = tegra_sor_crc_wait(sor, 100);
1095         if (err < 0)
1096                 goto unlock;
1097
1098         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1099         value = tegra_sor_readl(sor, SOR_CRCB);
1100
1101         seq_printf(s, "%08x\n", value);
1102
1103 unlock:
1104         drm_modeset_unlock_all(drm);
1105         return err;
1106 }
1107
1108 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1109 {
1110         struct drm_info_node *node = s->private;
1111         struct tegra_sor *sor = node->info_ent->data;
1112         struct drm_crtc *crtc = sor->output.encoder.crtc;
1113         struct drm_device *drm = node->minor->dev;
1114         int err = 0;
1115
1116         drm_modeset_lock_all(drm);
1117
1118         if (!crtc || !crtc->state->active) {
1119                 err = -EBUSY;
1120                 goto unlock;
1121         }
1122
1123 #define DUMP_REG(name)                                          \
1124         seq_printf(s, "%-38s %#05x %08x\n", #name, name,        \
1125                    tegra_sor_readl(sor, name))
1126
1127         DUMP_REG(SOR_CTXSW);
1128         DUMP_REG(SOR_SUPER_STATE0);
1129         DUMP_REG(SOR_SUPER_STATE1);
1130         DUMP_REG(SOR_STATE0);
1131         DUMP_REG(SOR_STATE1);
1132         DUMP_REG(SOR_HEAD_STATE0(0));
1133         DUMP_REG(SOR_HEAD_STATE0(1));
1134         DUMP_REG(SOR_HEAD_STATE1(0));
1135         DUMP_REG(SOR_HEAD_STATE1(1));
1136         DUMP_REG(SOR_HEAD_STATE2(0));
1137         DUMP_REG(SOR_HEAD_STATE2(1));
1138         DUMP_REG(SOR_HEAD_STATE3(0));
1139         DUMP_REG(SOR_HEAD_STATE3(1));
1140         DUMP_REG(SOR_HEAD_STATE4(0));
1141         DUMP_REG(SOR_HEAD_STATE4(1));
1142         DUMP_REG(SOR_HEAD_STATE5(0));
1143         DUMP_REG(SOR_HEAD_STATE5(1));
1144         DUMP_REG(SOR_CRC_CNTRL);
1145         DUMP_REG(SOR_DP_DEBUG_MVID);
1146         DUMP_REG(SOR_CLK_CNTRL);
1147         DUMP_REG(SOR_CAP);
1148         DUMP_REG(SOR_PWR);
1149         DUMP_REG(SOR_TEST);
1150         DUMP_REG(SOR_PLL0);
1151         DUMP_REG(SOR_PLL1);
1152         DUMP_REG(SOR_PLL2);
1153         DUMP_REG(SOR_PLL3);
1154         DUMP_REG(SOR_CSTM);
1155         DUMP_REG(SOR_LVDS);
1156         DUMP_REG(SOR_CRCA);
1157         DUMP_REG(SOR_CRCB);
1158         DUMP_REG(SOR_BLANK);
1159         DUMP_REG(SOR_SEQ_CTL);
1160         DUMP_REG(SOR_LANE_SEQ_CTL);
1161         DUMP_REG(SOR_SEQ_INST(0));
1162         DUMP_REG(SOR_SEQ_INST(1));
1163         DUMP_REG(SOR_SEQ_INST(2));
1164         DUMP_REG(SOR_SEQ_INST(3));
1165         DUMP_REG(SOR_SEQ_INST(4));
1166         DUMP_REG(SOR_SEQ_INST(5));
1167         DUMP_REG(SOR_SEQ_INST(6));
1168         DUMP_REG(SOR_SEQ_INST(7));
1169         DUMP_REG(SOR_SEQ_INST(8));
1170         DUMP_REG(SOR_SEQ_INST(9));
1171         DUMP_REG(SOR_SEQ_INST(10));
1172         DUMP_REG(SOR_SEQ_INST(11));
1173         DUMP_REG(SOR_SEQ_INST(12));
1174         DUMP_REG(SOR_SEQ_INST(13));
1175         DUMP_REG(SOR_SEQ_INST(14));
1176         DUMP_REG(SOR_SEQ_INST(15));
1177         DUMP_REG(SOR_PWM_DIV);
1178         DUMP_REG(SOR_PWM_CTL);
1179         DUMP_REG(SOR_VCRC_A0);
1180         DUMP_REG(SOR_VCRC_A1);
1181         DUMP_REG(SOR_VCRC_B0);
1182         DUMP_REG(SOR_VCRC_B1);
1183         DUMP_REG(SOR_CCRC_A0);
1184         DUMP_REG(SOR_CCRC_A1);
1185         DUMP_REG(SOR_CCRC_B0);
1186         DUMP_REG(SOR_CCRC_B1);
1187         DUMP_REG(SOR_EDATA_A0);
1188         DUMP_REG(SOR_EDATA_A1);
1189         DUMP_REG(SOR_EDATA_B0);
1190         DUMP_REG(SOR_EDATA_B1);
1191         DUMP_REG(SOR_COUNT_A0);
1192         DUMP_REG(SOR_COUNT_A1);
1193         DUMP_REG(SOR_COUNT_B0);
1194         DUMP_REG(SOR_COUNT_B1);
1195         DUMP_REG(SOR_DEBUG_A0);
1196         DUMP_REG(SOR_DEBUG_A1);
1197         DUMP_REG(SOR_DEBUG_B0);
1198         DUMP_REG(SOR_DEBUG_B1);
1199         DUMP_REG(SOR_TRIG);
1200         DUMP_REG(SOR_MSCHECK);
1201         DUMP_REG(SOR_XBAR_CTRL);
1202         DUMP_REG(SOR_XBAR_POL);
1203         DUMP_REG(SOR_DP_LINKCTL0);
1204         DUMP_REG(SOR_DP_LINKCTL1);
1205         DUMP_REG(SOR_LANE_DRIVE_CURRENT0);
1206         DUMP_REG(SOR_LANE_DRIVE_CURRENT1);
1207         DUMP_REG(SOR_LANE4_DRIVE_CURRENT0);
1208         DUMP_REG(SOR_LANE4_DRIVE_CURRENT1);
1209         DUMP_REG(SOR_LANE_PREEMPHASIS0);
1210         DUMP_REG(SOR_LANE_PREEMPHASIS1);
1211         DUMP_REG(SOR_LANE4_PREEMPHASIS0);
1212         DUMP_REG(SOR_LANE4_PREEMPHASIS1);
1213         DUMP_REG(SOR_LANE_POSTCURSOR0);
1214         DUMP_REG(SOR_LANE_POSTCURSOR1);
1215         DUMP_REG(SOR_DP_CONFIG0);
1216         DUMP_REG(SOR_DP_CONFIG1);
1217         DUMP_REG(SOR_DP_MN0);
1218         DUMP_REG(SOR_DP_MN1);
1219         DUMP_REG(SOR_DP_PADCTL0);
1220         DUMP_REG(SOR_DP_PADCTL1);
1221         DUMP_REG(SOR_DP_DEBUG0);
1222         DUMP_REG(SOR_DP_DEBUG1);
1223         DUMP_REG(SOR_DP_SPARE0);
1224         DUMP_REG(SOR_DP_SPARE1);
1225         DUMP_REG(SOR_DP_AUDIO_CTRL);
1226         DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS);
1227         DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS);
1228         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER);
1229         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0);
1230         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1);
1231         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2);
1232         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3);
1233         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4);
1234         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5);
1235         DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6);
1236         DUMP_REG(SOR_DP_TPG);
1237         DUMP_REG(SOR_DP_TPG_CONFIG);
1238         DUMP_REG(SOR_DP_LQ_CSTM0);
1239         DUMP_REG(SOR_DP_LQ_CSTM1);
1240         DUMP_REG(SOR_DP_LQ_CSTM2);
1241
1242 #undef DUMP_REG
1243
1244 unlock:
1245         drm_modeset_unlock_all(drm);
1246         return err;
1247 }
1248
1249 static const struct drm_info_list debugfs_files[] = {
1250         { "crc", tegra_sor_show_crc, 0, NULL },
1251         { "regs", tegra_sor_show_regs, 0, NULL },
1252 };
1253
1254 static int tegra_sor_debugfs_init(struct tegra_sor *sor,
1255                                   struct drm_minor *minor)
1256 {
1257         const char *name = sor->soc->supports_dp ? "sor1" : "sor";
1258         unsigned int i;
1259         int err;
1260
1261         sor->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1262         if (!sor->debugfs)
1263                 return -ENOMEM;
1264
1265         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1266                                      GFP_KERNEL);
1267         if (!sor->debugfs_files) {
1268                 err = -ENOMEM;
1269                 goto remove;
1270         }
1271
1272         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1273                 sor->debugfs_files[i].data = sor;
1274
1275         err = drm_debugfs_create_files(sor->debugfs_files,
1276                                        ARRAY_SIZE(debugfs_files),
1277                                        sor->debugfs, minor);
1278         if (err < 0)
1279                 goto free;
1280
1281         sor->minor = minor;
1282
1283         return 0;
1284
1285 free:
1286         kfree(sor->debugfs_files);
1287         sor->debugfs_files = NULL;
1288 remove:
1289         debugfs_remove_recursive(sor->debugfs);
1290         sor->debugfs = NULL;
1291         return err;
1292 }
1293
1294 static void tegra_sor_debugfs_exit(struct tegra_sor *sor)
1295 {
1296         drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files),
1297                                  sor->minor);
1298         sor->minor = NULL;
1299
1300         kfree(sor->debugfs_files);
1301         sor->debugfs_files = NULL;
1302
1303         debugfs_remove_recursive(sor->debugfs);
1304         sor->debugfs = NULL;
1305 }
1306
1307 static void tegra_sor_connector_reset(struct drm_connector *connector)
1308 {
1309         struct tegra_sor_state *state;
1310
1311         state = kzalloc(sizeof(*state), GFP_KERNEL);
1312         if (!state)
1313                 return;
1314
1315         if (connector->state) {
1316                 __drm_atomic_helper_connector_destroy_state(connector->state);
1317                 kfree(connector->state);
1318         }
1319
1320         __drm_atomic_helper_connector_reset(connector, &state->base);
1321 }
1322
1323 static enum drm_connector_status
1324 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1325 {
1326         struct tegra_output *output = connector_to_output(connector);
1327         struct tegra_sor *sor = to_sor(output);
1328
1329         if (sor->aux)
1330                 return drm_dp_aux_detect(sor->aux);
1331
1332         return tegra_output_connector_detect(connector, force);
1333 }
1334
1335 static struct drm_connector_state *
1336 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1337 {
1338         struct tegra_sor_state *state = to_sor_state(connector->state);
1339         struct tegra_sor_state *copy;
1340
1341         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1342         if (!copy)
1343                 return NULL;
1344
1345         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1346
1347         return &copy->base;
1348 }
1349
1350 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1351         .reset = tegra_sor_connector_reset,
1352         .detect = tegra_sor_connector_detect,
1353         .fill_modes = drm_helper_probe_single_connector_modes,
1354         .destroy = tegra_output_connector_destroy,
1355         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1356         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1357 };
1358
1359 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1360 {
1361         struct tegra_output *output = connector_to_output(connector);
1362         struct tegra_sor *sor = to_sor(output);
1363         int err;
1364
1365         if (sor->aux)
1366                 drm_dp_aux_enable(sor->aux);
1367
1368         err = tegra_output_connector_get_modes(connector);
1369
1370         if (sor->aux)
1371                 drm_dp_aux_disable(sor->aux);
1372
1373         return err;
1374 }
1375
1376 static enum drm_mode_status
1377 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1378                                struct drm_display_mode *mode)
1379 {
1380         /* HDMI 2.0 modes are not yet supported */
1381         if (mode->clock > 340000)
1382                 return MODE_NOCLOCK;
1383
1384         return MODE_OK;
1385 }
1386
1387 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1388         .get_modes = tegra_sor_connector_get_modes,
1389         .mode_valid = tegra_sor_connector_mode_valid,
1390 };
1391
1392 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1393         .destroy = tegra_output_encoder_destroy,
1394 };
1395
1396 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1397 {
1398         struct tegra_output *output = encoder_to_output(encoder);
1399         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1400         struct tegra_sor *sor = to_sor(output);
1401         u32 value;
1402         int err;
1403
1404         if (output->panel)
1405                 drm_panel_disable(output->panel);
1406
1407         err = tegra_sor_detach(sor);
1408         if (err < 0)
1409                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1410
1411         tegra_sor_writel(sor, 0, SOR_STATE1);
1412         tegra_sor_update(sor);
1413
1414         /*
1415          * The following accesses registers of the display controller, so make
1416          * sure it's only executed when the output is attached to one.
1417          */
1418         if (dc) {
1419                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1420                 value &= ~SOR_ENABLE;
1421                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1422
1423                 tegra_dc_commit(dc);
1424         }
1425
1426         err = tegra_sor_power_down(sor);
1427         if (err < 0)
1428                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1429
1430         if (sor->aux) {
1431                 err = drm_dp_aux_disable(sor->aux);
1432                 if (err < 0)
1433                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1434         }
1435
1436         err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
1437         if (err < 0)
1438                 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
1439
1440         if (output->panel)
1441                 drm_panel_unprepare(output->panel);
1442
1443         pm_runtime_put(sor->dev);
1444 }
1445
1446 #if 0
1447 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1448                               unsigned int *value)
1449 {
1450         unsigned int hfp, hsw, hbp, a = 0, b;
1451
1452         hfp = mode->hsync_start - mode->hdisplay;
1453         hsw = mode->hsync_end - mode->hsync_start;
1454         hbp = mode->htotal - mode->hsync_end;
1455
1456         pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1457
1458         b = hfp - 1;
1459
1460         pr_info("a: %u, b: %u\n", a, b);
1461         pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1462
1463         if (a + hsw + hbp <= 11) {
1464                 a = 1 + 11 - hsw - hbp;
1465                 pr_info("a: %u\n", a);
1466         }
1467
1468         if (a > b)
1469                 return -EINVAL;
1470
1471         if (hsw < 1)
1472                 return -EINVAL;
1473
1474         if (mode->hdisplay < 16)
1475                 return -EINVAL;
1476
1477         if (value) {
1478                 if (b > a && a % 2)
1479                         *value = a + 1;
1480                 else
1481                         *value = a;
1482         }
1483
1484         return 0;
1485 }
1486 #endif
1487
1488 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1489 {
1490         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1491         struct tegra_output *output = encoder_to_output(encoder);
1492         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1493         struct tegra_sor *sor = to_sor(output);
1494         struct tegra_sor_config config;
1495         struct tegra_sor_state *state;
1496         struct drm_dp_link link;
1497         u8 rate, lanes;
1498         unsigned int i;
1499         int err = 0;
1500         u32 value;
1501
1502         state = to_sor_state(output->connector.state);
1503
1504         pm_runtime_get_sync(sor->dev);
1505
1506         if (output->panel)
1507                 drm_panel_prepare(output->panel);
1508
1509         err = drm_dp_aux_enable(sor->aux);
1510         if (err < 0)
1511                 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1512
1513         err = drm_dp_link_probe(sor->aux, &link);
1514         if (err < 0) {
1515                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1516                 return;
1517         }
1518
1519         /* switch to safe parent clock */
1520         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1521         if (err < 0)
1522                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1523
1524         memset(&config, 0, sizeof(config));
1525         config.bits_per_pixel = state->bpc * 3;
1526
1527         err = tegra_sor_compute_config(sor, mode, &config, &link);
1528         if (err < 0)
1529                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1530
1531         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1532         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1533         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1534         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1535
1536         value = tegra_sor_readl(sor, SOR_PLL2);
1537         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1538         tegra_sor_writel(sor, value, SOR_PLL2);
1539         usleep_range(20, 100);
1540
1541         value = tegra_sor_readl(sor, SOR_PLL3);
1542         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1543         tegra_sor_writel(sor, value, SOR_PLL3);
1544
1545         value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1546                 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1547         tegra_sor_writel(sor, value, SOR_PLL0);
1548
1549         value = tegra_sor_readl(sor, SOR_PLL2);
1550         value |= SOR_PLL2_SEQ_PLLCAPPD;
1551         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1552         value |= SOR_PLL2_LVDS_ENABLE;
1553         tegra_sor_writel(sor, value, SOR_PLL2);
1554
1555         value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1556         tegra_sor_writel(sor, value, SOR_PLL1);
1557
1558         while (true) {
1559                 value = tegra_sor_readl(sor, SOR_PLL2);
1560                 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1561                         break;
1562
1563                 usleep_range(250, 1000);
1564         }
1565
1566         value = tegra_sor_readl(sor, SOR_PLL2);
1567         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1568         value &= ~SOR_PLL2_PORT_POWERDOWN;
1569         tegra_sor_writel(sor, value, SOR_PLL2);
1570
1571         /*
1572          * power up
1573          */
1574
1575         /* set safe link bandwidth (1.62 Gbps) */
1576         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1577         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1578         value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1579         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1580
1581         /* step 1 */
1582         value = tegra_sor_readl(sor, SOR_PLL2);
1583         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1584                  SOR_PLL2_BANDGAP_POWERDOWN;
1585         tegra_sor_writel(sor, value, SOR_PLL2);
1586
1587         value = tegra_sor_readl(sor, SOR_PLL0);
1588         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1589         tegra_sor_writel(sor, value, SOR_PLL0);
1590
1591         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1592         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1593         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1594
1595         /* step 2 */
1596         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
1597         if (err < 0)
1598                 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
1599
1600         usleep_range(5, 100);
1601
1602         /* step 3 */
1603         value = tegra_sor_readl(sor, SOR_PLL2);
1604         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1605         tegra_sor_writel(sor, value, SOR_PLL2);
1606
1607         usleep_range(20, 100);
1608
1609         /* step 4 */
1610         value = tegra_sor_readl(sor, SOR_PLL0);
1611         value &= ~SOR_PLL0_VCOPD;
1612         value &= ~SOR_PLL0_PWR;
1613         tegra_sor_writel(sor, value, SOR_PLL0);
1614
1615         value = tegra_sor_readl(sor, SOR_PLL2);
1616         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1617         tegra_sor_writel(sor, value, SOR_PLL2);
1618
1619         usleep_range(200, 1000);
1620
1621         /* step 5 */
1622         value = tegra_sor_readl(sor, SOR_PLL2);
1623         value &= ~SOR_PLL2_PORT_POWERDOWN;
1624         tegra_sor_writel(sor, value, SOR_PLL2);
1625
1626         /* XXX not in TRM */
1627         for (value = 0, i = 0; i < 5; i++)
1628                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
1629                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1630
1631         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1632         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1633
1634         /* switch to DP parent clock */
1635         err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1636         if (err < 0)
1637                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1638
1639         /* power DP lanes */
1640         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1641
1642         if (link.num_lanes <= 2)
1643                 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1644         else
1645                 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1646
1647         if (link.num_lanes <= 1)
1648                 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1649         else
1650                 value |= SOR_DP_PADCTL_PD_TXD_1;
1651
1652         if (link.num_lanes == 0)
1653                 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1654         else
1655                 value |= SOR_DP_PADCTL_PD_TXD_0;
1656
1657         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1658
1659         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1660         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1661         value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1662         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1663
1664         /* start lane sequencer */
1665         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1666                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1667         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1668
1669         while (true) {
1670                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1671                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1672                         break;
1673
1674                 usleep_range(250, 1000);
1675         }
1676
1677         /* set link bandwidth */
1678         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1679         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1680         value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1681         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1682
1683         tegra_sor_apply_config(sor, &config);
1684
1685         /* enable link */
1686         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1687         value |= SOR_DP_LINKCTL_ENABLE;
1688         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1689         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1690
1691         for (i = 0, value = 0; i < 4; i++) {
1692                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1693                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1694                                      SOR_DP_TPG_PATTERN_NONE;
1695                 value = (value << 8) | lane;
1696         }
1697
1698         tegra_sor_writel(sor, value, SOR_DP_TPG);
1699
1700         /* enable pad calibration logic */
1701         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1702         value |= SOR_DP_PADCTL_PAD_CAL_PD;
1703         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1704
1705         err = drm_dp_link_probe(sor->aux, &link);
1706         if (err < 0)
1707                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1708
1709         err = drm_dp_link_power_up(sor->aux, &link);
1710         if (err < 0)
1711                 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1712
1713         err = drm_dp_link_configure(sor->aux, &link);
1714         if (err < 0)
1715                 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1716
1717         rate = drm_dp_link_rate_to_bw_code(link.rate);
1718         lanes = link.num_lanes;
1719
1720         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1721         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1722         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1723         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1724
1725         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1726         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1727         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1728
1729         if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1730                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1731
1732         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1733
1734         /* disable training pattern generator */
1735
1736         for (i = 0; i < link.num_lanes; i++) {
1737                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1738                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1739                                      SOR_DP_TPG_PATTERN_NONE;
1740                 value = (value << 8) | lane;
1741         }
1742
1743         tegra_sor_writel(sor, value, SOR_DP_TPG);
1744
1745         err = tegra_sor_dp_train_fast(sor, &link);
1746         if (err < 0)
1747                 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1748
1749         dev_dbg(sor->dev, "fast link training succeeded\n");
1750
1751         err = tegra_sor_power_up(sor, 250);
1752         if (err < 0)
1753                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1754
1755         /* CSTM (LVDS, link A/B, upper) */
1756         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1757                 SOR_CSTM_UPPER;
1758         tegra_sor_writel(sor, value, SOR_CSTM);
1759
1760         /* use DP-A protocol */
1761         value = tegra_sor_readl(sor, SOR_STATE1);
1762         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1763         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1764         tegra_sor_writel(sor, value, SOR_STATE1);
1765
1766         tegra_sor_mode_set(sor, mode, state);
1767
1768         /* PWM setup */
1769         err = tegra_sor_setup_pwm(sor, 250);
1770         if (err < 0)
1771                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1772
1773         tegra_sor_update(sor);
1774
1775         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1776         value |= SOR_ENABLE;
1777         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1778
1779         tegra_dc_commit(dc);
1780
1781         err = tegra_sor_attach(sor);
1782         if (err < 0)
1783                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1784
1785         err = tegra_sor_wakeup(sor);
1786         if (err < 0)
1787                 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1788
1789         if (output->panel)
1790                 drm_panel_enable(output->panel);
1791 }
1792
1793 static int
1794 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1795                                struct drm_crtc_state *crtc_state,
1796                                struct drm_connector_state *conn_state)
1797 {
1798         struct tegra_output *output = encoder_to_output(encoder);
1799         struct tegra_sor_state *state = to_sor_state(conn_state);
1800         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1801         unsigned long pclk = crtc_state->mode.clock * 1000;
1802         struct tegra_sor *sor = to_sor(output);
1803         struct drm_display_info *info;
1804         int err;
1805
1806         info = &output->connector.display_info;
1807
1808         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1809                                          pclk, 0);
1810         if (err < 0) {
1811                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1812                 return err;
1813         }
1814
1815         switch (info->bpc) {
1816         case 8:
1817         case 6:
1818                 state->bpc = info->bpc;
1819                 break;
1820
1821         default:
1822                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1823                 state->bpc = 8;
1824                 break;
1825         }
1826
1827         return 0;
1828 }
1829
1830 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
1831         .disable = tegra_sor_edp_disable,
1832         .enable = tegra_sor_edp_enable,
1833         .atomic_check = tegra_sor_encoder_atomic_check,
1834 };
1835
1836 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1837 {
1838         u32 value = 0;
1839         size_t i;
1840
1841         for (i = size; i > 0; i--)
1842                 value = (value << 8) | ptr[i - 1];
1843
1844         return value;
1845 }
1846
1847 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1848                                           const void *data, size_t size)
1849 {
1850         const u8 *ptr = data;
1851         unsigned long offset;
1852         size_t i, j;
1853         u32 value;
1854
1855         switch (ptr[0]) {
1856         case HDMI_INFOFRAME_TYPE_AVI:
1857                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1858                 break;
1859
1860         case HDMI_INFOFRAME_TYPE_AUDIO:
1861                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1862                 break;
1863
1864         case HDMI_INFOFRAME_TYPE_VENDOR:
1865                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1866                 break;
1867
1868         default:
1869                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1870                         ptr[0]);
1871                 return;
1872         }
1873
1874         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1875                 INFOFRAME_HEADER_VERSION(ptr[1]) |
1876                 INFOFRAME_HEADER_LEN(ptr[2]);
1877         tegra_sor_writel(sor, value, offset);
1878         offset++;
1879
1880         /*
1881          * Each subpack contains 7 bytes, divided into:
1882          * - subpack_low: bytes 0 - 3
1883          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1884          */
1885         for (i = 3, j = 0; i < size; i += 7, j += 8) {
1886                 size_t rem = size - i, num = min_t(size_t, rem, 4);
1887
1888                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1889                 tegra_sor_writel(sor, value, offset++);
1890
1891                 num = min_t(size_t, rem - num, 3);
1892
1893                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1894                 tegra_sor_writel(sor, value, offset++);
1895         }
1896 }
1897
1898 static int
1899 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1900                                    const struct drm_display_mode *mode)
1901 {
1902         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1903         struct hdmi_avi_infoframe frame;
1904         u32 value;
1905         int err;
1906
1907         /* disable AVI infoframe */
1908         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1909         value &= ~INFOFRAME_CTRL_SINGLE;
1910         value &= ~INFOFRAME_CTRL_OTHER;
1911         value &= ~INFOFRAME_CTRL_ENABLE;
1912         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1913
1914         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1915         if (err < 0) {
1916                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1917                 return err;
1918         }
1919
1920         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1921         if (err < 0) {
1922                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1923                 return err;
1924         }
1925
1926         tegra_sor_hdmi_write_infopack(sor, buffer, err);
1927
1928         /* enable AVI infoframe */
1929         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1930         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1931         value |= INFOFRAME_CTRL_ENABLE;
1932         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1933
1934         return 0;
1935 }
1936
1937 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
1938 {
1939         u32 value;
1940
1941         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1942         value &= ~INFOFRAME_CTRL_ENABLE;
1943         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1944 }
1945
1946 static struct tegra_sor_hdmi_settings *
1947 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
1948 {
1949         unsigned int i;
1950
1951         for (i = 0; i < sor->num_settings; i++)
1952                 if (frequency <= sor->settings[i].frequency)
1953                         return &sor->settings[i];
1954
1955         return NULL;
1956 }
1957
1958 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
1959 {
1960         struct tegra_output *output = encoder_to_output(encoder);
1961         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1962         struct tegra_sor *sor = to_sor(output);
1963         u32 value;
1964         int err;
1965
1966         err = tegra_sor_detach(sor);
1967         if (err < 0)
1968                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1969
1970         tegra_sor_writel(sor, 0, SOR_STATE1);
1971         tegra_sor_update(sor);
1972
1973         /* disable display to SOR clock */
1974         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1975         value &= ~SOR1_TIMING_CYA;
1976         value &= ~SOR1_ENABLE;
1977         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1978
1979         tegra_dc_commit(dc);
1980
1981         err = tegra_sor_power_down(sor);
1982         if (err < 0)
1983                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1984
1985         err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI);
1986         if (err < 0)
1987                 dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err);
1988
1989         pm_runtime_put(sor->dev);
1990 }
1991
1992 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
1993 {
1994         struct tegra_output *output = encoder_to_output(encoder);
1995         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
1996         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1997         struct tegra_sor_hdmi_settings *settings;
1998         struct tegra_sor *sor = to_sor(output);
1999         struct tegra_sor_state *state;
2000         struct drm_display_mode *mode;
2001         unsigned int div, i;
2002         u32 value;
2003         int err;
2004
2005         state = to_sor_state(output->connector.state);
2006         mode = &encoder->crtc->state->adjusted_mode;
2007
2008         pm_runtime_get_sync(sor->dev);
2009
2010         /* switch to safe parent clock */
2011         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2012         if (err < 0) {
2013                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2014                 return;
2015         }
2016
2017         div = clk_get_rate(sor->clk) / 1000000 * 4;
2018
2019         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI);
2020         if (err < 0)
2021                 dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err);
2022
2023         usleep_range(20, 100);
2024
2025         value = tegra_sor_readl(sor, SOR_PLL2);
2026         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2027         tegra_sor_writel(sor, value, SOR_PLL2);
2028
2029         usleep_range(20, 100);
2030
2031         value = tegra_sor_readl(sor, SOR_PLL3);
2032         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2033         tegra_sor_writel(sor, value, SOR_PLL3);
2034
2035         value = tegra_sor_readl(sor, SOR_PLL0);
2036         value &= ~SOR_PLL0_VCOPD;
2037         value &= ~SOR_PLL0_PWR;
2038         tegra_sor_writel(sor, value, SOR_PLL0);
2039
2040         value = tegra_sor_readl(sor, SOR_PLL2);
2041         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2042         tegra_sor_writel(sor, value, SOR_PLL2);
2043
2044         usleep_range(200, 400);
2045
2046         value = tegra_sor_readl(sor, SOR_PLL2);
2047         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2048         value &= ~SOR_PLL2_PORT_POWERDOWN;
2049         tegra_sor_writel(sor, value, SOR_PLL2);
2050
2051         usleep_range(20, 100);
2052
2053         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2054         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2055                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2056         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2057
2058         while (true) {
2059                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2060                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2061                         break;
2062
2063                 usleep_range(250, 1000);
2064         }
2065
2066         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2067                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2068         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2069
2070         while (true) {
2071                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2072                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2073                         break;
2074
2075                 usleep_range(250, 1000);
2076         }
2077
2078         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2079         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2080         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2081
2082         if (mode->clock < 340000)
2083                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2084         else
2085                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2086
2087         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2088         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2089
2090         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2091         value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2092         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2093         value |= SOR_DP_SPARE_SEQ_ENABLE;
2094         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2095
2096         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2097                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2098         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2099
2100         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2101                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2102         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2103         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2104
2105         /* program the reference clock */
2106         value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2107         tegra_sor_writel(sor, value, SOR_REFCLK);
2108
2109         /* XXX not in TRM */
2110         for (value = 0, i = 0; i < 5; i++)
2111                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2112                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2113
2114         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2115         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2116
2117         /* switch to parent clock */
2118         err = clk_set_parent(sor->clk, sor->clk_parent);
2119         if (err < 0) {
2120                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2121                 return;
2122         }
2123
2124         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2125         if (err < 0) {
2126                 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2127                 return;
2128         }
2129
2130         value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2131
2132         /* XXX is this the proper check? */
2133         if (mode->clock < 75000)
2134                 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2135
2136         tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2137
2138         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2139
2140         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2141                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2142         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2143
2144         /* H_PULSE2 setup */
2145         pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) +
2146                       (mode->htotal - mode->hsync_end) - 10;
2147
2148         value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2149                 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2150         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2151
2152         value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2153         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2154
2155         value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2156         value |= H_PULSE2_ENABLE;
2157         tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2158
2159         /* infoframe setup */
2160         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2161         if (err < 0)
2162                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2163
2164         /* XXX HDMI audio support not implemented yet */
2165         tegra_sor_hdmi_disable_audio_infoframe(sor);
2166
2167         /* use single TMDS protocol */
2168         value = tegra_sor_readl(sor, SOR_STATE1);
2169         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2170         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2171         tegra_sor_writel(sor, value, SOR_STATE1);
2172
2173         /* power up pad calibration */
2174         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2175         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2176         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2177
2178         /* production settings */
2179         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2180         if (!settings) {
2181                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2182                         mode->clock * 1000);
2183                 return;
2184         }
2185
2186         value = tegra_sor_readl(sor, SOR_PLL0);
2187         value &= ~SOR_PLL0_ICHPMP_MASK;
2188         value &= ~SOR_PLL0_VCOCAP_MASK;
2189         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2190         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2191         tegra_sor_writel(sor, value, SOR_PLL0);
2192
2193         tegra_sor_dp_term_calibrate(sor);
2194
2195         value = tegra_sor_readl(sor, SOR_PLL1);
2196         value &= ~SOR_PLL1_LOADADJ_MASK;
2197         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2198         tegra_sor_writel(sor, value, SOR_PLL1);
2199
2200         value = tegra_sor_readl(sor, SOR_PLL3);
2201         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2202         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref);
2203         tegra_sor_writel(sor, value, SOR_PLL3);
2204
2205         value = settings->drive_current[0] << 24 |
2206                 settings->drive_current[1] << 16 |
2207                 settings->drive_current[2] <<  8 |
2208                 settings->drive_current[3] <<  0;
2209         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2210
2211         value = settings->preemphasis[0] << 24 |
2212                 settings->preemphasis[1] << 16 |
2213                 settings->preemphasis[2] <<  8 |
2214                 settings->preemphasis[3] <<  0;
2215         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2216
2217         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2218         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2219         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2220         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu);
2221         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2222
2223         /* power down pad calibration */
2224         value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2225         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2226         tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2227
2228         /* miscellaneous display controller settings */
2229         value = VSYNC_H_POSITION(1);
2230         tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2231
2232         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2233         value &= ~DITHER_CONTROL_MASK;
2234         value &= ~BASE_COLOR_SIZE_MASK;
2235
2236         switch (state->bpc) {
2237         case 6:
2238                 value |= BASE_COLOR_SIZE_666;
2239                 break;
2240
2241         case 8:
2242                 value |= BASE_COLOR_SIZE_888;
2243                 break;
2244
2245         default:
2246                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2247                 value |= BASE_COLOR_SIZE_888;
2248                 break;
2249         }
2250
2251         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2252
2253         err = tegra_sor_power_up(sor, 250);
2254         if (err < 0)
2255                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2256
2257         /* configure dynamic range of output */
2258         value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2259         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2260         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2261         tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2262
2263         /* configure colorspace */
2264         value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2265         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2266         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2267         tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2268
2269         tegra_sor_mode_set(sor, mode, state);
2270
2271         tegra_sor_update(sor);
2272
2273         err = tegra_sor_attach(sor);
2274         if (err < 0)
2275                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2276
2277         /* enable display to SOR clock and generate HDMI preamble */
2278         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2279         value |= SOR1_ENABLE | SOR1_TIMING_CYA;
2280         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2281
2282         tegra_dc_commit(dc);
2283
2284         err = tegra_sor_wakeup(sor);
2285         if (err < 0)
2286                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2287 }
2288
2289 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2290         .disable = tegra_sor_hdmi_disable,
2291         .enable = tegra_sor_hdmi_enable,
2292         .atomic_check = tegra_sor_encoder_atomic_check,
2293 };
2294
2295 static int tegra_sor_init(struct host1x_client *client)
2296 {
2297         struct drm_device *drm = dev_get_drvdata(client->parent);
2298         const struct drm_encoder_helper_funcs *helpers = NULL;
2299         struct tegra_sor *sor = host1x_client_to_sor(client);
2300         int connector = DRM_MODE_CONNECTOR_Unknown;
2301         int encoder = DRM_MODE_ENCODER_NONE;
2302         int err;
2303
2304         if (!sor->aux) {
2305                 if (sor->soc->supports_hdmi) {
2306                         connector = DRM_MODE_CONNECTOR_HDMIA;
2307                         encoder = DRM_MODE_ENCODER_TMDS;
2308                         helpers = &tegra_sor_hdmi_helpers;
2309                 } else if (sor->soc->supports_lvds) {
2310                         connector = DRM_MODE_CONNECTOR_LVDS;
2311                         encoder = DRM_MODE_ENCODER_LVDS;
2312                 }
2313         } else {
2314                 if (sor->soc->supports_edp) {
2315                         connector = DRM_MODE_CONNECTOR_eDP;
2316                         encoder = DRM_MODE_ENCODER_TMDS;
2317                         helpers = &tegra_sor_edp_helpers;
2318                 } else if (sor->soc->supports_dp) {
2319                         connector = DRM_MODE_CONNECTOR_DisplayPort;
2320                         encoder = DRM_MODE_ENCODER_TMDS;
2321                 }
2322         }
2323
2324         sor->output.dev = sor->dev;
2325
2326         drm_connector_init(drm, &sor->output.connector,
2327                            &tegra_sor_connector_funcs,
2328                            connector);
2329         drm_connector_helper_add(&sor->output.connector,
2330                                  &tegra_sor_connector_helper_funcs);
2331         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2332
2333         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2334                          encoder, NULL);
2335         drm_encoder_helper_add(&sor->output.encoder, helpers);
2336
2337         drm_mode_connector_attach_encoder(&sor->output.connector,
2338                                           &sor->output.encoder);
2339         drm_connector_register(&sor->output.connector);
2340
2341         err = tegra_output_init(drm, &sor->output);
2342         if (err < 0) {
2343                 dev_err(client->dev, "failed to initialize output: %d\n", err);
2344                 return err;
2345         }
2346
2347         sor->output.encoder.possible_crtcs = 0x3;
2348
2349         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2350                 err = tegra_sor_debugfs_init(sor, drm->primary);
2351                 if (err < 0)
2352                         dev_err(sor->dev, "debugfs setup failed: %d\n", err);
2353         }
2354
2355         if (sor->aux) {
2356                 err = drm_dp_aux_attach(sor->aux, &sor->output);
2357                 if (err < 0) {
2358                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
2359                         return err;
2360                 }
2361         }
2362
2363         /*
2364          * XXX: Remove this reset once proper hand-over from firmware to
2365          * kernel is possible.
2366          */
2367         if (sor->rst) {
2368                 err = reset_control_assert(sor->rst);
2369                 if (err < 0) {
2370                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2371                                 err);
2372                         return err;
2373                 }
2374         }
2375
2376         err = clk_prepare_enable(sor->clk);
2377         if (err < 0) {
2378                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2379                 return err;
2380         }
2381
2382         usleep_range(1000, 3000);
2383
2384         if (sor->rst) {
2385                 err = reset_control_deassert(sor->rst);
2386                 if (err < 0) {
2387                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2388                                 err);
2389                         return err;
2390                 }
2391         }
2392
2393         err = clk_prepare_enable(sor->clk_safe);
2394         if (err < 0)
2395                 return err;
2396
2397         err = clk_prepare_enable(sor->clk_dp);
2398         if (err < 0)
2399                 return err;
2400
2401         return 0;
2402 }
2403
2404 static int tegra_sor_exit(struct host1x_client *client)
2405 {
2406         struct tegra_sor *sor = host1x_client_to_sor(client);
2407         int err;
2408
2409         tegra_output_exit(&sor->output);
2410
2411         if (sor->aux) {
2412                 err = drm_dp_aux_detach(sor->aux);
2413                 if (err < 0) {
2414                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
2415                         return err;
2416                 }
2417         }
2418
2419         clk_disable_unprepare(sor->clk_safe);
2420         clk_disable_unprepare(sor->clk_dp);
2421         clk_disable_unprepare(sor->clk);
2422
2423         if (IS_ENABLED(CONFIG_DEBUG_FS))
2424                 tegra_sor_debugfs_exit(sor);
2425
2426         return 0;
2427 }
2428
2429 static const struct host1x_client_ops sor_client_ops = {
2430         .init = tegra_sor_init,
2431         .exit = tegra_sor_exit,
2432 };
2433
2434 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2435         .name = "eDP",
2436 };
2437
2438 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2439 {
2440         int err;
2441
2442         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2443         if (IS_ERR(sor->avdd_io_supply)) {
2444                 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2445                         PTR_ERR(sor->avdd_io_supply));
2446                 return PTR_ERR(sor->avdd_io_supply);
2447         }
2448
2449         err = regulator_enable(sor->avdd_io_supply);
2450         if (err < 0) {
2451                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2452                         err);
2453                 return err;
2454         }
2455
2456         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2457         if (IS_ERR(sor->vdd_pll_supply)) {
2458                 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2459                         PTR_ERR(sor->vdd_pll_supply));
2460                 return PTR_ERR(sor->vdd_pll_supply);
2461         }
2462
2463         err = regulator_enable(sor->vdd_pll_supply);
2464         if (err < 0) {
2465                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2466                         err);
2467                 return err;
2468         }
2469
2470         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2471         if (IS_ERR(sor->hdmi_supply)) {
2472                 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2473                         PTR_ERR(sor->hdmi_supply));
2474                 return PTR_ERR(sor->hdmi_supply);
2475         }
2476
2477         err = regulator_enable(sor->hdmi_supply);
2478         if (err < 0) {
2479                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2480                 return err;
2481         }
2482
2483         return 0;
2484 }
2485
2486 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
2487 {
2488         regulator_disable(sor->hdmi_supply);
2489         regulator_disable(sor->vdd_pll_supply);
2490         regulator_disable(sor->avdd_io_supply);
2491
2492         return 0;
2493 }
2494
2495 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
2496         .name = "HDMI",
2497         .probe = tegra_sor_hdmi_probe,
2498         .remove = tegra_sor_hdmi_remove,
2499 };
2500
2501 static const u8 tegra124_sor_xbar_cfg[5] = {
2502         0, 1, 2, 3, 4
2503 };
2504
2505 static const struct tegra_sor_soc tegra124_sor = {
2506         .supports_edp = true,
2507         .supports_lvds = true,
2508         .supports_hdmi = false,
2509         .supports_dp = false,
2510         .xbar_cfg = tegra124_sor_xbar_cfg,
2511 };
2512
2513 static const struct tegra_sor_soc tegra210_sor = {
2514         .supports_edp = true,
2515         .supports_lvds = false,
2516         .supports_hdmi = false,
2517         .supports_dp = false,
2518         .xbar_cfg = tegra124_sor_xbar_cfg,
2519 };
2520
2521 static const u8 tegra210_sor_xbar_cfg[5] = {
2522         2, 1, 0, 3, 4
2523 };
2524
2525 static const struct tegra_sor_soc tegra210_sor1 = {
2526         .supports_edp = false,
2527         .supports_lvds = false,
2528         .supports_hdmi = true,
2529         .supports_dp = true,
2530
2531         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
2532         .settings = tegra210_sor_hdmi_defaults,
2533
2534         .xbar_cfg = tegra210_sor_xbar_cfg,
2535 };
2536
2537 static const struct of_device_id tegra_sor_of_match[] = {
2538         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
2539         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
2540         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
2541         { },
2542 };
2543 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
2544
2545 static int tegra_sor_probe(struct platform_device *pdev)
2546 {
2547         struct device_node *np;
2548         struct tegra_sor *sor;
2549         struct resource *regs;
2550         int err;
2551
2552         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
2553         if (!sor)
2554                 return -ENOMEM;
2555
2556         sor->soc = of_device_get_match_data(&pdev->dev);
2557         sor->output.dev = sor->dev = &pdev->dev;
2558
2559         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
2560                                      sor->soc->num_settings *
2561                                         sizeof(*sor->settings),
2562                                      GFP_KERNEL);
2563         if (!sor->settings)
2564                 return -ENOMEM;
2565
2566         sor->num_settings = sor->soc->num_settings;
2567
2568         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
2569         if (np) {
2570                 sor->aux = drm_dp_aux_find_by_of_node(np);
2571                 of_node_put(np);
2572
2573                 if (!sor->aux)
2574                         return -EPROBE_DEFER;
2575         }
2576
2577         if (!sor->aux) {
2578                 if (sor->soc->supports_hdmi) {
2579                         sor->ops = &tegra_sor_hdmi_ops;
2580                 } else if (sor->soc->supports_lvds) {
2581                         dev_err(&pdev->dev, "LVDS not supported yet\n");
2582                         return -ENODEV;
2583                 } else {
2584                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
2585                         return -ENODEV;
2586                 }
2587         } else {
2588                 if (sor->soc->supports_edp) {
2589                         sor->ops = &tegra_sor_edp_ops;
2590                 } else if (sor->soc->supports_dp) {
2591                         dev_err(&pdev->dev, "DisplayPort not supported yet\n");
2592                         return -ENODEV;
2593                 } else {
2594                         dev_err(&pdev->dev, "unknown (DP) support\n");
2595                         return -ENODEV;
2596                 }
2597         }
2598
2599         err = tegra_output_probe(&sor->output);
2600         if (err < 0) {
2601                 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
2602                 return err;
2603         }
2604
2605         if (sor->ops && sor->ops->probe) {
2606                 err = sor->ops->probe(sor);
2607                 if (err < 0) {
2608                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
2609                                 sor->ops->name, err);
2610                         goto output;
2611                 }
2612         }
2613
2614         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2615         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
2616         if (IS_ERR(sor->regs)) {
2617                 err = PTR_ERR(sor->regs);
2618                 goto remove;
2619         }
2620
2621         if (!pdev->dev.pm_domain) {
2622                 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
2623                 if (IS_ERR(sor->rst)) {
2624                         err = PTR_ERR(sor->rst);
2625                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
2626                                 err);
2627                         goto remove;
2628                 }
2629         }
2630
2631         sor->clk = devm_clk_get(&pdev->dev, NULL);
2632         if (IS_ERR(sor->clk)) {
2633                 err = PTR_ERR(sor->clk);
2634                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
2635                 goto remove;
2636         }
2637
2638         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
2639                 struct device_node *np = pdev->dev.of_node;
2640                 const char *name;
2641
2642                 /*
2643                  * For backwards compatibility with Tegra210 device trees,
2644                  * fall back to the old clock name "source" if the new "out"
2645                  * clock is not available.
2646                  */
2647                 if (of_property_match_string(np, "clock-names", "out") < 0)
2648                         name = "source";
2649                 else
2650                         name = "out";
2651
2652                 sor->clk_out = devm_clk_get(&pdev->dev, name);
2653                 if (IS_ERR(sor->clk_out)) {
2654                         err = PTR_ERR(sor->clk_out);
2655                         dev_err(sor->dev, "failed to get %s clock: %d\n",
2656                                 name, err);
2657                         goto remove;
2658                 }
2659         } else {
2660                 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
2661                 sor->clk_out = sor->clk;
2662         }
2663
2664         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
2665         if (IS_ERR(sor->clk_parent)) {
2666                 err = PTR_ERR(sor->clk_parent);
2667                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
2668                 goto remove;
2669         }
2670
2671         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
2672         if (IS_ERR(sor->clk_safe)) {
2673                 err = PTR_ERR(sor->clk_safe);
2674                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
2675                 goto remove;
2676         }
2677
2678         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
2679         if (IS_ERR(sor->clk_dp)) {
2680                 err = PTR_ERR(sor->clk_dp);
2681                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
2682                 goto remove;
2683         }
2684
2685         /*
2686          * Starting with Tegra186, the BPMP provides an implementation for
2687          * the pad output clock, so we have to look it up from device tree.
2688          */
2689         sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
2690         if (IS_ERR(sor->clk_pad)) {
2691                 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
2692                         err = PTR_ERR(sor->clk_pad);
2693                         goto remove;
2694                 }
2695
2696                 /*
2697                  * If the pad output clock is not available, then we assume
2698                  * we're on Tegra210 or earlier and have to provide our own
2699                  * implementation.
2700                  */
2701                 sor->clk_pad = NULL;
2702         }
2703
2704         /*
2705          * The bootloader may have set up the SOR such that it's module clock
2706          * is sourced by one of the display PLLs. However, that doesn't work
2707          * without properly having set up other bits of the SOR.
2708          */
2709         err = clk_set_parent(sor->clk_out, sor->clk_safe);
2710         if (err < 0) {
2711                 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
2712                 goto remove;
2713         }
2714
2715         platform_set_drvdata(pdev, sor);
2716         pm_runtime_enable(&pdev->dev);
2717
2718         /*
2719          * On Tegra210 and earlier, provide our own implementation for the
2720          * pad output clock.
2721          */
2722         if (!sor->clk_pad) {
2723                 err = pm_runtime_get_sync(&pdev->dev);
2724                 if (err < 0) {
2725                         dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
2726                                 err);
2727                         goto remove;
2728                 }
2729
2730                 sor->clk_pad = tegra_clk_sor_pad_register(sor,
2731                                                           "sor1_pad_clkout");
2732                 pm_runtime_put(&pdev->dev);
2733         }
2734
2735         if (IS_ERR(sor->clk_pad)) {
2736                 err = PTR_ERR(sor->clk_pad);
2737                 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
2738                         err);
2739                 goto remove;
2740         }
2741
2742         INIT_LIST_HEAD(&sor->client.list);
2743         sor->client.ops = &sor_client_ops;
2744         sor->client.dev = &pdev->dev;
2745
2746         err = host1x_client_register(&sor->client);
2747         if (err < 0) {
2748                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2749                         err);
2750                 goto remove;
2751         }
2752
2753         return 0;
2754
2755 remove:
2756         if (sor->ops && sor->ops->remove)
2757                 sor->ops->remove(sor);
2758 output:
2759         tegra_output_remove(&sor->output);
2760         return err;
2761 }
2762
2763 static int tegra_sor_remove(struct platform_device *pdev)
2764 {
2765         struct tegra_sor *sor = platform_get_drvdata(pdev);
2766         int err;
2767
2768         pm_runtime_disable(&pdev->dev);
2769
2770         err = host1x_client_unregister(&sor->client);
2771         if (err < 0) {
2772                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2773                         err);
2774                 return err;
2775         }
2776
2777         if (sor->ops && sor->ops->remove) {
2778                 err = sor->ops->remove(sor);
2779                 if (err < 0)
2780                         dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
2781         }
2782
2783         tegra_output_remove(&sor->output);
2784
2785         return 0;
2786 }
2787
2788 #ifdef CONFIG_PM
2789 static int tegra_sor_suspend(struct device *dev)
2790 {
2791         struct tegra_sor *sor = dev_get_drvdata(dev);
2792         int err;
2793
2794         if (sor->rst) {
2795                 err = reset_control_assert(sor->rst);
2796                 if (err < 0) {
2797                         dev_err(dev, "failed to assert reset: %d\n", err);
2798                         return err;
2799                 }
2800         }
2801
2802         usleep_range(1000, 2000);
2803
2804         clk_disable_unprepare(sor->clk);
2805
2806         return 0;
2807 }
2808
2809 static int tegra_sor_resume(struct device *dev)
2810 {
2811         struct tegra_sor *sor = dev_get_drvdata(dev);
2812         int err;
2813
2814         err = clk_prepare_enable(sor->clk);
2815         if (err < 0) {
2816                 dev_err(dev, "failed to enable clock: %d\n", err);
2817                 return err;
2818         }
2819
2820         usleep_range(1000, 2000);
2821
2822         if (sor->rst) {
2823                 err = reset_control_deassert(sor->rst);
2824                 if (err < 0) {
2825                         dev_err(dev, "failed to deassert reset: %d\n", err);
2826                         clk_disable_unprepare(sor->clk);
2827                         return err;
2828                 }
2829         }
2830
2831         return 0;
2832 }
2833 #endif
2834
2835 static const struct dev_pm_ops tegra_sor_pm_ops = {
2836         SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
2837 };
2838
2839 struct platform_driver tegra_sor_driver = {
2840         .driver = {
2841                 .name = "tegra-sor",
2842                 .of_match_table = tegra_sor_of_match,
2843                 .pm = &tegra_sor_pm_ops,
2844         },
2845         .probe = tegra_sor_probe,
2846         .remove = tegra_sor_remove,
2847 };