2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/gpio.h>
13 #include <linux/hdmi.h>
14 #include <linux/of_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/reset.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_crtc.h>
21 #include <drm/drm_crtc_helper.h>
23 #include <sound/hda_verbs.h>
25 #include <media/cec-notifier.h>
32 #define HDMI_ELD_BUFFER_SIZE 96
43 struct tegra_hdmi_config {
44 const struct tmds_config *tmds;
45 unsigned int num_tmds;
47 unsigned long fuse_override_offset;
48 u32 fuse_override_value;
50 bool has_sor_io_peak_current;
56 struct host1x_client client;
57 struct tegra_output output;
60 struct regulator *hdmi;
61 struct regulator *pll;
62 struct regulator *vdd;
67 struct clk *clk_parent;
69 struct reset_control *rst;
71 const struct tegra_hdmi_config *config;
73 unsigned int audio_source;
74 unsigned int audio_sample_rate;
75 unsigned int audio_channels;
77 unsigned int pixel_clock;
81 struct drm_info_list *debugfs_files;
82 struct drm_minor *minor;
83 struct dentry *debugfs;
86 static inline struct tegra_hdmi *
87 host1x_client_to_hdmi(struct host1x_client *client)
89 return container_of(client, struct tegra_hdmi, client);
92 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
94 return container_of(output, struct tegra_hdmi, output);
97 #define HDMI_AUDIOCLK_FREQ 216000000
98 #define HDMI_REKEY_DEFAULT 56
106 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
109 u32 value = readl(hdmi->regs + (offset << 2));
111 trace_hdmi_readl(hdmi->dev, offset, value);
116 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
119 trace_hdmi_writel(hdmi->dev, offset, value);
120 writel(value, hdmi->regs + (offset << 2));
123 struct tegra_hdmi_audio_config {
130 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
131 { 25200000, 4096, 25200, 24000 },
132 { 27000000, 4096, 27000, 24000 },
133 { 74250000, 4096, 74250, 24000 },
134 { 148500000, 4096, 148500, 24000 },
138 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
139 { 25200000, 5880, 26250, 25000 },
140 { 27000000, 5880, 28125, 25000 },
141 { 74250000, 4704, 61875, 20000 },
142 { 148500000, 4704, 123750, 20000 },
146 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
147 { 25200000, 6144, 25200, 24000 },
148 { 27000000, 6144, 27000, 24000 },
149 { 74250000, 6144, 74250, 24000 },
150 { 148500000, 6144, 148500, 24000 },
154 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
155 { 25200000, 11760, 26250, 25000 },
156 { 27000000, 11760, 28125, 25000 },
157 { 74250000, 9408, 61875, 20000 },
158 { 148500000, 9408, 123750, 20000 },
162 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
163 { 25200000, 12288, 25200, 24000 },
164 { 27000000, 12288, 27000, 24000 },
165 { 74250000, 12288, 74250, 24000 },
166 { 148500000, 12288, 148500, 24000 },
170 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
171 { 25200000, 23520, 26250, 25000 },
172 { 27000000, 23520, 28125, 25000 },
173 { 74250000, 18816, 61875, 20000 },
174 { 148500000, 18816, 123750, 20000 },
178 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
179 { 25200000, 24576, 25200, 24000 },
180 { 27000000, 24576, 27000, 24000 },
181 { 74250000, 24576, 74250, 24000 },
182 { 148500000, 24576, 148500, 24000 },
186 static const struct tmds_config tegra20_tmds_config[] = {
187 { /* slow pixel clock modes */
189 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
190 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
191 SOR_PLL_TX_REG_LOAD(3),
192 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
193 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
194 PE_CURRENT1(PE_CURRENT_0_0_mA) |
195 PE_CURRENT2(PE_CURRENT_0_0_mA) |
196 PE_CURRENT3(PE_CURRENT_0_0_mA),
197 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
198 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
199 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
200 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
202 { /* high pixel clock modes */
204 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
205 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
206 SOR_PLL_TX_REG_LOAD(3),
207 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
208 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
209 PE_CURRENT1(PE_CURRENT_6_0_mA) |
210 PE_CURRENT2(PE_CURRENT_6_0_mA) |
211 PE_CURRENT3(PE_CURRENT_6_0_mA),
212 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
213 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
214 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
215 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
219 static const struct tmds_config tegra30_tmds_config[] = {
222 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
223 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
224 SOR_PLL_TX_REG_LOAD(0),
225 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
226 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
227 PE_CURRENT1(PE_CURRENT_0_0_mA) |
228 PE_CURRENT2(PE_CURRENT_0_0_mA) |
229 PE_CURRENT3(PE_CURRENT_0_0_mA),
230 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
231 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
232 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
233 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
234 }, { /* 720p modes */
236 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
237 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
238 SOR_PLL_TX_REG_LOAD(0),
239 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
240 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
241 PE_CURRENT1(PE_CURRENT_5_0_mA) |
242 PE_CURRENT2(PE_CURRENT_5_0_mA) |
243 PE_CURRENT3(PE_CURRENT_5_0_mA),
244 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
245 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
246 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
247 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
248 }, { /* 1080p modes */
250 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
251 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
252 SOR_PLL_TX_REG_LOAD(0),
253 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
254 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
255 PE_CURRENT1(PE_CURRENT_5_0_mA) |
256 PE_CURRENT2(PE_CURRENT_5_0_mA) |
257 PE_CURRENT3(PE_CURRENT_5_0_mA),
258 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
259 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
260 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
261 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
265 static const struct tmds_config tegra114_tmds_config[] = {
266 { /* 480p/576p / 25.2MHz/27MHz modes */
268 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
269 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
270 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
271 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
272 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
273 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
274 PE_CURRENT3(PE_CURRENT_0_mA_T114),
276 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
277 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
278 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
279 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
280 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
281 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
282 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
283 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
284 }, { /* 720p / 74.25MHz modes */
286 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
287 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
288 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
289 SOR_PLL_TMDS_TERMADJ(0),
290 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
291 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
292 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
293 PE_CURRENT3(PE_CURRENT_15_mA_T114),
295 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
296 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
297 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
298 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
299 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
300 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
301 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
302 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
303 }, { /* 1080p / 148.5MHz modes */
305 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
306 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
307 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
308 SOR_PLL_TMDS_TERMADJ(0),
309 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
310 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
311 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
312 PE_CURRENT3(PE_CURRENT_10_mA_T114),
314 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
315 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
316 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
317 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
318 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
319 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
320 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
321 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
322 }, { /* 225/297MHz modes */
324 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
325 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
326 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
327 | SOR_PLL_TMDS_TERM_ENABLE,
328 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
329 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
330 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
331 PE_CURRENT3(PE_CURRENT_0_mA_T114),
333 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
334 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
335 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
336 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
337 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
338 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
339 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
340 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
344 static const struct tmds_config tegra124_tmds_config[] = {
345 { /* 480p/576p / 25.2MHz/27MHz modes */
347 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
348 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
349 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
350 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
351 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
352 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
353 PE_CURRENT3(PE_CURRENT_0_mA_T114),
355 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
356 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
357 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
358 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
359 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
360 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
361 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
362 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
363 }, { /* 720p / 74.25MHz modes */
365 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
366 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
367 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
368 SOR_PLL_TMDS_TERMADJ(0),
369 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
370 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
371 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
372 PE_CURRENT3(PE_CURRENT_15_mA_T114),
374 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
375 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
376 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
377 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
378 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
379 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
380 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
381 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
382 }, { /* 1080p / 148.5MHz modes */
384 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
385 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
386 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
387 SOR_PLL_TMDS_TERMADJ(0),
388 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
389 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
390 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
391 PE_CURRENT3(PE_CURRENT_10_mA_T114),
393 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
394 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
395 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
396 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
397 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
398 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
399 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
400 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
401 }, { /* 225/297MHz modes */
403 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
404 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
405 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
406 | SOR_PLL_TMDS_TERM_ENABLE,
407 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
408 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
409 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
410 PE_CURRENT3(PE_CURRENT_0_mA_T114),
412 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
413 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
414 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
415 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
416 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
417 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
418 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
419 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
423 static const struct tegra_hdmi_audio_config *
424 tegra_hdmi_get_audio_config(unsigned int sample_rate, unsigned int pclk)
426 const struct tegra_hdmi_audio_config *table;
428 switch (sample_rate) {
430 table = tegra_hdmi_audio_32k;
434 table = tegra_hdmi_audio_44_1k;
438 table = tegra_hdmi_audio_48k;
442 table = tegra_hdmi_audio_88_2k;
446 table = tegra_hdmi_audio_96k;
450 table = tegra_hdmi_audio_176_4k;
454 table = tegra_hdmi_audio_192k;
461 while (table->pclk) {
462 if (table->pclk == pclk)
471 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
473 const unsigned int freqs[] = {
474 32000, 44100, 48000, 88200, 96000, 176400, 192000
478 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
479 unsigned int f = freqs[i];
480 unsigned int eight_half;
491 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
492 value = AUDIO_FS_LOW(eight_half - delta) |
493 AUDIO_FS_HIGH(eight_half + delta);
494 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
498 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
500 static const struct {
501 unsigned int sample_rate;
504 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
505 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
506 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
507 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
508 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
509 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
510 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
514 for (i = 0; i < ARRAY_SIZE(regs); i++) {
515 if (regs[i].sample_rate == hdmi->audio_sample_rate) {
516 tegra_hdmi_writel(hdmi, value, regs[i].offset);
522 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
524 const struct tegra_hdmi_audio_config *config;
527 switch (hdmi->audio_source) {
529 if (hdmi->config->has_hda)
530 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
537 if (hdmi->config->has_hda)
538 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
540 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
544 if (hdmi->config->has_hda)
545 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
547 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
552 * Tegra30 and later use a slightly modified version of the register
553 * layout to accomodate for changes related to supporting HDA as the
554 * audio input source for HDMI. The source select field has moved to
555 * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
556 * per block fields remain in the AUDIO_CNTRL0 register.
558 if (hdmi->config->has_hda) {
560 * Inject null samples into the audio FIFO for every frame in
561 * which the codec did not receive any samples. This applies
562 * to stereo LPCM only.
564 * XXX: This seems to be a remnant of MCP days when this was
565 * used to work around issues with monitors not being able to
566 * play back system startup sounds early. It is possibly not
567 * needed on Linux at all.
569 if (hdmi->audio_channels == 2)
570 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
576 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
580 * On Tegra20, HDA is not a supported audio source and the source
581 * select field is part of the AUDIO_CNTRL0 register.
583 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
584 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
586 if (!hdmi->config->has_hda)
589 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
592 * Advertise support for High Bit-Rate on Tegra114 and later.
594 if (hdmi->config->has_hbr) {
595 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
596 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
597 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
600 config = tegra_hdmi_get_audio_config(hdmi->audio_sample_rate,
604 "cannot set audio to %u Hz at %u Hz pixel clock\n",
605 hdmi->audio_sample_rate, hdmi->pixel_clock);
609 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
611 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
612 AUDIO_N_VALUE(config->n - 1);
613 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
615 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
616 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
618 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
619 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
621 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
622 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
624 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
625 value &= ~AUDIO_N_RESETF;
626 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
628 if (hdmi->config->has_hda)
629 tegra_hdmi_write_aval(hdmi, config->aval);
631 tegra_hdmi_setup_audio_fs_tables(hdmi);
636 static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
640 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
641 value &= ~GENERIC_CTRL_AUDIO;
642 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
645 static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
649 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
650 value |= GENERIC_CTRL_AUDIO;
651 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
654 static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
656 size_t length = drm_eld_size(hdmi->output.connector.eld), i;
659 for (i = 0; i < length; i++)
660 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
661 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
664 * The HDA codec will always report an ELD buffer size of 96 bytes and
665 * the HDA codec driver will check that each byte read from the buffer
666 * is valid. Therefore every byte must be written, even if no 96 bytes
667 * were parsed from EDID.
669 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
670 tegra_hdmi_writel(hdmi, i << 8 | 0,
671 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
673 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
674 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
677 static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
682 for (i = size; i > 0; i--)
683 value = (value << 8) | ptr[i - 1];
688 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
691 const u8 *ptr = data;
692 unsigned long offset;
697 case HDMI_INFOFRAME_TYPE_AVI:
698 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
701 case HDMI_INFOFRAME_TYPE_AUDIO:
702 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
705 case HDMI_INFOFRAME_TYPE_VENDOR:
706 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
710 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
715 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
716 INFOFRAME_HEADER_VERSION(ptr[1]) |
717 INFOFRAME_HEADER_LEN(ptr[2]);
718 tegra_hdmi_writel(hdmi, value, offset);
722 * Each subpack contains 7 bytes, divided into:
723 * - subpack_low: bytes 0 - 3
724 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
726 for (i = 3, j = 0; i < size; i += 7, j += 8) {
727 size_t rem = size - i, num = min_t(size_t, rem, 4);
729 value = tegra_hdmi_subpack(&ptr[i], num);
730 tegra_hdmi_writel(hdmi, value, offset++);
732 num = min_t(size_t, rem - num, 3);
734 value = tegra_hdmi_subpack(&ptr[i + 4], num);
735 tegra_hdmi_writel(hdmi, value, offset++);
739 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
740 struct drm_display_mode *mode)
742 struct hdmi_avi_infoframe frame;
746 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
748 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
752 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
754 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
758 tegra_hdmi_write_infopack(hdmi, buffer, err);
761 static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
765 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
766 value &= ~INFOFRAME_CTRL_ENABLE;
767 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
770 static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
774 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
775 value |= INFOFRAME_CTRL_ENABLE;
776 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
779 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
781 struct hdmi_audio_infoframe frame;
785 err = hdmi_audio_infoframe_init(&frame);
787 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
792 frame.channels = hdmi->audio_channels;
794 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
796 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
802 * The audio infoframe has only one set of subpack registers, so the
803 * infoframe needs to be truncated. One set of subpack registers can
804 * contain 7 bytes. Including the 3 byte header only the first 10
805 * bytes can be programmed.
807 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
810 static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
814 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
815 value &= ~INFOFRAME_CTRL_ENABLE;
816 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
819 static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
823 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
824 value |= INFOFRAME_CTRL_ENABLE;
825 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
828 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
830 struct hdmi_vendor_infoframe frame;
834 hdmi_vendor_infoframe_init(&frame);
835 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
837 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
839 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
844 tegra_hdmi_write_infopack(hdmi, buffer, err);
847 static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
851 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
852 value &= ~GENERIC_CTRL_ENABLE;
853 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
856 static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
860 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
861 value |= GENERIC_CTRL_ENABLE;
862 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
865 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
866 const struct tmds_config *tmds)
870 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
871 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
872 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
874 tegra_hdmi_writel(hdmi, tmds->drive_current,
875 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
877 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
878 value |= hdmi->config->fuse_override_value;
879 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
881 if (hdmi->config->has_sor_io_peak_current)
882 tegra_hdmi_writel(hdmi, tmds->peak_current,
883 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
886 static bool tegra_output_is_hdmi(struct tegra_output *output)
890 if (!output->connector.edid_blob_ptr)
893 edid = (struct edid *)output->connector.edid_blob_ptr->data;
895 return drm_detect_hdmi_monitor(edid);
898 static enum drm_connector_status
899 tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
901 struct tegra_output *output = connector_to_output(connector);
902 struct tegra_hdmi *hdmi = to_hdmi(output);
903 enum drm_connector_status status;
905 status = tegra_output_connector_detect(connector, force);
906 if (status == connector_status_connected)
909 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
913 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
914 .reset = drm_atomic_helper_connector_reset,
915 .detect = tegra_hdmi_connector_detect,
916 .fill_modes = drm_helper_probe_single_connector_modes,
917 .destroy = tegra_output_connector_destroy,
918 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
919 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
922 static enum drm_mode_status
923 tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
924 struct drm_display_mode *mode)
926 struct tegra_output *output = connector_to_output(connector);
927 struct tegra_hdmi *hdmi = to_hdmi(output);
928 unsigned long pclk = mode->clock * 1000;
929 enum drm_mode_status status = MODE_OK;
933 parent = clk_get_parent(hdmi->clk_parent);
935 err = clk_round_rate(parent, pclk * 4);
937 status = MODE_NOCLOCK;
942 static const struct drm_connector_helper_funcs
943 tegra_hdmi_connector_helper_funcs = {
944 .get_modes = tegra_output_connector_get_modes,
945 .mode_valid = tegra_hdmi_connector_mode_valid,
948 static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
949 .destroy = tegra_output_encoder_destroy,
952 static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
954 struct tegra_output *output = encoder_to_output(encoder);
955 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
956 struct tegra_hdmi *hdmi = to_hdmi(output);
960 * The following accesses registers of the display controller, so make
961 * sure it's only executed when the output is attached to one.
964 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
965 value &= ~HDMI_ENABLE;
966 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
973 tegra_hdmi_disable_stereo_infoframe(hdmi);
975 tegra_hdmi_disable_audio_infoframe(hdmi);
976 tegra_hdmi_disable_avi_infoframe(hdmi);
977 tegra_hdmi_disable_audio(hdmi);
980 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
981 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
983 pm_runtime_put(hdmi->dev);
986 static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
988 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
989 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
990 struct tegra_output *output = encoder_to_output(encoder);
991 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
992 struct tegra_hdmi *hdmi = to_hdmi(output);
993 unsigned int pulse_start, div82;
998 pm_runtime_get_sync(hdmi->dev);
1001 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1002 * is used for interoperability between the HDA codec driver and the
1005 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1006 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1008 hdmi->pixel_clock = mode->clock * 1000;
1009 h_sync_width = mode->hsync_end - mode->hsync_start;
1010 h_back_porch = mode->htotal - mode->hsync_end;
1011 h_front_porch = mode->hsync_start - mode->hdisplay;
1013 err = clk_set_rate(hdmi->clk, hdmi->pixel_clock);
1015 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1019 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1021 /* power up sequence */
1022 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1023 value &= ~SOR_PLL_PDBG;
1024 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1026 usleep_range(10, 20);
1028 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1029 value &= ~SOR_PLL_PWR;
1030 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1032 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1033 DC_DISP_DISP_TIMING_OPTIONS);
1034 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1035 DC_DISP_DISP_COLOR_CONTROL);
1037 /* video_preamble uses h_pulse2 */
1038 pulse_start = 1 + h_sync_width + h_back_porch - 10;
1040 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1042 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1044 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1046 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1047 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1049 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1050 VSYNC_WINDOW_ENABLE;
1051 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1054 value = HDMI_SRC_DISPLAYB;
1056 value = HDMI_SRC_DISPLAYA;
1058 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1059 (mode->vdisplay == 576)))
1060 tegra_hdmi_writel(hdmi,
1061 value | ARM_VIDEO_RANGE_FULL,
1062 HDMI_NV_PDISP_INPUT_CONTROL);
1064 tegra_hdmi_writel(hdmi,
1065 value | ARM_VIDEO_RANGE_LIMITED,
1066 HDMI_NV_PDISP_INPUT_CONTROL);
1068 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1069 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1070 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1072 hdmi->dvi = !tegra_output_is_hdmi(output);
1074 err = tegra_hdmi_setup_audio(hdmi);
1079 if (hdmi->config->has_hda)
1080 tegra_hdmi_write_eld(hdmi);
1082 rekey = HDMI_REKEY_DEFAULT;
1083 value = HDMI_CTRL_REKEY(rekey);
1084 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1085 h_front_porch - rekey - 18) / 32);
1088 value |= HDMI_CTRL_ENABLE;
1090 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1093 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1094 tegra_hdmi_setup_audio_infoframe(hdmi);
1097 tegra_hdmi_setup_stereo_infoframe(hdmi);
1101 for (i = 0; i < hdmi->config->num_tmds; i++) {
1102 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1103 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1108 tegra_hdmi_writel(hdmi,
1110 SOR_SEQ_PU_PC_ALT(0) |
1112 SOR_SEQ_PD_PC_ALT(8),
1113 HDMI_NV_PDISP_SOR_SEQ_CTL);
1115 value = SOR_SEQ_INST_WAIT_TIME(1) |
1116 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1118 SOR_SEQ_INST_PIN_A_LOW |
1119 SOR_SEQ_INST_PIN_B_LOW |
1120 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1122 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1123 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1125 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1126 value &= ~SOR_CSTM_ROTCLK(~0);
1127 value |= SOR_CSTM_ROTCLK(2);
1128 value |= SOR_CSTM_PLLDIV;
1129 value &= ~SOR_CSTM_LVDS_ENABLE;
1130 value &= ~SOR_CSTM_MODE_MASK;
1131 value |= SOR_CSTM_MODE_TMDS;
1132 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1135 tegra_hdmi_writel(hdmi,
1136 SOR_PWR_NORMAL_STATE_PU |
1137 SOR_PWR_NORMAL_START_NORMAL |
1138 SOR_PWR_SAFE_STATE_PD |
1139 SOR_PWR_SETTING_NEW_TRIGGER,
1140 HDMI_NV_PDISP_SOR_PWR);
1141 tegra_hdmi_writel(hdmi,
1142 SOR_PWR_NORMAL_STATE_PU |
1143 SOR_PWR_NORMAL_START_NORMAL |
1144 SOR_PWR_SAFE_STATE_PD |
1145 SOR_PWR_SETTING_NEW_DONE,
1146 HDMI_NV_PDISP_SOR_PWR);
1149 BUG_ON(--retries < 0);
1150 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1151 } while (value & SOR_PWR_SETTING_NEW_PENDING);
1153 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1154 SOR_STATE_ASY_OWNER_HEAD0 |
1155 SOR_STATE_ASY_SUBOWNER_BOTH |
1156 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1157 SOR_STATE_ASY_DEPOL_POS;
1159 /* setup sync polarities */
1160 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1161 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1163 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1164 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1166 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1167 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1169 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1170 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1172 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1174 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1175 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1177 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1178 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1179 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1180 HDMI_NV_PDISP_SOR_STATE1);
1181 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1183 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1184 value |= HDMI_ENABLE;
1185 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1187 tegra_dc_commit(dc);
1190 tegra_hdmi_enable_avi_infoframe(hdmi);
1191 tegra_hdmi_enable_audio_infoframe(hdmi);
1192 tegra_hdmi_enable_audio(hdmi);
1195 tegra_hdmi_enable_stereo_infoframe(hdmi);
1198 /* TODO: add HDCP support */
1202 tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1203 struct drm_crtc_state *crtc_state,
1204 struct drm_connector_state *conn_state)
1206 struct tegra_output *output = encoder_to_output(encoder);
1207 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1208 unsigned long pclk = crtc_state->mode.clock * 1000;
1209 struct tegra_hdmi *hdmi = to_hdmi(output);
1212 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1215 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1222 static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1223 .disable = tegra_hdmi_encoder_disable,
1224 .enable = tegra_hdmi_encoder_enable,
1225 .atomic_check = tegra_hdmi_encoder_atomic_check,
1228 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1230 struct drm_info_node *node = s->private;
1231 struct tegra_hdmi *hdmi = node->info_ent->data;
1232 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1233 struct drm_device *drm = node->minor->dev;
1236 drm_modeset_lock_all(drm);
1238 if (!crtc || !crtc->state->active) {
1243 #define DUMP_REG(name) \
1244 seq_printf(s, "%-56s %#05x %08x\n", #name, name, \
1245 tegra_hdmi_readl(hdmi, name))
1247 DUMP_REG(HDMI_CTXSW);
1248 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
1249 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
1250 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
1251 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
1252 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
1253 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
1254 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
1255 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
1256 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
1257 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
1258 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
1259 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
1260 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
1261 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
1262 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
1263 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
1264 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
1265 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
1266 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
1267 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
1268 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
1269 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
1270 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
1271 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
1272 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
1273 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
1274 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
1275 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
1276 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
1277 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1278 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
1279 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
1280 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1281 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1282 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1283 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1284 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1285 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1286 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1287 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1288 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1289 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1290 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1291 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1292 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1293 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1294 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1295 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1296 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1297 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1298 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1299 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1300 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1301 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1302 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1303 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1304 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1305 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1306 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1307 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1308 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1309 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1310 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1311 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1312 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1313 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1314 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1315 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1316 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1317 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1318 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1319 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1320 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1321 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1322 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1323 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1324 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1325 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1326 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1327 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1328 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1329 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1330 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1331 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1332 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1333 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1334 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1335 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1336 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1337 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1338 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1339 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1340 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1341 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1342 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1343 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1344 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1345 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1346 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1347 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1348 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1349 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1350 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1351 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1352 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1353 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1354 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1355 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1356 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1357 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1358 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1359 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1360 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1361 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1362 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1363 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1364 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1365 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1366 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1367 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1368 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1369 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1370 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1371 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1372 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1373 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1374 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1375 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1376 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1377 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1378 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1379 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1380 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1381 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1382 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1383 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1384 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1385 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1386 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1387 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1388 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1389 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1390 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1391 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1392 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1393 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1394 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1395 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1396 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1397 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1398 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1399 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1400 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1401 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1402 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
1403 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1404 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1);
1405 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1406 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1407 DUMP_REG(HDMI_NV_PDISP_INT_STATUS);
1408 DUMP_REG(HDMI_NV_PDISP_INT_MASK);
1409 DUMP_REG(HDMI_NV_PDISP_INT_ENABLE);
1410 DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1415 drm_modeset_unlock_all(drm);
1419 static struct drm_info_list debugfs_files[] = {
1420 { "regs", tegra_hdmi_show_regs, 0, NULL },
1423 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1424 struct drm_minor *minor)
1429 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1433 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1435 if (!hdmi->debugfs_files) {
1440 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1441 hdmi->debugfs_files[i].data = hdmi;
1443 err = drm_debugfs_create_files(hdmi->debugfs_files,
1444 ARRAY_SIZE(debugfs_files),
1445 hdmi->debugfs, minor);
1449 hdmi->minor = minor;
1454 kfree(hdmi->debugfs_files);
1455 hdmi->debugfs_files = NULL;
1457 debugfs_remove(hdmi->debugfs);
1458 hdmi->debugfs = NULL;
1463 static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1465 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1469 kfree(hdmi->debugfs_files);
1470 hdmi->debugfs_files = NULL;
1472 debugfs_remove(hdmi->debugfs);
1473 hdmi->debugfs = NULL;
1476 static int tegra_hdmi_init(struct host1x_client *client)
1478 struct drm_device *drm = dev_get_drvdata(client->parent);
1479 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1482 hdmi->output.dev = client->dev;
1484 drm_connector_init(drm, &hdmi->output.connector,
1485 &tegra_hdmi_connector_funcs,
1486 DRM_MODE_CONNECTOR_HDMIA);
1487 drm_connector_helper_add(&hdmi->output.connector,
1488 &tegra_hdmi_connector_helper_funcs);
1489 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1491 drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs,
1492 DRM_MODE_ENCODER_TMDS, NULL);
1493 drm_encoder_helper_add(&hdmi->output.encoder,
1494 &tegra_hdmi_encoder_helper_funcs);
1496 drm_mode_connector_attach_encoder(&hdmi->output.connector,
1497 &hdmi->output.encoder);
1498 drm_connector_register(&hdmi->output.connector);
1500 err = tegra_output_init(drm, &hdmi->output);
1502 dev_err(client->dev, "failed to initialize output: %d\n", err);
1506 hdmi->output.encoder.possible_crtcs = 0x3;
1508 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1509 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1511 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1514 err = regulator_enable(hdmi->hdmi);
1516 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1521 err = regulator_enable(hdmi->pll);
1523 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1527 err = regulator_enable(hdmi->vdd);
1529 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1536 static int tegra_hdmi_exit(struct host1x_client *client)
1538 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1540 tegra_output_exit(&hdmi->output);
1542 regulator_disable(hdmi->vdd);
1543 regulator_disable(hdmi->pll);
1544 regulator_disable(hdmi->hdmi);
1546 if (IS_ENABLED(CONFIG_DEBUG_FS))
1547 tegra_hdmi_debugfs_exit(hdmi);
1552 static const struct host1x_client_ops hdmi_client_ops = {
1553 .init = tegra_hdmi_init,
1554 .exit = tegra_hdmi_exit,
1557 static const struct tegra_hdmi_config tegra20_hdmi_config = {
1558 .tmds = tegra20_tmds_config,
1559 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1560 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1561 .fuse_override_value = 1 << 31,
1562 .has_sor_io_peak_current = false,
1567 static const struct tegra_hdmi_config tegra30_hdmi_config = {
1568 .tmds = tegra30_tmds_config,
1569 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1570 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1571 .fuse_override_value = 1 << 31,
1572 .has_sor_io_peak_current = false,
1577 static const struct tegra_hdmi_config tegra114_hdmi_config = {
1578 .tmds = tegra114_tmds_config,
1579 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1580 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1581 .fuse_override_value = 1 << 31,
1582 .has_sor_io_peak_current = true,
1587 static const struct tegra_hdmi_config tegra124_hdmi_config = {
1588 .tmds = tegra124_tmds_config,
1589 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1590 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1591 .fuse_override_value = 1 << 31,
1592 .has_sor_io_peak_current = true,
1597 static const struct of_device_id tegra_hdmi_of_match[] = {
1598 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1599 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1600 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1601 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1604 MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1606 static void hda_format_parse(unsigned int format, unsigned int *rate,
1607 unsigned int *channels)
1609 unsigned int mul, div;
1611 if (format & AC_FMT_BASE_44K)
1616 mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT;
1617 div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT;
1619 *rate = *rate * (mul + 1) / (div + 1);
1621 *channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT;
1624 static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1626 struct tegra_hdmi *hdmi = data;
1630 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1631 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1633 if (value & INT_CODEC_SCRATCH0) {
1634 unsigned int format;
1637 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1639 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1640 unsigned int sample_rate, channels;
1642 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1644 hda_format_parse(format, &sample_rate, &channels);
1646 hdmi->audio_sample_rate = sample_rate;
1647 hdmi->audio_channels = channels;
1649 err = tegra_hdmi_setup_audio(hdmi);
1651 tegra_hdmi_disable_audio_infoframe(hdmi);
1652 tegra_hdmi_disable_audio(hdmi);
1654 tegra_hdmi_setup_audio_infoframe(hdmi);
1655 tegra_hdmi_enable_audio_infoframe(hdmi);
1656 tegra_hdmi_enable_audio(hdmi);
1659 tegra_hdmi_disable_audio_infoframe(hdmi);
1660 tegra_hdmi_disable_audio(hdmi);
1667 static int tegra_hdmi_probe(struct platform_device *pdev)
1669 struct tegra_hdmi *hdmi;
1670 struct resource *regs;
1673 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1677 hdmi->config = of_device_get_match_data(&pdev->dev);
1678 hdmi->dev = &pdev->dev;
1680 hdmi->audio_source = AUTO;
1681 hdmi->audio_sample_rate = 48000;
1682 hdmi->audio_channels = 2;
1683 hdmi->stereo = false;
1686 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1687 if (IS_ERR(hdmi->clk)) {
1688 dev_err(&pdev->dev, "failed to get clock\n");
1689 return PTR_ERR(hdmi->clk);
1692 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1693 if (IS_ERR(hdmi->rst)) {
1694 dev_err(&pdev->dev, "failed to get reset\n");
1695 return PTR_ERR(hdmi->rst);
1698 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1699 if (IS_ERR(hdmi->clk_parent))
1700 return PTR_ERR(hdmi->clk_parent);
1702 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1704 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1708 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1709 if (IS_ERR(hdmi->hdmi)) {
1710 dev_err(&pdev->dev, "failed to get HDMI regulator\n");
1711 return PTR_ERR(hdmi->hdmi);
1714 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1715 if (IS_ERR(hdmi->pll)) {
1716 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1717 return PTR_ERR(hdmi->pll);
1720 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1721 if (IS_ERR(hdmi->vdd)) {
1722 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1723 return PTR_ERR(hdmi->vdd);
1726 hdmi->output.notifier = cec_notifier_get(&pdev->dev);
1727 if (hdmi->output.notifier == NULL)
1730 hdmi->output.dev = &pdev->dev;
1732 err = tegra_output_probe(&hdmi->output);
1736 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1737 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1738 if (IS_ERR(hdmi->regs))
1739 return PTR_ERR(hdmi->regs);
1741 err = platform_get_irq(pdev, 0);
1747 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1748 dev_name(hdmi->dev), hdmi);
1750 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1755 platform_set_drvdata(pdev, hdmi);
1756 pm_runtime_enable(&pdev->dev);
1758 INIT_LIST_HEAD(&hdmi->client.list);
1759 hdmi->client.ops = &hdmi_client_ops;
1760 hdmi->client.dev = &pdev->dev;
1762 err = host1x_client_register(&hdmi->client);
1764 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1772 static int tegra_hdmi_remove(struct platform_device *pdev)
1774 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1777 pm_runtime_disable(&pdev->dev);
1779 err = host1x_client_unregister(&hdmi->client);
1781 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1786 tegra_output_remove(&hdmi->output);
1788 if (hdmi->output.notifier)
1789 cec_notifier_put(hdmi->output.notifier);
1795 static int tegra_hdmi_suspend(struct device *dev)
1797 struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1800 err = reset_control_assert(hdmi->rst);
1802 dev_err(dev, "failed to assert reset: %d\n", err);
1806 usleep_range(1000, 2000);
1808 clk_disable_unprepare(hdmi->clk);
1813 static int tegra_hdmi_resume(struct device *dev)
1815 struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1818 err = clk_prepare_enable(hdmi->clk);
1820 dev_err(dev, "failed to enable clock: %d\n", err);
1824 usleep_range(1000, 2000);
1826 err = reset_control_deassert(hdmi->rst);
1828 dev_err(dev, "failed to deassert reset: %d\n", err);
1829 clk_disable_unprepare(hdmi->clk);
1837 static const struct dev_pm_ops tegra_hdmi_pm_ops = {
1838 SET_RUNTIME_PM_OPS(tegra_hdmi_suspend, tegra_hdmi_resume, NULL)
1841 struct platform_driver tegra_hdmi_driver = {
1843 .name = "tegra-hdmi",
1844 .of_match_table = tegra_hdmi_of_match,
1845 .pm = &tegra_hdmi_pm_ops,
1847 .probe = tegra_hdmi_probe,
1848 .remove = tegra_hdmi_remove,