drivers/gpu/drm/sun4i/sun4i_tcon.c

   1 /*
   2  * Copyright (C) 2015 Free Electrons
   3  * Copyright (C) 2015 NextThing Co
   4  *
   5  * Maxime Ripard <maxime.ripard@free-electrons.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_connector.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_crtc_helper.h>
  18 #include <drm/drm_encoder.h>
  19 #include <drm/drm_modes.h>
  20 #include <drm/drm_of.h>
  21 #include <drm/drm_panel.h>
  22
  23 #include <uapi/drm/drm_mode.h>
  24
  25 #include <linux/component.h>
  26 #include <linux/ioport.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_device.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/regmap.h>
  31 #include <linux/reset.h>
  32
  33 #include "sun4i_crtc.h"
  34 #include "sun4i_dotclock.h"
  35 #include "sun4i_drv.h"
  36 #include "sun4i_lvds.h"
  37 #include "sun4i_rgb.h"
  38 #include "sun4i_tcon.h"
  39 #include "sun6i_mipi_dsi.h"
  40 #include "sun8i_tcon_top.h"
  41 #include "sunxi_engine.h"
  42
  43 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
  44 {
  45         struct drm_connector *connector;
  46         struct drm_connector_list_iter iter;
  47
  48         drm_connector_list_iter_begin(encoder->dev, &iter);
  49         drm_for_each_connector_iter(connector, &iter)
  50                 if (connector->encoder == encoder) {
  51                         drm_connector_list_iter_end(&iter);
  52                         return connector;
  53                 }
  54         drm_connector_list_iter_end(&iter);
  55
  56         return NULL;
  57 }
  58
  59 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder)
  60 {
  61         struct drm_connector *connector;
  62         struct drm_display_info *info;
  63
  64         connector = sun4i_tcon_get_connector(encoder);
  65         if (!connector)
  66                 return -EINVAL;
  67
  68         info = &connector->display_info;
  69         if (info->num_bus_formats != 1)
  70                 return -EINVAL;
  71
  72         switch (info->bus_formats[0]) {
  73         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
  74                 return 18;
  75
  76         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
  77         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
  78                 return 24;
  79         }
  80
  81         return -EINVAL;
  82 }
  83
  84 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
  85                                           bool enabled)
  86 {
  87         struct clk *clk;
  88
  89         switch (channel) {
  90         case 0:
  91                 WARN_ON(!tcon->quirks->has_channel_0);
  92                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
  93                                    SUN4I_TCON0_CTL_TCON_ENABLE,
  94                                    enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
  95                 clk = tcon->dclk;
  96                 break;
  97         case 1:
  98                 WARN_ON(!tcon->quirks->has_channel_1);
  99                 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 100                                    SUN4I_TCON1_CTL_TCON_ENABLE,
 101                                    enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
 102                 clk = tcon->sclk1;
 103                 break;
 104         default:
 105                 DRM_WARN("Unknown channel... doing nothing\n");
 106                 return;
 107         }
 108
 109         if (enabled) {
 110                 clk_prepare_enable(clk);
 111                 clk_rate_exclusive_get(clk);
 112         } else {
 113                 clk_rate_exclusive_put(clk);
 114                 clk_disable_unprepare(clk);
 115         }
 116 }
 117
 118 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
 119                                        const struct drm_encoder *encoder,
 120                                        bool enabled)
 121 {
 122         if (enabled) {
 123                 u8 val;
 124
 125                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
 126                                    SUN4I_TCON0_LVDS_IF_EN,
 127                                    SUN4I_TCON0_LVDS_IF_EN);
 128
 129                 /*
 130                  * As their name suggest, these values only apply to the A31
 131                  * and later SoCs. We'll have to rework this when merging
 132                  * support for the older SoCs.
 133                  */
 134                 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 135                              SUN6I_TCON0_LVDS_ANA0_C(2) |
 136                              SUN6I_TCON0_LVDS_ANA0_V(3) |
 137                              SUN6I_TCON0_LVDS_ANA0_PD(2) |
 138                              SUN6I_TCON0_LVDS_ANA0_EN_LDO);
 139                 udelay(2);
 140
 141                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 142                                    SUN6I_TCON0_LVDS_ANA0_EN_MB,
 143                                    SUN6I_TCON0_LVDS_ANA0_EN_MB);
 144                 udelay(2);
 145
 146                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 147                                    SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
 148                                    SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
 149
 150                 if (sun4i_tcon_get_pixel_depth(encoder) == 18)
 151                         val = 7;
 152                 else
 153                         val = 0xf;
 154
 155                 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 156                                   SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
 157                                   SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
 158         } else {
 159                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
 160                                    SUN4I_TCON0_LVDS_IF_EN, 0);
 161         }
 162 }
 163
 164 void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
 165                            const struct drm_encoder *encoder,
 166                            bool enabled)
 167 {
 168         bool is_lvds = false;
 169         int channel;
 170
 171         switch (encoder->encoder_type) {
 172         case DRM_MODE_ENCODER_LVDS:
 173                 is_lvds = true;
 174                 /* Fallthrough */
 175         case DRM_MODE_ENCODER_DSI:
 176         case DRM_MODE_ENCODER_NONE:
 177                 channel = 0;
 178                 break;
 179         case DRM_MODE_ENCODER_TMDS:
 180         case DRM_MODE_ENCODER_TVDAC:
 181                 channel = 1;
 182                 break;
 183         default:
 184                 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
 185                 return;
 186         }
 187
 188         if (is_lvds && !enabled)
 189                 sun4i_tcon_lvds_set_status(tcon, encoder, false);
 190
 191         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 192                            SUN4I_TCON_GCTL_TCON_ENABLE,
 193                            enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
 194
 195         if (is_lvds && enabled)
 196                 sun4i_tcon_lvds_set_status(tcon, encoder, true);
 197
 198         sun4i_tcon_channel_set_status(tcon, channel, enabled);
 199 }
 200
 201 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
 202 {
 203         u32 mask, val = 0;
 204
 205         DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
 206
 207         mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
 208                 SUN4I_TCON_GINT0_VBLANK_ENABLE(1) |
 209                 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE;
 210
 211         if (enable)
 212                 val = mask;
 213
 214         regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
 215 }
 216 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
 217
 218 /*
 219  * This function is a helper for TCON output muxing. The TCON output
 220  * muxing control register in earlier SoCs (without the TCON TOP block)
 221  * are located in TCON0. This helper returns a pointer to TCON0's
 222  * sun4i_tcon structure, or NULL if not found.
 223  */
 224 static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
 225 {
 226         struct sun4i_drv *drv = drm->dev_private;
 227         struct sun4i_tcon *tcon;
 228
 229         list_for_each_entry(tcon, &drv->tcon_list, list)
 230                 if (tcon->id == 0)
 231                         return tcon;
 232
 233         dev_warn(drm->dev,
 234                  "TCON0 not found, display output muxing may not work\n");
 235
 236         return NULL;
 237 }
 238
 239 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
 240                         const struct drm_encoder *encoder)
 241 {
 242         int ret = -ENOTSUPP;
 243
 244         if (tcon->quirks->set_mux)
 245                 ret = tcon->quirks->set_mux(tcon, encoder);
 246
 247         DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
 248                          encoder->name, encoder->crtc->name, ret);
 249 }
 250
 251 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
 252                                     int channel)
 253 {
 254         int delay = mode->vtotal - mode->vdisplay;
 255
 256         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 257                 delay /= 2;
 258
 259         if (channel == 1)
 260                 delay -= 2;
 261
 262         delay = min(delay, 30);
 263
 264         DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
 265
 266         return delay;
 267 }
 268
 269 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
 270                                         const struct drm_display_mode *mode)
 271 {
 272         /* Configure the dot clock */
 273         clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
 274
 275         /* Set the resolution */
 276         regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
 277                      SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
 278                      SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
 279 }
 280
 281 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
 282                                            const struct drm_connector *connector)
 283 {
 284         u32 bus_format = 0;
 285         u32 val = 0;
 286
 287         /* XXX Would this ever happen? */
 288         if (!connector)
 289                 return;
 290
 291         /*
 292          * FIXME: Undocumented bits
 293          *
 294          * The whole dithering process and these parameters are not
 295          * explained in the vendor documents or BSP kernel code.
 296          */
 297         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
 298         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
 299         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
 300         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
 301         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
 302         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
 303         regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
 304         regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
 305         regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
 306         regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777);
 307
 308         /* Do dithering if panel only supports 6 bits per color */
 309         if (connector->display_info.bpc == 6)
 310                 val |= SUN4I_TCON0_FRM_CTL_EN;
 311
 312         if (connector->display_info.num_bus_formats == 1)
 313                 bus_format = connector->display_info.bus_formats[0];
 314
 315         /* Check the connection format */
 316         switch (bus_format) {
 317         case MEDIA_BUS_FMT_RGB565_1X16:
 318                 /* R and B components are only 5 bits deep */
 319                 val |= SUN4I_TCON0_FRM_CTL_MODE_R;
 320                 val |= SUN4I_TCON0_FRM_CTL_MODE_B;
 321         case MEDIA_BUS_FMT_RGB666_1X18:
 322         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 323                 /* Fall through: enable dithering */
 324                 val |= SUN4I_TCON0_FRM_CTL_EN;
 325                 break;
 326         }
 327
 328         /* Write dithering settings */
 329         regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
 330 }
 331
 332 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
 333                                      const struct drm_encoder *encoder,
 334                                      const struct drm_display_mode *mode)
 335 {
 336         /* TODO support normal CPU interface modes */
 337         struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
 338         struct mipi_dsi_device *device = dsi->device;
 339         u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
 340         u8 lanes = device->lanes;
 341         u32 block_space, start_delay;
 342         u32 tcon_div;
 343
 344         tcon->dclk_min_div = 4;
 345         tcon->dclk_max_div = 127;
 346
 347         sun4i_tcon0_mode_set_common(tcon, mode);
 348
 349         /* Set dithering if needed */
 350         sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
 351
 352         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 353                            SUN4I_TCON0_CTL_IF_MASK,
 354                            SUN4I_TCON0_CTL_IF_8080);
 355
 356         regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG,
 357                      SUN4I_TCON_ECC_FIFO_EN);
 358
 359         regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG,
 360                      SUN4I_TCON0_CPU_IF_MODE_DSI |
 361                      SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH |
 362                      SUN4I_TCON0_CPU_IF_TRI_FIFO_EN |
 363                      SUN4I_TCON0_CPU_IF_TRI_EN);
 364
 365         /*
 366          * This looks suspicious, but it works...
 367          *
 368          * The datasheet says that this should be set higher than 20 *
 369          * pixel cycle, but it's not clear what a pixel cycle is.
 370          */
 371         regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
 372         tcon_div &= GENMASK(6, 0);
 373         block_space = mode->htotal * bpp / (tcon_div * lanes);
 374         block_space -= mode->hdisplay + 40;
 375
 376         regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
 377                      SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space) |
 378                      SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay));
 379
 380         regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG,
 381                      SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay));
 382
 383         start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1);
 384         start_delay = start_delay * mode->crtc_htotal * 149;
 385         start_delay = start_delay / (mode->crtc_clock / 1000) / 8;
 386         regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG,
 387                      SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) |
 388                      SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay));
 389
 390         /*
 391          * The Allwinner BSP has a comment that the period should be
 392          * the display clock * 15, but uses an hardcoded 3000...
 393          */
 394         regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG,
 395                      SUN4I_TCON_SAFE_PERIOD_NUM(3000) |
 396                      SUN4I_TCON_SAFE_PERIOD_MODE(3));
 397
 398         /* Enable the output on the pins */
 399         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG,
 400                      0xe0000000);
 401 }
 402
 403 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
 404                                       const struct drm_encoder *encoder,
 405                                       const struct drm_display_mode *mode)
 406 {
 407         unsigned int bp;
 408         u8 clk_delay;
 409         u32 reg, val = 0;
 410
 411         WARN_ON(!tcon->quirks->has_channel_0);
 412
 413         tcon->dclk_min_div = 7;
 414         tcon->dclk_max_div = 7;
 415         sun4i_tcon0_mode_set_common(tcon, mode);
 416
 417         /* Set dithering if needed */
 418         sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
 419
 420         /* Adjust clock delay */
 421         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
 422         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 423                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
 424                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
 425
 426         /*
 427          * This is called a backporch in the register documentation,
 428          * but it really is the back porch + hsync
 429          */
 430         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 431         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 432                          mode->crtc_htotal, bp);
 433
 434         /* Set horizontal display timings */
 435         regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
 436                      SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
 437                      SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
 438
 439         /*
 440          * This is called a backporch in the register documentation,
 441          * but it really is the back porch + hsync
 442          */
 443         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 444         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 445                          mode->crtc_vtotal, bp);
 446
 447         /* Set vertical display timings */
 448         regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
 449                      SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
 450                      SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
 451
 452         reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
 453                 SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
 454                 SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
 455         if (sun4i_tcon_get_pixel_depth(encoder) == 24)
 456                 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
 457         else
 458                 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
 459
 460         regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
 461
 462         /* Setup the polarity of the various signals */
 463         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 464                 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
 465
 466         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 467                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
 468
 469         regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
 470
 471         /* Map output pins to channel 0 */
 472         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 473                            SUN4I_TCON_GCTL_IOMAP_MASK,
 474                            SUN4I_TCON_GCTL_IOMAP_TCON0);
 475
 476         /* Enable the output on the pins */
 477         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
 478 }
 479
 480 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
 481                                      const struct drm_display_mode *mode)
 482 {
 483         unsigned int bp, hsync, vsync;
 484         u8 clk_delay;
 485         u32 val = 0;
 486
 487         WARN_ON(!tcon->quirks->has_channel_0);
 488
 489         tcon->dclk_min_div = 6;
 490         tcon->dclk_max_div = 127;
 491         sun4i_tcon0_mode_set_common(tcon, mode);
 492
 493         /* Set dithering if needed */
 494         if (tcon->panel)
 495                 sun4i_tcon0_mode_set_dithering(tcon, tcon->panel->connector);
 496
 497         /* Adjust clock delay */
 498         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
 499         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 500                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
 501                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
 502
 503         /*
 504          * This is called a backporch in the register documentation,
 505          * but it really is the back porch + hsync
 506          */
 507         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 508         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 509                          mode->crtc_htotal, bp);
 510
 511         /* Set horizontal display timings */
 512         regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
 513                      SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
 514                      SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
 515
 516         /*
 517          * This is called a backporch in the register documentation,
 518          * but it really is the back porch + hsync
 519          */
 520         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 521         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 522                          mode->crtc_vtotal, bp);
 523
 524         /* Set vertical display timings */
 525         regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
 526                      SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
 527                      SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
 528
 529         /* Set Hsync and Vsync length */
 530         hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
 531         vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
 532         DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
 533         regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
 534                      SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
 535                      SUN4I_TCON0_BASIC3_H_SYNC(hsync));
 536
 537         /* Setup the polarity of the various signals */
 538         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 539                 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
 540
 541         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 542                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
 543
 544         /*
 545          * On A20 and similar SoCs, the only way to achieve Positive Edge
 546          * (Rising Edge), is setting dclk clock phase to 2/3(240°).
 547          * By default TCON works in Negative Edge(Falling Edge),
 548          * this is why phase is set to 0 in that case.
 549          * Unfortunately there's no way to logically invert dclk through
 550          * IO_POL register.
 551          * The only acceptable way to work, triple checked with scope,
 552          * is using clock phase set to 0° for Negative Edge and set to 240°
 553          * for Positive Edge.
 554          * On A33 and similar SoCs there would be a 90° phase option,
 555          * but it divides also dclk by 2.
 556          * Following code is a way to avoid quirks all around TCON
 557          * and DOTCLOCK drivers.
 558          */
 559         if (tcon->panel) {
 560                 struct drm_panel *panel = tcon->panel;
 561                 struct drm_connector *connector = panel->connector;
 562                 struct drm_display_info display_info = connector->display_info;
 563
 564                 if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE)
 565                         clk_set_phase(tcon->dclk, 240);
 566
 567                 if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
 568                         clk_set_phase(tcon->dclk, 0);
 569         }
 570
 571         regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
 572                            SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
 573                            val);
 574
 575         /* Map output pins to channel 0 */
 576         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 577                            SUN4I_TCON_GCTL_IOMAP_MASK,
 578                            SUN4I_TCON_GCTL_IOMAP_TCON0);
 579
 580         /* Enable the output on the pins */
 581         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
 582 }
 583
 584 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
 585                                  const struct drm_display_mode *mode)
 586 {
 587         unsigned int bp, hsync, vsync, vtotal;
 588         u8 clk_delay;
 589         u32 val;
 590
 591         WARN_ON(!tcon->quirks->has_channel_1);
 592
 593         /* Configure the dot clock */
 594         clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
 595
 596         /* Adjust clock delay */
 597         clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
 598         regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 599                            SUN4I_TCON1_CTL_CLK_DELAY_MASK,
 600                            SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
 601
 602         /* Set interlaced mode */
 603         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 604                 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
 605         else
 606                 val = 0;
 607         regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 608                            SUN4I_TCON1_CTL_INTERLACE_ENABLE,
 609                            val);
 610
 611         /* Set the input resolution */
 612         regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
 613                      SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
 614                      SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
 615
 616         /* Set the upscaling resolution */
 617         regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
 618                      SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
 619                      SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
 620
 621         /* Set the output resolution */
 622         regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
 623                      SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
 624                      SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
 625
 626         /* Set horizontal display timings */
 627         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 628         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 629                          mode->htotal, bp);
 630         regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
 631                      SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
 632                      SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
 633
 634         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 635         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 636                          mode->crtc_vtotal, bp);
 637
 638         /*
 639          * The vertical resolution needs to be doubled in all
 640          * cases. We could use crtc_vtotal and always multiply by two,
 641          * but that leads to a rounding error in interlace when vtotal
 642          * is odd.
 643          *
 644          * This happens with TV's PAL for example, where vtotal will
 645          * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
 646          * 624, which apparently confuses the hardware.
 647          *
 648          * To work around this, we will always use vtotal, and
 649          * multiply by two only if we're not in interlace.
 650          */
 651         vtotal = mode->vtotal;
 652         if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
 653                 vtotal = vtotal * 2;
 654
 655         /* Set vertical display timings */
 656         regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
 657                      SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
 658                      SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
 659
 660         /* Set Hsync and Vsync length */
 661         hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
 662         vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
 663         DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
 664         regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
 665                      SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
 666                      SUN4I_TCON1_BASIC5_H_SYNC(hsync));
 667
 668         /* Map output pins to channel 1 */
 669         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 670                            SUN4I_TCON_GCTL_IOMAP_MASK,
 671                            SUN4I_TCON_GCTL_IOMAP_TCON1);
 672 }
 673
 674 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
 675                          const struct drm_encoder *encoder,
 676                          const struct drm_display_mode *mode)
 677 {
 678         switch (encoder->encoder_type) {
 679         case DRM_MODE_ENCODER_DSI:
 680                 /* DSI is tied to special case of CPU interface */
 681                 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode);
 682                 break;
 683         case DRM_MODE_ENCODER_LVDS:
 684                 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
 685                 break;
 686         case DRM_MODE_ENCODER_NONE:
 687                 sun4i_tcon0_mode_set_rgb(tcon, mode);
 688                 sun4i_tcon_set_mux(tcon, 0, encoder);
 689                 break;
 690         case DRM_MODE_ENCODER_TVDAC:
 691         case DRM_MODE_ENCODER_TMDS:
 692                 sun4i_tcon1_mode_set(tcon, mode);
 693                 sun4i_tcon_set_mux(tcon, 1, encoder);
 694                 break;
 695         default:
 696                 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
 697         }
 698 }
 699 EXPORT_SYMBOL(sun4i_tcon_mode_set);
 700
 701 static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
 702                                         struct sun4i_crtc *scrtc)
 703 {
 704         unsigned long flags;
 705
 706         spin_lock_irqsave(&dev->event_lock, flags);
 707         if (scrtc->event) {
 708                 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
 709                 drm_crtc_vblank_put(&scrtc->crtc);
 710                 scrtc->event = NULL;
 711         }
 712         spin_unlock_irqrestore(&dev->event_lock, flags);
 713 }
 714
 715 static irqreturn_t sun4i_tcon_handler(int irq, void *private)
 716 {
 717         struct sun4i_tcon *tcon = private;
 718         struct drm_device *drm = tcon->drm;
 719         struct sun4i_crtc *scrtc = tcon->crtc;
 720         struct sunxi_engine *engine = scrtc->engine;
 721         unsigned int status;
 722
 723         regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
 724
 725         if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
 726                         SUN4I_TCON_GINT0_VBLANK_INT(1) |
 727                         SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT)))
 728                 return IRQ_NONE;
 729
 730         drm_crtc_handle_vblank(&scrtc->crtc);
 731         sun4i_tcon_finish_page_flip(drm, scrtc);
 732
 733         /* Acknowledge the interrupt */
 734         regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
 735                            SUN4I_TCON_GINT0_VBLANK_INT(0) |
 736                            SUN4I_TCON_GINT0_VBLANK_INT(1) |
 737                            SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT,
 738                            0);
 739
 740         if (engine->ops->vblank_quirk)
 741                 engine->ops->vblank_quirk(engine);
 742
 743         return IRQ_HANDLED;
 744 }
 745
 746 static int sun4i_tcon_init_clocks(struct device *dev,
 747                                   struct sun4i_tcon *tcon)
 748 {
 749         tcon->clk = devm_clk_get(dev, "ahb");
 750         if (IS_ERR(tcon->clk)) {
 751                 dev_err(dev, "Couldn't get the TCON bus clock\n");
 752                 return PTR_ERR(tcon->clk);
 753         }
 754         clk_prepare_enable(tcon->clk);
 755
 756         if (tcon->quirks->has_channel_0) {
 757                 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
 758                 if (IS_ERR(tcon->sclk0)) {
 759                         dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
 760                         return PTR_ERR(tcon->sclk0);
 761                 }
 762         }
 763
 764         if (tcon->quirks->has_channel_1) {
 765                 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
 766                 if (IS_ERR(tcon->sclk1)) {
 767                         dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
 768                         return PTR_ERR(tcon->sclk1);
 769                 }
 770         }
 771
 772         return 0;
 773 }
 774
 775 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
 776 {
 777         clk_disable_unprepare(tcon->clk);
 778 }
 779
 780 static int sun4i_tcon_init_irq(struct device *dev,
 781                                struct sun4i_tcon *tcon)
 782 {
 783         struct platform_device *pdev = to_platform_device(dev);
 784         int irq, ret;
 785
 786         irq = platform_get_irq(pdev, 0);
 787         if (irq < 0) {
 788                 dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
 789                 return irq;
 790         }
 791
 792         ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
 793                                dev_name(dev), tcon);
 794         if (ret) {
 795                 dev_err(dev, "Couldn't request the IRQ\n");
 796                 return ret;
 797         }
 798
 799         return 0;
 800 }
 801
 802 static struct regmap_config sun4i_tcon_regmap_config = {
 803         .reg_bits       = 32,
 804         .val_bits       = 32,
 805         .reg_stride     = 4,
 806         .max_register   = 0x800,
 807 };
 808
 809 static int sun4i_tcon_init_regmap(struct device *dev,
 810                                   struct sun4i_tcon *tcon)
 811 {
 812         struct platform_device *pdev = to_platform_device(dev);
 813         struct resource *res;
 814         void __iomem *regs;
 815
 816         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 817         regs = devm_ioremap_resource(dev, res);
 818         if (IS_ERR(regs))
 819                 return PTR_ERR(regs);
 820
 821         tcon->regs = devm_regmap_init_mmio(dev, regs,
 822                                            &sun4i_tcon_regmap_config);
 823         if (IS_ERR(tcon->regs)) {
 824                 dev_err(dev, "Couldn't create the TCON regmap\n");
 825                 return PTR_ERR(tcon->regs);
 826         }
 827
 828         /* Make sure the TCON is disabled and all IRQs are off */
 829         regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
 830         regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
 831         regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
 832
 833         /* Disable IO lines and set them to tristate */
 834         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
 835         regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
 836
 837         return 0;
 838 }
 839
 840 /*
 841  * On SoCs with the old display pipeline design (Display Engine 1.0),
 842  * the TCON is always tied to just one backend. Hence we can traverse
 843  * the of_graph upwards to find the backend our tcon is connected to,
 844  * and take its ID as our own.
 845  *
 846  * We can either identify backends from their compatible strings, which
 847  * means maintaining a large list of them. Or, since the backend is
 848  * registered and binded before the TCON, we can just go through the
 849  * list of registered backends and compare the device node.
 850  *
 851  * As the structures now store engines instead of backends, here this
 852  * function in fact searches the corresponding engine, and the ID is
 853  * requested via the get_id function of the engine.
 854  */
 855 static struct sunxi_engine *
 856 sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
 857                                 struct device_node *node,
 858                                 u32 port_id)
 859 {
 860         struct device_node *port, *ep, *remote;
 861         struct sunxi_engine *engine = ERR_PTR(-EINVAL);
 862         u32 reg = 0;
 863
 864         port = of_graph_get_port_by_id(node, port_id);
 865         if (!port)
 866                 return ERR_PTR(-EINVAL);
 867
 868         /*
 869          * This only works if there is only one path from the TCON
 870          * to any display engine. Otherwise the probe order of the
 871          * TCONs and display engines is not guaranteed. They may
 872          * either bind to the wrong one, or worse, bind to the same
 873          * one if additional checks are not done.
 874          *
 875          * Bail out if there are multiple input connections.
 876          */
 877         if (of_get_available_child_count(port) != 1)
 878                 goto out_put_port;
 879
 880         /* Get the first connection without specifying an ID */
 881         ep = of_get_next_available_child(port, NULL);
 882         if (!ep)
 883                 goto out_put_port;
 884
 885         remote = of_graph_get_remote_port_parent(ep);
 886         if (!remote)
 887                 goto out_put_ep;
 888
 889         /* does this node match any registered engines? */
 890         list_for_each_entry(engine, &drv->engine_list, list)
 891                 if (remote == engine->node)
 892                         goto out_put_remote;
 893
 894         /*
 895          * According to device tree binding input ports have even id
 896          * number and output ports have odd id. Since component with
 897          * more than one input and one output (TCON TOP) exits, correct
 898          * remote input id has to be calculated by subtracting 1 from
 899          * remote output id. If this for some reason can't be done, 0
 900          * is used as input port id.
 901          */
 902         of_node_put(port);
 903         port = of_graph_get_remote_port(ep);
 904         if (!of_property_read_u32(port, "reg", &reg) && reg > 0)
 905                 reg -= 1;
 906
 907         /* keep looking through upstream ports */
 908         engine = sun4i_tcon_find_engine_traverse(drv, remote, reg);
 909
 910 out_put_remote:
 911         of_node_put(remote);
 912 out_put_ep:
 913         of_node_put(ep);
 914 out_put_port:
 915         of_node_put(port);
 916
 917         return engine;
 918 }
 919
 920 /*
 921  * The device tree binding says that the remote endpoint ID of any
 922  * connection between components, up to and including the TCON, of
 923  * the display pipeline should be equal to the actual ID of the local
 924  * component. Thus we can look at any one of the input connections of
 925  * the TCONs, and use that connection's remote endpoint ID as our own.
 926  *
 927  * Since the user of this function already finds the input port,
 928  * the port is passed in directly without further checks.
 929  */
 930 static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
 931 {
 932         struct device_node *ep;
 933         int ret = -EINVAL;
 934
 935         /* try finding an upstream endpoint */
 936         for_each_available_child_of_node(port, ep) {
 937                 struct device_node *remote;
 938                 u32 reg;
 939
 940                 remote = of_graph_get_remote_endpoint(ep);
 941                 if (!remote)
 942                         continue;
 943
 944                 ret = of_property_read_u32(remote, "reg", &reg);
 945                 if (ret)
 946                         continue;
 947
 948                 ret = reg;
 949         }
 950
 951         return ret;
 952 }
 953
 954 /*
 955  * Once we know the TCON's id, we can look through the list of
 956  * engines to find a matching one. We assume all engines have
 957  * been probed and added to the list.
 958  */
 959 static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
 960                                                         int id)
 961 {
 962         struct sunxi_engine *engine;
 963
 964         list_for_each_entry(engine, &drv->engine_list, list)
 965                 if (engine->id == id)
 966                         return engine;
 967
 968         return ERR_PTR(-EINVAL);
 969 }
 970
 971 static bool sun4i_tcon_connected_to_tcon_top(struct device_node *node)
 972 {
 973         struct device_node *remote;
 974         bool ret = false;
 975
 976         remote = of_graph_get_remote_node(node, 0, -1);
 977         if (remote) {
 978                 ret = !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
 979                          of_match_node(sun8i_tcon_top_of_table, remote));
 980                 of_node_put(remote);
 981         }
 982
 983         return ret;
 984 }
 985
 986 static int sun4i_tcon_get_index(struct sun4i_drv *drv)
 987 {
 988         struct list_head *pos;
 989         int size = 0;
 990
 991         /*
 992          * Because TCON is added to the list at the end of the probe
 993          * (after this function is called), index of the current TCON
 994          * will be same as current TCON list size.
 995          */
 996         list_for_each(pos, &drv->tcon_list)
 997                 ++size;
 998
 999         return size;
1000 }
1001
1002 /*
1003  * On SoCs with the old display pipeline design (Display Engine 1.0),
1004  * we assumed the TCON was always tied to just one backend. However
1005  * this proved not to be the case. On the A31, the TCON can select
1006  * either backend as its source. On the A20 (and likely on the A10),
1007  * the backend can choose which TCON to output to.
1008  *
1009  * The device tree binding says that the remote endpoint ID of any
1010  * connection between components, up to and including the TCON, of
1011  * the display pipeline should be equal to the actual ID of the local
1012  * component. Thus we should be able to look at any one of the input
1013  * connections of the TCONs, and use that connection's remote endpoint
1014  * ID as our own.
1015  *
1016  * However  the connections between the backend and TCON were assumed
1017  * to be always singular, and their endpoit IDs were all incorrectly
1018  * set to 0. This means for these old device trees, we cannot just look
1019  * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
1020  * incorrectly identified as TCON0.
1021  *
1022  * This function first checks if the TCON node has 2 input endpoints.
1023  * If so, then the device tree is a corrected version, and it will use
1024  * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
1025  * to fetch the ID and engine directly. If not, then it is likely an
1026  * old device trees, where the endpoint IDs were incorrect, but did not
1027  * have endpoint connections between the backend and TCON across
1028  * different display pipelines. It will fall back to the old method of
1029  * traversing the  of_graph to try and find a matching engine by device
1030  * node.
1031  *
1032  * In the case of single display pipeline device trees, either method
1033  * works.
1034  */
1035 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
1036                                                    struct device_node *node)
1037 {
1038         struct device_node *port;
1039         struct sunxi_engine *engine;
1040
1041         port = of_graph_get_port_by_id(node, 0);
1042         if (!port)
1043                 return ERR_PTR(-EINVAL);
1044
1045         /*
1046          * Is this a corrected device tree with cross pipeline
1047          * connections between the backend and TCON?
1048          */
1049         if (of_get_child_count(port) > 1) {
1050                 int id;
1051
1052                 /*
1053                  * When pipeline has the same number of TCONs and engines which
1054                  * are represented by frontends/backends (DE1) or mixers (DE2),
1055                  * we match them by their respective IDs. However, if pipeline
1056                  * contains TCON TOP, chances are that there are either more
1057                  * TCONs than engines (R40) or TCONs with non-consecutive ids.
1058                  * (H6). In that case it's easier just use TCON index in list
1059                  * as an id. That means that on R40, any 2 TCONs can be enabled
1060                  * in DT out of 4 (there are 2 mixers). Due to the design of
1061                  * TCON TOP, remaining 2 TCONs can't be connected to anything
1062                  * anyway.
1063                  */
1064                 if (sun4i_tcon_connected_to_tcon_top(node))
1065                         id = sun4i_tcon_get_index(drv);
1066                 else
1067                         id = sun4i_tcon_of_get_id_from_port(port);
1068
1069                 /* Get our engine by matching our ID */
1070                 engine = sun4i_tcon_get_engine_by_id(drv, id);
1071
1072                 of_node_put(port);
1073                 return engine;
1074         }
1075
1076         /* Fallback to old method by traversing input endpoints */
1077         of_node_put(port);
1078         return sun4i_tcon_find_engine_traverse(drv, node, 0);
1079 }
1080
1081 static int sun4i_tcon_bind(struct device *dev, struct device *master,
1082                            void *data)
1083 {
1084         struct drm_device *drm = data;
1085         struct sun4i_drv *drv = drm->dev_private;
1086         struct sunxi_engine *engine;
1087         struct device_node *remote;
1088         struct sun4i_tcon *tcon;
1089         struct reset_control *edp_rstc;
1090         bool has_lvds_rst, has_lvds_alt, can_lvds;
1091         int ret;
1092
1093         engine = sun4i_tcon_find_engine(drv, dev->of_node);
1094         if (IS_ERR(engine)) {
1095                 dev_err(dev, "Couldn't find matching engine\n");
1096                 return -EPROBE_DEFER;
1097         }
1098
1099         tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
1100         if (!tcon)
1101                 return -ENOMEM;
1102         dev_set_drvdata(dev, tcon);
1103         tcon->drm = drm;
1104         tcon->dev = dev;
1105         tcon->id = engine->id;
1106         tcon->quirks = of_device_get_match_data(dev);
1107
1108         tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
1109         if (IS_ERR(tcon->lcd_rst)) {
1110                 dev_err(dev, "Couldn't get our reset line\n");
1111                 return PTR_ERR(tcon->lcd_rst);
1112         }
1113
1114         if (tcon->quirks->needs_edp_reset) {
1115                 edp_rstc = devm_reset_control_get_shared(dev, "edp");
1116                 if (IS_ERR(edp_rstc)) {
1117                         dev_err(dev, "Couldn't get edp reset line\n");
1118                         return PTR_ERR(edp_rstc);
1119                 }
1120
1121                 ret = reset_control_deassert(edp_rstc);
1122                 if (ret) {
1123                         dev_err(dev, "Couldn't deassert edp reset line\n");
1124                         return ret;
1125                 }
1126         }
1127
1128         /* Make sure our TCON is reset */
1129         ret = reset_control_reset(tcon->lcd_rst);
1130         if (ret) {
1131                 dev_err(dev, "Couldn't deassert our reset line\n");
1132                 return ret;
1133         }
1134
1135         if (tcon->quirks->supports_lvds) {
1136                 /*
1137                  * This can only be made optional since we've had DT
1138                  * nodes without the LVDS reset properties.
1139                  *
1140                  * If the property is missing, just disable LVDS, and
1141                  * print a warning.
1142                  */
1143                 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
1144                 if (IS_ERR(tcon->lvds_rst)) {
1145                         dev_err(dev, "Couldn't get our reset line\n");
1146                         return PTR_ERR(tcon->lvds_rst);
1147                 } else if (tcon->lvds_rst) {
1148                         has_lvds_rst = true;
1149                         reset_control_reset(tcon->lvds_rst);
1150                 } else {
1151                         has_lvds_rst = false;
1152                 }
1153
1154                 /*
1155                  * This can only be made optional since we've had DT
1156                  * nodes without the LVDS reset properties.
1157                  *
1158                  * If the property is missing, just disable LVDS, and
1159                  * print a warning.
1160                  */
1161                 if (tcon->quirks->has_lvds_alt) {
1162                         tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
1163                         if (IS_ERR(tcon->lvds_pll)) {
1164                                 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
1165                                         has_lvds_alt = false;
1166                                 } else {
1167                                         dev_err(dev, "Couldn't get the LVDS PLL\n");
1168                                         return PTR_ERR(tcon->lvds_pll);
1169                                 }
1170                         } else {
1171                                 has_lvds_alt = true;
1172                         }
1173                 }
1174
1175                 if (!has_lvds_rst ||
1176                     (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
1177                         dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n");
1178                         dev_warn(dev, "LVDS output disabled\n");
1179                         can_lvds = false;
1180                 } else {
1181                         can_lvds = true;
1182                 }
1183         } else {
1184                 can_lvds = false;
1185         }
1186
1187         ret = sun4i_tcon_init_clocks(dev, tcon);
1188         if (ret) {
1189                 dev_err(dev, "Couldn't init our TCON clocks\n");
1190                 goto err_assert_reset;
1191         }
1192
1193         ret = sun4i_tcon_init_regmap(dev, tcon);
1194         if (ret) {
1195                 dev_err(dev, "Couldn't init our TCON regmap\n");
1196                 goto err_free_clocks;
1197         }
1198
1199         if (tcon->quirks->has_channel_0) {
1200                 ret = sun4i_dclk_create(dev, tcon);
1201                 if (ret) {
1202                         dev_err(dev, "Couldn't create our TCON dot clock\n");
1203                         goto err_free_clocks;
1204                 }
1205         }
1206
1207         ret = sun4i_tcon_init_irq(dev, tcon);
1208         if (ret) {
1209                 dev_err(dev, "Couldn't init our TCON interrupts\n");
1210                 goto err_free_dotclock;
1211         }
1212
1213         tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
1214         if (IS_ERR(tcon->crtc)) {
1215                 dev_err(dev, "Couldn't create our CRTC\n");
1216                 ret = PTR_ERR(tcon->crtc);
1217                 goto err_free_dotclock;
1218         }
1219
1220         if (tcon->quirks->has_channel_0) {
1221                 /*
1222                  * If we have an LVDS panel connected to the TCON, we should
1223                  * just probe the LVDS connector. Otherwise, just probe RGB as
1224                  * we used to.
1225                  */
1226                 remote = of_graph_get_remote_node(dev->of_node, 1, 0);
1227                 if (of_device_is_compatible(remote, "panel-lvds"))
1228                         if (can_lvds)
1229                                 ret = sun4i_lvds_init(drm, tcon);
1230                         else
1231                                 ret = -EINVAL;
1232                 else
1233                         ret = sun4i_rgb_init(drm, tcon);
1234                 of_node_put(remote);
1235
1236                 if (ret < 0)
1237                         goto err_free_dotclock;
1238         }
1239
1240         if (tcon->quirks->needs_de_be_mux) {
1241                 /*
1242                  * We assume there is no dynamic muxing of backends
1243                  * and TCONs, so we select the backend with same ID.
1244                  *
1245                  * While dynamic selection might be interesting, since
1246                  * the CRTC is tied to the TCON, while the layers are
1247                  * tied to the backends, this means, we will need to
1248                  * switch between groups of layers. There might not be
1249                  * a way to represent this constraint in DRM.
1250                  */
1251                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
1252                                    SUN4I_TCON0_CTL_SRC_SEL_MASK,
1253                                    tcon->id);
1254                 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
1255                                    SUN4I_TCON1_CTL_SRC_SEL_MASK,
1256                                    tcon->id);
1257         }
1258
1259         list_add_tail(&tcon->list, &drv->tcon_list);
1260
1261         return 0;
1262
1263 err_free_dotclock:
1264         if (tcon->quirks->has_channel_0)
1265                 sun4i_dclk_free(tcon);
1266 err_free_clocks:
1267         sun4i_tcon_free_clocks(tcon);
1268 err_assert_reset:
1269         reset_control_assert(tcon->lcd_rst);
1270         return ret;
1271 }
1272
1273 static void sun4i_tcon_unbind(struct device *dev, struct device *master,
1274                               void *data)
1275 {
1276         struct sun4i_tcon *tcon = dev_get_drvdata(dev);
1277
1278         list_del(&tcon->list);
1279         if (tcon->quirks->has_channel_0)
1280                 sun4i_dclk_free(tcon);
1281         sun4i_tcon_free_clocks(tcon);
1282 }
1283
1284 static const struct component_ops sun4i_tcon_ops = {
1285         .bind   = sun4i_tcon_bind,
1286         .unbind = sun4i_tcon_unbind,
1287 };
1288
1289 static int sun4i_tcon_probe(struct platform_device *pdev)
1290 {
1291         struct device_node *node = pdev->dev.of_node;
1292         const struct sun4i_tcon_quirks *quirks;
1293         struct drm_bridge *bridge;
1294         struct drm_panel *panel;
1295         int ret;
1296
1297         quirks = of_device_get_match_data(&pdev->dev);
1298
1299         /* panels and bridges are present only on TCONs with channel 0 */
1300         if (quirks->has_channel_0) {
1301                 ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
1302                 if (ret == -EPROBE_DEFER)
1303                         return ret;
1304         }
1305
1306         return component_add(&pdev->dev, &sun4i_tcon_ops);
1307 }
1308
1309 static int sun4i_tcon_remove(struct platform_device *pdev)
1310 {
1311         component_del(&pdev->dev, &sun4i_tcon_ops);
1312
1313         return 0;
1314 }
1315
1316 /* platform specific TCON muxing callbacks */
1317 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
1318                                   const struct drm_encoder *encoder)
1319 {
1320         struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1321         u32 shift;
1322
1323         if (!tcon0)
1324                 return -EINVAL;
1325
1326         switch (encoder->encoder_type) {
1327         case DRM_MODE_ENCODER_TMDS:
1328                 /* HDMI */
1329                 shift = 8;
1330                 break;
1331         default:
1332                 return -EINVAL;
1333         }
1334
1335         regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1336                            0x3 << shift, tcon->id << shift);
1337
1338         return 0;
1339 }
1340
1341 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
1342                                   const struct drm_encoder *encoder)
1343 {
1344         u32 val;
1345
1346         if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1347                 val = 1;
1348         else
1349                 val = 0;
1350
1351         /*
1352          * FIXME: Undocumented bits
1353          */
1354         return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
1355 }
1356
1357 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
1358                               const struct drm_encoder *encoder)
1359 {
1360         struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1361         u32 shift;
1362
1363         if (!tcon0)
1364                 return -EINVAL;
1365
1366         switch (encoder->encoder_type) {
1367         case DRM_MODE_ENCODER_TMDS:
1368                 /* HDMI */
1369                 shift = 8;
1370                 break;
1371         default:
1372                 /* TODO A31 has MIPI DSI but A31s does not */
1373                 return -EINVAL;
1374         }
1375
1376         regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1377                            0x3 << shift, tcon->id << shift);
1378
1379         return 0;
1380 }
1381
1382 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon,
1383                                      const struct drm_encoder *encoder)
1384 {
1385         struct device_node *port, *remote;
1386         struct platform_device *pdev;
1387         int id, ret;
1388
1389         /* find TCON TOP platform device and TCON id */
1390
1391         port = of_graph_get_port_by_id(tcon->dev->of_node, 0);
1392         if (!port)
1393                 return -EINVAL;
1394
1395         id = sun4i_tcon_of_get_id_from_port(port);
1396         of_node_put(port);
1397
1398         remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1);
1399         if (!remote)
1400                 return -EINVAL;
1401
1402         pdev = of_find_device_by_node(remote);
1403         of_node_put(remote);
1404         if (!pdev)
1405                 return -EINVAL;
1406
1407         if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
1408             encoder->encoder_type == DRM_MODE_ENCODER_TMDS) {
1409                 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id);
1410                 if (ret)
1411                         return ret;
1412         }
1413
1414         if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP)) {
1415                 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id);
1416                 if (ret)
1417                         return ret;
1418         }
1419
1420         return 0;
1421 }
1422
1423 static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
1424         .has_channel_0          = true,
1425         .has_channel_1          = true,
1426         .set_mux                = sun4i_a10_tcon_set_mux,
1427 };
1428
1429 static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
1430         .has_channel_0          = true,
1431         .has_channel_1          = true,
1432         .set_mux                = sun5i_a13_tcon_set_mux,
1433 };
1434
1435 static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
1436         .has_channel_0          = true,
1437         .has_channel_1          = true,
1438         .has_lvds_alt           = true,
1439         .needs_de_be_mux        = true,
1440         .set_mux                = sun6i_tcon_set_mux,
1441 };
1442
1443 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
1444         .has_channel_0          = true,
1445         .has_channel_1          = true,
1446         .needs_de_be_mux        = true,
1447 };
1448
1449 static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
1450         .has_channel_0          = true,
1451         .has_channel_1          = true,
1452         /* Same display pipeline structure as A10 */
1453         .set_mux                = sun4i_a10_tcon_set_mux,
1454 };
1455
1456 static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
1457         .has_channel_0          = true,
1458         .has_lvds_alt           = true,
1459 };
1460
1461 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
1462         .supports_lvds          = true,
1463         .has_channel_0          = true,
1464 };
1465
1466 static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
1467         .has_channel_1          = true,
1468 };
1469
1470 static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
1471         .has_channel_1          = true,
1472         .set_mux                = sun8i_r40_tcon_tv_set_mux,
1473 };
1474
1475 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
1476         .has_channel_0          = true,
1477 };
1478
1479 static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = {
1480         .has_channel_0  = true,
1481         .needs_edp_reset = true,
1482 };
1483
1484 static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = {
1485         .has_channel_1  = true,
1486         .needs_edp_reset = true,
1487 };
1488
1489 /* sun4i_drv uses this list to check if a device node is a TCON */
1490 const struct of_device_id sun4i_tcon_of_table[] = {
1491         { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1492         { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1493         { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1494         { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1495         { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1496         { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1497         { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1498         { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1499         { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1500         { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1501         { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1502         { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1503         { }
1504 };
1505 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
1506 EXPORT_SYMBOL(sun4i_tcon_of_table);
1507
1508 static struct platform_driver sun4i_tcon_platform_driver = {
1509         .probe          = sun4i_tcon_probe,
1510         .remove         = sun4i_tcon_remove,
1511         .driver         = {
1512                 .name           = "sun4i-tcon",
1513                 .of_match_table = sun4i_tcon_of_table,
1514         },
1515 };
1516 module_platform_driver(sun4i_tcon_platform_driver);
1517
1518 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1519 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
1520 MODULE_LICENSE("GPL");