drivers/gpu/drm/sun4i/sun4i_tcon.c

   1 /*
   2  * Copyright (C) 2015 Free Electrons
   3  * Copyright (C) 2015 NextThing Co
   4  *
   5  * Maxime Ripard <maxime.ripard@free-electrons.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_connector.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_crtc_helper.h>
  18 #include <drm/drm_encoder.h>
  19 #include <drm/drm_modes.h>
  20 #include <drm/drm_of.h>
  21 #include <drm/drm_panel.h>
  22
  23 #include <uapi/drm/drm_mode.h>
  24
  25 #include <linux/component.h>
  26 #include <linux/ioport.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_device.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/regmap.h>
  31 #include <linux/reset.h>
  32
  33 #include "sun4i_crtc.h"
  34 #include "sun4i_dotclock.h"
  35 #include "sun4i_drv.h"
  36 #include "sun4i_lvds.h"
  37 #include "sun4i_rgb.h"
  38 #include "sun4i_tcon.h"
  39 #include "sun6i_mipi_dsi.h"
  40 #include "sun8i_tcon_top.h"
  41 #include "sunxi_engine.h"
  42
  43 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
  44 {
  45         struct drm_connector *connector;
  46         struct drm_connector_list_iter iter;
  47
  48         drm_connector_list_iter_begin(encoder->dev, &iter);
  49         drm_for_each_connector_iter(connector, &iter)
  50                 if (connector->encoder == encoder) {
  51                         drm_connector_list_iter_end(&iter);
  52                         return connector;
  53                 }
  54         drm_connector_list_iter_end(&iter);
  55
  56         return NULL;
  57 }
  58
  59 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder)
  60 {
  61         struct drm_connector *connector;
  62         struct drm_display_info *info;
  63
  64         connector = sun4i_tcon_get_connector(encoder);
  65         if (!connector)
  66                 return -EINVAL;
  67
  68         info = &connector->display_info;
  69         if (info->num_bus_formats != 1)
  70                 return -EINVAL;
  71
  72         switch (info->bus_formats[0]) {
  73         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
  74                 return 18;
  75
  76         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
  77         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
  78                 return 24;
  79         }
  80
  81         return -EINVAL;
  82 }
  83
  84 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
  85                                           bool enabled)
  86 {
  87         struct clk *clk;
  88
  89         switch (channel) {
  90         case 0:
  91                 WARN_ON(!tcon->quirks->has_channel_0);
  92                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
  93                                    SUN4I_TCON0_CTL_TCON_ENABLE,
  94                                    enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
  95                 clk = tcon->dclk;
  96                 break;
  97         case 1:
  98                 WARN_ON(!tcon->quirks->has_channel_1);
  99                 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 100                                    SUN4I_TCON1_CTL_TCON_ENABLE,
 101                                    enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
 102                 clk = tcon->sclk1;
 103                 break;
 104         default:
 105                 DRM_WARN("Unknown channel... doing nothing\n");
 106                 return;
 107         }
 108
 109         if (enabled) {
 110                 clk_prepare_enable(clk);
 111                 clk_rate_exclusive_get(clk);
 112         } else {
 113                 clk_rate_exclusive_put(clk);
 114                 clk_disable_unprepare(clk);
 115         }
 116 }
 117
 118 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
 119                                        const struct drm_encoder *encoder,
 120                                        bool enabled)
 121 {
 122         if (enabled) {
 123                 u8 val;
 124
 125                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
 126                                    SUN4I_TCON0_LVDS_IF_EN,
 127                                    SUN4I_TCON0_LVDS_IF_EN);
 128
 129                 /*
 130                  * As their name suggest, these values only apply to the A31
 131                  * and later SoCs. We'll have to rework this when merging
 132                  * support for the older SoCs.
 133                  */
 134                 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 135                              SUN6I_TCON0_LVDS_ANA0_C(2) |
 136                              SUN6I_TCON0_LVDS_ANA0_V(3) |
 137                              SUN6I_TCON0_LVDS_ANA0_PD(2) |
 138                              SUN6I_TCON0_LVDS_ANA0_EN_LDO);
 139                 udelay(2);
 140
 141                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 142                                    SUN6I_TCON0_LVDS_ANA0_EN_MB,
 143                                    SUN6I_TCON0_LVDS_ANA0_EN_MB);
 144                 udelay(2);
 145
 146                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 147                                    SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
 148                                    SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
 149
 150                 if (sun4i_tcon_get_pixel_depth(encoder) == 18)
 151                         val = 7;
 152                 else
 153                         val = 0xf;
 154
 155                 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
 156                                   SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
 157                                   SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
 158         } else {
 159                 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
 160                                    SUN4I_TCON0_LVDS_IF_EN, 0);
 161         }
 162 }
 163
 164 void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
 165                            const struct drm_encoder *encoder,
 166                            bool enabled)
 167 {
 168         bool is_lvds = false;
 169         int channel;
 170
 171         switch (encoder->encoder_type) {
 172         case DRM_MODE_ENCODER_LVDS:
 173                 is_lvds = true;
 174                 /* Fallthrough */
 175         case DRM_MODE_ENCODER_DSI:
 176         case DRM_MODE_ENCODER_NONE:
 177                 channel = 0;
 178                 break;
 179         case DRM_MODE_ENCODER_TMDS:
 180         case DRM_MODE_ENCODER_TVDAC:
 181                 channel = 1;
 182                 break;
 183         default:
 184                 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
 185                 return;
 186         }
 187
 188         if (is_lvds && !enabled)
 189                 sun4i_tcon_lvds_set_status(tcon, encoder, false);
 190
 191         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 192                            SUN4I_TCON_GCTL_TCON_ENABLE,
 193                            enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
 194
 195         if (is_lvds && enabled)
 196                 sun4i_tcon_lvds_set_status(tcon, encoder, true);
 197
 198         sun4i_tcon_channel_set_status(tcon, channel, enabled);
 199 }
 200
 201 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
 202 {
 203         u32 mask, val = 0;
 204
 205         DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
 206
 207         mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
 208                 SUN4I_TCON_GINT0_VBLANK_ENABLE(1) |
 209                 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE;
 210
 211         if (enable)
 212                 val = mask;
 213
 214         regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
 215 }
 216 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
 217
 218 /*
 219  * This function is a helper for TCON output muxing. The TCON output
 220  * muxing control register in earlier SoCs (without the TCON TOP block)
 221  * are located in TCON0. This helper returns a pointer to TCON0's
 222  * sun4i_tcon structure, or NULL if not found.
 223  */
 224 static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
 225 {
 226         struct sun4i_drv *drv = drm->dev_private;
 227         struct sun4i_tcon *tcon;
 228
 229         list_for_each_entry(tcon, &drv->tcon_list, list)
 230                 if (tcon->id == 0)
 231                         return tcon;
 232
 233         dev_warn(drm->dev,
 234                  "TCON0 not found, display output muxing may not work\n");
 235
 236         return NULL;
 237 }
 238
 239 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
 240                         const struct drm_encoder *encoder)
 241 {
 242         int ret = -ENOTSUPP;
 243
 244         if (tcon->quirks->set_mux)
 245                 ret = tcon->quirks->set_mux(tcon, encoder);
 246
 247         DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
 248                          encoder->name, encoder->crtc->name, ret);
 249 }
 250
 251 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
 252                                     int channel)
 253 {
 254         int delay = mode->vtotal - mode->vdisplay;
 255
 256         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 257                 delay /= 2;
 258
 259         if (channel == 1)
 260                 delay -= 2;
 261
 262         delay = min(delay, 30);
 263
 264         DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
 265
 266         return delay;
 267 }
 268
 269 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
 270                                         const struct drm_display_mode *mode)
 271 {
 272         /* Configure the dot clock */
 273         clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
 274
 275         /* Set the resolution */
 276         regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
 277                      SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
 278                      SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
 279 }
 280
 281 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
 282                                            const struct drm_connector *connector)
 283 {
 284         u32 bus_format = 0;
 285         u32 val = 0;
 286
 287         /* XXX Would this ever happen? */
 288         if (!connector)
 289                 return;
 290
 291         /*
 292          * FIXME: Undocumented bits
 293          *
 294          * The whole dithering process and these parameters are not
 295          * explained in the vendor documents or BSP kernel code.
 296          */
 297         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
 298         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
 299         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
 300         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
 301         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
 302         regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
 303         regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
 304         regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
 305         regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
 306         regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777);
 307
 308         /* Do dithering if panel only supports 6 bits per color */
 309         if (connector->display_info.bpc == 6)
 310                 val |= SUN4I_TCON0_FRM_CTL_EN;
 311
 312         if (connector->display_info.num_bus_formats == 1)
 313                 bus_format = connector->display_info.bus_formats[0];
 314
 315         /* Check the connection format */
 316         switch (bus_format) {
 317         case MEDIA_BUS_FMT_RGB565_1X16:
 318                 /* R and B components are only 5 bits deep */
 319                 val |= SUN4I_TCON0_FRM_CTL_MODE_R;
 320                 val |= SUN4I_TCON0_FRM_CTL_MODE_B;
 321         case MEDIA_BUS_FMT_RGB666_1X18:
 322         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 323                 /* Fall through: enable dithering */
 324                 val |= SUN4I_TCON0_FRM_CTL_EN;
 325                 break;
 326         }
 327
 328         /* Write dithering settings */
 329         regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
 330 }
 331
 332 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
 333                                      const struct drm_encoder *encoder,
 334                                      const struct drm_display_mode *mode)
 335 {
 336         /* TODO support normal CPU interface modes */
 337         struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
 338         struct mipi_dsi_device *device = dsi->device;
 339         u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
 340         u8 lanes = device->lanes;
 341         u32 block_space, start_delay;
 342         u32 tcon_div;
 343
 344         tcon->dclk_min_div = 4;
 345         tcon->dclk_max_div = 127;
 346
 347         sun4i_tcon0_mode_set_common(tcon, mode);
 348
 349         /* Set dithering if needed */
 350         sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
 351
 352         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 353                            SUN4I_TCON0_CTL_IF_MASK,
 354                            SUN4I_TCON0_CTL_IF_8080);
 355
 356         regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG,
 357                      SUN4I_TCON_ECC_FIFO_EN);
 358
 359         regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG,
 360                      SUN4I_TCON0_CPU_IF_MODE_DSI |
 361                      SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH |
 362                      SUN4I_TCON0_CPU_IF_TRI_FIFO_EN |
 363                      SUN4I_TCON0_CPU_IF_TRI_EN);
 364
 365         /*
 366          * This looks suspicious, but it works...
 367          *
 368          * The datasheet says that this should be set higher than 20 *
 369          * pixel cycle, but it's not clear what a pixel cycle is.
 370          */
 371         regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
 372         tcon_div &= GENMASK(6, 0);
 373         block_space = mode->htotal * bpp / (tcon_div * lanes);
 374         block_space -= mode->hdisplay + 40;
 375
 376         regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
 377                      SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space) |
 378                      SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay));
 379
 380         regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG,
 381                      SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay));
 382
 383         start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1);
 384         start_delay = start_delay * mode->crtc_htotal * 149;
 385         start_delay = start_delay / (mode->crtc_clock / 1000) / 8;
 386         regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG,
 387                      SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) |
 388                      SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay));
 389
 390         /*
 391          * The Allwinner BSP has a comment that the period should be
 392          * the display clock * 15, but uses an hardcoded 3000...
 393          */
 394         regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG,
 395                      SUN4I_TCON_SAFE_PERIOD_NUM(3000) |
 396                      SUN4I_TCON_SAFE_PERIOD_MODE(3));
 397
 398         /* Enable the output on the pins */
 399         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG,
 400                      0xe0000000);
 401 }
 402
 403 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
 404                                       const struct drm_encoder *encoder,
 405                                       const struct drm_display_mode *mode)
 406 {
 407         unsigned int bp;
 408         u8 clk_delay;
 409         u32 reg, val = 0;
 410
 411         WARN_ON(!tcon->quirks->has_channel_0);
 412
 413         tcon->dclk_min_div = 7;
 414         tcon->dclk_max_div = 7;
 415         sun4i_tcon0_mode_set_common(tcon, mode);
 416
 417         /* Set dithering if needed */
 418         sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
 419
 420         /* Adjust clock delay */
 421         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
 422         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 423                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
 424                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
 425
 426         /*
 427          * This is called a backporch in the register documentation,
 428          * but it really is the back porch + hsync
 429          */
 430         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 431         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 432                          mode->crtc_htotal, bp);
 433
 434         /* Set horizontal display timings */
 435         regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
 436                      SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
 437                      SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
 438
 439         /*
 440          * This is called a backporch in the register documentation,
 441          * but it really is the back porch + hsync
 442          */
 443         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 444         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 445                          mode->crtc_vtotal, bp);
 446
 447         /* Set vertical display timings */
 448         regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
 449                      SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
 450                      SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
 451
 452         reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
 453                 SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
 454                 SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
 455         if (sun4i_tcon_get_pixel_depth(encoder) == 24)
 456                 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
 457         else
 458                 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
 459
 460         regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
 461
 462         /* Setup the polarity of the various signals */
 463         if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
 464                 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
 465
 466         if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
 467                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
 468
 469         regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
 470
 471         /* Map output pins to channel 0 */
 472         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 473                            SUN4I_TCON_GCTL_IOMAP_MASK,
 474                            SUN4I_TCON_GCTL_IOMAP_TCON0);
 475
 476         /* Enable the output on the pins */
 477         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
 478 }
 479
 480 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
 481                                      const struct drm_encoder *encoder,
 482                                      const struct drm_display_mode *mode)
 483 {
 484         struct drm_connector *connector = sun4i_tcon_get_connector(encoder);
 485         struct drm_display_info display_info = connector->display_info;
 486         unsigned int bp, hsync, vsync;
 487         u8 clk_delay;
 488         u32 val = 0;
 489
 490         WARN_ON(!tcon->quirks->has_channel_0);
 491
 492         tcon->dclk_min_div = 6;
 493         tcon->dclk_max_div = 127;
 494         sun4i_tcon0_mode_set_common(tcon, mode);
 495
 496         /* Set dithering if needed */
 497         sun4i_tcon0_mode_set_dithering(tcon, connector);
 498
 499         /* Adjust clock delay */
 500         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
 501         regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 502                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
 503                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
 504
 505         /*
 506          * This is called a backporch in the register documentation,
 507          * but it really is the back porch + hsync
 508          */
 509         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 510         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 511                          mode->crtc_htotal, bp);
 512
 513         /* Set horizontal display timings */
 514         regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
 515                      SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
 516                      SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
 517
 518         /*
 519          * This is called a backporch in the register documentation,
 520          * but it really is the back porch + hsync
 521          */
 522         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 523         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 524                          mode->crtc_vtotal, bp);
 525
 526         /* Set vertical display timings */
 527         regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
 528                      SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
 529                      SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
 530
 531         /* Set Hsync and Vsync length */
 532         hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
 533         vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
 534         DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
 535         regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
 536                      SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
 537                      SUN4I_TCON0_BASIC3_H_SYNC(hsync));
 538
 539         /* Setup the polarity of the various signals */
 540         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 541                 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
 542
 543         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 544                 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
 545
 546         if (display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
 547                 val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
 548
 549         /*
 550          * On A20 and similar SoCs, the only way to achieve Positive Edge
 551          * (Rising Edge), is setting dclk clock phase to 2/3(240°).
 552          * By default TCON works in Negative Edge(Falling Edge),
 553          * this is why phase is set to 0 in that case.
 554          * Unfortunately there's no way to logically invert dclk through
 555          * IO_POL register.
 556          * The only acceptable way to work, triple checked with scope,
 557          * is using clock phase set to 0° for Negative Edge and set to 240°
 558          * for Positive Edge.
 559          * On A33 and similar SoCs there would be a 90° phase option,
 560          * but it divides also dclk by 2.
 561          * Following code is a way to avoid quirks all around TCON
 562          * and DOTCLOCK drivers.
 563          */
 564         if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE)
 565                 clk_set_phase(tcon->dclk, 240);
 566
 567         if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
 568                 clk_set_phase(tcon->dclk, 0);
 569
 570         regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
 571                            SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
 572                            SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |
 573                            SUN4I_TCON0_IO_POL_DE_NEGATIVE,
 574                            val);
 575
 576         /* Map output pins to channel 0 */
 577         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 578                            SUN4I_TCON_GCTL_IOMAP_MASK,
 579                            SUN4I_TCON_GCTL_IOMAP_TCON0);
 580
 581         /* Enable the output on the pins */
 582         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
 583 }
 584
 585 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
 586                                  const struct drm_display_mode *mode)
 587 {
 588         unsigned int bp, hsync, vsync, vtotal;
 589         u8 clk_delay;
 590         u32 val;
 591
 592         WARN_ON(!tcon->quirks->has_channel_1);
 593
 594         /* Configure the dot clock */
 595         clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
 596
 597         /* Adjust clock delay */
 598         clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
 599         regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 600                            SUN4I_TCON1_CTL_CLK_DELAY_MASK,
 601                            SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
 602
 603         /* Set interlaced mode */
 604         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 605                 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
 606         else
 607                 val = 0;
 608         regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
 609                            SUN4I_TCON1_CTL_INTERLACE_ENABLE,
 610                            val);
 611
 612         /* Set the input resolution */
 613         regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
 614                      SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
 615                      SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
 616
 617         /* Set the upscaling resolution */
 618         regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
 619                      SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
 620                      SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
 621
 622         /* Set the output resolution */
 623         regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
 624                      SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
 625                      SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
 626
 627         /* Set horizontal display timings */
 628         bp = mode->crtc_htotal - mode->crtc_hsync_start;
 629         DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 630                          mode->htotal, bp);
 631         regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
 632                      SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
 633                      SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
 634
 635         bp = mode->crtc_vtotal - mode->crtc_vsync_start;
 636         DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 637                          mode->crtc_vtotal, bp);
 638
 639         /*
 640          * The vertical resolution needs to be doubled in all
 641          * cases. We could use crtc_vtotal and always multiply by two,
 642          * but that leads to a rounding error in interlace when vtotal
 643          * is odd.
 644          *
 645          * This happens with TV's PAL for example, where vtotal will
 646          * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
 647          * 624, which apparently confuses the hardware.
 648          *
 649          * To work around this, we will always use vtotal, and
 650          * multiply by two only if we're not in interlace.
 651          */
 652         vtotal = mode->vtotal;
 653         if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
 654                 vtotal = vtotal * 2;
 655
 656         /* Set vertical display timings */
 657         regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
 658                      SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
 659                      SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
 660
 661         /* Set Hsync and Vsync length */
 662         hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
 663         vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
 664         DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
 665         regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
 666                      SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
 667                      SUN4I_TCON1_BASIC5_H_SYNC(hsync));
 668
 669         /* Map output pins to channel 1 */
 670         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
 671                            SUN4I_TCON_GCTL_IOMAP_MASK,
 672                            SUN4I_TCON_GCTL_IOMAP_TCON1);
 673 }
 674
 675 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
 676                          const struct drm_encoder *encoder,
 677                          const struct drm_display_mode *mode)
 678 {
 679         switch (encoder->encoder_type) {
 680         case DRM_MODE_ENCODER_DSI:
 681                 /* DSI is tied to special case of CPU interface */
 682                 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode);
 683                 break;
 684         case DRM_MODE_ENCODER_LVDS:
 685                 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
 686                 break;
 687         case DRM_MODE_ENCODER_NONE:
 688                 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode);
 689                 sun4i_tcon_set_mux(tcon, 0, encoder);
 690                 break;
 691         case DRM_MODE_ENCODER_TVDAC:
 692         case DRM_MODE_ENCODER_TMDS:
 693                 sun4i_tcon1_mode_set(tcon, mode);
 694                 sun4i_tcon_set_mux(tcon, 1, encoder);
 695                 break;
 696         default:
 697                 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
 698         }
 699 }
 700 EXPORT_SYMBOL(sun4i_tcon_mode_set);
 701
 702 static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
 703                                         struct sun4i_crtc *scrtc)
 704 {
 705         unsigned long flags;
 706
 707         spin_lock_irqsave(&dev->event_lock, flags);
 708         if (scrtc->event) {
 709                 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
 710                 drm_crtc_vblank_put(&scrtc->crtc);
 711                 scrtc->event = NULL;
 712         }
 713         spin_unlock_irqrestore(&dev->event_lock, flags);
 714 }
 715
 716 static irqreturn_t sun4i_tcon_handler(int irq, void *private)
 717 {
 718         struct sun4i_tcon *tcon = private;
 719         struct drm_device *drm = tcon->drm;
 720         struct sun4i_crtc *scrtc = tcon->crtc;
 721         struct sunxi_engine *engine = scrtc->engine;
 722         unsigned int status;
 723
 724         regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
 725
 726         if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
 727                         SUN4I_TCON_GINT0_VBLANK_INT(1) |
 728                         SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT)))
 729                 return IRQ_NONE;
 730
 731         drm_crtc_handle_vblank(&scrtc->crtc);
 732         sun4i_tcon_finish_page_flip(drm, scrtc);
 733
 734         /* Acknowledge the interrupt */
 735         regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
 736                            SUN4I_TCON_GINT0_VBLANK_INT(0) |
 737                            SUN4I_TCON_GINT0_VBLANK_INT(1) |
 738                            SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT,
 739                            0);
 740
 741         if (engine->ops->vblank_quirk)
 742                 engine->ops->vblank_quirk(engine);
 743
 744         return IRQ_HANDLED;
 745 }
 746
 747 static int sun4i_tcon_init_clocks(struct device *dev,
 748                                   struct sun4i_tcon *tcon)
 749 {
 750         tcon->clk = devm_clk_get(dev, "ahb");
 751         if (IS_ERR(tcon->clk)) {
 752                 dev_err(dev, "Couldn't get the TCON bus clock\n");
 753                 return PTR_ERR(tcon->clk);
 754         }
 755         clk_prepare_enable(tcon->clk);
 756
 757         if (tcon->quirks->has_channel_0) {
 758                 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
 759                 if (IS_ERR(tcon->sclk0)) {
 760                         dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
 761                         return PTR_ERR(tcon->sclk0);
 762                 }
 763         }
 764         clk_prepare_enable(tcon->sclk0);
 765
 766         if (tcon->quirks->has_channel_1) {
 767                 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
 768                 if (IS_ERR(tcon->sclk1)) {
 769                         dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
 770                         return PTR_ERR(tcon->sclk1);
 771                 }
 772         }
 773
 774         return 0;
 775 }
 776
 777 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
 778 {
 779         clk_disable_unprepare(tcon->sclk0);
 780         clk_disable_unprepare(tcon->clk);
 781 }
 782
 783 static int sun4i_tcon_init_irq(struct device *dev,
 784                                struct sun4i_tcon *tcon)
 785 {
 786         struct platform_device *pdev = to_platform_device(dev);
 787         int irq, ret;
 788
 789         irq = platform_get_irq(pdev, 0);
 790         if (irq < 0) {
 791                 dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
 792                 return irq;
 793         }
 794
 795         ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
 796                                dev_name(dev), tcon);
 797         if (ret) {
 798                 dev_err(dev, "Couldn't request the IRQ\n");
 799                 return ret;
 800         }
 801
 802         return 0;
 803 }
 804
 805 static struct regmap_config sun4i_tcon_regmap_config = {
 806         .reg_bits       = 32,
 807         .val_bits       = 32,
 808         .reg_stride     = 4,
 809         .max_register   = 0x800,
 810 };
 811
 812 static int sun4i_tcon_init_regmap(struct device *dev,
 813                                   struct sun4i_tcon *tcon)
 814 {
 815         struct platform_device *pdev = to_platform_device(dev);
 816         struct resource *res;
 817         void __iomem *regs;
 818
 819         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 820         regs = devm_ioremap_resource(dev, res);
 821         if (IS_ERR(regs))
 822                 return PTR_ERR(regs);
 823
 824         tcon->regs = devm_regmap_init_mmio(dev, regs,
 825                                            &sun4i_tcon_regmap_config);
 826         if (IS_ERR(tcon->regs)) {
 827                 dev_err(dev, "Couldn't create the TCON regmap\n");
 828                 return PTR_ERR(tcon->regs);
 829         }
 830
 831         /* Make sure the TCON is disabled and all IRQs are off */
 832         regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
 833         regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
 834         regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
 835
 836         /* Disable IO lines and set them to tristate */
 837         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
 838         regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
 839
 840         return 0;
 841 }
 842
 843 /*
 844  * On SoCs with the old display pipeline design (Display Engine 1.0),
 845  * the TCON is always tied to just one backend. Hence we can traverse
 846  * the of_graph upwards to find the backend our tcon is connected to,
 847  * and take its ID as our own.
 848  *
 849  * We can either identify backends from their compatible strings, which
 850  * means maintaining a large list of them. Or, since the backend is
 851  * registered and binded before the TCON, we can just go through the
 852  * list of registered backends and compare the device node.
 853  *
 854  * As the structures now store engines instead of backends, here this
 855  * function in fact searches the corresponding engine, and the ID is
 856  * requested via the get_id function of the engine.
 857  */
 858 static struct sunxi_engine *
 859 sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
 860                                 struct device_node *node,
 861                                 u32 port_id)
 862 {
 863         struct device_node *port, *ep, *remote;
 864         struct sunxi_engine *engine = ERR_PTR(-EINVAL);
 865         u32 reg = 0;
 866
 867         port = of_graph_get_port_by_id(node, port_id);
 868         if (!port)
 869                 return ERR_PTR(-EINVAL);
 870
 871         /*
 872          * This only works if there is only one path from the TCON
 873          * to any display engine. Otherwise the probe order of the
 874          * TCONs and display engines is not guaranteed. They may
 875          * either bind to the wrong one, or worse, bind to the same
 876          * one if additional checks are not done.
 877          *
 878          * Bail out if there are multiple input connections.
 879          */
 880         if (of_get_available_child_count(port) != 1)
 881                 goto out_put_port;
 882
 883         /* Get the first connection without specifying an ID */
 884         ep = of_get_next_available_child(port, NULL);
 885         if (!ep)
 886                 goto out_put_port;
 887
 888         remote = of_graph_get_remote_port_parent(ep);
 889         if (!remote)
 890                 goto out_put_ep;
 891
 892         /* does this node match any registered engines? */
 893         list_for_each_entry(engine, &drv->engine_list, list)
 894                 if (remote == engine->node)
 895                         goto out_put_remote;
 896
 897         /*
 898          * According to device tree binding input ports have even id
 899          * number and output ports have odd id. Since component with
 900          * more than one input and one output (TCON TOP) exits, correct
 901          * remote input id has to be calculated by subtracting 1 from
 902          * remote output id. If this for some reason can't be done, 0
 903          * is used as input port id.
 904          */
 905         of_node_put(port);
 906         port = of_graph_get_remote_port(ep);
 907         if (!of_property_read_u32(port, "reg", &reg) && reg > 0)
 908                 reg -= 1;
 909
 910         /* keep looking through upstream ports */
 911         engine = sun4i_tcon_find_engine_traverse(drv, remote, reg);
 912
 913 out_put_remote:
 914         of_node_put(remote);
 915 out_put_ep:
 916         of_node_put(ep);
 917 out_put_port:
 918         of_node_put(port);
 919
 920         return engine;
 921 }
 922
 923 /*
 924  * The device tree binding says that the remote endpoint ID of any
 925  * connection between components, up to and including the TCON, of
 926  * the display pipeline should be equal to the actual ID of the local
 927  * component. Thus we can look at any one of the input connections of
 928  * the TCONs, and use that connection's remote endpoint ID as our own.
 929  *
 930  * Since the user of this function already finds the input port,
 931  * the port is passed in directly without further checks.
 932  */
 933 static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
 934 {
 935         struct device_node *ep;
 936         int ret = -EINVAL;
 937
 938         /* try finding an upstream endpoint */
 939         for_each_available_child_of_node(port, ep) {
 940                 struct device_node *remote;
 941                 u32 reg;
 942
 943                 remote = of_graph_get_remote_endpoint(ep);
 944                 if (!remote)
 945                         continue;
 946
 947                 ret = of_property_read_u32(remote, "reg", &reg);
 948                 if (ret)
 949                         continue;
 950
 951                 ret = reg;
 952         }
 953
 954         return ret;
 955 }
 956
 957 /*
 958  * Once we know the TCON's id, we can look through the list of
 959  * engines to find a matching one. We assume all engines have
 960  * been probed and added to the list.
 961  */
 962 static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
 963                                                         int id)
 964 {
 965         struct sunxi_engine *engine;
 966
 967         list_for_each_entry(engine, &drv->engine_list, list)
 968                 if (engine->id == id)
 969                         return engine;
 970
 971         return ERR_PTR(-EINVAL);
 972 }
 973
 974 static bool sun4i_tcon_connected_to_tcon_top(struct device_node *node)
 975 {
 976         struct device_node *remote;
 977         bool ret = false;
 978
 979         remote = of_graph_get_remote_node(node, 0, -1);
 980         if (remote) {
 981                 ret = !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
 982                          of_match_node(sun8i_tcon_top_of_table, remote));
 983                 of_node_put(remote);
 984         }
 985
 986         return ret;
 987 }
 988
 989 static int sun4i_tcon_get_index(struct sun4i_drv *drv)
 990 {
 991         struct list_head *pos;
 992         int size = 0;
 993
 994         /*
 995          * Because TCON is added to the list at the end of the probe
 996          * (after this function is called), index of the current TCON
 997          * will be same as current TCON list size.
 998          */
 999         list_for_each(pos, &drv->tcon_list)
1000                 ++size;
1001
1002         return size;
1003 }
1004
1005 /*
1006  * On SoCs with the old display pipeline design (Display Engine 1.0),
1007  * we assumed the TCON was always tied to just one backend. However
1008  * this proved not to be the case. On the A31, the TCON can select
1009  * either backend as its source. On the A20 (and likely on the A10),
1010  * the backend can choose which TCON to output to.
1011  *
1012  * The device tree binding says that the remote endpoint ID of any
1013  * connection between components, up to and including the TCON, of
1014  * the display pipeline should be equal to the actual ID of the local
1015  * component. Thus we should be able to look at any one of the input
1016  * connections of the TCONs, and use that connection's remote endpoint
1017  * ID as our own.
1018  *
1019  * However  the connections between the backend and TCON were assumed
1020  * to be always singular, and their endpoit IDs were all incorrectly
1021  * set to 0. This means for these old device trees, we cannot just look
1022  * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
1023  * incorrectly identified as TCON0.
1024  *
1025  * This function first checks if the TCON node has 2 input endpoints.
1026  * If so, then the device tree is a corrected version, and it will use
1027  * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
1028  * to fetch the ID and engine directly. If not, then it is likely an
1029  * old device trees, where the endpoint IDs were incorrect, but did not
1030  * have endpoint connections between the backend and TCON across
1031  * different display pipelines. It will fall back to the old method of
1032  * traversing the  of_graph to try and find a matching engine by device
1033  * node.
1034  *
1035  * In the case of single display pipeline device trees, either method
1036  * works.
1037  */
1038 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
1039                                                    struct device_node *node)
1040 {
1041         struct device_node *port;
1042         struct sunxi_engine *engine;
1043
1044         port = of_graph_get_port_by_id(node, 0);
1045         if (!port)
1046                 return ERR_PTR(-EINVAL);
1047
1048         /*
1049          * Is this a corrected device tree with cross pipeline
1050          * connections between the backend and TCON?
1051          */
1052         if (of_get_child_count(port) > 1) {
1053                 int id;
1054
1055                 /*
1056                  * When pipeline has the same number of TCONs and engines which
1057                  * are represented by frontends/backends (DE1) or mixers (DE2),
1058                  * we match them by their respective IDs. However, if pipeline
1059                  * contains TCON TOP, chances are that there are either more
1060                  * TCONs than engines (R40) or TCONs with non-consecutive ids.
1061                  * (H6). In that case it's easier just use TCON index in list
1062                  * as an id. That means that on R40, any 2 TCONs can be enabled
1063                  * in DT out of 4 (there are 2 mixers). Due to the design of
1064                  * TCON TOP, remaining 2 TCONs can't be connected to anything
1065                  * anyway.
1066                  */
1067                 if (sun4i_tcon_connected_to_tcon_top(node))
1068                         id = sun4i_tcon_get_index(drv);
1069                 else
1070                         id = sun4i_tcon_of_get_id_from_port(port);
1071
1072                 /* Get our engine by matching our ID */
1073                 engine = sun4i_tcon_get_engine_by_id(drv, id);
1074
1075                 of_node_put(port);
1076                 return engine;
1077         }
1078
1079         /* Fallback to old method by traversing input endpoints */
1080         of_node_put(port);
1081         return sun4i_tcon_find_engine_traverse(drv, node, 0);
1082 }
1083
1084 static int sun4i_tcon_bind(struct device *dev, struct device *master,
1085                            void *data)
1086 {
1087         struct drm_device *drm = data;
1088         struct sun4i_drv *drv = drm->dev_private;
1089         struct sunxi_engine *engine;
1090         struct device_node *remote;
1091         struct sun4i_tcon *tcon;
1092         struct reset_control *edp_rstc;
1093         bool has_lvds_rst, has_lvds_alt, can_lvds;
1094         int ret;
1095
1096         engine = sun4i_tcon_find_engine(drv, dev->of_node);
1097         if (IS_ERR(engine)) {
1098                 dev_err(dev, "Couldn't find matching engine\n");
1099                 return -EPROBE_DEFER;
1100         }
1101
1102         tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
1103         if (!tcon)
1104                 return -ENOMEM;
1105         dev_set_drvdata(dev, tcon);
1106         tcon->drm = drm;
1107         tcon->dev = dev;
1108         tcon->id = engine->id;
1109         tcon->quirks = of_device_get_match_data(dev);
1110
1111         tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
1112         if (IS_ERR(tcon->lcd_rst)) {
1113                 dev_err(dev, "Couldn't get our reset line\n");
1114                 return PTR_ERR(tcon->lcd_rst);
1115         }
1116
1117         if (tcon->quirks->needs_edp_reset) {
1118                 edp_rstc = devm_reset_control_get_shared(dev, "edp");
1119                 if (IS_ERR(edp_rstc)) {
1120                         dev_err(dev, "Couldn't get edp reset line\n");
1121                         return PTR_ERR(edp_rstc);
1122                 }
1123
1124                 ret = reset_control_deassert(edp_rstc);
1125                 if (ret) {
1126                         dev_err(dev, "Couldn't deassert edp reset line\n");
1127                         return ret;
1128                 }
1129         }
1130
1131         /* Make sure our TCON is reset */
1132         ret = reset_control_reset(tcon->lcd_rst);
1133         if (ret) {
1134                 dev_err(dev, "Couldn't deassert our reset line\n");
1135                 return ret;
1136         }
1137
1138         if (tcon->quirks->supports_lvds) {
1139                 /*
1140                  * This can only be made optional since we've had DT
1141                  * nodes without the LVDS reset properties.
1142                  *
1143                  * If the property is missing, just disable LVDS, and
1144                  * print a warning.
1145                  */
1146                 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
1147                 if (IS_ERR(tcon->lvds_rst)) {
1148                         dev_err(dev, "Couldn't get our reset line\n");
1149                         return PTR_ERR(tcon->lvds_rst);
1150                 } else if (tcon->lvds_rst) {
1151                         has_lvds_rst = true;
1152                         reset_control_reset(tcon->lvds_rst);
1153                 } else {
1154                         has_lvds_rst = false;
1155                 }
1156
1157                 /*
1158                  * This can only be made optional since we've had DT
1159                  * nodes without the LVDS reset properties.
1160                  *
1161                  * If the property is missing, just disable LVDS, and
1162                  * print a warning.
1163                  */
1164                 if (tcon->quirks->has_lvds_alt) {
1165                         tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
1166                         if (IS_ERR(tcon->lvds_pll)) {
1167                                 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
1168                                         has_lvds_alt = false;
1169                                 } else {
1170                                         dev_err(dev, "Couldn't get the LVDS PLL\n");
1171                                         return PTR_ERR(tcon->lvds_pll);
1172                                 }
1173                         } else {
1174                                 has_lvds_alt = true;
1175                         }
1176                 }
1177
1178                 if (!has_lvds_rst ||
1179                     (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
1180                         dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n");
1181                         dev_warn(dev, "LVDS output disabled\n");
1182                         can_lvds = false;
1183                 } else {
1184                         can_lvds = true;
1185                 }
1186         } else {
1187                 can_lvds = false;
1188         }
1189
1190         ret = sun4i_tcon_init_clocks(dev, tcon);
1191         if (ret) {
1192                 dev_err(dev, "Couldn't init our TCON clocks\n");
1193                 goto err_assert_reset;
1194         }
1195
1196         ret = sun4i_tcon_init_regmap(dev, tcon);
1197         if (ret) {
1198                 dev_err(dev, "Couldn't init our TCON regmap\n");
1199                 goto err_free_clocks;
1200         }
1201
1202         if (tcon->quirks->has_channel_0) {
1203                 ret = sun4i_dclk_create(dev, tcon);
1204                 if (ret) {
1205                         dev_err(dev, "Couldn't create our TCON dot clock\n");
1206                         goto err_free_clocks;
1207                 }
1208         }
1209
1210         ret = sun4i_tcon_init_irq(dev, tcon);
1211         if (ret) {
1212                 dev_err(dev, "Couldn't init our TCON interrupts\n");
1213                 goto err_free_dotclock;
1214         }
1215
1216         tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
1217         if (IS_ERR(tcon->crtc)) {
1218                 dev_err(dev, "Couldn't create our CRTC\n");
1219                 ret = PTR_ERR(tcon->crtc);
1220                 goto err_free_dotclock;
1221         }
1222
1223         if (tcon->quirks->has_channel_0) {
1224                 /*
1225                  * If we have an LVDS panel connected to the TCON, we should
1226                  * just probe the LVDS connector. Otherwise, just probe RGB as
1227                  * we used to.
1228                  */
1229                 remote = of_graph_get_remote_node(dev->of_node, 1, 0);
1230                 if (of_device_is_compatible(remote, "panel-lvds"))
1231                         if (can_lvds)
1232                                 ret = sun4i_lvds_init(drm, tcon);
1233                         else
1234                                 ret = -EINVAL;
1235                 else
1236                         ret = sun4i_rgb_init(drm, tcon);
1237                 of_node_put(remote);
1238
1239                 if (ret < 0)
1240                         goto err_free_dotclock;
1241         }
1242
1243         if (tcon->quirks->needs_de_be_mux) {
1244                 /*
1245                  * We assume there is no dynamic muxing of backends
1246                  * and TCONs, so we select the backend with same ID.
1247                  *
1248                  * While dynamic selection might be interesting, since
1249                  * the CRTC is tied to the TCON, while the layers are
1250                  * tied to the backends, this means, we will need to
1251                  * switch between groups of layers. There might not be
1252                  * a way to represent this constraint in DRM.
1253                  */
1254                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
1255                                    SUN4I_TCON0_CTL_SRC_SEL_MASK,
1256                                    tcon->id);
1257                 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
1258                                    SUN4I_TCON1_CTL_SRC_SEL_MASK,
1259                                    tcon->id);
1260         }
1261
1262         list_add_tail(&tcon->list, &drv->tcon_list);
1263
1264         return 0;
1265
1266 err_free_dotclock:
1267         if (tcon->quirks->has_channel_0)
1268                 sun4i_dclk_free(tcon);
1269 err_free_clocks:
1270         sun4i_tcon_free_clocks(tcon);
1271 err_assert_reset:
1272         reset_control_assert(tcon->lcd_rst);
1273         return ret;
1274 }
1275
1276 static void sun4i_tcon_unbind(struct device *dev, struct device *master,
1277                               void *data)
1278 {
1279         struct sun4i_tcon *tcon = dev_get_drvdata(dev);
1280
1281         list_del(&tcon->list);
1282         if (tcon->quirks->has_channel_0)
1283                 sun4i_dclk_free(tcon);
1284         sun4i_tcon_free_clocks(tcon);
1285 }
1286
1287 static const struct component_ops sun4i_tcon_ops = {
1288         .bind   = sun4i_tcon_bind,
1289         .unbind = sun4i_tcon_unbind,
1290 };
1291
1292 static int sun4i_tcon_probe(struct platform_device *pdev)
1293 {
1294         struct device_node *node = pdev->dev.of_node;
1295         const struct sun4i_tcon_quirks *quirks;
1296         struct drm_bridge *bridge;
1297         struct drm_panel *panel;
1298         int ret;
1299
1300         quirks = of_device_get_match_data(&pdev->dev);
1301
1302         /* panels and bridges are present only on TCONs with channel 0 */
1303         if (quirks->has_channel_0) {
1304                 ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
1305                 if (ret == -EPROBE_DEFER)
1306                         return ret;
1307         }
1308
1309         return component_add(&pdev->dev, &sun4i_tcon_ops);
1310 }
1311
1312 static int sun4i_tcon_remove(struct platform_device *pdev)
1313 {
1314         component_del(&pdev->dev, &sun4i_tcon_ops);
1315
1316         return 0;
1317 }
1318
1319 /* platform specific TCON muxing callbacks */
1320 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
1321                                   const struct drm_encoder *encoder)
1322 {
1323         struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1324         u32 shift;
1325
1326         if (!tcon0)
1327                 return -EINVAL;
1328
1329         switch (encoder->encoder_type) {
1330         case DRM_MODE_ENCODER_TMDS:
1331                 /* HDMI */
1332                 shift = 8;
1333                 break;
1334         default:
1335                 return -EINVAL;
1336         }
1337
1338         regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1339                            0x3 << shift, tcon->id << shift);
1340
1341         return 0;
1342 }
1343
1344 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
1345                                   const struct drm_encoder *encoder)
1346 {
1347         u32 val;
1348
1349         if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1350                 val = 1;
1351         else
1352                 val = 0;
1353
1354         /*
1355          * FIXME: Undocumented bits
1356          */
1357         return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
1358 }
1359
1360 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
1361                               const struct drm_encoder *encoder)
1362 {
1363         struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1364         u32 shift;
1365
1366         if (!tcon0)
1367                 return -EINVAL;
1368
1369         switch (encoder->encoder_type) {
1370         case DRM_MODE_ENCODER_TMDS:
1371                 /* HDMI */
1372                 shift = 8;
1373                 break;
1374         default:
1375                 /* TODO A31 has MIPI DSI but A31s does not */
1376                 return -EINVAL;
1377         }
1378
1379         regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1380                            0x3 << shift, tcon->id << shift);
1381
1382         return 0;
1383 }
1384
1385 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon,
1386                                      const struct drm_encoder *encoder)
1387 {
1388         struct device_node *port, *remote;
1389         struct platform_device *pdev;
1390         int id, ret;
1391
1392         /* find TCON TOP platform device and TCON id */
1393
1394         port = of_graph_get_port_by_id(tcon->dev->of_node, 0);
1395         if (!port)
1396                 return -EINVAL;
1397
1398         id = sun4i_tcon_of_get_id_from_port(port);
1399         of_node_put(port);
1400
1401         remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1);
1402         if (!remote)
1403                 return -EINVAL;
1404
1405         pdev = of_find_device_by_node(remote);
1406         of_node_put(remote);
1407         if (!pdev)
1408                 return -EINVAL;
1409
1410         if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
1411             encoder->encoder_type == DRM_MODE_ENCODER_TMDS) {
1412                 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id);
1413                 if (ret)
1414                         return ret;
1415         }
1416
1417         if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP)) {
1418                 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id);
1419                 if (ret)
1420                         return ret;
1421         }
1422
1423         return 0;
1424 }
1425
1426 static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
1427         .has_channel_0          = true,
1428         .has_channel_1          = true,
1429         .set_mux                = sun4i_a10_tcon_set_mux,
1430 };
1431
1432 static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
1433         .has_channel_0          = true,
1434         .has_channel_1          = true,
1435         .set_mux                = sun5i_a13_tcon_set_mux,
1436 };
1437
1438 static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
1439         .has_channel_0          = true,
1440         .has_channel_1          = true,
1441         .has_lvds_alt           = true,
1442         .needs_de_be_mux        = true,
1443         .set_mux                = sun6i_tcon_set_mux,
1444 };
1445
1446 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
1447         .has_channel_0          = true,
1448         .has_channel_1          = true,
1449         .needs_de_be_mux        = true,
1450 };
1451
1452 static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
1453         .has_channel_0          = true,
1454         .has_channel_1          = true,
1455         /* Same display pipeline structure as A10 */
1456         .set_mux                = sun4i_a10_tcon_set_mux,
1457 };
1458
1459 static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
1460         .has_channel_0          = true,
1461         .has_lvds_alt           = true,
1462 };
1463
1464 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
1465         .supports_lvds          = true,
1466         .has_channel_0          = true,
1467 };
1468
1469 static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
1470         .has_channel_1          = true,
1471 };
1472
1473 static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
1474         .has_channel_1          = true,
1475         .set_mux                = sun8i_r40_tcon_tv_set_mux,
1476 };
1477
1478 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
1479         .has_channel_0          = true,
1480 };
1481
1482 static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = {
1483         .has_channel_0  = true,
1484         .needs_edp_reset = true,
1485 };
1486
1487 static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = {
1488         .has_channel_1  = true,
1489         .needs_edp_reset = true,
1490 };
1491
1492 /* sun4i_drv uses this list to check if a device node is a TCON */
1493 const struct of_device_id sun4i_tcon_of_table[] = {
1494         { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1495         { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1496         { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1497         { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1498         { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1499         { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1500         { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1501         { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1502         { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1503         { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1504         { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1505         { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1506         { }
1507 };
1508 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
1509 EXPORT_SYMBOL(sun4i_tcon_of_table);
1510
1511 static struct platform_driver sun4i_tcon_platform_driver = {
1512         .probe          = sun4i_tcon_probe,
1513         .remove         = sun4i_tcon_remove,
1514         .driver         = {
1515                 .name           = "sun4i-tcon",
1516                 .of_match_table = sun4i_tcon_of_table,
1517         },
1518 };
1519 module_platform_driver(sun4i_tcon_platform_driver);
1520
1521 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1522 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
1523 MODULE_LICENSE("GPL");